IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.

11, NOVEMBER 2009 2531

A Unified Approach for the Derivation of Robust

Control for Boost PFC Converters
Grace Chu, Student Member, IEEE, Chi K. Tse, Fellow, IEEE, Siu Chung Wong, Senior Member, IEEE,
and Siew-Chong Tan, Member, IEEE

Abstract—In this paper, a generalized approach for the system-

atic generation of robust control rules for the boost power fac-
tor correction converter is presented. Based on a cascading multi-
loop control structure, a unified approach for deriving the control
functions for the inner current loop and the outer voltage loop is
proposed. The resulting control provides unity power factor and
regulated average output voltage with fast transient response. The
control performance is robust under all practical conditions as a re-
sult of the application of feedback linearization. This method elim-
inates the nonlinearity and the dependence of the error dynamics
on the input disturbance. The control parameters can be designed
according to the desired steady-state and transient response per-
formances. The resulting control rules are readily implemented
in analog circuitries. Experiments are conducted to evaluate the
control performance.
Index Terms—AC–DC power conversion, power electronics,
power quality, power supplies, power system control. Fig. 1. (a) Block diagram of a typical PFC converter. (b) Ideal waveforms.

I. INTRODUCTION
OWER factor correction (PFC) is mandatorily required for
P medium- to high-power offline power supplies for improv-
ing input power quality. Power supplies with PFC capability
usually contain a preregulator whose function is to ensure a
near unity power factor at the input. The usual form of a PFC
preregulator is a boost converter [1] controlled by a fast con-
trol loop, also known as inner current loop, such that the input
current follows the same sinusoidal waveform as the input volt-
age [2]. The PFC preregulator is often terminated with a storage
capacitor that interfaces with a downstream converter to provide
a tightly regulated output voltage to the eventual load. The PFC
preregulator is thus required to maintain a regulated averaged
output voltage across its terminating storage capacitor. A block
diagram of a boost PFC preregulator and the corresponding
waveforms are shown in Fig. 1.
The objectives of the control circuit for the PFC preregulator
are twofold. First, a near unity power factor should be main-
tained at the input side via an inner current loop. Second, a
constant average voltage should be maintained across the out-
put storage capacitor via an output regulation loop. The first
objective implies that the input current should be sinusoidal and
in phase with the supply voltage, resulting in a squared sinu-
soidal power input function, as shown in Fig. 1(b), where vi is
Manuscript received December 18, 2008; revised February 17, 2009. Current
version published December 18, 2009. This work was supported by Hong Kong
Research Grants Council under Grant PolyU 5289/05E. Recommended for
publication by Associate Editor P. Mattavelli.
The authors are with the Department of Electronic and Information Engi-
neering, Hong Kong Polytechnic University, Kowloon, Hong Kong (e-mail:
05900469r@polyu.edu.hk; encktse@polyu.edu.hk; enscwong@polyu.edu.hk;
ensctan@eie.polyu.edu.hk).
Digital Object Identifier 10.1109/TPEL.2009.2020986
0885-8993/$26.00 © 2009 IEEE
Fig. 2. Separation of time scale and the modeling approach for the current
loop and the voltage loop.
the rectified line voltage, iref is the reference current, pi is the
input power, and vo is the output voltage. Clearly, output voltage
ripple is inevitable for power balance since the input power is a
squared sinusoidal function, and the size of the storage capacitor
can be chosen to keep the ripple magnitude to a reasonable level.
In practice, the storage capacitor also affects the dynamical re-
sponse of the output regulation loop, and as a compromise, the
output voltage would be regulated at every rectified line cycle.
This indicates that the line frequency is the maximum band-
width allowed in the output regulation loop under the condition
of unity power factor [3].
In order to program the input current to follow the sinusoidal
envelope, the input current has to be controlled cycle-by-cycle
at the switching frequency. This implies that the bandwidth
required by the current control is much higher than that of the
voltage control, as illustrated in Fig. 2. The cascading multiloop
control structure exploits the separation of time scale into two
control loops [8], [16], with the inner loop being a fast current
loop and the outer loop being a slow voltage loop. Average
current mode (ACM) control is the most widely used multiloop
control method for PFC converters [4]–[6]. Numerous methods
have been proposed in the literature to improve the performance

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2532
of the two control loops in terms of the input current distortion
and the transient response of the output voltage.
For the inner current loop, the phenomenon of zero-crossing
distortion under high-operating line frequency was reported and
analyzed by Sun [7]. This spurred a series of research interest
toward the elimination of such a distortion. In the same work,
Sun proposed a solution by adding a phase delay in the reference
current to compensate the leading phase of the current. Alter-
natively, Wall and Jackson [8] feedforwarded the input voltage
and output voltage signal to the current error to reduce the input
current distortion. Later, Chen and Sun [9] presented a more
complete feedforward scheme by including the derivative of the
reference current in the feedforward signal. Recently, Louganski
and Lai [10] presented a method of adding an extra RC network
in the current amplifier compensation network to compensate
the phase lead in the current signal.
For the outer voltage loop, with limited bandwidth, the out-
put voltage has a slow transient response with a relatively large
overshoot. Numerous approaches have been reported in the lit-
erature to improve the transient response. One approach aims
at removing the rectified line frequency ripple in the feedback
signal, which allows a further increase in the voltage loop’s
bandwidth without deteriorating the input current distortion.
The use of the analog notch filter to filter the line frequency
ripple was first reported by Williams [11]. With the advance in
DSP technology, the digital implementation of the notch filter
and its variant enables sophisticated filtering functions to be re-
alized conveniently [12]–[15]. Besides the filtering method, the
line frequency ripple can also be compensated by inserting a
nonlinear function in the voltage loop, which is also known as
active ripple cancellation [16]–[18]. Other approaches focus on
maintaining the output voltage within a predefined regulation
band. When the output voltage goes beyond the regulation band
in the event of a step load, certain actions will be taken to bring
the output voltage back to the regulation band [11], [19], [20].
Besides, the voltage feedforward control also provides an effec-
tive method to improve the transient response performance. For
example, Figueres et al. [21] feedforwarded the load-current
signal to the output of the voltage error amplifier.
In these previous works, the current loop control and the volt-
age loop control are specifically developed to tackle particular
undesirable phenomena. However, a systematic derivation pro-
cedure that is applicable to both control loops is still missing.
Specifically, in the feedforward control schemes, the resulting
closed-loop systems become too complex for analysis and for-
mal study of their large-signal behaviors. This necessitates the
use of trial-and-error procedures in the design of the control
parameters, while the design constraints and the optimal design
solution remain unknown.
In this paper, based on a cascading multiloop control struc-
ture, a generalized approach applicable to both the current loop
and the voltage loop is introduced for systematic generation
of robust control rules for PFC converters. The block diagram
is depicted in Fig. 3. Instead of focusing on particular phe-
nomena in each loop, we attempt to reduce the system error
dynamics to a simple linear form based on the method of feed-
back linearization [22]–[26]. Feedback linearization is an ap-
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
Fig. 3. Boost PFC converter with the derived control based on the cascaded
multiloop control structure.
proach for transforming a nonlinear system into an equivalent
linear system. It is completely different from the conventional
(Jacobian) linearization in that the feedback linearization is
achieved by state transformation and feedback, rather than by
linear approximation of the dynamics. This approach eliminates
all the undesirable phenomena incurred by the nonlinearity and
the dependency of the system dynamics on the input distur-
bance, and thus results in improved control performance and
robustness under variations of operating condition.
Another issue addressed by this paper is the choice of the
control parameters. Based on the generalized approach, the er-
ror dynamical equations give clear pictures of the closed-loop
behaviors of the two control loops, which offer insights into the
design of the control parameters. Due to the linear nature of
the resulting error dynamics, effective tools from linear control
can be fully utilized to analyze the steady-state frequency re-
sponse and the transient response. The control parameters can
be selected according to the Bode plots of the loop gain and the
transient response waveforms to ensure system stability and sat-
isfactory performance. The performance of the resulting control
rules will be evaluated by experiments.
The rest of the paper is outlined as follows. In Section II, we
begin with the inner-loop current control. Theoretical derivation
and frequency response analysis are presented in Sections II-A
and II-B. Next, we proceed to the outer-loop voltage control
in Section III. In addition to the theoretical derivation and the
frequency response analysis in Sections III-A and III-B, tran-
sient response is explored in Section III-C. Then, experimental
verification is presented in Section IV, in which the practical im-
plementation of the derived control is discussed in Section IV-A,
and the experimental results are presented in Sections IV-B and
IV-C. Finally, a conclusion is given in Section V.
II. INNER-LOOP CURRENT CONTROL
A. Theoretical Derivation
In this section, a generalized approach based on the method of
feedback linearization [22], [23] is applied to generate the inner-
loop current control rule. The averaged model of the inductor
current is represented by
diL 1 ¯ o)
= (vi − dv (1)
dt L
where d¯ = 1 − d with d being the continuous duty cycle.
CHU et al.: UNIFIED APPROACH FOR THE DERIVATION OF ROBUST CONTROL FOR BOOST PFC CONVERTERS 2533

Fig. 5. (a) Block diagram of the current error dynamics under the derived
current control rule. (b) Block diagram in general form.

Alternatively, it can be applied to the standard PFC controller by

adding input voltage feedforward and the corresponding func-
tional circuitries (e.g., summation, inversion) to the controller
Fig. 4. Boost PFC converter with the derived inner-loop control rule. circuit, resulting in a control rule that covers the functions of
the feedforward control schemes proposed previously [8], [9].
The objective of the control is to track the inductor current Based on the proposed derivation, the properties of the resulting
along the reference current iref generated by the outer loop. control rule will be further explored in the following sections.
Here, we denote the current error by ei where
B. Frequency Response Analysis
ei = iref − iL . (2)
In this section, the frequency response of the current error
The dynamics of the current error is dynamics is investigated. Under the derived current control rule,
dei diref diL diref 1 vo ¯ (7) gives a complete picture of the steady-state behavior of the
= − = − vi + d. (3) closed-loop system, which can be written as
dt dt dt dt L L

Here, d¯ is the input of the current error dynamics. In a closed- diL diref
= + Ki1 (iref − iL ) + Ki2 (iref − iL )dt. (9)
loop system, d¯ is generated by the control circuit using the dt dt
feedback signals. Based on the method of feedback linearization,
Due to the linear nature, (9) can be expressed in the s-domain
the dynamics can be made linear if d¯ is configured as


 as
diref vi L diref 1

¯
d = via − + = Lvia − L + vi 1
dt L vo dt vo siL = siref + (iref − iL ) Ki1 + Ki2 . (10)
s
(4)
with via being an equivalent input. The block diagram of (10) is depicted in Fig. 5(a), which can
Hence, the resulting error dynamics becomes be manipulated into a general form as shown in Fig. 5(b). Upon
inspection of Fig. 5(b), the round-trip loop gain is
dei
= via . (5) Ki2 (1 + (sKi1 /Ki2 ))
dt Gi = . (11)
Clearly, a desired dynamical behavior can be imposed to the s2
current error by the choice of via . Here, via can be chosen to be The shapes of the Bode plots are determined by (11), which
the linear PI function of the current error in order to minimize contains a double pole at the origin and a mid-frequency zero
the steady-state error [27], i.e., determined by Ki1 and Ki2 . Equation (11) also indicates that
 the ideal loop gain is independent of the operating condition,
via = −Ki1 ei − Ki2 ei dt (6) thus leading to robust steady-state performance. To account for
the nonideality in practical converters, an improved transfer
with Ki1 > 0 and Ki2 > 0. function G
can be formulated by
By substituting (6) into (5), the current error dynamics
Ki2 (1 + (sKi1 /Ki2 ))
becomes G
i = Hi (12)
 s2
dei
+ Ki1 ei + Ki2 ei dt = 0. (7) where Hi is a transfer function to account for the effects of the
dt
parasitic components, the additional low-pass filters, and the
With Ki1 and Ki2 being positive, the current error converges propagation delay of the control signals on the loop gain, i.e.,
to zero exponentially. By combining (4) and (6), the general
current control is given by sLe−sT d

 Hi =
 r(1 + (s/ωp1 ))(1 + (s/ωp2 ))(1 + (s/ωp3 ))2
1 diref
d¯ = vi − L − L Ki1 ei + Ki2 ei dt (8)
vo dt sL(1 − (Td s/2))
≈ .
which is illustrated in Fig. 4. The resulting current control (8) r(1+ (s/ωp1))(1+ (s/ωp2))(1 + (s/ωp3))2 (1 + (Td s/2))
can be implemented as an individual current control circuit. (13)

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2534 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009

Fig. 6. Bode plots of G
i with various combinations of control parameters. (a) K i 1 is varying with K i 2 fixed at 4 × 109 . (b) K i 2 is varying with K i 1 fixed at
6 × 104 .

In (13), the delay function e−sT d is approximated by (1 − Assume that the converter has a very high efficiency with
(Td s/2))/(1 + (Td s/2)) using the first-order Padé approxima- η ≈ 1. By power balance, the averaged diode current can be
tion with Td being the propagation delay. Variable ωp1 is the pole represented as
created by the resistance in series with the inductor, ωp1 = r/L,
Vi IL
and r = rL + Rs + do rds ON + (1 − do )rf ON , with rL being the iD (t) = sin2 ωt (14)
vo (t)
parasitic resistance of the inductor, Rs being the sensing re-
sistor, and rds ON and rf ON being the ON-time resistance of the where iD (t) is the diode current, Vi the peak input voltage,
MOSFET and the diode, respectively. Also, do is the nominal IL the peak inductor current, and vo (t) the output voltage. To
duty cycle, and ωp2 and ωp3 are the poles of the additional simplify the derivation, we assume that the output capacitor is
low-pass filters. large enough to guarantee a small line frequency ripple in the
Based on (12), Bode plots of the current loop gain can be output voltage, and the average of iD (t) over a rectifier line
computed. Fig. 6 shows the computed Bode plots with different cycle T /2 is approximated as
combinations of Ki1 and Ki2 . Other parameters are constant and
measured from the experimental circuit (see Fig. 12) with the IL Vi
iD = . (15)
following values: ωp1 = 1081 rad·s−1 , ωp2 = 396000 rad·s−1 , 2vo
ωp3 = 106 rad·s−1 , and Td = 1 µs. In Fig. 6(a), under a fixed
Here, we denote x as the average value of x(t) over a rectified
Ki2 , as Ki1 increases, the crossover frequency is slightly in-
line cycle.
creased, and the phase margin is increased by a larger amount. In
The averaged model of the voltage loop is represented by
Fig. 6(b), under a fixed Ki1 , as Ki2 increases, the crossover fre-
quency is slightly decreased, and the phase margin is decreased 1
v̇o (t) = (iD (t) − io (t)) (16)
by a larger amount. Hence, Ki1 and Ki2 can be selected ac- C
cording to the desired crossover frequency and phase margin to
where io (t) is the output current. Equation (16) is further aver-
ensure current loop stability and a satisfactory current-tracking
aged over the rectified line cycle to become
performance.


dvo 1 Vi IL
III. OUTER-LOOP VOLTAGE CONTROL = − io . (17)
dt C 2vo
A. Theoretical Derivation
Under the assumption of an ideal current loop, IL = Iref with
In this section, we demonstrate the generation of the outer- Iref being the peak reference current, which can be regarded as
loop voltage control using the same approach. In the control the control input of the voltage loop, i.e.,
derivation, we adopt the low-frequency model of the voltage

loop to account for the separation of time scale between the dvo 1 Vi Iref
= − io . (18)
voltage control and the current control. dt C 2vo

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CHU et al.: UNIFIED APPROACH FOR THE DERIVATION OF ROBUST CONTROL FOR BOOST PFC CONVERTERS 2535

Similarly, the voltage control can be regarded as a tracking

control problem in the resolution of the rectified line frequency.
Here, we denote the voltage error by
ev = Vref − vo (19)
where Vref is the constant reference voltage.
The dynamics of the voltage error is


dev dVref dvo 1 Vi Iref
= − = io − . (20)
dt dt dt C 2vo
The reference signal Iref is the amplitude of the reference cur-
rent, which is the control output generated by the outer loop.
Based on the feedback linearization, the error dynamics (20)
can be made linear if Iref is chosen as Fig. 7. Boost PFC converter with the derived outer-loop voltage control.
2vo
Iref = (io − Cvv a ) (21)
Vi
with vv a being an equivalent input. Thus, the resulting error
dynamics is simplified to
dev
= vv a . (22)
dt
Similar to the current loop derivation, vv a is chosen to be a linear
PI function for minimizing the steady-state error in the output
Fig. 8. (a) Block diagram of the voltage error dynamics under the derived
voltage, i.e., voltage control rule. (b) Block diagram in general form.

vv a = −Kv 1 ev − Kv 2 ev dt (23)
dynamics. Third, with the unity power factor already ensured
with Kv 1 > 0 and Kv 2 > 0. By substituting (23) into (22), the by the S/H function, more flexibility is offered to the design
voltage error dynamics becomes of the control parameters. Finally, maintaining fixed sampling
 instants enables easy prediction of the transient response wave-
dev
+ Kv 1 ev + Kv 2 ev dt = 0. (24) forms under the derived control rule, which will be shown in the
dt
subsequent sections. The drawback of using the S/H function
With Kv 1 and Kv 2 being positive, the voltage error converges is that it is noise sensitive, and the high-frequency noise in the
to zero exponentially. Finally, combining (21) and (23) gives the incoming signal needs to be filtered to avoid false triggering.
resulting voltage control rule Fig. 7 depicts the simplified schematic of the outer-loop voltage

 
2vo control rule with the S/H circuit included. Properties of the de-
Iref = io − C Kv 1 ev + Kv 2 ev dt . (25) rived control will be further explored in the following sections.
Vi
Again, (25) can be implemented as an individual voltage con-
troller. Alternatively, the resulting control can be implemented
by adding the load-current feedforward and the correspond- B. Frequency Response Analysis
ing functions (e.g. summation, inversion) in standard controller In this section, the frequency response of the voltage error
circuits, which become similar to some previously proposed dynamics is investigated. The dynamics of the voltage error
load-current feedforward schemes [21]. However, the direct im- (24) can be written as
plementation of the resulting control has a drawback that the 
dvo dvref
input current can be distorted by the line frequency ripple in the = + Kv 1 (vref − vo ) + Kv 2 (vref − vo )dt. (26)
feedfowarded load-current signal and feedbacked output voltage dt dt
signal. This problem can be solved by applying the sample-and- Due to the linear nature, (26) is readily expressed in the s-domain
hold (S/H) function to the control output signal such that the as
control output is sampled at every zero-crossing of the line volt-

age. This approach offers several advantages. First, unity power 1
svo = svref + (vref − vo ) Kv 1 + Kv 2 . (27)
factor is ensured even in the presence of the line frequency rip- s
ple in the feedforward and feedback signals. Second, according
In a likewise manner, the block diagram of (27) is depicted
to the Nyquist’s sampling theorem [29], the maximum band-
in Fig. 8, and the loop gain Gv is obtained as
width of the voltage loop is automatically limited to the line
frequency. This ensures the validity of our basic assumption, Kv 2 (1 + (sKv 1 /Kv 2 ))
which is the decoupling of the current loop and voltage loop Gv = . (28)
s2

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2536 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009

Fig. 9. Bode plots of G v with various combinations of control parameters. (a) K v 1 is varying with K v 2 fixed at 4.5 × 104 . (b) K v 2 is varying with K v 1 fixed
at 380.

The shapes of the Bode plots are determined by (28). Having It is worthy to note that since the S/H function samples the
a similar structure as Gi , Gv also contains a double pole at control output signal at the rectified line frequency, the hold time
the origin and a zero determined by Kv 1 and Kv 2 . Similarly, Th and therefore the resulting Bode plots vary with the operating
the robustness of the steady-state performance is reflected by line frequency. Such variation can be minimized by a conser-
the independence of the loop gain of the operating conditions, vative choice of Kv 1 and Kv 2 . For a cautious design, Kv 1 and
which is a straightforward result of the linearization of the er- Kv 2 should be designed based on the Bode plots corresponding
ror dynamics. To account for the nonidealities in the practical to the lowest operating frequency.
converter, an improved transfer function G
v can be formulated
by C. Transient Response
Kv 2 (1 + (sKv 1 /Kv 2 )) In addition to the steady-state performance and the system
G
v = Hv (29)
s2 stability, output transient response can be predicted based on
the mathematical derivation in Section III-A.
where Hv is the transfer function accounting for the effects of
Differentiating the voltage error’s dynamics (24) gives
the S/H function and the low-pass filter on the loop gain, i.e.,
1 d2 ev dev
Hv = (30) + Kv 1 + Kv 2 ev = 0 (31)
(1 + (s/ωp4 )) (1 + sTh ) dt2 dt
which is a homogeneous second-order differential equation gov-
where ωp4 is the pole frequency of the low-pass filter and Th is
erning the transient response of the voltage error. Solving (31)
the hold time of the S/H circuit, which approximately equals a
gives
half line cycle T /2.
Using (29), Bode plots of the voltage loop gain can be com- b1 (t) + b2 (t)
puted. Fig. 9 shows the computed Bode plots with different ev (t) = − √ (32)
2 D
combinations of Kv 1 and Kv 2 . Measured from the experimental
circuit (see Fig. 12), ωp4 ≈ 3 × 103 rad·s−1 and Th ≈ 1 ms. In where
Fig. 9(a), under a fixed Kv 2 , as Kv 1 increases, the crossover fre-
quency is slightly increased, and the phase margin is increased D = Kv21 − 4Kv 2 (33)
with a larger amount. In Fig. 9(b), under a fixed Ki1 , as Ki2
√ √
b1 (t) = e0.5(−K v 1 − D )t
(−Kv 1 ev (0) + Dev (0) − 2ėv (0))
increases, the crossover frequency is slightly increased, but the
phase margin is decreased drastically. Hence, Kv 1 and Kv 2 can (34)
be selected according to the desired crossover frequency and √ √
b2 (t) = e0.5(−K v 1 + D )t
(Kv 1 ev (0) + Dev (0) + 2ėv (0)).
phase margin to ensure voltage loop stability and satisfactory
regulation performance. (35)

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CHU et al.: UNIFIED APPROACH FOR THE DERIVATION OF ROBUST CONTROL FOR BOOST PFC CONVERTERS 2537

Fig. 10. Transient response of the error voltage with various combinations of control parameters. (a) K v 1 is varying with K v 2 fixed at 4.5 × 104 . (b) K v 2 is
varying with K v 1 fixed at 380.

Under the derived voltage control rule, the initial conditions

ev (0) and ėv (0) can be obtained from the steady-state condi-
tion with the instant of the load change being known. Using
(32), transient response waveforms of the error voltage can be
traced. For illustration, Fig. 10 shows the transient response
waveforms computed from (32) with different combinations of
Kv 1 and Kv 2 . Referring to Fig. 10(a), with Kv 2 fixed, increas-
ing Kv 1 results in increased damping of the error voltage wave-
form. However, excessively large Kv 1 results in overdamped re-
sponse with prolonged settling time, while an excessively small
Kv 1 results in oscillatory response with prolonged settling time.
Likewise, with Kv 1 fixed in Fig. 10(b), increasing Kv 2 results
in increased damping of the error waveform with longer set-
tling time, whereas decreasing Kv 2 results in less damping with
shorter settling time. Hence, the control parameters Kv 1 and
Kv 2 can be adjusted according to the desired transient response
waveforms, in conjunction with the Bode plots for stability and Fig. 11. Boost PFC converter with complete control scheme.
performance tradeoffs.
Although our study focuses on high-line-frequency applica-
tions for illustrating the current distortion issue, the derived schematic of the hardware prototype is shown in Fig. 12, and
control rules can also be applied to mains line frequency of 50 the key circuit parameters are shown in Table I.
or 60 Hz. In this case, no mandatory change is required for For implementation of the outer-loop voltage control, the
the design of the current loop. As for the voltage loop, since control voltage generated from the control circuit is obtained
the sampling frequency of the S/H circuit is lowered to 100 or from (25) with proper scaling
120 Hz, the corresponding pole or phase drop will move down 


to around 50 or 60 Hz. In order to ensure stability, the control β12
vv c = Vref io − C Kv 1 ev + Kv 2 ev dt (36)
parameters need to be adjusted using the Bode plots to allow β2
sufficient phase margin.
where β1 is the ratio of Vf f to Vi,rm s and β2 is the scaling
IV. EXPERIMENTAL RESULTS factor of the input voltage feeding into the multiplier. In our
experimental circuit, β1 = 0.02364 and β2 = 0.02516. vio is
A. Practical Implementation the sensed load current using a small resistor. vo is replaced by
Combining the derived inner-loop current control and the Vref for simplified implementation. The control voltage is fed
outer-loop voltage control, the complete robust control scheme into the S/H circuit with the sampling pulse generated by the
of the boost PFC converter is depicted in Fig. 11. A labora- zero-crossing detection circuit. The output of the S/H circuit
tory prototype of the boost PFC converter and the general con- is then fed into the multiplier circuit to produce the reference
trol circuit are constructed using analog devices. A simplified current for the cascading current loop.

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2538 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009

Fig. 12. Simplified schematics of the boost PFC converter with the derived control rules implemented as individual control circuitries.

TABLE I where Rv l , Rv z , and Cv z are the main components in the com-

CIRCUIT PARAMETERS USED IN THE EXPERIMENTS
pensation network of the voltage error amplifier (see Fig. 12).
The implementation of the current control rule can be simpli-
fied by employing the pulsewidth modulator (PWM) gain as the
dividing function [28]. This can be done by using a ramp with its
amplitude proportional to the output voltage. The amplitude is
denoted by β3 vo and β3 = 0.01852 in our experimental circuit.
Then, considering that the voltage across the sensing resistor Rs
is the input, the control voltage feeding into the modulator is a
modified version of (8) without the dividing function, i.e.,

The control parameters Kv 1 and Kv 2 can be related to the 

β3
component values by vic = Rs vi − Lv̇iref − L Ki1 (viref − Rs iL )
Rs
 
Rv z β2 β2
Kv 1 = Kv 2 = (37) + Ki2 (viref − Rs iL )dt (38)
Rv l CVref β12 Rv l Cv z CVref β12

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CHU et al.: UNIFIED APPROACH FOR THE DERIVATION OF ROBUST CONTROL FOR BOOST PFC CONVERTERS 2539

Fig. 13. Simplified schematics of the control circuit implementing conven-

tional ACM control using UCC3817.

where viref is the reference current profile generated by the

multiplier circuit. The control parameters Ki1 and Ki2 are
associated with the component values by
Riz Rs Rs
Ki1 = Kv 2 =
Ril Lβ3 Ril Ciz Lβ3
where Ril , Riz , and Ciz are the main components in the com-
pensation network of the current amplifier (see Fig. 12).
For comparison purposes, another control circuit implement-
ing the conventional ACM control using UCC3817 is con-
structed. The control circuit is applied to the same boost power
stage as in Fig. 12. The design of the compensation parameters
follows the conventional design approach [5] with the current
loop crossover frequency being one-tenth of the switching fre-
quency at around 10 kHz and a 30◦ phase margin. Likewise, the
voltage loop crossover frequency is one-tenth of the nominal
line frequency at around 50 Hz to ensure low distortion in the
input current. The phase margin is 45◦ . The simplified schematic
is shown in Fig. 13.
B. Current Loop Control Evaluation
A series of experiments have been conducted to evaluate the
performance of derived inner-loop current control. The selected
control parameters are Ki1 = 6 × 104 and Ki2 = 4 × 109 for
yielding consistent crossover frequency and phase margin with
the ACM control in the current loop gain. First, Bode plots of
the current loop gain are measured under the nominal conditions
with dc line voltage of 110 V. The results are plotted along with
the analytical results in Fig. 14. The measured data generally
match with the theoretical results. The accuracy of the loop
gain transfer function is thus verified. The discrepancies can be
attributed to the tolerance of the compensation components and
the presence of parasitic components in the power converter,
such as the output capacitance of the power MOSFET that has
not been accounted for in our derivation. In addition, it is worthy
to note that the obtained results correspond to the cases of an
Fig. 14. Experimental and theoretical Bode plots of the current loop gain with
K i 1 = 6 × 104 and K i 2 = 4 × 109 .
(39)
Fig. 15. Experimental waveforms resulting from the derived current control
at f = 800 Hz. Inductor current: 0.5 A/division; input voltage: 100 V/division.
ac line just when the line angle is 45◦ , 135◦ , 225◦ , and 315◦ ,
because only in these cases, the diode current averaged in a
switching period equals the load current, as it occurs when a dc
line is used.
Then, the derived control is compared with the conventional
ACM control in current-tracking performance. Under the de-
rived control, the zero-crossing distortion in the input current
is eliminated and high power factor is achieved even under the
condition of high line frequency and low power. For illustration,
Fig. 15 shows the current waveforms under the derived control
for a line frequency of 800 Hz.
Finally, the converter is tested for input current distortion
over a range of line frequency, input voltage, and output load-
ing. As a result, the current distortion is relatively low over
a range of line frequency from 300 to 800 Hz, input voltage
from 80 to 140 Vrm s , and output power from 30 to 120 W. For
illustration, Fig. 16 shows the resulting waveforms in some se-
lected operating conditions. The power factor is measured and
plotted along with that using the ACM control in Fig. 17. The

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2540 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009

Fig. 16. Experimental waveforms of inductor current and input voltage under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz, input
voltage of (c) 80 V and (d) 130 V, and output power of (e) 120 W and (f) 50 W. Inductor current: (a)–(d) and (f) 0.5 A/division and (c) 1 A/division. Input voltage:
100 V/division.

measured power factor resulting from the derived control is
higher than that from the conventional ACM control in all tested
conditions. It is rather consistent over the range of line fre-
quency, as shown in Fig. 17(a). Over the range of input voltage
and output power, although the measured power factor shows
some deviations in Fig. 17(b) and (c), the overall derivation is
smaller than that under the ACM control. The discrepancies are
mainly attributed to the occurrence of discontinuous conduc-
tion mode (DCM). Since the control rule is derived based on the
assumption of continuous conduction mode (CCM), the occur-
rence of DCM in extreme line and load conditions invalidates
our derivation and incurs control errors. The aforementioned
results confirm that the derived current control is capable of
maintaining a relatively high power factor with various operat-
ing conditions, and the robustness of the control performance is
verified.
C. Voltage Loop Control Evaluation
Similar experiments have been conducted to evaluate the per-
formance of outer-loop voltage control. The selected control
parameters are Kv 1 = 381 and Kv 2 = 4.51 × 104 for yielding
consistent crossover frequency and phase margin with the ACM
control in the voltage loop gain. First, Bode plots of the voltage
loop gain are measured under the dc line voltage of 110 V. The
measured Bode plots are plotted along with the analytical results
in Fig. 18. The measured data agree with the theoretical results
and verify the loop gain characteristic. The deviations can be
attributed to the components’ tolerance and the round-off error
of the S/H function.
Second, the derived voltage control is compared with the
conventional ACM control in transient response performance.
The output current is stepping from 0.4 to 0.14 A. Fig. 19
shows the resulting waveforms. Under the derived control,
the transient response improves with the overshoot ampli-
tude reduced from 5 to 2.5 V and the settling time short-
ened from 25 to 20 ms. The results verify the capability of
the derived control of improving the transient response perfor-
mance. It should be noted that the aforementioned configura-
tion is not optimal for transient response because the crossover
frequency of the voltage loop is set at only 50 Hz for consistency
with the ACM design. A shorter recovery time can be achieved

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CHU et al.: UNIFIED APPROACH FOR THE DERIVATION OF ROBUST CONTROL FOR BOOST PFC CONVERTERS 2541

Fig. 17. Power factor measured under the variations of (a) line frequency, (b) input voltage, and (c) output power.

by increasing the crossover frequency with other combinations

Fig. 18. Experimental and theoretical Bode plots of the voltage loop gain with
control parameters K v 1 = 381 and K v 2 = 4.51 × 104 .
of Kv 1 and Kv 2 , such as the examples in Fig. 20(c) and (d),
which will be discussed next.
Third, the derived voltage control is examined in terms of
the transient response waveforms with different combinations
of Kv 1 and Kv 2 . The resulting transient response waveforms
match with the predicted waveforms using (32). Fig. 20 shows
some illustrative waveforms with some selected combinations
of Kv 1 and Kv 2 . The results verify the accuracy of the de-
rived error dynamics and the predicted effects of the control
parameters.
Finally, the converter is tested over a range of input voltage
and loading condition for output transient response. It turns out
that as the input voltage varies from 80 to 140 Vrm s , and the
voltage overshoot and the settling time are consistent at around
2.5 V and 20 ms, respectively. For illustration, Fig. 21(a) and (b)
shows the transient waveforms at some selected input voltages.
As the loading condition varies, although the voltage overshoot
changes with the load step, the settling time remains approx-
imately constant at around 20 ms. Fig. 21(c) and (d) shows
the transient response waveforms at some selected loading con-
ditions. The aforementioned results confirm the robustness of
the derived voltage control in the variations of line voltage and
loading condition.

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2542 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009

Fig. 19. Transient response waveforms under (a) the ACM control and (b) the derived voltage control. Output voltage: (a) 2 V/division and (b) 1 V/division.
Output current for both (a) and (b): 0.2 A/division. Time scale: 10 ms/division.

Fig. 20. Transient response waveforms with various combinations of K v 1 and K v 2 . (a) K v 1 = 380 and K v 2 = 4.5 × 104 . (b) K v 1 = 220 and K v 2 =
4.5 × 104 . (c) K v 1 = 510 and K v 2 = 4.5 × 104 . (d) K v 1 = 380 and K v 2 = 2.5 × 104 . Output voltage: 1 V/division. Output current: 0.2 A/division. Time
scale: 10 ms/division.

Fig. 21. Transient response waveforms at various operating conditions: line voltage at (a) 140 Vrm s and (b) 80 Vrm s ; stepping load current of (c) 0.4–0.14 A
and (d) 0.2–0.14 A. Output voltage: 1 V/division. Output current: 0.2 A/division. Time scale: 10 ms/division.

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CHU et al.: UNIFIED APPROACH FOR THE DERIVATION OF ROBUST CONTROL FOR BOOST PFC CONVERTERS
V. CONCLUSION
In this paper, we have presented a unified approach for sys-
tematic derivation of robust control rules for the inner current
loop and the outer voltage loop of the boost PFC converter. By
eliminating the nonlinearity and the dependency of the error dy-
namics on the input disturbance, the derivation approach leads
to nonlinear control rules that improve the converter’s steady-
state and transient response performances. Moreover, the control
performance is consistent with the variations of operation con-
dition. The derived control rules are readily implemented using
analog devices. The control parameters can be designed accord-
ing to frequency response analysis to ensure system stability
and a satisfactory steady-state performance. They can also be
adjusted for the desired transient response waveforms. Based
on experimental data, the effectiveness and the robustness of
the derived control rules are verified. The derived current con-
trol achieves low input current distortion, and the control per-
formance is consistent with the variations in line frequency,
line voltage, and loading condition. The derived voltage control
achieves improved transient response, and the control perfor-
mance is robust with the variations of line voltage and loading
condition.
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Grace Chu (S’06) received the B.Eng. degree (with
first-class honors) in 2002 from Hong Kong Polytech-
nic University, Kowloon, Hong Kong, where she is
currently working toward the Ph.D. degree in the area
of modeling, analysis, and design of power-factor-
correction power supplies.
From 2002 to 2005, she was an Engineer at Astec
Custom Power, Hong Kong.
Ms. Chu received a number of scholarships and
prizes, including the Simatelex Foundation Schol-
arship in 1999 and the Outstanding Student of the
Engineering Faculty in 2000.
2544
Chi K. Tse (M’90–SM’97–F’06) received the B.Eng.
(Hons.) degree (with first-class honors) in electrical
engineering and the Ph.D. degree from the University
of Melbourne, Melbourne, Vic., Australia, in 1987
and 1991, respectively.
He is currently the Chair Professor and the
Head of the Department of Electronic and Informa-
tion Engineering, Hong Kong Polytechnic University,
Kowloon, Hong Kong. His current research interests
include power electronics, complex networks, and
nonlinear systems. He is the author of Linear Cir-
cuit Analysis (London, U.K.: Addison-Wesley, 1998) and Complex Behavior of
Switching Power Converters (Boca Raton, FL: CRC Press, 2003), and the coau-
thor of Chaos-Based Digital Communication Systems (Heidelberg, Germany:
Springer-Verlag, 2003) and Chaotic Signal Reconstruction With Applications to
Chaos-Based Communications (Singapore: World Scientific, 2007). He is the
coholder of a U.S. patent and two pending patents. He is an Associate Editor
for the International Journal of Systems Science and International Journal of
Circuit Theory and Applications, and a Guest Editor of a few other journals.
Prof. Tse was awarded the L.R. East Prize by the Institution of Engineers,
Australia, in 1987, the IEEE TRANSACTIONS ON POWER ELECTRONICS Prize Pa-
per Award in 2001, and the International Journal of Circuit Theory and Appli-
cations Best Paper Award in 2003. In 2007, he was awarded the Distinguished
International Research Fellowship by the University of Calgary, Canada. At
Hong Kong Polytechnic University, he received twice the President’s Award for
Achievement in Research, the Faculty’s Best Researcher Award, the Research
Grant Achievement Award, and a few other teaching awards. From 1999 to 2001,
he was an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYS-
TEMS PART I—FUNDAMENTAL THEORY AND APPLICATIONS. Since 1999, he has
been an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS.
During 2005, he was an IEEE Distinguished Lecturer. He is currently the Editor-
in-Chief of the IEEE CIRCUITS AND SYSTEMS SOCIETY NEWSLETTER, and the
Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART
I—REGULAR PAPERS and the IEEE CIRCUITS AND SYSTEMS MAGAZINE.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 11, NOVEMBER 2009
Siu-Chung Wong (M’02–SM’09) received the B.Sc.
degree in physics from the University of Hong Kong,
Hong Kong, in 1986, the M.Phil. degree in electron-
ics from the Chinese University of Hong Kong, Hong
Kong, in 1989, and the Ph.D. degree from the Univer-
sity of Southampton, Southampton, U.K., in 1997.
He is currently an Assistant Professor in the De-
partment of Electronic and Information Engineering,
Hong Kong Polytechnic University, Kowloon, Hong
Kong. His current research interests include model-
ing of power converters, nonlinear analysis of power
electronics, LED lighting systems, automobile lighting systems, and Internet
traffic analysis.
Dr. Wong is a member of the Electrical College, The Institution of Engineers,
Australia.
Siew-Chong Tan (S’01–M’05) received the B.Eng.
(with honors) and M.Eng. degrees in electrical and
computer engineering from the National University
of Singapore, Singapore, in 2000 and 2002, respec-
tively, and the Ph.D. degree from Hong Kong Poly-
technic University, Kowloon, Hong Kong, in 2005.
From 2005 to 2008, he was a Research Associate,
a Postdoctoral Fellow, and then, a Lecturer in the
Department of Electronic and Information Engineer-
ing, Hong Kong Polytechnic University, where he is
currently an Assistant Professor. His current research
interests include nonlinear control of power converters, design and modeling of
switched-capacitor converters, and LED driver’s design.