module 3iNAND (iA, iB, iC, oY);

input iA, iB, iC;

output oY;

wire oY;
wire tP,tQ;
assign tP = iA&iB;
assign tQ = tP&iC;
assign oY = ~ tQ;

endmodule

module 3iNAND_tb();
reg dA, dB, dC'
wire mY;

integer loop;

initial
begin
for(loop=0; loop<7; loop=loop+1)
begin
{dA, dB, dC} = loop;
#10;
end
end

logic 3iNAND example (dA, dB, dC, mY);

endmodule
==================================module=======================================

module prac3.1 (iA, iB, iC, oD);

input iA, iB, iC;
output oD;

wire oD;
wire tP, tQ;

assign tP = ~(iA&iB);
assign tQ = iA&iB&~iC;
assign oD = tP | tQ;
endmodule
================================testbench==========================================
module prac3_1module_tb();
reg iA, iB, iC;
wire oD;

integer loop;
initial
begin
for(loop=0; loop<8; loop=loop+1)
begin
{iA, iB, iC} = loop;
#10;
end
end

logic prac3.1 contoh(iA, iB, iC, oD);

endmodule