TMS 6713 Board (I) (Ii) Instructions Set & Interrupts. (Iii) Addressing Modes (Iv) C Code Composer Studio. (V) Circular Buffering

AICTE Sponsored FDP On ADSP
TOPICS TO BE DISCUSSED
National Institute of Science & Technology
TMS 6713 Board
(i) Architecture.
(ii) Instructions Set & Interrupts.
(iii) Addressing Modes
(iv) C Code Composer Studio.
(v) Circular Buffering.
PRESENTED BY SURUCHI KUMARI [1]

Introduction
The TMS320C6000 DSP processor family has

been introduced by Texas Instruments to meet high
performance demands in signal processing
applications, to deliver speed.
They are designed for million instructions per

second (MIPS) intensive applications such as 3G
wireless, DSL/cable modems and digital imaging.

Processing of Digital Signal

 The processing of a digital signal can be

implemented on various platforms such as a
DSP processor, a customized Very Large
Scale Integrated (VLSI) circuit, or a general
purpose microprocessor.
 Differences between a DSP and a single function
VLSI implementation
1. Application flexibility.
2.Cost-effective.

Processing of Digital Signal

Differences between a DSP and Microprocessors
 Instruction sets of DSP are smaller and optimized for signa

processing operations .
Allow specialized addressing modes circular addressing.
In DSP processors, it is possible to perform several
accesses to memory in a single instruction cycle .
DSP possess appropriate peripherals that allow efficient
input/output (I/O) interfacing to other devices.

A DSP SYSTEM
There are many reasons to

process an analog signal in a
digital fashion .
The main reason is that

digital processing allows
programmability.
Digital circuits provide a

more stable and tolerant
output than analog circuits .


Features
The DSK comes with a full compliment of on-board

devices that suit a wide variety of application environments.
Key features include:
1. A Texas Instruments TMS320C6713 DSP operating at

225 MHz.
2. An AIC23 stereo codec .
3. 16 Mbytes of synchronous DRAM .
4. 512 Kbytes of non-volatile Flash memory (256 Kbytes
usable in default configuration) .

Features
 4 user accessible LEDs and DIP(dual inline package) switches .
 Software board configuration through registers implemented in

CPLD .
 Configurable boot options.
 Standard expansion connectors for daughter card use
 JTAG emulation through on-board JTAG emulator with USB

host interface or external emulator .
 Single voltage power supply (+5V).

THE BLOCK DIAGRAMS OF THE GENERIC C6X


THE BLOCK DIAGRAMS OF THE GENERIC C64X


THE BLOCK DIAGRAMS OF THE GENERIC C6711

ARCHITECTURES
 The C6x CPU consists of eight functional units divided

into two sides: (A) and (B).
Each side has :
 a .M unit (used for multiplication operation).

 a .L unit (used for logical and arithmetic operations).
 a .S unit (used for branch, bit manipulation and
arithmetic operations)

ARCHITECTURES
 a .D unit (used for loading, storing and arithmetic

operations).
 Some instructions such as ADD can be done by

more than one unit.
 There are sixteen 32-bit registers associated with

each side. Interaction with the CPU must be done
through these registers

Functional unit

Required Software/Hardware
The software tool needed to generate TMS320C6x

executable files is called Code Composer Studio
(CCS).
CCS incorporates the assembler, linker, compiler,
simulator, and debugger utilities.
In the absence of a target board, which allows one to
run an executable file on an actual C6x processor, the
simulator can be used to verify code functionality by
using data already stored in a data file.

 When using the simulator, an Interrupt Service

Routine (ISR) cannot be used to read in signal
samples from a signal source.
 To be able to process signals in real-time on an

actual C6x processor, a DSP Starter Kit
(DSK) or an Evaluation Module (EVM) board
is needed for code development.

 A DSK board can easily be connected to a PC host

through its parallel or USB port.
 The signal interfacing with the DSK board is done

through its two standard audio jacks.

General Purpose Register Files

 The CPU contains two general purpose register files A and B.
These can be used for data or as data address pointers.
Each file contains sixteen 32-bit registers (A0-A15 for file A and B0-B15 for
file B).
The registers A1, A2, B0, B1, B2 can also be used as condition registers. The
registers A4-A7 and B4-B7 can be used for circular addressing.
These registers provide 32-bit and 40-bit fixed-point data.
The 32-bit data can be stored in any register.
For 40-bit data, processor stores least significant 32 bits in an even register
and remaining 8 bits in upper (odd) register.

Internal buses
 The internal buses consist of a 32-bit program address

bus, a 256-bit program data bus accommodating eight 32-
bit instructions, two 32-bit data address buses (DA1 and
DA2), two 32-bit (64-bit for C64 version) load data buses
(LD1 and LD2), and two 32-bit (64-bit for the floating-
point version) store data buses (ST1 and ST2).
 There are a 32-bit DMA data and a 32-bit DMA address

bus.
 The external, memory is accessed through a 20-bit

address bus and a 32-bit data bus.

C6x Internal Buses


Peripherals on C6x
 The peripherals on a typical C6x processor include External

Memory Interface (EMIF), DMA, Boot Loader,
Multichannel Buffered Serial Port (McBSP), Host Port
Interface (HPI), Timer, and Power Down unit.
 EMIF provides the necessary timing for accessing external

memory.
 DMA allows the movement of data from one place in

memory to another place without interfering with the CPU
operation.

Peripherals on C6x
Boot Loader boots the loading of code from off-chip

memory or HPI to internal memory.
 McBSP provides a high-speed multi-channel serial

communication link.
HPI allows a host to access internal memory.

Timer provides two 32-bit counters.
Power Down unit is used to save power for durations

when the CPU is inactive.
Pipelined CPU
 In general, it takes several steps to perform an

instruction.
 Basically, these steps are fetching, decoding,
and execution.
 If these steps are done serially, not all of the
resources on the processor, such as multiple
buses or functional units, are fully utilized.

Pipelined CPU
In order to increase throughput, DSP CPUs are

designed to be pipelined.
 Figure illustrates the difference in processing time for

three instructions executed on a serial or non-pipelined
and a pipelined CPU.
 As can be seen, a pipelined CPU requires fewer clock

cycles to complete the same number of instructions.

Pipelined CPU

Stages of Pipelining
On the C6x processor, fetching consists of four

phases, each requiring a clock cycle.
These include generate fetch address (denoted byF1),
send address to memory (F2), wait for data (F3), and
read opcode from memory (F4).
Decoding consists of two phases, each requiring a
clock cycle.
These are dispatching to appropriate functional units
(denoted by D1), and decoding (D2).

Stages of pipelining
Due to the delays associated with the instructions

multiply (MPY − 1 delay), load (LDx − 4 delays), and
branch (B − 5 delays), the execution step may consist of
up to six phases (denoted by E1 through E6),
accommodating a maximum of 5 delays.
Hence, as shown in Figure 3-8, the F step consists of

four, the D step of two, and the E step of six possible
substeps, or phases.

Stages of pipelining
When the outcome of an instruction is used

by the next instruction, an appropriate
number of NOPs (no operation or delay) must
be added after multiply (one NOP),load (four
NOPs/or NOP 4), and branch (five NOPs/or
NOP 5) instructions in order to allow the
pipeline to operate properly

Stages of Pipelining

VelociTI
The C6x architecture is based on the very

long instruction word (VLIW) architecture.
In such an architecture, several instructions

are captured and processed simultaneously.
This is referred to as a fetch packet (FP).

C6x Fetch Packet


VelociTI
The C6x uses VLIW, allowing eight

instructions to be captured simultaneously from
on-chip memory onto its 256-bit wide program
data bus.
The original VLIW architecture has been

modified by TI to allow several so-called
execute packets (EP) to be included within the
same Fetch Packet.
VelociTI
 An EP constitutes a group of parallel instructions.
 Parallel instructions are indicated by double pipe symbols ( || ),

and, as the name implies, they are executed together, or in
parallel.
 Instructions within an EP move together through every stage of

the pipeline. This VLIW modification is called VelociTI.
 Compared with VLIW, VelociTI reduces code size and

increases performance when instructions reside off-chip.

Memory Management
 The external memory used by a DSP processor can be either

static or dynamic.
 Static memory (SRAM) is faster than dynamic memory

(DRAM), but it is more expensive, since it takes more space
on silicon.
 DRAMs also need to be refreshed periodically.
 A good compromise between cost and performance is

achieved by using SDRAM (Synchronous DRAM).
 Synchronous memory requires clocking, as compared to

asynchronous memory, which does not.
Memory Management
 The address bus is 32 bits wide, the total memory

space consists of 2^32 =4 G bytes.
 This space is divided, according to a memory map,
into the
1. Internal program memory (PMEM)
2. Internal data memory (DMEM)
3. Internal peripherals.
4. External memory spaces named CE0, CE1, CE2, and
CE3.
 There are two memory map configurations: memory
map 0 and memory map 1.

Memory Management
C6X Memory map 0 C6X Memory map 1

Linking
Linking places code, constant, and

variable sections into appropriate locations
in memory.
Also, it combines several .obj object files

into the final executable .out output file.

TIMERS
The C62x/C67x has two 32-bit general-purpose timers

that can be used to:
1. Time events .
2. Count events.
3. Generate pulses .
4. Interrupt the CPU.
5. Send synchronization events to the DMA
controller.

TIMERS
When an internal clock is provided, the timer

generates timing sequences to trigger peripheral or
external devices such as DMA controller or A/D
converter respectively.
When an external clock is provided, the timer can

count external events and interrupt the CPU after a
specified number of events.

TIMERS
The timer works in one of the two signaling

modes depending on whether clocked by an internal
or an external source.
The timer has an input pin (TINP) and an output

pin (TOUT).
The TINP pin can be used as a general purpose

input, and the TOUT pin can be used as a general-
purpose output.
External Memory Interface

 The external memory interface (EMIF) supports an

interface to several external devices, allowing additional
data and program memory space beyond that which is
included on-chip.
 The types of memories supported include:
• Synchronous burst SRAM (SBSRAM)
• Synchronous DRAM (SDRAM)
• Asynchronous devices, including asynchronous
SRAM, ROM, and FIFO’s.
 The EMIF provides highly programmable timings to
these interfaces.

External shared-memory devices

 There are two data ordering standards in byte-addressable

microcontrollers exist:
1. Little-endian ordering, in which bytes are ordered from right to

left, the most significant byte having the highest address.
2. Big-endian ordering, in which bytes are ordered from left to
right, the most significant byte having the lowest address.
 The EMIF reads and writes both big- and little-endian devices.
 There is no distinction between ROM and asynchronous
interface.
 For all memory types, the address is internally shifted to
compensate for memory widths of less than 32 bits.
CONCLUSION
The choice of a DSP processor to implement

an algorithm in real-time is application
dependent.
There are many factors that influence this
choice.
These
factors include, cost, performance, power
consumption, ease-of-use, time-to-market, and
integration/interfacing capabilities.

TMS 6713 Board (I) (Ii) Instructions Set & Interrupts. (Iii) Addressing Modes (Iv) C Code Composer Studio. (V) Circular Buffering

Transféré par

Informations du document

Description originale:

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

TMS 6713 Board (I) (Ii) Instructions Set & Interrupts. (Iii) Addressing Modes (Iv) C Code Composer Studio. (V) Circular Buffering

Transféré par

Droits d'auteur :

Formats disponibles

AICTE Sponsored FDP On ADSP

TMS 6713 Board

PRESENTED BY SURUCHI KUMARI [1]

The TMS320C6000 DSP processor family has

They are designed for million instructions per

PRESENTED BY SURUCHI KUMARI [2]

Processing of Digital Signal

 The processing of a digital signal can be

PRESENTED BY SURUCHI KUMARI [3]

Processing of Digital Signal

Differences between a DSP and Microprocessors

 Instruction sets of DSP are smaller and optimized for signa

PRESENTED BY SURUCHI KUMARI [4]

There are many reasons to

The main reason is that

Digital circuits provide a

PRESENTED BY SURUCHI KUMARI [6]

PRESENTED BY SURUCHI KUMARI [7]

The DSK comes with a full compliment of on-board

1. A Texas Instruments TMS320C6713 DSP operating at

PRESENTED BY SURUCHI KUMARI [8]

 4 user accessible LEDs and DIP(dual inline package) switches .

 Software board configuration through registers implemented in

 Configurable boot options.

 Standard expansion connectors for daughter card use

 JTAG emulation through on-board JTAG emulator with USB

 Single voltage power supply (+5V).

THE BLOCK DIAGRAMS OF THE GENERIC C6X

PRESENTED BY SURUCHI KUMARI [10]

THE BLOCK DIAGRAMS OF THE GENERIC C64X

PRESENTED BY SURUCHI KUMARI [11]

PRESENTED BY SURUCHI KUMARI [12]

 The C6x CPU consists of eight functional units divided

 a .M unit (used for multiplication operation).

PRESENTED BY SURUCHI KUMARI [13]

 a .D unit (used for loading, storing and arithmetic

 Some instructions such as ADD can be done by

 There are sixteen 32-bit registers associated with

PRESENTED BY SURUCHI KUMARI [14]

PRESENTED BY SURUCHI KUMARI [15]

The software tool needed to generate TMS320C6x

PRESENTED BY SURUCHI KUMARI [16]

 When using the simulator, an Interrupt Service

 To be able to process signals in real-time on an

PRESENTED BY SURUCHI KUMARI [17]

 A DSK board can easily be connected to a PC host

 The signal interfacing with the DSK board is done

PRESENTED BY SURUCHI KUMARI [18]

General Purpose Register Files

 The CPU contains two general purpose register files A and B.

These can be used for data or as data address pointers.

These registers provide 32-bit and 40-bit fixed-point data.

The 32-bit data can be stored in any register.

PRESENTED BY SURUCHI KUMARI [19]

 The internal buses consist of a 32-bit program address

 There are a 32-bit DMA data and a 32-bit DMA address

 The external, memory is accessed through a 20-bit

PRESENTED BY SURUCHI KUMARI [20]

C6x Internal Buses

PRESENTED BY SURUCHI KUMARI [21]

 The peripherals on a typical C6x processor include External

 EMIF provides the necessary timing for accessing external