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Lab Report 1

Digital System Design Lab

Name: Asghar Ismail

18-CP-01

Section: Alpha

Department: Computer Engineering

Submitted To: Sir Naveed Baloch

Due Date: 12th April 2021


Lab Tasks:

Question no 1: Implement all the codes given in the manual in


modelsim.

Half Adder

Code: Test bench :


module HalfAdder(HA_SUM , HA_COUT , module HalfAdder_tb;
HA_IN1 , HA_IN2);
reg HA_IN1 , HA_IN2;
output HA_SUM, HA_COUT; wire HA_SUM , HA_COUT ;
input HA_IN1 , HA_IN2;
HalfAdder DUT ( .HA_SUM(HA_SUM) ,
xor x1(HA_SUM , HA_IN1 , HA_IN2); .HA_COUT(HA_COUT) , .HA_IN1(HA_IN1) ,
and a1(HA_COUT , HA_IN1 , HA_IN2); .HA_IN2(HA_IN2));

endmodule initial
begin
HA_IN1 = 1'b0 ; HA_IN2 = 1'b0 ;
#10 HA_IN1 = 1'b0 ; HA_IN2 = 1'b1 ;
#10 HA_IN1 = 1'b1 ; HA_IN2 = 1'b0 ;
#10 HA_IN1 = 1'b1 ; HA_IN2 = 1'b1 ;

end
endmodule

Output:
Full Adder

Code : Test bench :


module FullAdder(FA_SUM , FA_COUT , FA_IN1 , module FullAdder_tb;
FA_IN2 , FA_CIN); reg FA_IN1 , FA_IN2 , FA_CIN;
wire FA_SUM , FA_COUT;
output FA_SUM, FA_COUT;
input FA_IN1 , FA_IN2 , FA_CIN; reg FA_IN1 , FA_IN2 , FA_CIN;
wire W_HA0HA1 , W_HA0O1 , W_HA1O1; wire FA_SUM , FA_COUT;

HalfAdder HA0(.HA_SUM(W_HA0HA1) , FullAdder DUT (.FA_SUM(FA_SUM) ,


.HA_IN1(FA_IN1) ,.HA_IN2(FA_IN2), .FA_COUT(FA_COUT) , .FA_IN1(FA_IN1)
.HA_COUT(W_HA0O1) ); , .FA_IN2(FA_IN2) , .FA_CIN(FA_CIN));
initial
HalfAdder HA1(.HA_SUM(FA_SUM) , begin
.HA_IN1(W_HA0HA1) ,.HA_IN2(FA_CIN),
.HA_COUT(W_HA1O1) ); FA_IN1 = 1'b0 ; FA_IN2 = 1'b0 ; FA_CIN = 1'b0;
#10 FA_IN1 = 1'b0 ; FA_IN2 = 1'b0 ; FA_CIN = 1'b1;
or O1(FA_COUT , W_HA0O1 , W_HA1O1); #10 FA_IN1 = 1'b0 ; FA_IN2 = 1'b1 ; FA_CIN = 1'b0;
#10 FA_IN1 = 1'b0 ; FA_IN2 = 1'b1 ; FA_CIN = 1'b1;
endmodule #10 FA_IN1 = 1'b1 ; FA_IN2 = 1'b0 ; FA_CIN = 1'b0;
#10 FA_IN1 = 1'b1 ; FA_IN2 = 1'b0 ; FA_CIN = 1'b1;
#10 FA_IN1 = 1'b1 ; FA_IN2 = 1'b1 ; FA_CIN = 1'b0;
#10 FA_IN1 = 1'b1 ; FA_IN2 = 1'b1 ; FA_CIN = 1'b1;

end
endmodule

Output:
Decoder:

Code: Testbench :
module Decoder_2x4 (D0 , D1 , D2 , D3 , A , B);
module Decoder_2x4_tb;
input A,B;
output D0,D1 ,D2,D3; reg A,B;
reg D0,D1 ,D2,D3; wire D0 , D1 ,D2,D3;

always@(A or B) Decoder_2x4 DUT (.D0(D0) , .D1(D1) ,


if(A == 0 && B== 0) .D2(D2) ,.D3(D3) , .A(A) ,.B(B));
begin D0 = 1 ; D1 = 0 ; D2 = 0 ; D3 =0; end
else if(A == 0 && B== 1) initial
begin D0 = 0 ; D1 = 1 ; D2 = 0 ; D3 =0; end begin
else if(A == 1 && B== 0)
begin D0 = 0 ; D1 = 0 ; D2 = 1 ; D3 =0; end A = 1'b0 ; B= 1'b0;
else #10 A = 1'b0 ; B= 1'b1;
begin D0 = 0 ; D1 = 0 ; D2 = 0 ; D3 =1; end #10 A = 1'b1 ; B= 1'b0;
#10 A = 1'b1 ; B= 1'b1;
endmodule
end
endmodule

Output:
Multiplexer :

????

Question no 3: Implement 8-bit Full adder and verify the result.

Eight-bit Adder:

CODE: Test bench:


module EightBitAdder(SUM ,CARRY ,IN1 , IN2 , module EightBitAdder_tb ;
CIN);
output[7:0]SUM ; reg [7:0] IN1 ;
output CARRY; reg [7:0] IN2 ;
input[7:0]IN1,IN2; wire CARRY ;
input CIN; wire [7:0] SUM ;
wire [6:0] W_C; reg CIN ;
EightBitAdder
FullAdder FA0 (.FA_SUM(SUM[0]) , DUT (
.FA_IN1(IN1[0]) , .FA_IN2(IN2[0]) , .IN1 (IN1 ) ,
.FA_COUT(W_C[0]),.FA_CIN(CIN)); .IN2 (IN2 ) ,
FullAdder FA1 (.FA_SUM(SUM[1]) , .CARRY (CARRY ) ,
.FA_IN1(IN1[1]), .FA_IN2(IN2[1]) , .SUM (SUM ) ,
.FA_COUT(W_C[1]),.FA_CIN(W_C[0])); .CIN (CIN ) );
FullAdder FA2 (.FA_SUM(SUM[2]) ,
.FA_IN1(IN1[2]) , .FA_IN2(IN2[2]) ,
.FA_COUT(W_C[2]),.FA_CIN(W_C[1]));
FullAdder FA4 (.FA_SUM(SUM[3]) , initial //Test patterns
.FA_IN1(IN1[3]) , .FA_IN2(IN2[3]) , begin
.FA_COUT(W_C[3]),.FA_CIN(W_C[2])); IN1=8'd1; IN2=8'd1; CIN=0'b0;//testing normal
FullAdder FA5 (.FA_SUM(SUM[4]) , case no.
.FA_IN1(IN1[4]) , .FA_IN2(IN2[4]) , #10 IN1=8'd5; IN2=8'd4; CIN =1'b1;
.FA_COUT(W_C[4]),.FA_CIN(W_C[3])); #10 CIN =1'b1;
FullAdder FA6 (.FA_SUM(SUM[5]) ,
.FA_IN1(IN1[5]) , .FA_IN2(IN2[5]) , end
.FA_COUT(W_C[5]),.FA_CIN(W_C[4])); endmodule
FullAdder FA7 (.FA_SUM(SUM[6]) ,
.FA_IN1(IN1[6]) , .FA_IN2(IN2[6]) ,
.FA_COUT(W_C[6]),.FA_CIN(W_C[5]));
FullAdder FA8 (.FA_SUM(SUM[7]) ,
.FA_IN1(IN1[7]) , .FA_IN2(IN2[7]) ,
.FA_COUT(CARRY),.FA_CIN(W_C[6]));

endmodule
Output:
Question no 4: Implement 4-bit, 2X1 multiplexer in behavioral
modeling.

4-BIT 2X1 MUX

CODE: TEST BENCH :


module Mux_2x1_4Bit(MUX_OUT , MUX_IN1 , module Mux_2x1_4Bit_tb ;
MUX_IN2, MUX_SEL); reg MUX_SEL ;
reg [3:0] MUX_IN1 ;
output [3:0] MUX_OUT; wire [3:0] MUX_OUT ;
input [3:0] MUX_IN1 , MUX_IN2 ; reg [3:0] MUX_IN2 ;
input MUX_SEL; Mux_2x1_4Bit
reg [3:0] MUX_OUT;
DUT ( .MUX_SEL (MUX_SEL ) , .MUX_IN1
always@(MUX_IN1 , MUX_IN2 , MUX_SEL) (MUX_IN1 ) , .MUX_OUT (MUX_OUT )
begin .MUX_IN2 (MUX_IN2 ) );
if(MUX_SEL == 0) initial
MUX_OUT = MUX_IN1; begin
else MUX_IN1 = 4'b0000 ; MUX_IN2 = 4'b0000 ;
#10 MUX_IN1 = 4'b0001 ; MUX_IN2 = 4'b0010
MUX_OUT = MUX_IN2; ; MUX_SEL = 1'b0;
end #10 MUX_IN1 = 4'b0001 ; MUX_IN2 = 4'b0010
endmodule ; MUX_SEL = 1'b1;
End endmodule

Output:
Question no 5: Design a BCD to seven segment decoders. The
purpose of the decoder is to translate a 4-Bit Binary number to
seven-bit code which can be displayed on the seven segments.

BCD_7_SEG_DECODER

Code: TEST BENCH :


module BCD_7_SEG_DECODER(bcd,seven_seg); module BCD_7_SEG_DECODER_tb ;
input [3:0] bcd; reg [3:0] bcd ;
output reg [6:0] seven_seg; wire [6:0] seven_seg ;
BCD_7_SEG_DECODER
always @(bcd) DUT ( .bcd (bcd ) , .clk (clk ) ,
begin .seven_seg (seven_seg ) );
case (bcd)
4'b0000 : begin seven_seg = 7'b1111110; end initial
4'b0001 : begin seven_seg = 7'b0110000; end begin
4'b0010 : begin seven_seg = 7'b1101101; end // Initialize Inputs
4'b0011 : begin seven_seg = 7'b1111001; end bcd = 4'b0000;
4'b0100 : begin seven_seg = 7'b0110011; end #10bcd = 4'b0001;
4'b0101 : begin seven_seg = 7'b1011011; end #10bcd = 4'b0010;
4'b0110 : begin seven_seg = 7'b1011111; end #10bcd = 4'b0011;
4'b0111 : begin seven_seg = 7'b1110000; end #10bcd = 4'b0100;
4'b1000 : begin seven_seg = 7'b1111111; end #10bcd = 4'b0101;
4'b1001 : begin seven_seg = 7'b1110011; end #10bcd = 4'b0110;
#10bcd = 4'b1000;
default : begin seven_seg = 7'b0000000; end #10bcd = 4'b1001;
endcase end
end endmodule
endmodule
Output:
Question no 6: Write Verilog code for the even parity generator
circuit given in Figure p2-1a. Write code at gate level and data
flow level. Also write test bench for the design.

Even Parity Check:

Code : Test bench :

module Even_Parity ( P , A0, A1 , A2); module Even_Parity_tb ;

output P; wire P ; reg A0 ; reg A1 ; reg A2 ;


input A0 , A1 ,A2; Even_Parity DUT ( .P (P ) , .A0 (A0 ) , .A1
wire P_A0A1; (A1 ) , .A2 (A2 ) );

xor P1(P_A0A1 , A0 ,A1); initial


xor P2(P , P_A0A1 , A2); begin
A0 = 1'b0 ; A1 = 1'b0 ; A2 = 1'b0;
endmodule #10 A0 = 1'b0 ; A1 = 1'b0 ; A2 = 1'b1;
#10 A0 = 1'b0 ; A1 = 1'b1 ; A2 = 1'b0;
#10 A0 = 1'b0 ; A1 = 1'b1 ; A2 = 1'b1;
#10 A0 = 1'b1 ; A1 = 1'b0 ; A2 = 1'b0;
#10 A0 = 1'b1 ; A1 = 1'b0 ; A2 = 1'b1;
#10 A0 = 1'b1 ; A1 = 1'b1 ; A2 = 1'b0;
#10 A0 = 1'b1 ; A1 = 1'b1 ; A2 = 1'b1;
End
endmodule

Output:
Question no 7: Think of Circuit which odd parity generator is.
Repeat Q-6 for odd parity generator.

ODD Parity:

Code : Test Bench :


module Odd_Parity ( O , A0, A1 , A2); module Odd_Parity_tb ;
reg A0 ; reg A1 ; reg A2 ; wire O ;
output O; Odd_Parity DUT ( .A0 (A0 ) , .A1 (A1 ) ,
input A0 , A1 ,A2; .A2 (A2 ) , .O (O ) );
wire O_A0A1;
initial
xor O1(O_A0A1 , A0 ,A1); begin
xnor O2(O , O_A0A1 , A2);
A0 = 1'b0 ; A1 = 1'b0 ; A2 = 1'b0;
endmodule #10 A0 = 1'b0 ; A1 = 1'b0 ; A2 = 1'b1;
#10 A0 = 1'b0 ; A1 = 1'b1 ; A2 = 1'b0;
#10 A0 = 1'b0 ; A1 = 1'b1 ; A2 = 1'b1;
#10 A0 = 1'b1 ; A1 = 1'b0 ; A2 = 1'b0;
#10 A0 = 1'b1 ; A1 = 1'b0 ; A2 = 1'b1;
#10 A0 = 1'b1 ; A1 = 1'b1 ; A2 = 1'b0;
#10 A0 = 1'b1 ; A1 = 1'b1 ; A2 = 1'b1;
end
endmodule

Output :