Académique Documents
Professionnel Documents
Culture Documents
Abstract — Constant frequency One Cycle Control (OCC), as The input voltage is a DC voltage, vG, the converter is
proposed by Smedley [1], is a powerful method for controlling formed by the switch, S and the diode, D. The inductor, L,
switching power converters. The dimensioning of this control composes an LC low pass filter in conjunction with capacitor
method is not of common knowledge and as far as the authors C. Let us consider that the converter operates with a constant
know, has not yet been published for two level AC output PWM frequency, in continuous conduction mode and with an
converters. This paper describes OCC for two level switched output voltage vO. 1
power converters. Its instability problems and solutions are The output voltage is the sum of the switched voltage
analysed and dimensioning equations are deducted. This average and the ripple voltage at the switching frequency, fs.
technique allows the construction of stable high bandwidth Considering the duty-cycle δ as the relation between the on
power converters with low output THD and high PSRR. The time of the switch, ton, and Ts, the switched voltage average in
obtained analytical expressions are compared with experimental a switched cycle is:
results, showing good correlation. T δTs
1 s 1
I. INTRODUCTION
vS Ts
= ∫
Ts 0
v S dt =
Ts ∫v
0
G dt. (1)
Pulse Width Modulation (PWM) is traditionally used in To achieve the desired average output voltage, a circuit to
constant frequency power supply’s converters. The typical control ton is needed.
switched AC output converter consists in a modulator that Considering that at the start of the analysis the switch is
converts the input signal into a PWM signal (by comparison turned on, then the control system only has to provide the
to a saw tooth or triangular wave), a bridge or half bridge instant when the switch has to be turned off (ton). The
power converter configuration and a low pass filter to objective is to attain an average value proportional to the
“demodulate” the output signal. reference vREF, as expressed in equation (2):
To achieve sufficient PSRR and low THD of the output t on
1
signal a linear negative feedback loop is often used. In order
to assure system stability, linearised models have to be Ts ∫v
0
G dt = v REF . (2)
A. Unipolar OCC
OCC principle is very simple. The aim of the control system
is to attain an average output level proportional to the
reference signal, OCC performs this control action in each
switching period, Ts.
Let us consider the buck converter represented in Fig. 1.
1
Acknowledgement: the present work is partially supported by the
FCT (Fundação para a Ciência e Tecnologia) by the
Fig. 1. Buck converter. SFRH/BD/40330/2007 contract.
Fig. 3. OCC signals. Fig. 4. OCC signals in a Fig. 5. OCC applied to a half-
non-ideal system. bridge converter.
The control law could be represented as: In the general half-bridge or full-bridge inverters vG1 and
t3 vG2 are equal, implying that m1=m2. Like this, the perturbation
vS ∆vn will not disappear and there will be an oscillation at half
∫ R C dt = v
t1 i i
REF . (3)
the switching frequency.
If an offset voltage, vOS, is added to the integrator’s input to
If fs is much higher than the maximum frequency of the null m2, the error propagation ends. To achieve this condition
signal to reproduce, vREF, it could be concluded that between the added voltage has to be -vG1. Fig 8 illustrates the obtained
two successive switching periods the reference signal is waveforms, showing that in this situation the ∆v1 perturbation
almost constant, being similar in the intervals [t0, t1] and [t2, disappears in one switching cycle [4].
t3], and also in [t1, t2] and [t3, t4]. The control law is now:
vS
vS
t3
The vS average in Ts, Ts , could be represented by: vOS
1
t2
1
Ts ∫ R C −
Ros1C i
dt = v REF .
(7)
= ∫ v S dt =
Ts ∫0
t1 i i
vS Ts
v S dt. (4)
Ts t 0 In order to obtain an output switching average voltage
vS proportional to vREF a parcel has to be added to vREF to null
The circuit gain, G, is the relation between Ts and the vOS contribution. Fig. 9 shows a way to do that by using a
vREF , accordingly to equations (3) and (4) it will be: resistance network. We must now design the system such that
T vOS disappears in equation (7).
1 s
Ts ∫0
v S dt C. Design
vS
= = Ri C i f s = G.
Ts
T
(5) We consider the circuit represented in Fig. 9, where the
v REF 1 s voltages vG1 and vG2 are equal (being represented by vG) and
Ri C i ∫0
v S dt
for the sake of simplicity, vG=–vOS. To avoid error
transmission between successive cycles, Ri and Ros1 values
Although the OCC controlled unipolar circuit have to be equal.
aforementioned in section A is inherently stable, the bipolar By using the superposition theorem, the voltage at the input
circuit has some stability issues. of the comparator, vCMP, due to vINTt, vREF and vOS can be
Fig. 7 shows the time evolution of the integrator’s voltage calculated by summing its several contributions:
when it is exposed to a disturbing signal, ∆v1 [4]. Two vINT contribution:
distinct situations are analysed: in the first case vG1 e vG2 are Rref Ros 2
equal, meaning that the integrators output voltage slope (m1 vINT
Rref + Ros 2
and m2) are equal (disregarding its signal); if vG1>vG2, then vCMP1 = ⇔ vCOMP1 = β1vINT ; (8)
Rref Ros 2
m1>m2. + Rint
By analysing Fig. 7 it could be seen that the error Rref + Ros 2
propagation depends on the integrator’s voltage slope: m1 and vREF contribution:
m2 [4]. For t=nTs, the propagated error due to ∆v1, ∆vn, is:
Rint Ros 2
vREF
m Rint + Ros 2
∆v n = (− 2 ) n −1 ∆v1 . (6) vCMP 2 =
Rint Ros 2
⇔ vCOMP 2 = β 2 vREF ; (9)
m1 + Rref
Rint + Ros 2
vOS contribution:
III. EXPERIMENTAL RESULTS
Rint Rref
vOS A switching converter in half bridge configuration was built
Rint + Rref
vCMP 3 = ⇔ vCOMP 3 = β 3vOS ; (10) using an IR2110 driver and IRFB41N15D transistors, ±vG
Rint Rref
+ Ros 2 =±32V, fs=333kHz and a low pass filter at the output. The
Rint + Rref
OCC components were designed by means of the deducted
The sum of the three contributions gives: equations, giving a theoretical gain of 18.79 (due to the
vCMP = β 1v INT + β 2 v REF + β 3 vOS . (11)
available component values).
Fig. 10 a) shows the measured experimental OCC signals.
The OCC analysis is initiated at t=0. We designate toff as the The experimental diagrams are referred (from top) to: clock
instant when vS switches from vG to -vG, which coincides with signal, vS, vINT and vO. Fig. 10 b) shows vREF and vO at 10kHz
time when the input voltage of the comparator reaches zero. input frequency and allows us to calculate a practical gain of
Also, as referred before, vG=–vOS and equation (7) becomes: 18.9, very close to the predicted value. The measured THD is
0 = β 1v INT + β 2 v REF − β 3 vG . (12)
always lower then 0.5% (1W, 20-20kHz, 8Ω load).