Paper Id: CERIE - 195 Field of work: Nanoscience and Nanotechnology

Proceedings of the
Conference on Engineering Research, Innovation and Education 2011
CERIE 2011, 11-13 January 2011, Sylhet, Bangladesh

A CMOS IC USING NANO-POWER ELECTRONIC CIRCUITS FOR

LIFE-SAVING APPLICATIONS IN BANGLADESH
R. Sultana and A. Begum
Department of Electronics and Communication Engineering
University of Information Technology and Sciences, Dhaka, Bangladesh

S. Binzaid, PhD
Founder and Director, SERES, Bangladesh
seres-usa.com
+210-688-0281

Nano-power electronics is an area of emerging semiconductor VLSI technology where scaled down CMOS
circuits are primarily used in this work. A fabricable CMOS integrated chip (IC) is designed using Magic
CAD tools and it was also incorporated with scalable design techniques of MOSIS. A circuit components
reduction technique is applied to redesign a sense amplifier circuit to lower the power to nano-watts level.
This scalable design technique improved power by lowering from 7.15E-03 watts to 1.31-09 watts for the
sense amplifier. Applications of this IC have been explored and it is found be a life-saving design for
launches in Bangladesh waterways. Application of two types of sensor is identified to use with this IC that
can sense the catastrophic situations ahead of time by the proper placement in the launch. Floor plan of all
components and their pin-assignments of the IC layout are described. PSPICE simulation to verify the
operation and power consumption of components in the chip is presented in the paper.

Key words: Nano-Power; CMOS; Scalable Design; MOSIS, CAD; PSPICE

1. INTRODUCTION be utilized in Bangladesh. The objectives are

Nano-power electronics is a fast developing field of
engineering. The circuitry is composed of micro
and nano-meter device scale, having ultra-low
power electronic components. There are different
types of semiconductor switches and devices that
operate in nano-power range. Nano-power
electronics have recently been used in various fields
of engineering, biotechnology, physics, chemistry,
space systems etc [1]. Upcoming technology
includes nano scale electronics and semiconductor
nanotechnology would also primarily consider
consumption at nano-power levels. Micro and nano
scale electromechanical systems including MEMS
(Microelectromachanical System) which function
with other nano power elements built within
systems. They are very useful for engineering,
medical science and many other areas of life saving
applications [2].
1.1 Goals and Objectives
The goals of this project are to provide an overview
of nano-power electronics design of an integrated
chip and an assessment of how that technology can
*
Corresponding Author: Second B. Author,
E-mail: rupai_2005@yahoo.com
following:
 To design, simulate and verify nano-power
electronic circuits by using scalable
CMOS technology.
 Layout of a test chip that can be fabricated
by MOSIS standard processes using the
scalable design CIF file.
 To discuss about sensing signals and
process by the chip using nano-power
circuits that can save lives from
catastrophic events.
2. CIRCUIT DESIGN, SIMULATION
AND VARIFICATION OF SENSE
AMPLIFIERS
The main concern of this work involved with two
amplifiers to compare and determine their
performance. These are sense amplifier based flip-
flop and advanced modified sense amplifier. The
sense amplifier based flip-flops are run with digital
signals [3]. Borivoje and Oklobdzija designed this
high-performance and low-power digital system
and it works at low milliwatts power. It contains
total twelve transistors. Four of them are large and
the others are normal in size. It is a CMOS design
having six PMOS and six NMOS transistors. The
circuit has four inputs: R, R-bar, S, S-bar and two
outputs: Q, Q-bar.
Fig 1: Schematic of sense amplifier based flip-flop
Fig 2: MAGIC layout of sense amplifier based flip-
flop
PSPICE simulations and verification are necessary
by converting circuit layouts into mathematical
models; thus determine their behaviors. Figure 3
shows the input signals R, R-bar and S-bar of the
sense amplifier based flip-flop. Figure 4 shows the
output signal Q. The mathematical representation of
these simulations show that the total power
dissipation of the sense amplifier based flip-flop is
7.15E-03 watts. It is a very good sense amplifier
where no power sensitive issues present. This
milliwatts-power flip-flop based amplifier has some
other advantages, as it is a logical toggle switch.
Fig 3: Input signals of sense amplifier based flip-
flop
Fig 4: Output signal of sense amplifier based flip-
flop
On the other hand, advanced modified sense
amplifier is a mixed signal circuit, deigned by Dr.
Shuza Binzaid [4]. The circuitry of advanced
modified sense amplifier is very simple. It contains
two PMOS and three NMOS transistors. It has two
input terminals V1, V2, enable and the output
terminal Vout.
Figure 7 shows the two input signals and the enable
signal. Figure 8 shows the output signal. The
simulation and verification of the advanced
modified sense amplifier shows that the total power
dissipation is 1.31E-09 watts. This sense amplifier
is fast and it operates at nanowatts, which can be
suitable even for the remote power scavenging
applications.

Fig 5: Schematic of the advanced modified sense
amplifier
Fig 6: MAGIC layout of the advanced modified
sense amplifier
Fig 7: Input signals of the advanced modified sense
amplifier with buffer inverter
Fig 8: Output signals of the advanced modified
sense amplifier with buffer inverter
By comparing the simulation and verification
results, it is confirmed that the advanced modified
sense amplifier dissipate less power than the sense
amplifier based flip flop
3. DESIGN OF THE NANO-POWER
CHIP
In this work, a nano-power chip has been designed
following rules of MOSIS silicon process
technology. The MOSIS scalable CMOS design
techniques were used with MAGIC 2-D CAD tools
for designing VLSI layout. SPICE circuit
simulation tools were used to simulate each circuit
component in the chip in order to verify the
integrity and performance [5-8].
In figure 9, showing the designed chip floor plan
having 20 pins. It contains a PMOS transistor, a
NMOS transistor, a NAND gate, a buffer inverter,
an inverter, an advanced modified sense amplifier,
a sense amplifier based flip-flop. Pin assignments
are presented in table 1.
Fig 9: Floor plan of the chip
Table 1: List of devices in the chip and their pin
assignments
SL Name of Pad Pin Name
No devices Assigned
1 PMOS
17,18 OP6, IN9
Transistor
2 NMOS
15,16 OP5, IN8
Transistor
3 NAND Gate IN6, IN7,
12,13,14
OP4
4 Inverter 1,2 OP1, IN1
5 Inverter
19,20 OP7,IN10
Buffer
6 Sense
IN4, OP3,
Amplifier 7,8,9,10,11 IN5,Vdd,
Based Flip-
GND
Flop
7 Advanced
Modified 3,4,5,6 OP2, IN2,
Fig 11: Complete chip with pad frames
Sense IN3, Enable
Amplifier
MAGIC layout rule checker command ‘drc’ is
Every integrated chip has an interface to the applied to the design for the final checkup [9]. Then
external world through the metal pins of its a CIF file is made. Then MOSIS header is added to
package. These pins are connected inside package the file when no errors were found in CIF file. This
to metal on the silicon chip by welded micro-thin CIF file with header can be sent for fabrication
gold wires. The connecting metals in the chip using MOSIS service. The MOSIS service is a
silicon are called pads. The pad frame is also prototyping service that offers fast turnaround
known as the I/O region. A quad package pad standard cell and full custom VLSI circuit
frame is used for the projected chip. Figure 10 development at very low cost. MOSIS has
shows the layout of a pad. Figure 11 shows the developed methods for merging many different
completed chip with pad frame. It contains testable designs from various organizations and place onto a
devices and circuits. Each side of the chip is having single wafer. Wafer fabrication runs are scheduled
5 pins around the quad pad frame. MOSIS service on a regular basis for available fab processes of
can also facilitate with packaging vendors of such present semiconductor technologies with multi-
quad pad frame designs. layer metal CMOS/bulk technologies. MOSIS also
provides different technologies for custom
fabrication and also various chip packages [10].

4. LIFE-SAVING REAL APPLICATIONS

OF THE CHIP

Bangladesh is a riverine country. Rivers play an

important rule on transport media. Every year there
occur many accidents in rivers. As unfortunate
results, many lives and properties are at loss.
Overloading and clashing of transports like boats,
launches, ferries are the main reasons of these
accidents.

The designed chip in this project can prevent

Fig 10: Layout of a bonding pad on silicon
accidents caused due to overloading or clashing
especially with dockyards. Figure 12 shows a ship,
which has two types of sensors. They are the sensor
belt for the docking sides and the pressure sensor of
the buoyancy [11].
 This chip with sense amplifiers can be used to
detect collision forces and also the overloading
conditions of the ship. This chip easily monitors
and determines certain dangers; thus help avoiding
catastrophic situations. So the system can save
lives.

REFERENCES
1.
Fig 12: Applications on a ship showing sensors
positions for sense amplifier circuits 2.
A pressure sensor is used for monitoring the
buoyancy conditions of the floating factors of the 3.
ship. It can be placed under the center of the keel.
When the ship becomes overloaded, it can sense the
threshold to electronic system with the designed
chip for producing an alarm signal to captain of the
ship, before leaving the dock. An electronic circuit 4.
can also send the signal to the dockyard regulatory
service teams about the ship’s risky situation.
The Sensor belt is for sensing the force on the frame 5.
of the ship if a clash is caused by the ship with the
dockyard or any obstacle. It is placed on the
surroundings of the ship’s hull. The system can
measure the electrical signal of the pressure V1, 6.
caused by clashing force and then compare it to the
reference critical voltage V2 input to the chip. If the
strength of the clash crosses the safe level, then the
chip can produce signal Vout for the alarm and thus 7.
it can prevent a catastrophic event.
5. CONCLUTION 8.
A mixed signal chip is designed for low power
practical applications. All the circuit layouts were
completed by using MAGIC and their simulations
for electrical characteristics were completed by
using SPICE tools. Also following MOSIS SCMOS 9.
design rules, layout of pads was complete and DRC
was verified. A 20-pin pad frame was designed for
the chip. These chip components include two types
of sense amplifiers: sense amplifier based flip-flop
and advanced modified sense amplifier. Spice
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advanced modified sense amplifier is improved
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Also from these results, it is found that the power
dissipation was reduced by 5.46E-06 times.
For future work of this project, it is planned to
implement the designed chip to a water transport.
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