Design and Verification with System Verilog

Semester VI, Elective B - 2011

Dept of ECE, NMIT
Faculty : Prof Kameshwar Rao

Question Bank (with answer Hints)

1. What is 'logic' type ? Discuss the advantages of 'logic' type in systemverilog ? What is the limitation of
'logic' type ?
Logic type is a new type in system verilog – it is a 4-state type like reg and wire.
It can be used in continuous assignment as well as in always block. Limitation is that it cannot be driven
by multiple assignment statements, because there is no resolution as in wire, wand and wor type.
2. What is 4-state logic ? What is the advantage of 4-state over 2-state logic ? What is the advantage of 2-
state over 4-state. Give example of 4-state type ? Give example of 3 2-state types in systemverilog.
4-state logic has 4 states – 0,1,x,z. X for unknown and z for high impedance. Advantages of 4-state over
2-state are – it can detect unintentional shorts, unreachable logic throug h the 'x' state, also 'z' can model
high impedance. 'logic' type is 4-state. 2-state logic simulates much faster than 4-state and uses less
memory. Example of 2-state types in systemverilog – bit, byte, int, shortint
3. What is always_comb ? Give 3 advantages of always_comb over always block.
always_comb can be used in place of always block when only combinational logic is intended.
always_comb – no need to specify the sensitivity list, if latch is detected then compiler will give an
error, designer intent is clear – also it is simulated once at time 0.
4. Write systemverilog model of a 20-bit program counter with asynchronous reset using logic type, clock
signal is clk.
logic [19:0] pc;
logic clk, reset;
always_ff (posedge clk, negedge reset)
if (!reset) pc = '0;
else pc = pc + 1;
5. What is enumerated type ? Define enumerated type for the following set of opcodes – ADD=2, SUB=3,
JE=10, JNE-11, LD=12, ST=13 with type logic and size 4 bits.
Enumerated type is a set of symbols or labels or names – each name can be assigned a value. The base
type is int, the first symbol has value 0.
enum logic[3:0] {ADD=4'b0010, SUB, JE=4'b1010, JNE, LD, ST}} opcode;
6. A state machine has 100 states ? Define enumerated type for the states using labeled sequences.
Enum {S[100] states;
7. Use always_comb and unique case statement to code a 2 bit multiplexor with no latch inference – output
Y, inputs A,B,C,D and select line is Sel of size 2 bits
 always_comb
unique case (Sel)
2'b00 : out = A;
2'b01 : out = B;
2'b10 : out = C;
2'b11 : out = D;
endcase
8. A cpu has 2 types of instructions with following structure:
1. Double operand instruction : opcode (4 bits), Byte (1 bit), Mode (3 bits), Src (4 bits), Destn (4 bits)
2. Jump Instructions : opcode (4 bits), Cond (2 bits) Offset (10 bits)
Write a grouped instruction using structures and unions and typedef so that the instructions can be stored
in a Memory array
See ppt for similar example.
9. What is a packed structure ?
A packed structure is a structure in which the fields are stored without gap. A packed structure can be
assigned like a vector. Packed structures are useful to describe control registers, for example a timer
control register might have several fields – count value, divide-ratio etc, but the entire register needs to
be accessed as one entity.

10. Write systemverilog code to create a latch of size 8 bits with D as input, Q as output and enable signal
EN.
always_latch
if (EN)
D = Q;
11. What is a Register File ? Write systemverilog model for a register with 32 registers of 16 bit each, with 2
read addresses /data addr1/rd_data1, addr2/rd_data2, and 1 write address/data waddr/wr_data, clocked
on clk.
Register file is a set of registers with common address and data busses. It is used in CPU to store
temporary values. Register files are much faster to access than external memory.
Logic [15:0] Regfile [0:31];
logic [4:0] addr1, addr2, waddr;
always_ff (posedge clk)
begin
rd_data1= Regfile[addr1];
rd_data2 = Regfile[addr2];
if (rf_wr_en) Regfile[waddr] = wr_data;
end
12. Write systemverilog type declarations for a Memory with 1024 locations. Each location needs to store a
struct corresponding to the following instruction format - Double operand instruction : opcode (4 bits),
BW (1 bit), Mode (3 bits), Src (4 bits), Destn (4 bits). Create a typdef Instr_t of struct for the instruction
and then declare the memory as array of Instr_t.
Typedef struct {
logic [3:0] opcode;
logic BW;
logic [2:0] Mode;
logic [3:0] Src, Destn;
} Instr_t;
Instr_t MEM [0:1023];