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Dated, the………………………….

Digital MOSFET Circuit:

Digital circuits employing MOSFETs are broken down into three categories –
(I) P-MOS – uses only P-channel enhancement MOSFETs,
(II) N-MOS – uses only N-channel enhancement MOSFETs and
(III) CMOS – uses both P- and N-channel device.
VDD
+5V

Q1 D

G S
VOUT
D VIN Q1 Q2
VOUT= V IN
Q2
0V (logic 0) RON=100kΩ ROFF=1010Ω +5V (logic 1)
+ G S +5V (logic 1) RON=100kΩ RON=1kΩ +0.05V (logic 0)
VIN
-

Fig.: N-MOS Inverter.

In an N-MOS inverter, with gate connected to the drain and drain to the positive source, Q1 serves as a pull-up
resistor of typically 100kΩ.
The drain of Q2 is always biased positive relative to the source. The gate-to-source voltage VIN is the input voltage,
which is used to control the channel resistance and therefore determines whether the device is on or off.
When VIN=0V, there is no conductive channel between source and drain, and the device is off with channel
resistance 1010Ω. The output voltage shows logic 1.
VIN=+5V will cause the MOSFET to conduct, and the channel resistance between source and drain has dropped to a
value of 1000Ω. The output voltage now shows logic 0.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

CMOS Inverter:
VDD

G S

Q1
D
A Y= A
Q2 D

G S

Fig.: CMOS inverter.

The inverter is the most fundamental building block of CMOS logic. It consists of a pair of N-channel and P-channel
MOSFETs connected in cascade configuration as shown in the figure.
When the input is in the HIGH state, P-channel MOSFET Q1 is in the cut-off state while the N-channel MOSFET Q2 is
conducting. The conducting MOSFET provides a path from ground to output and the output is LOW.

Lec-19, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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When the input is in the LOW state, Q1 is in conduction while Q2 is in cut-off. The conducting P-channel device
provides a path for VDD to appear at the output, so that the output is in HIGH or logic 1 state.
A floating input could lead to conduction of both MOSFETs and a short-circuit condition. It should therefore be
avoided.
There is no conduction path between VDD and ground in either of the input conditions. That is why there is practically
zero power dissipation in static conditions. There is only dynamic power dissipation, which occurs during switching
operations as the MOSFET gate capacitance is charged and discharged.

CMOS NAND Gate:

VDD

S
Input PMOSFET NMOSFET Output
G S G
A B Q1 Q2 Q3 Q4 Y
Q2
D
Q1
D 0 0 ON ON OFF OFF 1
Y= A.B
0 1 OFF ON OFF ON 1
1 0 ON OFF ON OFF 1
Q3 D 1 1 OFF OFF ON ON 0
A S
G
Q4 D

B S
G

Fig.: CMOS two-input NAND gate.

In a two-input NAND gate –
(I) two P-channel MOSFETs (Q1 and Q2) are connected in parallel between VDD and the output terminal, and
(II) two N-channel MOSFETs (Q3 and Q4) are connected in series between ground and output terminal.
For the output to be in a logic 0 state, it is essential that both the series-connected N-channel devices conduct and
both the parallel-connected P-channel devices remain in the cut-off state. This is possible only when both the inputs
are in a logic 1 state.
When both the inputs are in a logic 0 state, both the N-channel devices are nonconducting and both the P-channel
devices are conducting, which produces a logic 1 at the output.
For the remaining two input combinations, either of the two N-channel devices will be nonconducting and either of the
two parallel-connected P-channel devices will be conducting. That is, either Q3 off and Q2 on, or Q4 off and Q1 on.
The output in both cases is a logic 1.
Under no possible input combination of logic states there is a direct conduction path between VDD and ground. So
there is near-zero power dissipation in CMOS gates under static conditions.

CMOS NOR Gate:

In a two-input NOR gate –
(I) two P-channel MOSFETs (Q1 and Q2) are connected in series between VDD and the output terminal, and
(II) two N-channel MOSFETs (Q3 and Q4) are connected in parallel between ground and output terminal.
For the output to be in a logic 1 state, it is essential that both the series-connected P-channel devices conduct and
both the parallel-connected N-channel devices remain in the cut-off state. This is possible only when both the inputs
are in a logic 0 state.

Lec-19, Pg-02 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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Ref. No............................ August 10, 2010

Dated, the………………………….

VDD

G S
A Input PMOSFET NMOSFET Output
Q1
D
A B Q1 Q2 Q3 Q4 Y
0 0 ON ON OFF OFF 1
G S 0 1 ON OFF OFF ON 0
B
Q2 1 0 OFF ON ON OFF 0
D
1 1 OFF OFF ON ON 0
Y= ( A + B )

Q3 D Q4 D

G S G S

Fig.: Two-input NOR gate in CMOS.

When both the inputs are in a logic 1 state, both the N-channel devices are conducting and both the P-channel
devices are nonconducting, which produces a logic 0 at the output.
For the remaining two input combinations, either of the two parallel N-channel devices will be conducting and either of
the two series-connected P-channel devices will be nonconducting. That is, either Q1 off and Q3 on, or Q2 off and Q4
on. The output in both cases is logic 0.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

CMOS Fan-Out:

1 5pF

5pF

To other loads
Fig.: Each CMOS input adds to the total load capacitance seen by the driving gate’s output.
CMOS inputs have an extremely large resistance (1010Ω) that draws essentially no current from the signal source.
But, each CMOS input typically presents a 5-pF load to ground. This input capacitance limits the number of CMOS
inputs that one CMOS output can drive.
The CMOS output must charge and discharge the parallel combination of all of the input capacitances, so that the
output switching time will be increased in proportion to the number of loads being driven. Typically, each CMOS load
increases the driving circuit’s propagation delay by 3ns.
Thus, CMOS fan-out depends on the permissible maximum propagation delay.

Lec-19, Pg-03 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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Ref. No............................ August 10, 2010

Dated, the………………………….

CMOS Series Characteristics:

4000/14000 Series:
Devices in the 4000/14000 series have very low power dissipation and can operate over a wide range of power-
supply voltages (3 to 15V).
They are very slow compared to TTL and other CMOS series and have very low output current capabilities.
They are not pin-compatible or electrically compatible with any TTL series.
74C Series:
This CMOS series is pin-compatible with and functionally equivalent to TTL devices having the same number. This
makes it possible to replace some TTL circuits by an equivalent CMOS design.
The performance characteristics of the 74C series are about the same as those of the 4000 series.
74HC/HCT, High-Speed CMOS:
This is an improved version of the 74C series, which has a tenfold increase in switching speed, comparable to that of
the 74LS devices, and a much higher output current capability than that of the 74C.
74HC/HCT ICs are pin-compatible with and functionally equivalent to TTL ICs with the same device number.
74HCT devices are electrically compatible with TTL, but 74HC devices are not. So 74HCT IC can be connected
directly to any TTL IC.
74AC/ACT, Advanced CMOS:
This series is functionally equivalent to the various TTL series but is not pin-compatible with TTL.
The device inputs are less sensitive to signal changes occurring on other IC pins.
74AC devices are not electrically compatible with TTL, but 74ACT devices can be connected directly to TTL.
ACL (Advanced CMOS Logic) offers advantages over HC series in noise immunity, propagation delay and maximum
clock speed.
74AHC/AHCT, Advanced High-Speed CMOS:
The devices in this series are three times faster and can be used as direct replacements for HC series devices.
They offer similar noise immunity to HC without the overshoot/undershoot problems often associated with higher
drive characteristics required for comparable speed.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Lec-19, Pg-04 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)