Académique Documents
Professionnel Documents
Culture Documents
2000
MODEL RELEASE
MODEL CHASSIS
53FDX01B DP-05
43FDX01B DP-05F
53SDX01B DP-06
61SDX01B DP-06
DIGITAL
53SWX01W DP-07
61SWX01W DP-07
53SDX88BA DP86V
60SDX88BA DP86V
-".,(*#'/'
MODEL No 53SDX88BA 53SDX01B 53FDX01B 43FDX01B 53SWX01W IQ50H95W IQ50H94W 50NHP400
60SDX88BA 61SDX01B 61SWX01W IQ60H95W IQ60H94W 60NHP400
CHASSIS DP86V DP06 DP05 DP05F DP07 ZP04 (OEM) ZP05 (OEM) SP05 (OEM)
Aspect 4X3 4X3 4X3 4X3 16 X 9 4X3 4X3 4X3
Listening Mod Standard No Yes No No Yes No No No
Listening Mod Night No Yes No No Yes No No No
Listening Mod Maximum No Yes No No Yes No No No
Spk Setup Front L-R Internal No Yes No No Yes No No No
wExt Amp wLarge No Yes No No Yes No No No
wExt Amp wSmall No Yes No No Yes No No No
Surround No Yes No No Yes No No No
Sub Woofer No Yes No No Yes No No No
Dig Input Coaxial V1/V2 No Yes No No Yes No No No
Optical V1/V2 No Yes No No Yes No No No
SRS Mode On-Off No No Yes Yes No Yes Yes Yes
Graphic EQ 7 band Yes No No No No No No No
Wireless Sound System MainPinPRear Yes No No No No No No No
Wireless Sound System MainPinP No No No No No No No No
Sub Woofer System Sub Volume Yes Yes No No Yes No No No
INFORMATION Special Event Reminder Yes No No No No No No No
Calendar Yes No No No No No No No
Auto Help No No No No No No No No
GUIDE+ PROGRAM GUIDE WITH IR BLASTER
OTHERS On TV Advanced Auto Demo Hold Power Yes Yes Yes Yes Yes Yes Yes Yes
On TV Menu Button Yes Yes Yes Yes Yes Yes Yes Yes
On TV Cursor Key on Ft Panel Yes Yes Yes Yes Yes Yes Yes Yes
On Remote Sleep Timer Yes Yes Yes Yes Yes Yes Yes Yes
2000 Model Functions (1 of 2)
On Remote Help Yes Yes Yes Yes Yes Yes Yes Yes
On Remote Commercial Skip Yes Yes Yes Yes Yes Yes Yes Yes
On PinP Single PinP Size No Yes Yes Yes Yes Yes Yes Yes
On PinP Multi PinP 7 Pix Yes No No No No No No No
On PinP Multi PinP 4 Pix No No No No No No No No
On PinP Multi PinP 3 Pix No Yes Yes Yes Yes Yes Yes Yes
On PinP Multi PinP Split Screen Yes Yes No No Yes No No No
On PinP Strobe Action Yes (7Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix) Yes (3Pix)
On PinP Variable position on Single PinP No No No No No No No No
Set Up Plug and Play Easy Set Up wColor Yes Yes Yes Yes Yes No No No
Set Up Auto Clock XDS No Yes Yes Yes Yes Yes Yes Yes
Set Up Power Resume Yes Yes Yes Yes Yes Yes Yes Yes
V Chip Yes Yes Yes Yes Yes Yes Yes Yes
SP Matrix No No No No No No No No
Page 01 -01
Soft Mute Yes Yes Yes Yes Yes Yes Yes Yes
MODEL No 53SDX88BA 53SDX01B 53FDX01B 43FDX01B 53SWX01W IQ50H95W IQ50H94W 50NHP400
60SDX88BA 61SDX01B 61SWX01W IQ60H95W IQ60H94W 60NHP400
CHASSIS DP86V DP06 DP05 DP05F DP07 ZP04 (OEM) ZP05 (OEM) SP05 (OEM)
CONTROL PANEL 2 Piece Yes Yes Yes Yes Yes No No Yes
1 Piece No No No No No Yes Yes No
FRONT PANEL Power Yes Yes Yes Yes Yes Yes Yes Yes
CH Up Cursor Up Yes Yes Yes Yes Yes Yes Yes Yes
CH Down Cursor Down Yes Yes Yes Yes Yes Yes Yes Yes
Vol Up Cursor Right Yes Yes Yes Yes Yes Yes Yes Yes
Vol Down Cursor Left Yes Yes Yes Yes Yes Yes Yes Yes
Input Exit Yes Yes Yes Yes Yes Yes Yes Yes
Menu Yes Yes Yes Yes Yes Yes Yes Yes
Magic Focus Dig Array Static Yes M.F. Yes M.F. Yes (ST) Yes (ST) Yes M.F. Yes (ST) Yes (ST) Yes (ST)
IR Receiver Yes Yes Yes Yes Yes Yes Yes Yes
Dimmer Sensor Yes Yes Yes Yes Yes Yes Yes Yes
Input 3 S Input Yes Yes Yes Yes Yes Yes Yes Yes
V Input Yes Yes Yes Yes Yes Yes Yes Yes
L/Mono Input Yes Yes Yes Yes Yes Yes Yes Yes
R Input Yes Yes Yes Yes Yes Yes Yes Yes
REAR PANEL Ant A Yes Yes Yes Yes Yes Yes Yes Yes
Ant B Yes Yes Yes Yes Yes Yes Yes Yes
To Converter Yes Yes Yes Yes Yes Yes Yes Yes
Input 1 Component No Yes Yes Yes Yes Yes Yes Yes
S Input Yes Yes Yes Yes Yes Yes Yes Yes
V Input Yes Yes Yes Yes Yes Yes Yes Yes
L/Mono Input Yes Yes Yes Yes Yes Yes Yes Yes
R Input Yes Yes Yes Yes Yes Yes Yes Yes
Input 2 Component Yes Yes Yes Yes Yes Yes Yes Yes
2000 Model Functions (2 of 2)
Page 01 -02
Sub Woofer Out Yes Yes No No Yes No No No
Rear Spk Out L Yes Yes No No Yes No No No
R Yes Yes No No Yes No No No
PTV MODEL TO CHASSIS CROSS REFERENCE CHART
PAGE 01-03
PTV CHASSIS TO MODEL CROSS REFERENCE CHART
PAGE 01-04
CTV MODEL TO CHASSIS CROSS REFERENCE CHART
PAGE 01-05
CTV CHASSIS TO MODEL CROSS REFERENCE CHART
PAGE 01-06
REAR PANEL for the
53SDX01B, 61SBX01B (DP-06) and 61SWX01W, 53SWX01W (DP-07)
OPTICAL
INPUT ANT A STOP
COAXIAL CONNECT ONLY 8 Ohm SPEAKERS
DO NOT SHORT CIRCUIT
INPUT
THESE TERMINALS.
REAR SPEAKER To (such damage is NOT COVERED
by your television warranty)
8 ONLY Converter
+ + S-VIDEO S-VIDEO S-VIDEO
R L
ANT B
- -
VIDEO Y VIDEO Y VIDEO
R L PRCR PRCR
R R R
AUDIO SUB
AUDIO AUDIO AUDIO
TO HI-FI WOOFER
MONITOR
INPUT 1 INPUT 2 OUT
PAGE 01-07
REAR PANEL for the 53FDX01B (DP-05) and 43FDX01B (DP05F)
ANT A
To
Converter
S-VIDEO S-VIDEO S-VIDEO
ANT B
VIDEO Y VIDEO Y VIDEO
PRCR PRCR
R R R
AUDIO
AUDIO AUDIO AUDIO
TO HI-FI
MONITOR
INPUT 1 INPUT 2 OUT
PAGE 01-08
MICROPROCESSOR
INFORMATION
SECTION 2
MICROPROCESSOR PORT DESCRIPTION
DP-0X MICROPROCESSOR PORT DESCRIPTION EXPLANATION:
The DP-0X Microprocessor is a Dual In-Line 64 pin chip. Generic number is MN102H51K. The Microprocessor
is responsible for many different operations related to the control of the Projection Television. Some of these con-
trols are automatic and some require customer intervention, either by the Remote control or front panel keys and/
or by the customer’s menu.
When power is first applied, the Microprocessor receives it’s B+. This Microprocessor utilizes a 3.3V power sup-
ply instead of the usual 5V as in past chassis.
As the 3.3V is rising, the Reset IC (I006) holds the reset pin (54) low long enough for the main B+ to stabilize.
After stabilization, the Reset IC brings pin (54) high. During the Reset condition, the Microprocessor is initiated
into its start up state. At the same time this is happening, the Microprocessor Oscillator is generating the Micro-
processor’s internal clock. The Crystal responsible for this is X001 (4Mhz) connected to pins (52 and 53). When
trouble shooting a Microprocessor for problems, it’s very important to remember the sequence described above.
Always examine the process before looking for any other problem area. The order is;
1. Vcc Applied. Generated from the Always Voltage (STY+7V I905) on the Sub Power Supply then through
the (STBY +5V I008 on the Signal PWB) to the 3.3V regulator Q026.
2. Ground is available. Look for open traces, etc….
3. The Reset circuit is working (I006). It should hold the Reset pin on the Microprocessor Low until main Vcc
is stabilized.
4. The Oscillator is running. Be careful here because a low resistance measuring probe will kill the Oscillator or
give a false reading.
After checking for the preliminary functionality of the circuits described above, then check for active clock pulses
leaving data port pins. (See the Data Communications Circuit Diagram for details). If some other IC is grounding
the data or clock pins, the Microprocessor will not work. This usually require a Pull-Up resistor. If no Pull-Up
resistor is noted in the schematic, then the responsibility for Pull-Up lies within the Microprocessor. Unloading
the pin in a good way to investigate for Pull-Up.
When a command is entered by either Remote Control, Front Keys or some internal process, the Microprocessor
runs a set of predetermined routines. These routines are hard programmed into the Microprocessor RAM and are
unchangeable. There are routine instructions that can be modified by either the customer or the Servicer and in-
volve pre-programmed routines and variables entered by the customer or technician. These would include such
things as changing the channel , audio set-ups, on/off timer, auto-link, etc...
PAGE 02-01
MICROPROCESSOR PORT DESCRIPTION
Continued from Preceding Page
Controlling the On and Off state of the High Voltage Power Supply.
The Power On/Off function switch has STBY+3.3V applied for the Sub Power Supply, via pin (8) of the PFS
connector through a 1K resistor. The output of the Power On/Off switch is sent through pin (6) of the PFS to
Q014. Q014 is turned on at this time and connected to it’s Emitter is Data from the Microprocessor pin (21). The
Data is routed from Q014’s Collector to Key In pin (10) of the Microprocessor. When the Microprocessor re-
ceives this data at pin (10), it knows to turn on or off the television. This function is performed by and output
from pin (53) which controls Q002. This output from this pin is High when the set is On and Low when the set is
Off.
(For more details related to Power On/Off, see the Power On & Off Circuit Diagram Explanation and Diagram).
(Continued on page 3)
PAGE 02-02
MICROPROCESSOR PORT DESCRIPTION
(Continued from page 2)
Interaction between the Servicer’s Menu and Chassis I2C Data Bus controls.
When it becomes necessary for the Service Technician to make an adjustment to the set, the Service Menu must
be entered. This is accomplished with the TV turned off, then by pressing and holding the INPUT Key and then
the POWER SWITCH. The Adjustment Menu will be displayed at this time. With the Service Menu activated, the
Technician moves up and down to the desired adjustment using the Remote control or front panel Up or Down
cursor keys. To make the adjustment, the Technician uses the Remote control or front panel Left and Right cursor
Keys to change the data values for the particular adjustment.
The Microprocessor controls the individual IC related to the adjustment using I2C technology. I2C technology
allows the Microprocessor to control and IC using only two pins, (SCL and SDA).
The following pins on the Microprocessor and the ICs that it controls are described in the following table.
2 SDA1 and 3 SCL1 I401 AV Selector, I002 EEPROM, I003 DAC 1, I004 DAC 2
59 SDA2 and 60 SCL2 U204 3D/YC, I701 Deflection Drive, IX01 Rainforest,
IS03 Front Audio Control, IS05 Front EQ, IS10 Center EQ, IS08 Center/LFE/
PinP Audio Control, IS01 DAC3, I201 1H Main Video, and I403 H Sub Video.
57 SDA3 and 58 SCL3 IS11 Rear Audio Control.
(See the Adjustment Section for actual adjustment made in the Service Mode condition).
Automatically Scanning the Tuner’s searching for Active Channels when requested by the Customer from
the Menu.
When the Projection is first installed, the active channels must be scanned and memorized in the Channel Scan
List. This list is actually stored within the EEPROM and the Microprocessor uses the information to Scan up or
down. Held within the Microprocessor is the Initial FCC Lookup table. This table give information related to all
the channels frequency, band, and channel number. The frequency is actually a given value for the Phase Lock
Loop circuit within the tuner. Then band is data to tell the band selection circuit in the tuner where the particular
channel is located and the channel number is given to the microprocessor to indicate what OSD outputs to pro-
duce. When the set is first opened, it’s in what is called Factory Reset Condition. For the Tuner this means that
the signal source is AIR, and channels 2 through 13 are in the channel scan list. Before the customer runs Auto
Program, they must set the signal source to the type they are using, Air, Cable 1 or Cable 2. After the source is
set, the customer then proceeds with Auto Programming.
When Auto Programming is initiated, the Microprocessor has a specific program to run. This program starts by
placing the tuner in the lowest channel in the lowest band. That would normally be channel 2. Then the program
instruct the Microprocessor to look for Sync. To do this, the Microprocessor actually need Horizontal Blanking
(H.Blk) at pin (49) which is labeled H.Sync and Video Sync (24) labeled Main/Sub SD Det.
Horizontal Blanking is use as a gate pulse for the coincidence detector. Within the coincidence detector is a cir-
cuit that looks at the timing of the Sync in relationship to (H.BLK). If the signal being checked is not in time with
(H.Blk). The signal is ignored. However, if the signal being monitored is in coincidence with (H.Blk) the signal
is deemed to be true Video Sync and that particular channel is stored as an active channel in the EEPROM Scan
List.
Then the Microprocessor sends information to the tuner to move up one channel and the whole process begins
again. This is repeated until every channel is checked. After completion of the scan, the microprocessor retrieves
information from the EEPROM concerning the first channel in the lowest band that appears in the scan list and
directs the tuner to tune to that channel.
(Continued on page 4)
PAGE 02-03
MICROPROCESSOR PORT DESCRIPTION
(Continued from page 3)
Automatically Controlling the Tuners when Channels are changed. (See Figure 1)
MAIN TUNER:
When channels are changed, the Microprocessor runs another routine. This routine detects the command if it’s
input by the Remote Control or the Front keys, whether it’s Scan Up/Down or direct access, and begins to control
the Tuner. First the Microprocessor output a Mute command to blank the video, then data is sent to the tuner to
move it to the desired channel. After that the Microprocessor again checks the coincidence detector for active
sync. If active sync is detected, the Microprocessor opens what is called the AFC Loop. The AFC Loops com-
prises two cycles trying to lock the tuner to the specific IF frequency of 45.5 Mhz. A DC voltage is sent from ei-
ther the Main Tuner U201 pin (10) or the PinP Tuner U202 pin (21) back to the Microprocessor pin (6). This
DC voltage indicates the error between the IF detected and the IF frequency reference. This error voltage tells the
Microprocessor to do one of two things. 1st, if the error is large, the Microprocessor changes the Programmable
Divider’s division rate to a larger or smaller degree to get closer to the actual IF frequency desired. Or 2nd move
the Pulse Swallow division rate to either 1/32 or 1/33. The Pulse Swallow tuning circuit is a second divider that is
on the output from the Prescaler. The main Prescaler takes the very high frequency output from the tuners mixer
circuit which is produced when the tuners main oscillator is beat against the incoming RF frequency. The Pro-
grammable Divider is instructed by the Microprocessor exactly what division rate to apply to the Beat Frequency
generating the IF frequency. The IF frequency is then sent through the Pulse Swallow circuit which again divides
the IF frequency at a much smaller rate . This allows the IF output frequency to become much more finite and can
correct for much smaller errors between the Phase comparators reference frequency. The error voltage generated
is directed back to the main internal Oscillator in the front end and corrects for Tuning errors.
(See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data Com-
munication for controlling the Main Tuner).
INTEGRATED TUNER
BM (B+ Mains)
IF Out IF In
IF
Main Comparator
Osc
Ref
Interface Freq.
45.5K
Tuning MAIN
Voltage Figure 1
+33V
MICROPROCESSOR
(Continued on page 5)
PAGE 02-04
MICROPROCESSOR PORT DESCRIPTION
(Continued from page 4)
Automatically Controlling the Tuners when Channels are changed. (See Figure 1)
PinP TUNER:
As far as the internal function of the PinP Tuner, it is the same as the Main Tuner.
(See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data Com-
munication for controlling the Main Tuner).
When the customer presses the PinP button on the Remote Control, the Microprocessor outputs Clock, Data and
Enable controls to the Flex Converter. The Flex Converter also has the PinP circuit inside. The Clock, Data and
Enable pins on the Microprocessor are pins (20 Clock, 21 Data and 46 FCENABLE) These are routed to the
Level Shift IC, I014 pins (2, 3 and 4). They are output on pins (18, 17 and 16) to the Flex Converter U205 con-
nector PFC1 and input on pins (10, 11 and 12). The Flex Converter’s PinP unit is then switched on and insertion
is made into the regular Main Video line. The position of the PinP window, the PinP window itself and other dif-
ferent display conditions are controlled by this process. When SWAP is pressed on the remote control, the chan-
nel or input that the PinP tuner was on, now becomes the Main Video’s source and the channel or input that the
Main signal was on, now becomes the PinP source.
Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer.
The Rainforest IC has many enhancement circuits built in. These would include the Black Peak Expansion circuit,
the Dynamic Noise Reduction circuit, Time Compression and of course Sharpness, Black Level and Contrast ad-
justments as well.
• Black Peak Expansion Circuit:
This circuit is utilized to increase the contrast ratio. The standard video signal is 1 Volt Peak to Peak (p/p
hear after), the actual video (Y) content is 730mVp/p. The 1 Vp/p is explained it IRE figures from this
point on. The Standard video signal is divided into units called IRE. The units are equal to 140 total for
the 1Vp/p signal. Sync occupies 40IRE which are negative. And the Luminance represents 100 IRE
units. Each unit represents 7.1428mVp/p of information. (See Figure 2 below.)
The Black Peak Expansion circuit monitors the 1/2 way point of luminance, (50 IRE or 357mV) and
pulls the signal towards pure black or the 7.5 IRE level. This increases the distance from Black Peak to
White Peak which is contrast.
• Dynamic Noise Reduction Circuit:
This circuit again monitors the area from 50 IRE down and subtracts noise. This circuit is dynamic
meaning that it characteristics change. In other words, the subtraction process is greater near black level
that it is near 50 IRE. The subtraction is 6dB at maximum, meaning that there would be some frequency
loss near black, but the noise which is seen as white speckles would be reduced.
• Time Compression Circuit:
Any time an analog signal is passed through a capacitive circuit, its high frequencies are reduced. To re-
place these high frequencies, Hitachi uses Time Compression. This circuit is on the order of Aperture
Compensation, however it differs in the fact that it uses 5 delay lines. The actual signal should look like
Figure 2
(Continued on page 6)
PAGE 02-05
MICROPROCESSOR PORT DESCRIPTION
(Continued from page 5)
Figure 3, however after passing through a capacitive circuit, it looks like Figure 4. After Time Compres-
sion takes place, the beginning rise is advanced. Just before white peak the signal is delayed. Just before
the signal falls the signal is advanced and just before the signal reaches black peak the signal is delayed.
This causes the signal to appear more like the actual signal and thus restores the high frequencies lost
through capacitance.
• Sharpness:
During the Time Compression process, switching pulses that are detected at the transition point, (A tran-
sition is the point at which the luminance signal goes for black to white or white to black) are used in the
sharpness circuit.. This signal is the routed through a sort of variable resistor and according to how much
sharpness the customer has selected, determines how much of the transition signal is added to the origi-
nal signal. The greater the sharpness setting, the greater the transition signal added.
• ST LED is routed from the Main Tuner at pin (19), through Q204, to the DAC1 I003 pin (10). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pins 3 SCL1
and 2 SDA2. The Microprocessor knows how to switch the tuners decoder circuit by making judgment upon
these inputs. Then the Microprocessor can use Clock, Data and Enable lines to control the Tuner.
(Continued on page 7)
PAGE 02-06
MICROPROCESSOR PORT DESCRIPTION
(Continued from page 6)
• SAP LED is routed from the Main Tuner at pin (20), through Q203, to the DAC1 I003 pin (9). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pins 3 SCL1
and 2 SDA2.
The Microprocessor knows how to switch the tuners decoder circuit by making judgment upon these inputs. Then
the Microprocessor can us Clock, Data and Enable lines to control the Tuner.
Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20, 21 and 44) re-
spectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the Clock and Data lines
must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data arrive at I014 at pins (2
and 3) and are output at pins (18 and 17). They arrive at the Main Tuner at pins (4 and 5).
The PinP Tuner doesn’t have MTS capability. It only output mono audio, so no switching takes place for the PinP
Tuner U202 audio circuit. The only difference for the PinP tuner control lines is related to the PinP Enable line.
This is output from the Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin (17). Clock and Data are
the same as for the Main Tuner.
(See Microprocessor Data Communications Circuit Diagram and Explanation for further details).
Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, and 2, and
Tuner 2 (AUX) or In From Converter.
The different inputs can be selected by the Remote Control or the Front Panel switches. This is accomplished by
the INPUT button. Each time the Input button is pressed, the different inputs are sequentially selected. The se-
quential order is, Main Tuner, AVX 1, AVX 2, AVX 3, AVX 4, 2nd Antenna and back to Main Tuner. Also, if
there are S-Inputs on AVX1, 2 or 4, there is an internal mechanical switch inside the S-Jack that tells the Micro-
processor an S-Jack is inserted. Then when that particular input is selected, it automatically selects S as it’s
source. The same thing holds true for Component inputs. The set should never have Component inputs and S-Jack
inserted at the same time and a black and white picture will be displayed.
(See Video Signal Processing for details related to Video Switching.)
PAGE 02-07
DP-0X CHASSIS MICROPROCESSOR I-001 PIN/PORT DESCRIPTION 1 through 35
Pin No. ID Function Active
1 IRIN Receives Remote Control Inferred pulses. Data
2 SDA1 Serial Data Sent and Received from the EEPROM, A/V Selector, DAC1, DAC2. Function of I2C. Data
3 SCL1 Serial Clock Synchronization Sent to the EEPROM, A/V Selector, DAC1, DAC2. Function of I2C. Data
4 Dimmer Receives DC voltage generated from the Photo Receiver on the Front Panel monitoring Room Light. For AI DC
5 AD Key In Receives Level Shifted DC voltage from Front Panel Key presses. DC
6 Main/Sub AFC Receives the Main Tuner AFC or Sub AFC DC Voltage switched by I005. Used during channel change. DC
7 Key In When the Power switch is pressed, Clock data from pin 21 is routed through Q014 back to this pin. Power is toggled On or Off. Data
8 Not Used Not Used N/A
9 Not Used Not Used N/A
10 Main FV Det Receives Composite 1 V Sync from I015 pin 4 for OSD Positioning. Sync
11 Sub FV Det Receives Composite 2 V Sync from I016 pin 4 for OSD Positioning. Sync
12 DSP Busy Receives the Busy command from the Digital Surround Processor on the Surround PWB. DC
13 DSP SO Control command to the DSP Unit for controlling Modes. Data
14 DSP Dir Receives Digital Surround Processor Error information from the DSP unit on the Surround PWB. Data
15 DSP SS Control command to the DSP Unit for controlling Modes. Data
16 DSP SCK Digital Surround Processor Clock. Data
17 DSP S1 Control command to the DSP Unit for controlling Modes. Data
18 DSP ERR Mute Mutes Audio when a DSP Dir input is detected. (DSP Error). DC High
19 DSP Reset Resets the DSP module on the Surround PWB DC High
20 Clock Sent to the Level Shift I014 then to both Tuners and the Flex Converter as a timing signal. Also see pin 7. Data
21 Data Sent to the Level Shift I014 then to both Tuners and the Flex Converter to control each unit. Data
22 Comp 1/2 FH Det Either Component One or Two Horizontal Input from I005 through Q046. Used for OSD Display. And Auto Link DC
23 AC In Receives Timing pulses for advancing the Clock. Received from the Smitt Amp Q008 and Q009 60Hz.
24 Main/Sub SD Det Station Detection. Used during Auto Programming and when channels are changed to open AFC Loop. Switched by I005. Sync
25 VDD Stby +3.3V generated by 0029. Main Microprocessor B+. DC
26 CHL Clamp level High DC
27 VRefFHS Use as a reference signal within the Microprocessor High Frequencies. DC
28 CVBS0 Composite Sync used for Closed Caption Detection for the Main Tuner. Sync
29 VSS Ground N/A
30 CVBS1 Not Used. Composite Sync used for Closed Caption Detection for the PinP Tuner. N/A
31 VREFLS Reference Signal used within the Microprocessor Low Frequencies. N/A
32 CLL Internal function of the Microprocessor. N/A
33 AVDD Stby +3.3V generated by 0029. DC
34 COMP Internal function of the Microprocessor. DC
Page 02-08
SCL SCL2 60
A/V SCL
I401 I701 Deflection
Selector SDA
SDA2 59 SDA
SCL SO Select 50 SCL
EEPROM I002 IX01 Rainforest
SDA Reset 54 SDA IC
PAGE 02-10
DP-05 and DP-05F MICROPROCESSOR PORT DESCRIPTION
DP-05F PORT DESCRIPTION
Refer to the DP-05 and DP-05F System Control Port Description Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 System Control Port Description Cir-
cuit Diagram is;
• The DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no
Rear or Center Audio, so the Serial Data Communications (SCL3 and SDA3) to the Rear Audio B+ isn’t
Used.
• The Data Communications to the Level Shift IC (I014) going to the (DSP) is not used.
• The Rear Audio IC, Center Audio IC and the Center Graphic EQ IC are not used.
• The Front Audio Control IC designation is (IA05).
• The DAC3 IC designation is (IA01).
All else remains the same.
(See Next page for diagram).
PAGE 02-11
DP-05 and DP-05F SYSTEM CONTROL PORT DESCRIPTION
I001
Dimmer 4 VDD (3.3V) 61 CLOCK
U201
POO 41 DATA
MAIN
FE Enable1 44 ENABLE TUNER
VSS (Gnd) 29
Main/Sub AFC 6 AFC
AC In 23
DATA
OSD X1 48 U202
CLOCK PinP
OSD Xo 47
FE Enable2 43 ENABLE TUNER
OSD B 39
Key In 7 AFC
OSD R 37 Power Switch
OSD G 38
Clock 20 Clock
I014 U205
Half Tone 40 Data 21 Data
Level Flex Conv &
Shift PinP Unit
OSD Blk 51 FC Enable 46 Enable
Power On/Off 53
17 N/A
DSP SI
VRef 36 DSP Err Mute 18 N/A
B+Fail 9 DSP Sck 16 N/A
DSP S0 13 N/A
N/A 57 SDA3
DSP Busy 12 N/A
N/A 58 SCL3
SCL SCL
SO Select 50 Deflection
EEPROM I002 I701
SDA SDA
Reset 54
SCL SCL
IRef 35 IX01 Rainforest
DAC 1 I003 IC
SDA SDA
BVCOI 42
SCL
SCL 3 SCL1 AVDD 3.3V 33 IA05 Front Audio
DAC 2 I004
SDA Control
SDA 2 SDA1 Test 52
Main V. Chip Data and CCD 28 SCL
CLL 32 IA01 DAC3
SDA
Sub V. Chip Data 30
Sub FV Det 11
SCL
OSC In 62 I201 1 H Main Video
Main FV Det 10
SDA
OSC Out 63 Comp 34
SCL
VSS (Gnd) 64 I403 1 H Sub Video
G+Reset 8 N/C
SDA
IRIn 1
VRefHS 27 VSync 55
CLH 26 H.Blk/H.Sync 49
PAGE 02-12
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
Use this explanation in conjunction with the Microprocessor Data Communications circuit diagram.
The Microprocessor must keep in communication with the Chassis to maintain control over the individual cir-
cuits. Some of the circuits must return information as well so the Microprocessor will know how to respond to
different request.
The Microprocessor uses a combination of I2C Bus communication and the Serial Data, Clock and Load lines for
control. The I2C communication scheme only requires 2 lines for control. These lines are called SDA and SCL.
Serial Data and Serial Clock respectively.
The Microprocessor also requires the use of what are called Fan Out IC or DACs, (Digital to Analog Converters).
This allows the Microprocessor to use only two lines to control many different circuits.
Also, due to the fact that this Microprocessor operates at the new 3.3Vdc voltage, it requires a Level Shift IC to
bring up the DC level of the control lines to make it compatible with the connected ICs.
The Microprocessor communicates with the following ICs:
The following explanation will deal with the communication paths used between the Microprocessor and the re-
spected ICs.
ON THE SIGNAL PWB:
Main Tuner U201
The Microprocessor controls the Main Tuner by Clock, Data and Enable lines.
Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20 Clock, 21 Data
and 44 FEENABLE1) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as
the Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data
from the Microprocessor arrive at I014 (Level Shift) at pins (2 and 3) and are output at pins (18 and 17).
They arrive at the Main Tuner at pins (4 and 5).
(Continued on page 14)
PAGE 02-13
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
(Continued from page 13)
EEPROM I002
The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List,
Customer set ups for Video, Audio, Surround etc… are memorized as well. Also, some of the Microprocessors
internal sub routines have variables that are stored in the EEPROM, such as the window for Closed Caption
detection.
Data and Clock lines are SDA1 from pin (2) of the Microprocessor to pin (5) of the EEPROM and SCL2 from
pin (3) of the Microprocessor to pin (6) of the EEPROM. Data travels in both directions on the Data line.
DAC1 I003
This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion
IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The
Main Microprocessor send Clock and Data via I2C bus to the DAC1 IC. The output from the Microprocessor is
pin (2 SDA1 and 3 SCL1) which arrives at the DAC1 IC at pins (5 and 6) respectively.
The following is a list of the input and output pins on DAC1.
PIN FUNCTION
1 IR Det The IR pulse from the Remote Control is monitored when Auto Link is set. (See Auto Link in Index).
2 YN Det Active Low. This pin monitors for active sync when Auto Link is set. (See Auto Link in Index).
3 Blk Main Normal High, Blanking Low. Blanks Y-Cb/Cr into Flex Converter.
4 MTS Places the Main Tuner pin (21 mode) into MTS Stereo. If Tuner receiving MTS signal. See pin 10.
5 F Mono Places the Main Tuner pin (22 mono) into forced Mono Mode.
6 Ant Switches the antenna block into Antenna A or Antenna B when selected.
7 Blk Sub Normal High, Blanking Low. Blanks PinP Sub Y-Cb/Cr on Terminal PWB before going into Flex Converter.
8 Gnd Ground
9 SAP Det The Main Tuner outputs an SAP LED signal when SAP is detected. Active Low.
10 ST Det The Main Tuner outputs an ST LED signal when Stereo is detected. Active Low.
11 SAD0 Ground Not Used
12 SAD1 Ground Not Used
13 SAD2 Ground Not Used
14 SDA Data I2C communications between DAC1 and Microprocessor
15 SCL Clock I2C communications between DAC1 and Microprocessor
16 Vcc IC B+. (STBY +5V)
PAGE 02-14
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
(Continued from page 14)
DAC2 I004
This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion
IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The
Main Microprocessor send Clock and Data via I2C bus to the DAC2 IC. The output from the Microprocessor is
pin (2 SDA1 and 3 SCL1) which arrives at the DAC2 IC at pins (5 and 6) respectively.
The following is a list of the input and output pins on DAC2.
PIN FUNCTION
1 YUV Det1 Detects activity on Component Input number 1.
2 YUV Det2 Detects activity on Component Input number 2.
3 FH Det Out 1 Test Point 1 (TP1).
4 Sel5 Controls IX02 on 2H PWB. Selects either Y Cb/Cr or Y IQ to compensate for Chroma Phase angle used in Auto Color.
5 F Mono Places the Main Tuner pin (22 mono) into forced Mono Mode.
6 FH Det Out 1 Test Point 2 (TP2).
7 31/33 Notifies the DCU related to Horizontal Frequency. Either 31.5Khz for everything but HD or 33.75Khz for HD.
The DCU uses two sets of memory. One for everything but HD and one for HD. This relates to both Digital Convergence
adjustment data and for Magic Focus memory.
Also notifies the Dynamic Focus Horizontal Parabolic generator to compensate for phase distortion. Also, notifies I701
Horizontal Drive generation IC concerning the Horizontal operation frequency.
8 Gnd Ground
9 CS Sel Not Used.
10 Busy Informs the Microprocessor that the DCU is in the Digital Convergence Adjustment Mode. The Micro. Ignores IR pulses.
11 SAD0 Ground Not Used
12 SAD1 Ground Not Used
13 SAD2 IC B+. (STBY +5V).
14 SDA Data I2C communications between DAC2 and Microprocessor
15 SCL Clock I2C communications between DAC2 and Microprocessor
16 Vcc IC B+. (STBY +5V).
3D Y/C U204
The 3D Y/C module is a Luminance/Chrominance separator, as well as a 3D adder. Separation takes place digi-
tally inside the module. Using advanced separation technology, this module separates and doesn’t produce dot
pattern interference or dot crawl. The 3D effect is a process of adding additional signals to the Luminance and
Chrominance. These signals relate specifically to transitions. Transitions are the point where the signal goes
from dark to light or vice versa. The 3D adds a little more black before the transition goes to white and a little
more white just before it gets to white. It also adds a little more white just before it goes dark and a little more
dark just before it arrives. This gives the impression that the signal pops out of the screen or a 3D effect.
The Microprocessor communicates with the 3D Y/C module via I2C bus data and clock. The communications
ports are from the Microprocessor pins (59 SDA2 and 60 SCL2) to the 3D Y/C PYC1 connector pins (2 and 3)
respectively.
The Microprocessor also is able to turn on and off circuits within the 3D Y/C module determined by customer
menu set-up.
PAGE 02-15
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
(Continued from page 15)
ON THE TERMINAL PWB:
A/V Selector I401
The A/V Selector IC is responsible for selecting the input source for the Main Picture as well as the source for
the PinP or Sub picture. Communication from the Microprocessor via pins (2 SDA1 and 3 SCL1) to the PST1
connector pins (5 and 6) respectively then to I401 pins (34 and 33) respectively.
PAGE 02-16
MICROPROCESSOR DATA COMMUNICATION DESCRIPTION
(Continued from page 16)
9 P. Vol Perfect Volume On/Off controlled by the customer’s menu. Note, when in Pro-Logic mode, Perfect Volume is Off.
10 DSPREQ DSP Request Input.
11 SAD0 Ground Not Used
12 SAD1 Ground Not Used
13 SAD2 Ground Not Used
14 SDA2 Data I2C communications between DAC3 and Microprocessor
15 SCL2 Clock I2C communications between DAC3 and Microprocessor
16 Vcc IC B+. (STBY +5V)
PAGE 02-17
DP0X CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PYC1
Sweep Control
3 SCL2 U204
PSD2 PSZ2 2H Video PWB
IOO1 I701 2 SDA2 3DY/C
2 16 SDA2
2 26 SCL2 IX01
1 17 SCL2 34 SDA2 I201 Rainforest
Main Video 1 27 SDA2 RGB Processor
Deflection PWB 33 SCL2 Chroma
SDA2 59
SCL2 60
PSU1
PST1
U201 Data 5 2
SDA2
4 IS03
SDA2
Enable Tuner 1 1 34 SDA2 I403 Front
Clock 4 SCL2
Sub Video 1 5 SCL2 Audio Control
FEENABLE1 44 6 Main 2 33 SCL2
Chroma
Signal PWB
DP-05 & DP-05F MICROPROCESSOR DATA COMMUNICATION Description
DP-05 and DP-05F DATA COMMUNICATIONS DESCRIPTION
Refer to the DP-05 and DP-05F Microprocessor Data Communication Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Microprocessor Data Communication
Circuit Diagram is;
• The DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is no
Rear or Center Audio, so the Serial Data Communications (SCL3 and SDA3) to the Rear Audio B+ isn’t
Used.
• The Data Communications to the Level Shift IC (I014) going to the (DSP) is not used.
• The Rear Audio IC, Center Audio IC and the Center Graphic EQ IC are not used.
• The Front Audio Control IC designation is (IA05).
• The DAC3 IC designation is (IA01).
All else remains the same.
(See Next page for diagram).
PAGE 02-19
DP-05 and DP-05F CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PYC1
Sweep Control
3 SCL2 U204
PSD2 PSZ2 2H Video PWB
I701 2 SDA2 3DY/C
2 16 SDA2
2 26 SCL2 IX01
1 17 SCL2 34 SDA2 I201 Rainforest
Main Video 1 27 SDA2 RGB Processor
IOO1 33 SCL2 Chroma
Deflection PWB
SDA2 59
SCL2 60
PST1 PSU1
U201 Data 5 2
SDA2
4 IS03
I403 SDA2
Enable Tuner 1 1 34 SDA2
SCL2
Front
Clock 4 Sub Video 1 5 Audio Control
FEENABLE1 44 6 Main 2 33 SCL2 SCL2
Chroma
SDA1 2 5 SDA1
IOO2 SDA2
EEPROM 17 IS10
SCL1 3 6 SCL1 Center
SCL2
16 Equalizer
PFC1
Signal PWB
ON SCREEN DISPLAY (OSD) SIGNAL PATH DESCRIPTION
The Microprocessor is responsible for generating On Screen Display (OSD) related to the Main Menu, Volume
Control, Channel Number, Closed Caption Display, Clock, etc… It also generates the OSD for the Service Menu.
However there are actually two different sources for generating OSD, the Microprocessor and the Digital Conver-
gence Unit, (DCU).
PAGE 02-21
ON SCREEN DISPLAY (OSD) SIGNAL PATH DESCRIPTION
(Continued from page 21)
DCU AS THE SOURCE:
The DCU (Digital Convergence Unit) generates it’s own OSD patterns and text. The DCU generates these
characters in the same fashion as the Microprocessor. The DCU generates Digital Red from pin (11), Digital
Green from pin (12) and Digital Blue from pin (10) output from the PDG and then through (QK06 Dig Red,
QK07 Dig Green and QK08 Dig Blue). The DCU characters are then routed through the PSD1 connector pins
(2 Red, 4 Green and 6 Blue) and then through (QX01 Red, QX02 Green and QX03 Blue) and then sent to
the Rainforest IC IX01 pins (35 Analog Red In, 34 Analog Green In and 33 Analog Blue In) as Digital Con-
vergence graphic signals.
When the DCU is activated by pressing the Service Only switch on the Deflection PWB, the DCU outputs a
BUSY signal. This signal does two things.
1. It tells the Microprocessor to ignore Infrared Remote commands. It does this by outputting the BUSY sig-
nal from pin (10) of the PDG connector and then through the PSD1 connector pin (1). Then to I004 the
Analog to Digital converter. The Analog to Digital converter outputs this information in digital form
through the I2C bus to the microprocessor. The I2C data is output from pin (14 SDA1 and 15 SCL1) and
arrives at the Microprocessor I001 pins (2 and 3). When the Microprocessor receives this BUSY signal, it
ignores all Infrared Remote commands.
2. It blanks video so that the DCU graphics can be see easily. This is accomplished by the same BUSY signal
being routed from pin (10) of the PDG connector and then through the PSD1 connector pin (1). It is then
routed through the PSZ1 connector pin (7) to the Rainforest IC IX01 pin (32) as YS2 signal which mutes
video.
PAGE 02-22
DP-0X CHASSIS "On Screen Display, OSD" SIGNAL CIRCUIT DIAGRAM
To CRTs
BUSY QX36
G Out 42 3 G
Deflection PWB
AUDIO and VIDEO MUTE SIGNAL PATH DESCRIPTION
V MUTE 1 EXPLANATION:
There are certain times when the Microprocessor or other circuits must Mute the video or audio. The Microproc-
essor is responsible for Muting the Audio/Video during Channel Change, Power On/Off, Child Lock, AVX Se-
lected with no input, etc….
This is accomplished via pin (45) of the Microprocessor. When V Mute is activated, a high is routed through
D028 to the base of Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON.
The emitter of Q023 is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This
high is now called V Mute 1. V Mute 1 is routed to two circuits, for Video Mute and for Audio Mute.
PAGE 02-24
AUDIO and VIDEO MUTE SIGNAL PATH DESCRIPTION
(Continued from page 24)
F.Spk Off FRONT SPEAKER OFF:
When the customer accesses the Main Menu and selects the Front Speaker Off selection, DAC IS01 on the Sur-
round PWB outputs a high from pin (6), see the Surround Mute Circuit diagram and explanation for details.
This high is routed through the PSU1 connector pin (6) to the anode of two diodes;
1. To the anode of DC03, to the base of QC03 which turn ON and grounds pin (11) of IC01 placing the
Front Audio output IC into Mute.
2. To the anode of DC02, then to the base of QC01 and QC02 which grounds the audio input to pin (4
Right audio in and 2 Left audio in) of IC01.
AC LOSS DETECTION:
AC is monitored by the AC Loss detection circuit. The AC input from PQS1 pin (10) is rectified by DN09.
This charges up C009 and through DN08 it charges C008. When AC is first applied, C008 charges slightly be-
hind C009 preventing activation of Q001. If AC is lost, C009 discharges rapidly pulling the base of Q001 low,
however DN08 blocks C008 from discharging and the emitter of Q001 is held high. This action turns on Q001
and produces a high. This high is routed through D029 to the base of Q022 turning it ON. The collector goes
low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to STBY +11V, so when
it turns ON, it’s collector output goes HIGH. This high is now called V Mute 1. V Mute 1 is routed to two cir-
cuits, see V Mute 1 explanation on the previous page.
SPOT:
SPOT is generated from the deflection PWB when either Horizontal or Vertical deflection is lost. This is to pre-
vent a horizontal or vertical line from being burnt into the CRTs. See Horizontal and Vertical Sweep Loss De-
tection circuit and explanation for details. This high is input from PSD2 pin (6), through D027 to the base of
Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON. The emitter of Q023
is connected to STBY +11V, so when it turns ON, it’s collector output goes HIGH. This high is now called V
Mute 1. V Mute 1 is routed to two circuits, see V Mute 1 explanation on the previous page.
PAGE 02-25
DP-0X Series Chassis AUDIO and VIDEO MUTE Circuit
(See also Surround Mute Circuit)
SBY +11V
"SPOT" R198 D031
From I904 Horizontal Sweep Loss Det.
Pin 3 Vertical Sweep Loss Det. D030
AC Photo C070
(From Deflection PWB)
Coupler R190 R191 Q023 2H Video PWB
AC Sig 10V p/p
Q001
2 PSD3 Q024 SW+9V
PQS1 R192 PSZ2
Q022 RX52 IX01
10 R010
R195 DX10
RN15
R008
ERRMute 18 7 I014
Level Shift
PSU2 DC04 Mute = Lo
13 QC03 RC09 IC01
DC03 RC07 11 Mute
Audio 6
DSP ERR Mute FRONT
CC09
PSU1 RC08 L&R
CC08 Audio
VMute
V Mute 2
14 Output
Right Ft. Audio CC02 CC04
9 4 R In R Out 7
Left Ft. Audio CC01
8 2 L In L Out 12
PAGE 02-26
PAGE 02-27
DP-05 and DP-05F Series Chassis AUDIO and VIDEO MUTE Circuit
(See also Surround Mute Circuit)
SBY +11V
"SPOT" D031
From I904 R198
Horizontal Sweep Loss Det.
Pin 3 Vertical Sweep Loss Det. D030
AC Photo C070
(From Deflection PWB)
Coupler R190 R191 Q023 2H Video PWB
AC Sig 10V p/p
Q001
2 PSD3 Q024 SW+9V
PQS1 R192 PSZ2
Q022 RX52 IX01
10 R010
D027 R193 R195 V Blk FC DX10
RN15
R008
R196 13 RX57
R011
ERRMute 18 7 I014
Level Shift
DC04 Mute = Lo
13 QC03 RC09 IC01
DC03 RC07 11 Mute
ERR Mute
FRONT
CC09
PSU1 RC08 L&R
CC08 Audio
V Mute 2
VMute
14 Output
Right Ft. Audio CC02 CC04
9 4 R In R Out 7
Left Ft. Audio CC01
8 2 L In L Out 12
PAGE 02-28
PAGE 02-29
DP-0X Series Chassis SURROUND MUTE Circuit
(See also Audio Video Mute Circuit)
PSU2 PMU1
Surround
ERR Mute 6 8 DSP
Module
RSpkOff
Mute = Lo
QS10 RSJ9 IS16
Sub Woofer DS49 DS37 11 Mute
RSJ7
CSM9 REAR
QS20 SD50 DS36 RSJ8
DS48 CSM8 Audio
Output
REAR R CSM1 CSM3
HiFi L
DS35 4 R In R Out 7
DS45 CSM2
REAR L
QS17 SD47 2 L In L Out 12
RSJ6 QS09 CSM4
QS08
DS44
PAGE 02-30
HiFi R RSJ5
Mute
QS16 SD46 DS34
DP-05 and DP-05F SRS MUTE SIGNAL CIRCUIT DESCRIPTION
DP-05 and DP-05F SRS MUTE SIGNAL CIRCUIT DESCRIPTION
Refer to the DP-05 and DP-05F SRS Mute Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 AV Mute Circuit Diagram is;
• The DP-05 and the DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround PWB. There is
no Rear or Center Audio, so the Mute to the Rear and Center Audio ICs isn’t Used.
• The (DSP) is not used. So ERRMUTE isn’t routed to the Surround PWB DSP module.
PAGE 02-31
DP-05 and DP-05F Series Chassis SRS MUTE Circuit
(See also Audio Video Mute Circuit)
PSU1 IA01
SCL2 1 2 SCL
HiFi L
SDA2 2 3 SDA
QA11
VMute DA08 DA11
V Mute 2 14
HiFi R
DA04 DA16
QA12
Mute
ERRMute 7
PAGE 02-32
DP-0X MEMORY INITIALIZATION PROCEDURE
(EEPROM RESET)
WARNING: This should only be done in extreme cases. I2C Data will be reset as well.
Be sure and write down all data values before continuing.
NOTE: All customers' Auto Programming and Set-Ups are returned to factory settings.
Jumper 3.3V
R100
7 20
KEY-IN1 CLOCK
I001
MicroProcessor
PAGE 02-33
MEMORY SWITCH SETTINGS ON SET FROM FACTORY
To Access Service Menu, press and hold INPUT then POWER
NTSC SIGNAL INPUT
PAGE 01 PAGE 02
ADJUST MODE HP DP062b TA1300 NTSC
Sub Brit H Posi 30
Service
FLEX CONT
Def Reset 47 VD-Pos 3F
V/P Reset UPD64081
3DYC Reset DYGA 09
Flex Reset DCGA 06
DSP Reset VAPGA 05
CCD Reset VAPIN 0B
Fact Reset YHCOR 00
Mem Init
PAGE 03 PAGE 04
TA1270-M FLEX CONT NTSC
TINT (TV) 3C 39 HHPF1 00
TOFFO (TV) 00 41 V-CRG 00
TOFQ 00 42 H-CRG 00
Sub CNT 0F 43 V-ENH 00
Sub Clr 1B 44 H-ENH 00
96 YVHENH 0B
100 CVHENH 12
PAGE 05 PAGE 06
FLEX CONT NTSC FLEX CONT NTSC
71 YV-ENH 00 97 YV NLP 00
79 CV-ENH 00 98 YH NLP 0A
87 YH-ENH 07 101 Y-LMT FF
94 CH-ENH 0F 83 YH FTQ 00
66 YV-DSB 00 91 CY FRQ 02
75 CV-DSB 00 70 YV LTI 00
82 YH-DSB 00 78 CV CTI 00
90 CH-DSB 00 86 YH LTI 01
68 YV-CLP 00 93 CH CTI 01
84 YH-CLP 00
PAGE 07 PAGE 08
FLEX CONT NTSC FLEX CONT NTSC
69 YVDSBC 00 65 YNRRDC 00
77 CVDSBC 00 74 CNRRDC 00
85 YHDSBC 00 67 YNR-DC 00
92 CHDSBC 00 76 CNR-DC 00
95 Y-CRG 00 81 YNR-O 00
99 C-CRG 00 89 CNR-O 00
64 YNR-IN 04 45 CB-BLK 07
73 CNR-IN 04 46 CR-BLK 07
80 YNRPAS 00 27 FRMBRT 60
88 CNRPAS 02 102 CLPOUT 7F
PAGE 02-34
MEMORY SWITCH SETTINGS ON SET FROM FACTORY
PAGE 09 PAGE 10
FLEX CONT NTSC FLEX CONT NTSC
10 MPLL-S 0F 23 V-POS 1F
17 SPLL-S 0F 24 VSIZ 7F
12 MPLL-E 0F 50 HD-POS 3F
19 SPLL-E 0F 48 VBLK-T 7F
11 MVW-PH 05 49 VBLK-B 7F
18 SVW-PH 05 51 HBLK-R 7F
14 MHS-HP 0F 52 HBLK-L 7F
21 SHS-HP 0F 40 READ-F 10
13 MY-CLP 03
20 SY-CLP 03
PAGE 11 PAGE 12
FLEX CONT NTSC FLEX CONT NTSC
35 FRMTOP-2 07 120 TV/CINE 01
FRMTOP-L 07 121 T/C DET 07
36 FRMBTM-2 07 122 T/C UNL 01
FRMBTM-L 07 123 T/C LCK 03
37 FRM RGT 07 126 T/C ARE 05
38 FRM LFT 07 127 T/C CBR 07
59 BS-TOP 07 128 T/C YBR 07
60 BS-BTM 07
61 BS-RGT 07
62 BS-LFT 07
PAGE 13 PAGE 14
TA1298 NTSC TA1298 NTSC
SHARP 0C COLOR 40
APACON 06 TINT 45
YNR 00 R-Y PH 02
R/B GH 01
G-Y PH 00
G/B GH 00
Color System
00
PAGE 15 PAGE 16
TA1298 NTSC TA1298 NTSC
RGB BRT 50 CLRG 00
RGB CNT 50 CLT 00
G DRV (W) 39 YOUTG 00
B DRV (W) 2D YGPNT 00
SUB CLR 10 S TRK 00
SUB CNT 1F RGBG 00
VSM PH 05 DC PNT 00
VSM GA 00 DC RAT 00
OS ACL 01 DC LMT 00
RGB ACL 00
PAGE 02-35
MEMORY SWITCH SETTINGS ON SET FROM FACTORY
PAGE 17 PAGE 18
TA1298 NTSC V CHIP RATINGS
BSP 03 POLLING 0F
APL/BS 00 TIMEOUT 05
B COR 01 STATUS 02
B GA 00
B DET 00 AFC/CLOCK TEST
DABL PN 00
DABL GA 07
ABL PN 07
ABL GA 05
PAGE 02-36
DP-0X SERIES CHASSIS DAC 1 and DAC 2 INFORMATION
16 Vcc
IR Det 1 Detects IR from Remote for Auto Link Remote Set Up
8 Gnd
YN Det 2 Detects the presents of Luminanace Sync from the Main Signal Path Active Low
11 Not Used
Blk Main 3 Inputs Blanking for Main Signal to the Flex Converter
12 Not Used
MTS 4 Places the Main Tuner into MTS mode if Stereo MTS Detected by Microprocessor
13 Not Used
F Mono 5 Places the Main Tuner into Forced MONO mode
ANT 6 Switches the Antenna Switch Assembly from Antenna 1 to Antenna 2
Blk Sub 7 Inputs Blanking for Sub Signal to the Flex Converter
SAP Det 9 Receives the Low from the Main Tuner indicating SAP signal received.
ST Det 10 Receives the Low from the Main Tuner indicating Stereo signal received.
I003 SDA 14 Serial Data from Microprocessor
DAC1 SCL 15 Serial Clock from Microprocessor
16 Vcc
YUV/Det1 1 Detects Component 1 input activity
8 Gnd
YUV/Det2 2 Detects Component 2 input activity
11 Not Used
FH Det 3 Not Used
12 Not Used
SEL5 4 Select 5 output. Controls Chromal Rotation Switch IX02 on 2H Video PWB. Hi = NTSC Lo = Y Cr/Cb
13 Not Used
31/33 5 Output Deflection Frequency Control 31.5 kHz or 33.75 kHz.
FH Det 2 6 Not Used
G Power 7 Not Used
C/S Sel 9 Not Used
PAGE 02-37
Busy 10 Receives Busy from DCU stopping Microprocessor from responding to Remote commands.
I004 SDA 14 Serial Data from Microprocessor
DAC2 SCL 15 Serial Clock from Microprocessor
POWER SUPPLY
INFORMATION
SECTION 3
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
Use the DP-0X Series Power On and Off Diagram along with this explanation:
The power supply in the DP-0X chassis works very similar to the previous models, with only a few exceptions.
This power supply runs all the time when the AC is applied. The use of the power supply creating Stand By Volt-
age supplies eliminates the need for a Stand-By transformer. The following explanation will describe the Turning
ON and OFF of the projection television.
The Microprocessor I001 generates the ON-OFF control signal from pin (53). The logic states of this pin are
High = On and Low = Off. When the set is turned On, the high from pin (53) is routed to the Relay Driver Q002
base. This turns on Q002 and it’s collector goes low.
This On/Off from the Relay Driver Q002 will perform the following :
• Turns on the SW5+V I907 and SW+12V I908 regulators. Which do not operated in Standby.
• Turns on the Shut Down “Power Shorted” detection circuit, Q908 and Q909.
• Turns on the Horizontal Vcc supply to the Horizontal and Vertical drive IC, I701.
• Turns on the Relay providing AC to the Deflection Power Supply on the Power/Deflection PWB.
OFF = Low
8 Def.B+
On = High DP35
Sub Power C705
Micro Supply PWB Figure 1
PAGE 03-01
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
Continued From Previous Page
PAGE 03-02
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
Continued From Previous Page
SOME SHUT-DOWN DETECTION CIRCUITS SHUT OFF DURING STAND-BY: (See Figure 4)
During Stand-By, all of the secondary voltages produced by the Switching Transformer (T901) are reduced to
approximately 50% of their normal voltage, except the STBY voltages after regulation. This could cause a po-
tential problem with the Short Detection circuits for shutdown. To avoid accidental shut down, Q903 also con-
trols the activity of Q908 and Q909. During Stand-By, the output from the Microprocessor On/Off pin (35) is
Low. This Low is inverted by Q002 and this High is routed to the base of Q903 turning it On. This allows the
Base of Q908 to be pulled Low through D945. This action turns off Q908. When Q908 is off, it doesn’t supply
emitter voltage to the collector of Q909. The base of Q909 is connected to 6 Low Detection inputs, (See the
Sub Power Supply Shut Down Circuit explanation and diagram for further details). When the power supply
operates at 50%, the Short Detection circuit could activate. By turning off Q909, no accidental shut down op-
eration can occur.
D945
Power/
S-901 Def. Power Sub Power Supply PWB
Deflection PWB AC In Supply Relay
I001 PQD1 SW+5V
Micro-
processor 2 3
AC for Def. Power 1
Supply Q911
Power
2 1 4
On/Off SW+12V
53 PQS1
1 I908 2 SW+12V
ON = Hi D928
+28V SW+12V Reg IC
OFF = Lo 5 3
Q903
Q002
R951
8 5 I907 2 SW+5V
D948
1 SW+5V Reg IC 3
Signal PWB Off On Figure 5
PAGE 03-03
DP-0X SERIES "POWER ON & OFF" DIAGRAM
AC In
PQD1 SW+5V
OV in STBY
I001 2 3
AC for Def. 1
Microprocessor Power Supply Q911
VDD Power 2 1 4
OV in STBY
Reset SW+12V
3.3V On/Off
Power/ S-901 Def. Power 25.25V
61 54 53 PQS1 Deflection PWB Supply Relay 25.96V
1 I908 2 SW+12V
ON = Hi D928
+28V SW+12V Reg IC
OFF = Lo 5 3
Q903 OV in STBY
3.3V 3.3V Q002 Off On
2.35V
R951 5.78V
8
D945 5 I907 2 SW+5V
D948
R053
R957 1 SW+5V Reg IC 3
25.96V
C032 R950
BOTH OFF IN STBY
Q908 C948
3 R958 Q909
D946
To Gate of Q905
I006 +28V (Shutdown SCR)
2
Reset R949 R959
1
11.9V
I906 C949
2 Sub Power PWB
STBY+11V 6 Shutdown
L004
D947 Inputs,
3.3V
Q026
R029 Active Low
3.3V
C074
3.9V PQD2 OFF IN STBY
STBY+5V
STANDBY MODE:
4 Green LED’s and the Red LED are lit in the standby mode with the AC applied and the TV OFF;
• D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
• Audio Front 29V Regulator SW+29V indicated by D912 Color GREEN
• Audio Rear and Center 29V Regulator SW+29V indicated by D913 Color GREEN
• STBY+11V Regulator I906 indicated by D949 Color GREEN
• STBY+7V Regulator I905 indicated by D927 Color GREEN
POWER ON MODE:
When the Power is turned ON, the other LED lights and the Red LED remains lit as well;
• D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
• SW+5V Regulator I907 indicated by D931
LED USAGE:
The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics can be
made. By observing the operation of the Red and Green LEDs, the technician can determine if the Sub Power
Supply is running or not.
The following will examine each LED and how they are lit.
D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
This LED indicates any of three different scenarios,
1. Is there B+ (Vcc) available to the Sub Power Supply Driver IC? LED will be ON
2. Is the B+ (Vcc) available to the Sub Power Supply Driver IC missing? LED will be OFF
3. Is the Set in Shut Down? LED will be OFF
As can be see, there are two different scenarios that can cause D903 to be off, Missing Start up voltage for the
Driver IC and/or the Sub Power Supply is in Shut Down.
B+ GENERATION FOR THE SUB POWER SUPPLY DRIVER IC. See Figure 1
Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. I901 requires
21V DC to operate normal. However, it will begin operation between 9~10V DC on pin (4) of I901.
When AC is applied, AC is routed through the main fuse F901 (a 5 Amp fuse), then through the Line filters L901,
902, 903 and 904 to prevent any internal high frequency radiation for radiating back into the AC power line. Af-
Hot Cold
FUSE Noise Filter Rectifier
AC Input Switching
F901 5A L901,2, 3,4 D901
Transformer
Rectifier T901
D901
4
Switching 3
Control
I901
D903 Protect
Protect Photocoupler
Figure 1 SCR Q901 I903
(Continued on page 6)
PAGE 03-05
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
(Continued from page 5)
ter passing the filters it arrives at the main full wave bridge rectifier D901 where it is converted to DC voltage.
One leg of the AC is routed to a half wave rectifier D902 where it is rectified, routed through R905 and R906
(both a 5.6K ohm resistor), filtered by C907, clamped by a 30V Zener D904 and made available to pin (4) of I901
as start up voltage. The Red LED D903 is illuminated by this power supply. When this voltage reaches 9~10 Vdc,
the internal Regulator of I901 is turned On and begins the operation of I901.
Figure 2 is a simplified diagram of the main Power Supply used in the DP-0X series Projection Television
chassis.
The primary control element of the power supply is I901 (the Switching Regulator IC), in conjunction with
transformer T901. These two components, along with the supporting circuitry, comprise a closed loop regulation
system.
Unlike previous Pulse Width Modulated (PWM) Switch Mode Hitachi power supplies, the regulation system in
the this chassis utilizes Frequency Control Modulation with an operational frequency of 105KHZ. Primary
regulation is provided by Q902, I902 and Q910, regulating the switching frequency at pin (3) of I901 via pin 1,
the regulation input to the IC.
AC
Raw 150V
4
Run V T901
Switch Mode 28V
Drain 3 Transformer
I901
Switch
Mode Regulate 1
Q910
Buffer
I902
Opti-Coupler
Q902
Buffer
IC
Q901 I903 Q905 Shutdown
SCR Opti-Coupler SCR Inputs
Figure 2
Three primary voltages are developed that are needed to sustain run, maintain regulation, and support shutdown
circuitry; Run Voltage generated from pin (8 and 9) of T901, +28V used for regulation, and STBY +11V,
respectively.
The “STBY” represents “always on”, designating a supply that is active when the unit is connected to AC power.
The Power Supply utilizes a Shutdown circuit that can trigger Q905 from 16 input sources. (6 of these are not op-
erational in Stand By mode). I903 is activated by Q905, applying gate voltage to Q901, which grounds out the
Vcc at pin (4) of I901, disabling the power supply.
(Continued on page 7)
PAGE 03-06
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
(Continued from page 6)
Audio Rear and Center 29V Regulator SW+29V indicated by D913 (Not in the DP-05F Chassis)/.
The Audio Rear and Center 29V supply is generated from pin (16) of T901. This output is protected by E993,
rectified by D911 and filtered by C917. This supply is routed to the Rear Audio Output IC IS16 and Center Audio
Output IC IC15.
This voltage is what illuminates the Green Visual Trouble Shooting LED, D913.
PAGE 03-07
DP0X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
(SUB POWER PWB) SIGNAL POWER SUPPLY 5 GREEN L.E.D.s and 1 RED L.E.D.
(6 Total L.E.Ds. for visual trouble sensing observation)
Audio Audio Stby Stby Sw
Front 29V Rear/C 29V +11V +7V +5V
8.0V Stby Not In 11.8V Stby 7.28V Stby 0.0V Stby
30.67V Run DP05F 11.9V Run 7.39V Run 5.78V Run
Not On
In Stby
R926 D949 D927 D931
D903
Q901 Shutdown SCR
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
DP-05 and DP-05F SUB POWER SUPPLY LEDs USED FOR TROUBLE SHOOTING
Refer to the DP-05 and DP-05F LEDs used for Trouble Shooting Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Sub Power Supply LEDs used for
Trouble Shooting is that the DP-05 and DP-05F doesn’t have the DSP Module. Therefore, it uses a SRS Surround
PWB. There is no Rear or Center Audio, so the LED for monitoring the Rear Audio B+ isn’t there. (D913) is not
used. So there will only be (4) Green LEDs and (1) Red LED on the Sub Power Supply.
All else remains the same.
(See Next page for diagram).
PAGE 03-09
DP-05 and DP-05F CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
(SUB POWER PWB) SIGNAL POWER SUPPLY 4 GREEN L.E.D.s and 1 RED L.E.D.
(5 Total L.E.Ds. for visual trouble sensing observation)
Audio Stby Stby Sw
Front 29V +11V +7V +5V
8.0V Stby 11.8V Stby 7.28V Stby 0.0V Stby
30.67V Run 11.9V Run 7.39V Run 5.78V Run
Not On
R926
In Stby
D949 D927 D931
D903
Q901 Shutdown SCR
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
Use this explanation in conjunction with the Sub Power Supply Shutdown diagram.
The sub power supply in the DP-0x chassis works very similar to the previous models, with some very significant
exceptions. This power supply runs at 50% efficiency when the AC is applied and the set is OFF. The use of the
power supply creating the SBY+11V supply eliminates the need for a Stand-By transformer. The following
explanation will describe the Turning ON and OFF of the projection television.
PAGE 03-11
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 11)
This circuit consist of a diode connected by its cathode to a positive B+ power supply. Under normal conditions,
the diode is reversed biases, which keeps the base of Q1 pulled up, forcing it OFF. However, if there is a short or
excessive load on the B+ line, the diode in effect will have a LOW on its cathode, turning it ON. This will allow a
current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal.
PAGE 03-12
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 12)
Negative Voltage Loss Detection
• SW-12V Loss Detection (D939, D940)
If any one of these circuits activate the power supply will STOP, and create a Power Supply Shutdown Condition.
PAGE 03-13
SUB POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 13)
Source of the internal Switch MOS FET is routed out of pin (2) through three low ohm resistors to hot ground.
This on and off action, causes the transformer to saturate building up the magnet field. When the internal Switch
MOS FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as
the drive windings. The drive windings at pin (8 and 9) produce a run voltage pulse which is rectified by D905,
filtered by C908 then routed through R908, clamped by D904 and now becomes run voltage (12.7V) for I901.
PAGE 03-14
DP-0X SIGNAL POWER SUPPLY (Low Voltage) SHUT-DOWN CIRCUIT
T901
D902 R905 R906 R908 D905 8 11 28V
AC
Sw+12V Sw-12V
D904 C908
9 12 R941 R942
C907
Vin 4
R960 I901 D921 R945 D940 D939
Power
IC D936 D935
D903 I903 Sw +12V
R909
4 1 D933 D932
Q901 Sw +5V
R911
3 2 D941
C947
PAGE 03-15
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
DEFLECTION POWER SUPPLY VISUAL LEDs.
DP-0X Chassis has 1 Green and 1 Red LED on Deflection Power Supply PWB.
This chassis utilizes 1 Green LED in the power supply cold side and a Red LED in the HOT side.
The power supply operates it two different modes, Standby and Projection On mode.
POWER ON MODE:
When the Power is turned ON, the LEDs lights;
• DP37 Indicating Vcc applied to the Power Supply Driver IC IP01 Colored RED
• DP29 Indicating 120V Deflection B+ is available Colored GREEN
LED USAGE:
The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics can be
made. By observing the operation of the Red and Green LEDs, the technician can determine if the Deflection
Power Supply is running or not. Remember, this power supply doesn’t operate when the set is in Standby.
The following will examine each LED and how they are lit.
DP37 Indicating Vcc applied to the Power Supply Driver IC IP01 Colored RED
This LED indicates any of three different scenarios,
1. Is there B+ (Vcc) available to the Deflection Power Supply Driver IC? LED will be ON
2. Is the B+ (Vcc) available to the Deflection Power Supply Driver IC missing? LED will be OFF
3. Is the Set in Shut Down? LED will be OFF
As can be see, there are two different scenarios that can cause DP37 to be off, (1) Missing Start up voltage for the
Driver IC and/or (2) the Deflection Power Supply is in Shut Down.
B+ GENERATION FOR THE DEFLECTION POWER SUPPLY DRIVER IC. See Figure 1
Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. IP01 requires
10.7V DC to operate normal. However, it will begin operation at 9~10V DC on pin (4) of IP01.
When AC is applied by the relay on the Sub Power Supply R901, AC is routed through the connector PQD1.
Then it arrives at the main full wave bridge rectifier DP01 where it is converted to DC voltage. One leg of the AC
is routed to a half wave rectifier DP02 where it is rectified, routed through RP02 and RP03 (both a 5.6K ohm re-
sistor), filtered by CP05, and made available to pin (4) of IP01 as start up voltage. The Red LED DP37 is illumi-
nated by this power supply. When this voltage reaches 9~10Vdc, the internal Regulator of IP01 is turned On and
begins the operation of IP01.
PAGE 03-16
LEDs USED FOR VISUAL TROUBLE SHOOTING DESCRIPTION
(Continued from page 16)
Figure 2 is a simplified diagram of the main Power Supply used in the DP-0X series Projection Television
chassis.
The primary control element of the power supply is IP01 (the Switching Regulator IC), in conjunction with
transformer TP91. These two components, along with the supporting circuitry, comprise a closed loop regulation
system.
Unlike previous Pulse Width Modulated (PWM) Switch Mode Hitachi power supplies, the regulation system in
the this chassis utilizes Frequency Control Modulation with an operational frequency of 60KHZ to 85KHZ,
corresponding to full load and no load conditions, respectively. Primary regulation is provided by IP03, IP04 and
into IP01, regulating the switching frequency at pin (3) of I901 via pin 1, the regulation input to the IC.
Two primary secondary voltages are developed that are needed to sustain run and maintain regulation;
1. Run Voltage generated from pin (8 and 9) of TP91 rectified by DP03 and supplies run voltage to IP01 pin
(4) and
2. 120V Deflection Voltage generated from pin (13) of TP91, rectified by DP11 used for regulation and power-
ing the Deflection and regulation circuitry.
AC
Raw 150V
4
Run V TP91 120V
Switch Mode Deflection B+
Drain 3 Transformer
IP01 DP29
Switch
Mode Regulate 1
IP04
Opti-Coupler
IP03
Regulator IC
IC
HOT COLD
DP37
Figure 2
GREEN LED:
120V Deflection B+ DP29
The Deflection B+ 120V supply is generated from pin (13) of TP91. This output is rectified by DP11 and filtered
by CP17. This supply is routed to the Horizontal Drive Circuit and the High Voltage generation circuit.
This voltage is what illuminates the Green Visual Trouble Shooting LED, DP29.
PAGE 03-17
DP0X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
DEFLECTION PWB 1 GREEN L.E.D.s and 1 RED L.E.D.
(2 Total L.E.Ds. for visual trouble sensing observation)
120V Deflection B+
RP28
RP29
Osc B+ DP29
DP02 65V
IP03 Regulator
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
Use this explanation in conjunction with the Deflection Power Supply Shutdown diagram.
POWER SUPPLY FREQUENCY OF OPERATION DURING RUN
When the Horizontal deflection is in operation, the power supply frequency fluctuates in accordance to screen
brightness, causing differing demands for High Voltage replacement. The normal operational range for the power
supply is between 80 KHz to 100 KHz. The lower the frequency, the higher the current supplied to the load.
During Stand-By, it operates at 200KHz.
PAGE 03-19
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 19)
Any Positive
B+ VOLTAGE TOO HIGH DETECTION.
B+ Supply
(See Figure 3) Voltage Too High
In this circuit, a Zener diode is connected to a voltage Detector
divider or in some cases, directly to a B+ power supply. If
the B+ voltage increases, the voltage at the voltage divider
or the cathode of the zener diode will rise. If it gets to a
predetermined level, the zener will fire. This action
creates a Shutdown Signal. Shut-Down Signal Figure 3
There are a total of 14 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are
specifically detected by the main power driver IC, IP01 that protect it from excessive current or over voltage.
All of the Shutdown detection circuits can be categorized by the four previously described circuits
PAGE 03-20
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 20)
Voltage Too High Detection
11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24). Sensed from the Heater Voltage gener-
ated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the Horizontal
Driver IC IH02, to defeat Horizontal Drive Output.
12. Side Pincushion failure generating a High. (D754, and D753).
13. Deflection B+ Too High. (DP17, RP21 and RP22).
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28)
If any one of these circuits are activated, the power supply will STOP, and create a Power Supply Shutdown
Condition.
4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34
The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this
circuit that creates a Low on the cathode of D760, the low will be routed to the base of Q754, turning it
Off. This output High is routed through DP34 to the gate of the Shut Down SCR QP01.
5. Shorted Deflection Transformer or Misoperation (D756 and Q754) then through DP34
The Deflection circuit generates the actual Drive signal used in the High Voltage section. If a problem
occurs in this circuit, the CRTs could be damaged or burnt. D757 is connected to D759 which is nor-
mally rectifying pulses off the Deflection Transformer T753. This rectified voltage is normally sent
through D757, D756 to the base of Q754 keeping it On and it’s collector Low. If the Deflection circuit
fails to produce the pulses for rectification, the base voltage of Q754 disappears and the transistor turns
Off generating a High on its collector. This output High is routed through DP34 to the gate of the Shut
Down SCR QP01.
PAGE 03-21
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 21)
6. Heater Loss Detection (DH26, DH27,QH07 and DP34) This voltage does not go to the CRTs.
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as
heater voltage, its used for Excessive High Voltage Detection. If a problem occurs in this circuit, the Ex-
cessive High Voltage Detection circuit wouldn’t operate. So it would be possible for there to be High
Voltage but the circuit detecting Excessive High Voltage couldn’t work. DH26 is connected to DH24
which is normally rectifying pulses off the Flyback Transformer TH01. This rectified voltage is nor-
mally sent through DH26, DH27 to the base of QH07 keeping it On and it’s collector Low. If the
Heater Pulse fails to produce the pulses for rectification, the base voltage of Q754 disappears and the
transistor turns Off generating a High on its collector. This output High is routed through DH30 to the
anode of DP34 to the gate of the Shut Down SCR QP01.
9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18)
If an excessive current condition of the Deflection B+ is detected by RP17 a 0.47 ohm resistor, the base
of QP02 would drop. This would turn on QP02 and the high produced at the collector would fire zener
DP15. This High would be routed through DP16 through DP18 to the gate of the Shut Down SCR QP01
and Shut Down occurs.
10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34)
If an excessive current condition of the Vertical B+ is detected by R645 a 0.68 ohm resistor, the base of
Q609 would drop. This would turn on Q609 and the high produced at the collector would be routed
through D615 through DP34 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
PAGE 03-22
DEFLECTION POWER SUPPLY SHUT DOWN CIRCUIT DESCRIPTION
(Continued from page 22)
VOLTAGE TOO HIGH DETECTION
Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works.
11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24). Sensed from the Heater Voltage
generated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the
Horizontal Driver IC IH02, to defeat Horizontal Drive Output
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as
heater voltage, its used for Excessive High Voltage Detection). If this voltage goes too high indicating an
excessive High Voltage condition, the voltage divider comprised of RH54 and RH55 would impress a
high on the cathode of DH31. This high is routed through DH34 to the gate of the Shut Down SCR
QP01 and a Shut Down occurs.
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28)
The Heater Voltage for the CRTs filament is generated in the Deflection Power Supply. This voltage is
monitored by DP27. If this voltage goes too high, the zener DP27 will fire. This high is routed through
DP28 to the gate of the Shut Down SCR QP01 and Shut Down occurs.
PAGE 03-23
DP0X DEFLECTION POWER SUPPLY SHUTDOWN DIAGRAM
Deflection B+ (120V)
RP17
TP91 Excessive Current Det.
DP11 0.47 Deflection B+ 120V
13 CP33 Deflection B+ (120V)
RP21
S-901 Excessive Voltage Det.
QP02
Def. Power RP22 Vertical Circuit
Supply Relay
DP15 DP17 Excessive Current Det. Pin 10
SW+5V
I601
AC In 28V R645
S12V DP16
2 3 0.68
PQD2 DP18
Q911 Q609
1 4 QP01
5 ShutDown Flyback
PQD1 S.C.R. TH01
D753 D754
Side Pin Failure
DP24 DP29 DP28 High Det.
Q777 6 7 9.36V
1 8 C769
Deflection Transformer
Inoperative Det.
T752
H.Blk
PAGE 03-24
VIDEO
INFORMATION
SECTION 4
Video Circuit Block Diagram Explanation
I401 - Luminance Audio Selector IC
Main Tuner (TV1V) in pin 63
Sub Tuner (TV2V) in pin 60
Video 1 in from Terminal PWB pin 8
S-Video 1 (Y) from Terminal PWB pin 10
S-Video 1 (C) from Terminal PWB pin 12
Video 2 in from Terminal PWB pin 1
S-Video 2 (Y) from Terminal PWB pin 3
S-Video 2 (C) from Terminal PWB pin 5
Video 3 in from Front Control PWB pin 15
S-Video 3 (Y) from Front Control PWB pin 17
S-Video 3 (C) from Front Control PWB pin 19
Yin1 PinP Luminance from 2L Comb filter pin 49
Cin1 PinP Chroma from 2L Comb filter pin 51
Page 04-01
DP-0X SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC
12
PST2 Q216 Q235 I201
Q402
V2 1 V/Yout2 Main Y 5 Main Y
S Det. S-Y2 44 /Video /Video
40 37
3
S-2 In S-C2 Q401 47
5 Main C
Cout2 47 7 6 48
Main C
Q213 Q214 Main
PYC1 Video/
Chroma
13
U204 11
PAGE 04-02
3DYC 9
Terminal PWB 7 Signal PWB 2 of 2
Component Video Circuit Block Diagram Explanation
I401 - Luminance/Audio Select IC
VIn4 Comp 1 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function.
VIn5 Comp 2 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function.
Flex Converter
Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404.
Combines the two sets of signals (Main and Sub).
Converts output signals to 2H (31.75kHz) YCbCr unless signals are already 31.75kHz or higher.
IX01 - Rainforest IC
Receives the three color difference signals from IX02.
Outputs to the three CRT PWBs.
Page 04-03
DP-0X SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC U205
Terminal PWB Signal PWB
Component 2 I205 PFC1
I401 I406 PST2 Q232
Inputs Q439 1
Cr/Pr2 1 Cr/Pr Q427 1
Cr/Pr 1 21 5
Cr/Pr1 3 13 7 233 Q234
16 2
Q438 2 1 Q229
Cb/Pb2 1 Cb/Pb Q426 3
Cb/Pb 14 19 4
5 11 9 Q230 Q231
Comp 2 for 30 11 2
Auto Link 2 1 Q226
Y2 1 Y Q425 5
Y 8 15 3
6 9 11 Q227 Q228
Q437 9 2
FLEX CONVERTER
Component 1 Y1 2 Signal PWB
Inputs Q434 I407 Main R-Y Cr Out
Y 1 Cr/Pr
48
Comp 1for 22 1 Main B-Y Cb Out
Auto Link 3 47 I201 Main Picture
16 Q440 Main Y Out Preparation IC
Cb/Pb 2 37
Q435 1 Cb/Pb
14
5 PST2
Cr/Pr
11 Q441
2
Terminal Q436
8
1 Y I404
6 1 Q416
PWB 7 Sub R-Y Cr Out
9 Q442 21 19 19
2
1 Q417 Q418
Q414 2
Sub R-Y Cr Out 1 Q419
I403 48
Q413 Sub B-Y Cb Out
9
19 17
Sub B-Y Cb Out
18
47 3 Q420 Q421
2
1 Q422
11 Sub Y Out
Q412 Sub Y Out 15 15 17
37 5 Q423 Q424
2
Refer to the DP-05 and DP-05F Component Signal Path (Main & Terminal) Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Video Circuit Diagram
is;
• The DP-05 and DP-05F PinP circuit doesn’t route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through the
Selector IC.
• The Sub Component Selector IC (I407) is not used.
• The Sub Component/NTSC Signal Selector IC (I404) is not used.
PAGE 04-05
DP-05 and DP-05F SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC U205
Terminal PWB Signal PWB
Component 2 I205 PFC1
I401 Inputs I406 PST2 1 Q232
Q439
Cr/Pr2 1 Cr/Pr Q427 1
Cr/Pr 1 21 5
Cr/Pr1 3 13 7 233 Q234
16 2
Q438 2 1 Q229
Cb/Pb2 1 Cb/Pb Q426 3
Cb/Pb 14 19 4
5 11 9 Q230 Q231
Comp 2 for 30 11 2
Auto Link 2 1 Q226
Y2 1 Y Q425 5
Y 8 15 3
6 9 11 Q227 Q228
Q437 9 2
FLEX CONVERTER
Component 1 Y1 2
Signal PWB
Inputs Q434
Main R-Y Cr Out
Y 48
Comp 1for 22 Main B-Y Cb Out Main Picture
Auto Link 47 I201 Preparation IC
Cb/Pb Main Y Out
37
Q435
Terminal
PWB PST2
Cr/Pr
Q436
Q416
Q414 Sub R-Y Cr Out Sub R-Y Cr Out
48 19 19
I403 Q417 Q418
Q419
Q413 Sub B-Y Cb Out Sub B-Y Cb Out
47 17 18
Q420 Q421
Q422
Q412 Sub Y Out Sub Y Out
37 15 17
Q423 Q424
IX01 - Rainforest IC
Receives the three color difference signals from IX02.
Outputs to the three CRT PWBs.
Page 04-07
DP-0X CHROMA ROTATION CIRCUIT EXPLANATION
QUESTION:
What is the function of QX22, QX23, QX24, QX25, QX26 and QX27 on the output of
the 3D Y/C Comb filter.
See Chroma After Flex Converter Diagram schematic for details.
FROM:
Alvie Rodgers C.E.T. Technical Trainer.
ANSWER:
The RGB Processor IX01 (TA1298AN) has a function called Skin Tone
correction. This circuit is also named “Auto Color or Auto Flesh Tone”.
The Auto Color function works only with Y/I-Q signals. The YUV signal out of the
Comb filter must be converted to YIQ before entering IX01 (Rainforest IC) in order to
use “Auto Color”. Y Pr/Pb YUV signals must be converted.
IQ signals are made from UV signal by giving them a 330 phase shift.
See figure below for details.
The Switching IC IX02 shown on the Chroma After Flex Converter Diagram selects
either the NTSC Y/IQ signal without rotation or the Y Pr/Pb with rotation as deter-
mined by the control signal Select 5 (SEL5).
Not shown is the input pin for Select 5 (SEL5) control signal. This control signal is in-
put via pin (5 and 12).
(V)
(I) 900
1230 330
(Q)
330
(U) The U Signal is rotated 33 degrees to
00 Convert it to a Q signal.
PAGE 04-08
DP-0X SERIES CHASSIS CHROMA AFTER FLEX CONVERTER SIGNAL PATH
Signal PWB
YCBCR YIQ
U205 CONVERTER
PFC2 PSZ2
QX25 QX27
2H CB I
2H B 18 17
2H CB
FLEX CONVERTER
QX24
2H CR
QX55
QX23
2H CB
QX26
2H CR 2H CR QX22 Q
2H R 20 19
QX54
2H CR
2H CB
IX01 IX02
1
CR/I 14 QX52
V/I In 51 5 I I
11
2
CB/Q 1 2H CB
1 QX53
U/Q In 52 3 Q
Q
16
2
2
SEL5 High = NTSC Low = Y Pr/Pb
PAGE 04-09
12
Rainforest IC
RGB Processor
YCBCR/YIQ 2H VIDEO PWB
Selector
Sync Circuit Block Diagram Explanation
I401 - Luminance Audio Selector IC
VOut1 PinP (Sub) Video to I005 Main/Sub Select IC and also to I001 microprocessor for Sub CCD.
V/YOut2 Main Video or S-Video (Y) to I005 Main/Sub Select IC and also to I001 microprocessor for
Main CCD.
VIn4 Component 1 Y in for CCD (480i only) and Auto Link.
VIn5 Component 2 Y in for CCD (480i only) and Auto Link.
I001 - Microprocessor IC
Sub video in on pin 30 for CCD.
Main video in on pin 28 for CCD.
Component 1 vertical frequency detect on pin 10, from I015.
Component 2 vertical frequency detect on pin 11, from I016.
Component 1/2 horizontal frequency detect on pin 22, from I005.
SD Select out on pin 50 to control I005 during Sub picture changes; example PinP CH up or down.
Main/Sub SD detect in on pin 24 from I005.
Page 04-10
DP-0X SERIES CHASSIS SYNC SIGNAL PATH
Comp 2 H Out
Comp 1 H Out
30 SD Det
Micro 24
Processor
Composite 1 Aux Input 1 For 480i
V1 8 Comp SDA1 2
S Det. S-Y1 Sync Sep Comp 1
10 Only CCD
S-1 In S-C1 PST1
& V Chip
Aux Inputs
12 2 SCL1 3
I015
Composite 2 Aux Input 2 Comp1 In 22 8 1 Comp 1 4 10 Vert Freq
V2 1 Det Comp1
S Det. S-Y2
3 Sync Sep Comp 2
S-2 In S-C2
5
2 I016
Comp2 In 30 9 1 Comp 2 4 11 Vert Freq
Det Comp2
Q434 Q431
Component 1 Y Q021 Main for
28 CCD
PAGE 04-11
Page 04-12
DP-0X SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
U205 MHW
8 10 11
Flex Converter
16 MVW
See 7 12 13
Component 18 Q428
Signal Path
PTS3 I405 I409
1
20 SHW Sub H. Sync 2 4 2
15 2 1 1 15
1
SVW 2
Sub V. Sync 10 Select 4 H.Out
14 4 3 3 Sub I403
Sync 14
Sub Video/
Chroma
Sel. 40
PTS2 9 Select 4 V.Out
1
9 3 13
4
5
TERMINAL PWB 2
PAGE 04-13
Refer to the DP-05 and DP-05F Component Sync Separation Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Sync Separation Circuit
Diagram is;
• The DP-05 and DP-05F PinP circuit doesn’t route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through the
Selector IC.
• The Sub Component Selector IC (I407) is not used.
• The Sub Component Sync Separator IC (I408) is not used.
• The Sub Component or Main NTSC Sync Selection IC (I405) is not used.
PAGE 04-14
DP-05 and DP-05F SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
U205 MHW
8 10 11
Flex Converter
16 MVW
See 7 12 13
Component 18 PTS3
Signal Path I403
20 SHW Sub H. Sync H.Out
15 2 1 1 14
Sub Video/ 40
SVW Sub V. Sync V.Out Chroma
14 4 3 3 13
Preparation
IC
PTS2
9
TERMINAL PWB
See Sub Video
PAGE 04-15
Also connected to the ABL voltage line is DH33. This zener diode acts as a clamp for the ABL voltage. If the
ABL voltage tries to increase above 12V due to a dark scene which decreases the current demand on the
flyback, the ABL voltage will rise to the point that DH33 dumps the excess voltage into the 12 line.
Page 04-16
DP0X CHASSIS A.B.L. CIRCUIT DIAGRAM
QX13 SW +9V
PSZ2 RX34 IX01
RX32 RX33 RX35 DX05 RX37 ABL Rainforest
5 45 IC 2H Video
CX31 CX32 PWB
DX03 RX36
CX19 or
CX34 Signal Sub
PSZ1
PWB
SDA2
16 27 SDA2
SCL2
17 28 SCL2
See uP
Data
Signal TH01 To Anodes
Path High Voltage B+ 120V V2 B+
C To
Focus
CH25
ABL Pull-Up Resistors
Deflection PWB RH58 RH59 RH56
Deflection B+ 120V V1
[ Current Path ]
DH33
Sw +12V
PSD3
Clamp
CH31
1
PAGE 04-17
Signal
As Brightness goes Up, ABL Voltage goes Down. (Inverse Proportional)
PWB
Sweep Loss Detection Block Diagram Explanation
The key component in the Sweep Loss Detection circuit is QN04. This transistor is normally biased off. When
the base becomes more negative, it will be turned on, causing the Standby 11V to be applied to two different
circuits, the Spot circuit and the High Voltage Drive circuit.
SPOT CIRCUIT
When QN04 is turned on, the 11V standby will be applied to the anode of DN11, forward biasing it. This
voltage will then pass through DN11, get zenered by DN09, and go to pin 2 of PSD3, where it will activate the
Video Mute circuitry Q022 - Q024 on the Signal PWB. This is done to prevent CRT burn. Another input to
this circuit is the I701 DAC3 line. This will activate when accessing certain adjustment parameters in the
service mode; i.e. turning off vertical drive for making CRT drive or cut-off adjustments.
CONCERNING QN04
There are several factors that can affect the operation of QN04; namely loss of vertical or horizontal blanking
and spot killer or spot protect from a shutdown in the deflection power supply.
Page 04-18
DP0X SWEEP LOSS DETECTION CIRCUIT
SW+12V
Vertical RN05
RN03 RN04 QN02
Blanking See Deflection
From DN01 Power Supply
QN01 Circuit Diagram
Pin 11 I601
RN01
V. Blk. CN02
DN02 SPOTPROTECT
CN01
RN02 DN03
DN14
RN07
RN10 Stby 11V
SW+12V
RN09 QN04
Horizontal
Blanking DN04 RN06
CN03
DN05 High Voltage
From QN03 RN08 Driver IC
Q755 Emitter
IH02
CN04 QN05
DN06 RN15 DN13
H. Blk. 14 Stops
RN11 Drive
RN13
RN12
PAGE 04-19
ZP-04 (Zenith) Video Circuit Block Diagram Explanation
I401 - Luminance Audio Selector IC
Main Tuner (TV1V) in pin 63
Sub Tuner (TV2V) in pin 60
Video 1 in from Terminal PWB pin 8
S-Video 1 (Y) from Terminal PWB pin 10
S-Video 1 (C) from Terminal PWB pin 12
Video 2 in from Terminal PWB pin 1
S-Video 2 (Y) from Terminal PWB pin 3
S-Video 2 (C) from Terminal PWB pin 5
Video 3 in from Front Control PWB pin 15
S-Video 3 (Y) from Front Control PWB pin 17
S-Video 3 (C) from Front Control PWB pin 19
Yin1 PinP Luminance from 2L Comb filter pin 49
Cin1 PinP Chroma from 2L Comb filter pin 51
Page 04-20
ZP-04 SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)
Lum/Audio Selector IC
12
PST2 I201
Aux Input 2 Q402 Main Q216 Q235
Main
V2 1 V/Yout2 44 5 40 37
S Det. S-Y2 Y Y
3 /Video /Video
S-2 In S-C2 Q401 48
5 Main C
Cout2 47 7 6 47
Terminal PWB Main C
Q213 Q214
3 Line Comb Filter
Main
IJ01 IJ02 PYC1 Video/
QJ06 S-CIn
8 25 25 8 6 10 1 5 3 13 Chroma
QJ08 QJ07 QJ05
Page 04-21
QJ10
QJ02 9
QJ04 QJ01 Signal PWB 2 of 2
QJ09
QJ03 7
QJ12 QJ11
11
Video In
AUDIO
INFORMATION
SECTION 5
Audio Circuit Block Diagram Explanation
Page 05-01
DP-0X CHASSIS AUDIO SIGNAL PATH
(Main, Terminal & Audio Output)
Left Monitor Out
I401 38
PFV Terminal
Front Control PWB Right Monitor Out
3L PWB 40
8 16
Avx 3 In Aux Input 3
3R
7 18 Lum/Audio
Selector IC
TV 1 Left
27 16 62
U201 Tuner
1 of 2 TV 1 Right Audio
Main Tuner 26 17 64
PST1 PST1 Signal PWB 2 of 2 PSU1
I001 SCL1 SCL1
43 11 Select L Left Select
11
3 6 33 Main Audio
Microprocessor Select R Right Select
2 SDA1
5 SDA1 34 45 12 12
Aux Inputs
1R 11
2L 2
AVX 2 PinP 55 PST2
Signal PWB 1 of 2 2R 4 Mono PinP
Audio 1
3L 51 In 61
AVX 3 20U202
3R 49
PinP Tuner
Terminal PWB
PL Front Output IC
Front Left
FL Front Left F L Out
2 12 IC01 2
Woofer 8
Main Audio
4 Front Right F R Out
4 9
Tweet DC02 Front Speaker Off
PR
PAGE 05-02
Tweet
Surround Sound Circuit Block Diagram Explanation
IS19 - Perfect Volume IC
This IC receives main selected Left and Right audio and if the perfect volume feature is enabled via customer
controls, will act as a limiter/compressor to keep sound levels at the same relative level. Output is sent to the
DSP Module as well as to IS03 Front Audio Control IC.
IS02 - Buffer IC
This IC receives the Front Left and Front Right signals from the DSP on it’s non-inverting inputs and outputs
them to the Front Audio Control IC.
IS04 - Buffer IC
This IC receives the Front Left and Front Right signals from the Front Audio Control IC on it’s inverting inputs
and outputs them to the Front Audio Graphic Equalizer IC.
IS09 - Buffer IC
This IC receives each of the processed Center Channel and Subwoofer signals from IS08 on it’s inverting
inputs. The Subwoofer output is routed to QS18 and then on to the Subwoofer output connector. The Center
Channel output is sent to the Center Channel Graphic Equalizer IC IS10.
IS12 - Buffer IC
This IC receives the Rear Left and Rear Right signals from the Rear Audio Control IC on it’s inverting inputs
and outputs them to the Rear Audio Output IC.
Page 05-03
DP0X CHASSIS SURROUND AUDIO SIGNAL PATH
See Audio Signal Path (Main & Terminal)
PSU1 FL FR
Out to Hi-Fi
QS13 QS12 QS14 QS15 Out to Hi-Fi
FR FR IS05
9 19
Front 30
FL FL
8 12 Graphic 1
FL 20 EQ
FR 11 IS03
PMU2 PMU3
Front
Audio
L FL IS02 Control IS04
11 1 IS19 3 1 1 6 - FL 6 - FL
Perfect 17 7
5 + 2 5 +
Volume FR FR
R 3 + 9 3 +
FR 14 1
12 10 8 3 2 2 - 2 -
S QS01
6 - G
+ 7 SW Sel 1
Coaxial Input Digital 5 D
Board Gnd IS06 - 2 14 SW
11 Optical Input HC4051 1 +
3
IS08 IS09 QS18 Sub Woofer
Gnd 9 3 +
QS01 1
IS18 JS03 SW Sel 2
- 3 2 -
1 + Center/
2
8 3 IS07 Sub IS10
2X SW 6 6 -
Center
PMU4 + 7 Woofer CL 6 - Cent.
Invert Sub Woofer Gnd 5 7 1 12
3 Audio 2 5 + Graphic
12 C 5 17 Control EQ
Center
IS17 FPFRX
5 3 IS11 IS16 SP PCR IS15
IS12
Digital Output Rear 6 - SL Rear 12 Cent 4
SL 3 17 7 2 1 2 7
to DSP Audio 2 5 + Audio Audio
Control 9 3 + SR Output PCL Output
Actual Input Coax SR 4 14 1 4 7 2 2
2 - IC 1 12 IC
Invert 1
QS10 QS06
PAGE 05-04
IA06 - Buffer IC
This IC receives the Front Left and Front Right signals from the Front Audio Control IC on it’s inverting inputs
and the outputs are sent back to the Signal PWB via the PSU1 connector to the Front Audio Output IC.
Page 05-05
DP-05 AND DP-05F CHASSIS SRS AUDIO SIGNAL PATH
PSU1
FR
9
FL
8
IA06
IA03 IA05
See Audio Signal Path (Main & Terminal)
IA02 6 - FL
7
L Perfect SRS FL 5 5 +
11 1 Volume 3 22 14 2 Front
Audio
R FR Control 18 3 +
1
FR
12 10 8 21 13 21 2 -
11 12
10 11
SRS LOGIC
MODE MODE 1 QA07 QA08 FL
BYPASS (SRS Off) L Out to Hi-Fi
SRS SOUND H
MODE MODE 2
SRS STEREO L QA09 QA10 FR
SRS MONAURAL H Out to Hi-Fi
SRS1
SCL2 IA01 4
1 2
DAC3 SRS2
SDA2
2 3 5
PAGE 05-06
DIGITAL
CONVERGENCE
INFORMATION
SECTION 6
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
Use this explanation in conjunction with the Digital Convergence Interconnect circuit diagram.
The Digital Convergence circuit is responsible for maintaining proper convergence of all three colors being pro-
duced by the CRTs. Many different abnormalities
The Digital convergence Interconnect Diagram depicts how the Digital Convergence Circuit is interfaced with the
rest of the Projection’s circuits. The main components and/or circuits are;
• THE DIGITAL CONVERGENCE UNIT (DCU)
• INFERRED REMOTE RECEIVER
• ON SCREEN DISPLAY PATH
• CONVERGENCE OUTPUT STKs
• CONVERGENCE YOKES
• MAGIC FOCUS SENSORS AND INTERFACE
• MICROPROCESSOR
• RAINFOREST IC (Video Processor).
• SERVICE ONLY SWITCH
• MAGIC FOCUS SWITCH
Technician's Eye
SCREEN
Adjust through observation
M
IR
RO
Light
R
Stored during Initialize
Stored Light Sensor Data
Remote EEPROM Timing
Control 2K Bit Controller
CLAMP
1st S/H
LPF
AC Applied, Copy from EEPROM, then caculations will be made. Time, approx. 20 sec.
Figure 1
The Block above shows the relationship of the DCU to the rest of the set. Note that the light being produced by
the CRTs is what is used by the sensors for Magic Focus. This allows the DCU to make adjustments regardless of
circuit changes, by actually using the light on the screen to make judgments.
PAGE 06-01
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
(Continued from page 1)
represents a specific correction signal for that specific location. When the Service Technician makes any adjust-
ment, the new information must be stored in memory, EEPROM. The EEPROM only stores the 117 different ad-
justment points data, the SRAM interpolates to come up the additional 139 adjustment points for a total of 256 per
color. The EEPROM data is slow in relationship to the actual deflection raster change. The SRAM is a very fast
memory. So, during the first application of AC power, the EEPROM data is read and the SRAM makes the inter-
polation and as long as power remains, interpolation no longer has to be made.
This can be seen during an adjustment. If the Interpolation key is pressed on the remote control, what is happen-
ing is that the SRAM must make those additional calculations beyond the 117 made by the Servicer and this is all
placed into memory.
(Continued on page 3)
PAGE 06-02
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
(Continued from page 2)
MAGIC FOCUS SENSORS SHOWN ON FIGURE 1:
This process is a joint effort between the digital convergence module and 8 Photo-sensors, physically located on
the edge of the cabinet, just behind the screen. The physical placement of the sensors assures that they will not
produce a shadow on the screen that can be seen by the customer.
Magic Focus is activated when the set is on and by pressing the Magic Focus button inside the front control
panel door. An on-screen graphic will be displayed to confirm that the automatic convergence mode (Magic Fo-
cus) has begun.
The digital convergence module produces different patterns for each CRT, and the sensors pick up the transmitted
light, generate a DC voltage. This voltage is sent to the DCU and converted to digital data and compared with the
memorized sensor initialization data. Distinct patterns will be generated in each primary color. As the process
continues, the digital module manipulates the convergence correction waveforms that it is producing to force the
convergence back into the original memorized configuration.
When all cycles have been completed, the set will return to the original signal and the convergence will be
corrected. In most cases, activating the Magic Focus will allow the set to correct itself, without further
adjustments.
OUTPUT STKs:
These are output amplifiers that take the correction waveforms generated by the DCU and amplify them to be
used by the Convergence Yoke assemblies for each color.
RV is Red Vertical Convergence correction. Adjust the location either up or down for Red.
RH is Red Horizontal Convergence correction. Adjust the location either left or right for Red.
GV is Green Vertical Convergence correction. Adjust the location either up or down for Red.
GH is Green Horizontal Convergence correction. Adjust the location either left or right for Red.
BV is Blue Vertical Convergence correction. Adjust the location either up or down for Red.
BH is Blue Horizontal Convergence correction. Adjust the location either left or right for Red.
(Continued on page 4)
PAGE 06-03
DIGITAL CONVERGENCE INTERCONNECT DESCRIPTION
(Continued from page 3)
CONVERGENCE YOKES:
Each CRT has a Deflection Yoke and a Convergence Yoke assembly. The Deflection manipulates the beam in
accordance to the waveforms produced within the Horizontal Deflection circuit or the Vertical Deflection circuit.
The Convergence Yoke assembly manipulates the Beam in accordance with the correction waveforms produced
by the DCU.
MICROPROCESSOR:
The Microprocessor is only involved in the Digital Convergence circuit related to IR (Inferred Remote Control
Signals). When the DCU is put into the Digital Convergence Adjustment Mode, DCAM, the Microprocessor ig-
nores IR pulses. This is accomplished by the Busy signal from the DCU.
PAGE 06-04
DP-0X CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
Memory SDA 1
PSZ1 2H Video PWB
5 QX07
IX01 PZC
I002 6 I001 OSD B 39
OSD B
14 14 Rainforest QX41
OSD G QX08 41 5 B
OSD G 38 16 16
SCL 1 OSD R QX09
QX36
To CRTs
OSD R 37 18 18
SDA1
I004 14 2
QX01 42 3 G
DAC2
Main Dig OSD R
Dig OSD G
8
QX02
8
15 3 SCL1 QX31
10 IR In Up Dig OSD B
10
QX03
10
43 1 R
1 IR 12 12
Signal PCB
+28P +33V
S0 S0 Mute
12 9 9 1 IK02 2 +28V
10
3
Deflection PWB 11
DP-05, DP-05F, DP-06, DP-07 REMOTE CONTROL CLU-572 TSI
Used with
43FDX01B, 53FDX01B, 000
7 8 9
RED (7 X 5)
LAST
SLEEP 0 CH
RASTER PHASE
C.C. HELP ASPECT
C.S.
INPUT
BLUE (13X9)
CROSSHATCH
U EXIT
MEN VIDEO
REMOVE
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
SV
MUT
E REC
ALL GREEN (3 X 3)
CS HD
SC
VCR
/TV
PLU IDE
S+ INFO GU
CALCULATE
CENTERING
PIP PIP CH FRZ
READ OLD
INITIALIZE PIP-MODE SWAP ROM DATA
PIP MODE + PRESS (2X)
PIP CH PROG TV/VCR SLOW
WRITE TO
ROM
REC
PRESS
(2X)
HITACHI
CLU-572TSI
PAGE 06-06
AP-93R REMOTE CONTROL CLU-573 TSI
000
CURSOR
1 2 3
POSITION
BUTTONS 4 5 6
RED
7 8 9
7X5
LAST
SLEEP 0 CH RASTER
PHASE
BLUE INPUT
HELP
C.S.
13X9
CROSSHATCH
U EXIT
MEN VIDEO
REMOVE
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
GREEN
MUT ALL
SV E REC 3X3
CS HD
SC
VCR V
/T
PLU IDE
S+ INFO GU
CALCULATE
PIP PIP CH FRZ
CENTERING
SWAP
READ FROM
INITIALIZE MOVE
ROM
PROG TV/VCR SLOW
WRITE TO
ROM
REC
HITACHI
CLU-573TSI
PAGE 06-07
DP85 SERIES CHASSIS "CLU-614MP" REMOTE CONTROL
REMOTE PERSONALITY WHILE IN THE
DIGITAL CONVERGENCE ADJUSTMENT MODE D.C.A.M.
AUDIO
"ANT" = "PHASE"
* (Aligns Cursor to Grid)
LAST
PAGE 06-08
CLU-436UI REMOTE CONTROL FOR AP-91 and AP-01 CHASSIS
Used With
50DX01B, 50EX01B, POWER
60EX01B, 43GX01B,
46GX01B, 50GX20B
TV CABLE VCR
Phase
PIP SWAP MOVE FRZ
FRZ: Raster Position
REC PAUSE
STOP
INPUT EXIT
LST-CH
CURSOR CONTROL
RECALL:
L
I
G
1 2 3 H 2: Cursor Up
I
5: Cursor Down
7 8 9 0:
HITACHI
CLU-436UI
PAGE 06-09
DP-05 and 05F DIGITAL CONVERGENCE CIRCUIT DIAGRAM EXPLANATION
PAGE 06-10
DP-05 and 05F CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
Memory PSZ1 2H Video PWB
5
SDA 1
I001 OSD B 39 OSD B QX07
IX01 PZC
I002 6 14 14 Rainforest QX41
B
SCL 1
Main Up OSD G 38 OSD G
OSD R
16
QX08
16
41 5
QX09 QX36
To CRTs
SDA1 OSD R 37 18 18
I004 14 2 Dig OSD R
8
QX01
8
42 3 G
DAC2 15 3 SCL1 Dig OSD G QX02 QX31
IR In 10 10
Dig OSD B QX03 43 1 R
10 1 IR 12 12
Signal PCB
PWB Signal PWB -5V 1 PDC +28P 10 CYV+
PDG BV 9 2
2 +33V 5
Deflection PWB BV + - CYV-
+5V 3 1 8 7 1
BUSY BH CYH-
IR Receiver 2 14 13 3
1 D Size 6
3 2 1
QM01
PFS Dig R QK06 18
2 V Sync 7 GV
IR-In
2 3 8 GV + - PCG
IR-In Dig G 4 15 16
Stby +5V QK07 2
4 9 CYV+
3 17 8 12 4
Static Conv.
5 10
9 Dig B 1
QK08 Digital CYV-
SM09 6 11
MAG SW
5 7 12 Convergence -28P -33V
Ft. Control Unit
"Mounted on GH
9
CYH+
4
Deflection GH + -
5 6 7 PCR
PWB" IK04 CYV+
6 31/33 11 2
RV
+ - CYV-
RV
7 14 13 1
CYH+
3
DEFLECTION
CIRCUIT
INFORMATION
SECTION 7
DEFLECTION DRIVER IC (I701) B+ GENERATION DESCRIPTION
DEFLECTION DRIVER IC B+ GENERATION CIRCUIT:
(See the Deflection Vcc Production Circuit Diagram for Details)
EXPLANATION:
The B+ for the Deflection Driver IC (I701) is switched On and Off with the TV. Control for this process is pre-
formed by the Microprocessor On/Off (Power On/Off) pin.
The Power On/Off pin (53) of the Microprocessor I001 is High when the set is turned On. This High is sent to the
low voltage Power Supplies on the Signal PWB via Q003 and Q004. This turns on the +9V Regulator I009, the
SW+5V Regulator I010 and the +5V Regulator IS13 on the Surround PWB.
The High from the Microprocessor is also routed through the Relay Driver transistor Q002 and inverted to a Low,
then through the connector PQS1 pin (8), to the Sub Power Supply. (Also called the Low Voltage Power Supply
PWB). Here it turns on the necessary circuits for the Sub Power Supply. (See the Power On/Off Circuit Descrip-
tion for detail).
This Low is now routed through the connector PQD2 pin (1), to the Deflection PWB. The Low forward biases
DP21 and pulls the base of QP04 Low which turns it On. The emitter of QP04 is connected to the Stby +11V
power supply via the connector PQD2 pin (3). When QP04 turns On, the collector goes high and is routed
through DP35 and DP36 to pin (8) of I701, the Horizontal Driver IC. When B+ is applied, the Driver IC begins
producing Horizontal Drive for the Deflection Circuit.
(See Deflection Circuit description for more details).
PAGE 07-01
DP0X DEFLECTION Vcc PRODUCTION CIRCUIT
I701
HVcc 8
SUB DEFLECTION
PWB
PAGE 07-02
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
HORIZONTAL DRIVE CIRCUIT DIAGRAM DESCRIPTION:
(Use the Horizontal Drive Circuit Diagram for details)
CIRCUIT DESCRIPTION
When B+ arrives at the Horizontal Driver IC I701 pin (8), horizontal drive is output from pin (15). The drive sig-
nal is routed to the Horizontal Driver Transistor Q751. This transistor switches the ground return for pin (8) of the
Driver transformer (T751). 28 volts is supplied to pin (5) and this switching allows EMF to develop. As this sig-
nal collapses, it creates a pulse on the output pin of (T751) at pin (4) to the base of the Deflection Horizontal out-
put transistor Q777. This transistor switches the primary windings of the Deflection Transformer T752.
This transformer produces the following output pulses;
• Deflection Pulse from pin (7): This pulse is used by;
1. The Side Pin Cushion Circuit: The Side Pin Cushion circuit for pin cushion correction.
2. The DF OUT Circuit: Generated from the Horizontal Blanking pulse. A Dynamic Focus waveform is
created. This is a parabolic waveform that is superimposed upon the static focus voltage to compensate
for beam shape abnormalities which occur on the outside edges of the screen because the beam has to
travel further to those locations.
3. To X-Ray Protect: This signal is monitored by the X-Ray Protect circuit to place the power supply into
shut down if the Deflection circuit doesn’t operate.
• +28V, M26V and RETRACE PULSE +28P and M28P: The positive 28V and the negative 28V is routed
to the Deflection transformer I752. They enter the transformer as a pure DC voltage then a 7.5V P/P horizon-
tal pulse is added to the DC voltage and leaves as +28P and M28P. From here these voltages are routed to the
Convergence output section and they are rectified. They become +33V and -33V respectively. This process
prevents the need for another power supply. (Note: the M stands for Minus voltage.)
Deflection Pulse from pin (7): The Horizontal Pulse is also routed to the Horizontal Blanking generation transis-
tor Q755. This transistor generates the 13V P/P called H Blk. This signal goes to the following circuits;
• To pin (10) of I701 as FBP In. Here this signal is used as a comparison signal. It is compared to the refer-
ence signal coming in at pin (3) Horizontal Sync. If there are any differences between these two signals, the
output Drive signal from pin (15) is corrected.
• To the Convergence circuit for correction waveform generation.
• Sweep Loss Circuit to shut off the CRTs if Horizontal deflection is lost.
• Through the connector PSD3 pin (6): The H Blk signal is routed from here to the Signal PWB to be used by
different circuits.
The Microprocessor uses this signal for OSD positioning and for Station Detection during Auto programming
within the coincidence detector.
The PinP unit uses this signal for switching purposes. Like the read/write clock, positioning, etc…
The Horizontal Blanking signal H Blk from Q755 is also sent to the High Voltage Driver IC IH01 pin (3). This
IC uses this signal as its reference signal to produce the High Voltage Drive waveform output from pin (1). This
output is routed to the driver transistors, QH08, QH09 and QH10. Then to the High Voltage Horizontal Output
Transistor QH01. This transistor switches the primary of the Flyback transformer TH01. 120V2 is sent through
pin (2) and output pin (10) to the collector of the Horizontal Output Transistor QH01.
A sample of the High Voltage is output from the Flyback transformer TH01 pin (12). This voltage is sent to pin
(9) of the High Voltage Driver IC IH01. This voltage is compared to the reference voltage available at pin (12). If
there is a difference between the two voltages, an error voltage is generated and output from pin (10) and input
again at pin (11) where it manipulates the PWM (Pulse With Modulation) signal producing the Horizontal Drive
signal output from pin (1).
It’s important to notice that the High Voltage circuit can not function without the Horizontal Deflection circuit
providing a drive signal.
PAGE 07-03
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
GENERAL INFORMATION:
The DP-0X deflection circuit differs from conventional Hitachi product. It utilizes in a sense, two horizontal out-
put circuits. One for Deflection and one for High Voltage. There are many terms around the Horizontal circuit
that are not shown on the Diagram. Some of these terms are explained first:
CUT OFF:
Cut of collapses the Vertical circuit during I2C Bus alignments, during CRT Set Up.
I2C:
Communication from the Microprocessor I001 to I701 during sweep variations due to Standard/NTSC 480P
(Progressive mode) and 1080I High Definition mode, (HD) and Service Adjustments.
ABL:
ABL voltage is generated by monitoring the current through the Flyback transformer. This voltage will fluctuate
down when the scene is bright and up when the scene is dark. The ABL voltage will manipulate the screen bright-
ness and contrast to prevent blooming under these conditions.
HV SYNC:
The composite sync is routed to the Sync processor inside the Horizontal Driver IC I701 which determines the
sweep frequency for the signal being provided. (Everything but HD is 31.5KHz and HD is 33.75KHz).
H and V BLK:
• H Blk: Horizontal and Vertical Blanking is developed within the Deflection circuit. The Horizontal Blanking
pulse operates around 13V P/P and is produced by taking a sample pulse from the Deflection transformer
T752.
• V Blk: The Vertical Blanking pulse is generated from the Vertical output IC, I601 pin (11). This pulse nor-
mally operates at 23V P/P.
IR:
The Infrared Pulses coming from the remote control are routed through the Deflection PWB to the Digital Con-
vergence Unit. During DCAM (Digital Convergence Adjustment Mode), the Remote Control provides manipula-
tion pulses for the DCU.
MAGIC SW:
When the customer presses the Magic Focus button on the front of the set, it produces a command for the DCU to
begin the Magic Focus process.
(Continued on page 5)
PAGE 07-04
HORIZONTAL DRIVE CIRCUIT DESCRIPTION
(Continued from page 4)
D SIZE:
Digital Size is a control signal for raster enlargement when MAGIC FOCUS is operated. Raster enlargement is
required for the MAGIC FOCUS PATTERN to hit the photo sensors.
This signal is output from DCU and routed to the base of Q613 for enlarging horizontal size through the Pin
Cushion circuit and through Q608 to the Vertical Output IC I601 pin (4) to enlarge the vertical size.
In case of AP-85, this control signal is called "A.SIZE". It's the same function between DIG.SIZE and A.SIZE.
31/33:
31/33 represents the actual Deflection Frequency; 31 = 31.5KHz and 33 = 33.75KHz. The microprocessor knows
the actual frequency of the incoming signal via Sync supplied.
• To the Horizontal Driver IC I701: This tell the Driver IC what output frequency to operate at.
• To the DCU: This signal is sent to the DCU to tell it what frequency the Deflection circuit is running at so it
will know what memory to use. The DCU has two different memory modes. One for Progressive mode
31.5KHz and one for HD mode 33.75KHz.
• To the Dynamic Focus Circuit: This signal is also sent to the Dynamic Focus circuit Horizontal Parabola
generation circuit to compensate for the higher frequency.
TO CONVERGENCE YOKES:
The DCU provides compensation signal for deflection abnormalities to the convergence output IC. The Conver-
gence output IC in turn, amplify the signals and rout them to the convergence yokes.
+B 120V1:
The Deflection transformer receives the 120V V1 DC source.
+B 120V2:
The High Voltage Transformer TH01 (Flyback) receives the 120V V2 DC source.
HV PARABOLA:
See DF Out.
FOCUS 9KV:
Focus voltage supplied to the CRT’s.
30Kv HV:
32,000 volts DC supplied to the CRT’s anodes.
TO DEFLECTION YOKES:
Horizontal and Vertical deflection wave forms driving the deflection yokes.
PAGE 07-05
DP0X SERIES CHASSIS HORIZONTAL DRIVE CIRCUIT
H. Def. Yoke R
I701
HVCC
10 FBP In VCC 8 Switched AVCC
H. Def. Yoke G
H. Def. Yoke B
HVCO 7
Osc.
15 H Out
HD 3 H. Sync In
To Side Pin Circuit
11 E 12
r Ref. V.
r FBP In
o HV Sample
PAGE 07-06
10 r 9 12
ADJUSTMENT
INFORMATION
SECTION 8
DP-0X CHASSIS FACTORY RESET CONDITION
AUDIO
MTS Mode STEREO
PERFECT VOLUME OFF
AUTO NOISE CANCEL OFF
LOUDNESS OFF
DYNAMIC BASS OFF
THEATER MODE SPORTS
FDX CHASSIS
BASS 1/2
TREBLE 1/2
BALANCE 1/2
SRS OFF
PAGE 08-01
DP-0X CHASSIS FACTORY RESET CONDITION
PAGE 08-02
DP0X CHASSIS SIGNAL PWB
MICROPROCESSOR
PFS
IC01
PR
I001
PP1
PL 2H
VIDEO
PWB
DIGITAL BOARD
HC4051
I012
I007
I010
U205
FLEX
U201 U202 U204
Conv.
Main PinP 3D/
and
Tuner Tuner YC
PinP
Unit
QS4
TERMINAL PWB
REAR
VIEW
PAGE 08-03
DP0X CHASSIS DEFLECTION PWB
CONVERGENCE
HEAT SINK
SK01: Digital
SERVICE Convergence Unit
IK04 IK05
SWITCH
PSD1
IK01
QF06
QH01
YOKE PLUGS
TH01
REAR
VIEW
PMR
R630 PMG
FBT
V.Size
Adj. PMB D656
D657 RH44
R686
High Voltage ADJ.
H.Size
Q657 RH44
Adj. HD
DP37
R683 DP29 Red LED
H.Size +B 120V Green LED
D752 Q777
Adj.
DP01
PQD2
IP01
PQD1
TP91
PDC1
Q701
I601
PAGE 08-04
DP0X CHASSIS CONTROL PWB
CH -
VOL VOL
MENU/
DOWN POWER
UP SELECT
INPUT
EFC1
CH +
R L V REMOTE CONTROL
S LIGHT RECEIVER
AUTO DIGICON
MO1 (MAGIC FOCUS) HM01
DM09
QM02
FT FS
PAGE 08-05
DP0X CHASSIS SUB POWER PWB
1 9 1 10 7 1
PQU1 PQS1 PQD2 PQD1 PA
2 1
2 1
PQS2 PQU2
1 11 1 8 F901
6 Amp
D913
Audio R/C SW +29V
GREEN
3
PQS4
D912
Audio F SW +29V 1
S901
GREEN
I905
D901
D927 REAR
STBY +7V VIEW
GREEN
D903
IC POWER
D931 MONITOR RED
I907 SW +5V
GREEN
D949 I901
STBY +11V
GREEN
I906
T901
SWITCHING
S904 TRANSFORMER
S903
S902
PAGE 08-06
DP-0X CHASSIS CRT PWB
PGV
SHORT TO
P851
R879 KILL THE
COLOR
GND PTSG
P852
E831
Cathode
GREEN
W801
PRV
P801 SHORT TO
KILL THE
R829 COLOR
GND PTSR
E801 P802
Cathode
RED
W801
PVB
P8A1 SHORT TO
KILL THE
PTSB COLOR
GND
P8A2
E8A1
CATHODE
BLUE
PAGE 08-07
DP-0X CHASSIS CLOCK SPEED ACCELERATION PROCEDURE AND CHECK
Use the Clock Speed acceleration to confirm, clock advancement, On/Off Timer, etc.
1) Select Set Up from the Main Menu the Cursor Left and Cursor Right Buttons.
2) Select Clock Set using the Cursor Up and Cursor Down Buttons.
3) Press the Cursor Right button to select Clock Set
4) Set the clock using the Cursor Up, Cursor Down, Cursor Right buttons. The clock is started when
the Cursor Left button is pressed.
5) Connect the JIG (Diode) shown below between I001 Pins 13 and 35.
6) Check that the clock indicaiton is displayed using the RECALL button and the clock is advancing
1 minute per second.
Diode
13 35
DSP SO I Ref
I001
MicroProcessor
PAGE 08-08
DP-0X CHASSIS HIGH VOLTAGE ADJUSTMENT PROCEDURE
1) Connect High Voltage meter to 3) Receive an NTSC generator 6) Lock Paint the control. If avail-
FBT High Voltage output. signal. (Picture should be sta- able.
Connect Ground of High Volt- tionary for this adjustment.
age meter to CRT Ground or 4) Video Controls should be set to
FBT Ground. Factor Settings.
2) Check that the High Voltage 5) Adjust the High Voltage to the
adjustment VR (RH44) is set to following specifications by
it’s mechanical center on the turning RH44 slowly.
Deflection PWB. This VR is • ADJ. SPEC. = 31.5 kV +/ - 0.5
located just behind the Flyback kV for (DP07)
transformer as viewed from the • ADJ. SPEC. = 30.0 kV +/ - 0.5
Front of the set. (See diagram kV for (DP05/DP05F and
below) DP06)
CONVERGENCE
TH01
HEAT SINK
FBT
RH44
High Voltage ADJ.
PAGE 08-09
DP-0X CHASSIS HIGH VOLTAGE LIMITER CHECK
CH30 RH54
DH31
RH55
PAGE 08-10
DP-0X CHASSIS FLYBACK PROTECTION CIRCUIT CHECK
PAGE 08-11
DP-0X CHASSIS SWEEP LOSS DETECTION CIRCUIT CHECK
CN01 CN04
QN01 RN01
QN05 RN11
RN02 RN12
A B
Add JIG to check Hi Add JIG to check Hi
Volt Limit Circuit Volt Limit Circuit
JIG = 100 ohm 1/8W JIG = 100 ohm 1/8W
PAGE 08-12
DP-0X CHASSIS VOLTAGE CHECK
PAGE 08-13
DP-0X MAGNET AND YOKE LOCATION
DP-0X MAGNETS
Adjustment Points
1 2 3
FRONT
4
4 6
4
5
5
5
PAGE 08-14
DP-0X CHASSIS ADJUSTMENT ORDER
PAGE 08-15
DP-0X CHASSIS PRE-HEAT RUN ADJUSTMENTS
on Blue CRT).
Pre set between the 12
o’clock and 2 o’clock
position.
2) SCREEN VR ON
FOCUS PACK.
Pre Set fully counter
SCREEN VR
clockwise.
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 08-16
DP-0X CHASSIS CUT-OFF (SCREENS) ADJUSTMENT
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 08-17
DP-0X CHASSIS PRE-FOCUS ADJUSTMENT
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 08-18
DP-0X CHASSIS DCU CROSSHATCH PHASE ADJUSTMENT
PAGE 08-19
DP-0X CHASSIS HORIZONTAL PHASE (COARSE) ADJUSTMENT
Adjustment Preparation: 5) Enter the I 2C Bus align- 5) Enter the I 2C Bus align-
1) Cut Off, DCU Phase ad- ment menu and select ment menu and select
justments should be fin- Item [12] H POSI and ad- Item [12] H POSI and ad-
ished. just the data so that the just the data so that the
2) Video Control: Brightness center of Video matches center of Video matches
90%, Contrast Max. the location of the Digital the location of the Digital
Crosshatch pattern noted Crosshatch pattern noted
Adjustment Procedure in step {4}. in step {4}.
PROGRESSIVE MODE: 6) Exit from the I C Menu. 6) Exit from the I2C Menu.
2
PAGE 08-20
DP-0X CHASSIS TILT (RASTER INCLINATION) ADJUSTMENT
l =< 2mm
PAGE 08-21
DP-0X CHASSIS BEAM ALIGNMENT ADJUSTMENT
Preparation for adjustment: 2) Put Green (G) tube beam align- 8) Conduct beam alignment for
1) Pre Heat, Pre-optical focus, ment magnet to the cancel state Red and Blue in the same way.
DCU Phase Data, H. Pos as shown in Figure 1. (See Fig- 9) Red (R) focus on focus pack.
Course and Raster Tilt adjust- ure 1.) 10) Blue (B) focus on focus pack.
ment should be completed. 3) Turn the Green (G) static focus 11) Upon completion of adjust-
2) Brightness: 90% VR counterclockwise all the ment, place a small amount of
Contrast Max. way and make sure of position white paint on the beam align-
4) Receive cross hatch signals, or of cross hatch center on screen. ment magnets, to assure they
dot pattern 4) Turn Green (G) static focus VR don’t move. (If available).
RASTER TILT adjustment clockwise all the way.
should be finished. 5) Turn two Beam alignment mag-
5) SCREEN FORMAT should net in any desired direction and
be PROGRESSIVE mode. move cross hatch center to posi-
Adjustment procedure: tion found in step (3). (See Fig-
1) Green (G) tube beam alignment ure 2 below).
adjustment: 6) If image position does not shift
Short-circuit 2P subminiature when Green static focus VR is
connector plug pins of Red (R) turned, adjustment complete.
and Blue (B) on the CRT boards 7) If image position does move,
and project only Green (G). repeat steps [2] through [6].
ADJUSTMENT
Figure 1 TABS BEAM SHAPE &
PICTURE TUBE SIDE ALIGNMENT MAGNET
PAGE 08-22
DP-0X CHASSIS RED AND BLUE RASTER OFF SET ADJUSTMENT
INFORMATION:
Raster Off set is necessary to conserve Memory allocation.
It is very important to remember that the Red is off-set Left of Center and Blue is off-set Right of center.
Please use the following information to accurately offset Red and Blue from center.
Also see Overlay Dimensions for further details.
Red Blue
Geometric Center
PAGE 08-23
DP-0X HORIZONTAL SIZE ADJUSTMENT
53 Inch 1050 +/- 5mm 1050 +/- 5mm 1050 +/- 5mm 1050 +/- 5mm 1135 +/- 5mm 1135 +/- 5mm
46 Inch - - - - - -
HORIZONTAL SIZE
l
Between Outside Lines
PAGE 08-24
DP-0X VERTICAL SIZE ADJUSTMENT
VERTICAL SIZE: 2) Press “Power Off” to exit NOTE: The Vertical Fre-
(Display Mode PROGRES- Service Menu. quency is shared between
SIVE or HD) Vertical rate Progressive and HD modes.
stays the same. NOTE: Centering magnet
may be moved to facilitate. Alternate Method:
1) Adjust using R630 Distance is important, not Adjust Vertical Size until the
(Vertical Size Adj. VR) to centering. size matches the chart below.
match marks on the Over-
lay. (See Figure Below)
L= DP06 DP05/05F DP07
53 Inch 670 +/- 5mm 670 +/- 5mm 550 +/- 5mm
46 Inch - - -
VERTICAL SIZE
PAGE 08-25
DP-0X BEAM FORM ADJUSTMENT
BEAM SHAPE (FORM) Adjustments procedure: 5) Also adjust the Red and Blue
Preparation for adjustment 1) Green CRT beam shape adjust- CRT beam shapes according to
IMPORTANT: Screen format ment. the steps (1) to (3).
should be “PROGRESSIVE“. 2) Short-circuit 2P sub-mini con- 6) After the adjustment is com-
1) Pre Heat, Cut-Off, Pre-optical nectors on Red and Blue CRT pleted, return R, G and B static
focus, DCU Phase Data, H. Pos PWB to project only the Green VRs to the Best Focus point.
Course, Raster Tilt, Beam beam.
Alignment, Raster Position, 3) Turn the green static focus VR
Vertical and Horizontal Size fully clockwise.
adjustment should be com- 4) Make the dot at the screen cen-
pleted. ter a true circle, using the 4-Pole
2) Brightness: 90%, Contrast: magnet shown in (Figure 2 be-
Max. low.)
3) Input a NTSC DOT signal.
ADJUSTMENT
TABS
PICTURE TUBE SIDE
a 2-POLE BEAM
ALIGNMENT MAGNET
Figure 1 Figure 2
PAGE 08-26
DP-0X LENS FOCUS ADJUSTMENT
Preparation for adjustment 7) (See Figure 1) Loosen the 9) After completing optical
fixing screw on the lens focus, tighten the fixing
1) Receive the Cross-hatch assembly so that the lens screws for each lens.
pattern signal. cylinder can be turned. 10)When adjusting the Green
2) The electrical focus adjust- (Be careful not to loosen Optical focus, be very
ment should have been the screw too much, as careful. Green is the most
completed. this may cause movement dominant of the color guns
3) Deflection Yoke tilt of the lens cylinder when and any error will be eas-
should have been adjusted. tightening.) ily seen.
4) Brightness = 50% 8) Rotate the cylinder back 11)Repeat Electrical Focus if
5) Contrast = 60% to 70% and forth to obtain the best necessary.
focus point, while observ-
Adjustment procedure ing the Cross-Hatch.
(Observe the center of the
6) Short the 2 pin sub- screen).
miniature connector on the
CRT P.W.B. TS, to pro- • Hint: Located just below
duce only the color being the screen are the two
adjusted and adjust one at wooden panels. Remove
a time. (The adjustment the panels to allow access
order of R, G and B is just to the focus rings on the
an example.) Lenses.
FIXING SCREW
r
de
in
yl
C
ns
Le
LENS ASSEMBLY R, G, B.
Figure 1
PAGE 08-27
DP-0X STATIC FOCUS ADJUSTMENT
Screen VR
Screen VRs
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 08-28
DP-0X BLUE DE-FOCUS ADJUSTMENT
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 08-29
DP-0X WHITE BALANCE ADJUSTMENT
Note: When Vertical is collapsed, make adjustments quickly, the image can burn the CRTs.
White balance adjustment 3) Gradually turn the screen 6) Turn the Brightness and
1) Screen adjustment adjustment VRs (red, Contrast OSD all the way
2) High brightness white green, blue) clockwise and up.
balance set them where the red,
3) Low brightness white green and blue lines are 7) Make the whites as white
balance equal and just barely visi- as possible using the drive
ble. adjustment VRs (Red
Adjustment VRs: 4) Return Service item on I 2C R829 and Green R879).
Screen adjustment VRs on ADJ to Off by Cursor 8) Set the Brightness and
Focus Block Right. Number [2]. Contrast to minimum.
Drive adjustment VRs on Adjust the Sub Brightness (10800 Kelvin)
CRT P.W.B. Number [1] SUBBRT us- 9) Adjust the low brightness
Red Drive = R829R ing I2C Bus alignment areas to black and white,
Green Drive = R879G procedure so only the using screen adjustment
Preparation for adjustment slightest white portions of VRs (red, green, blue).
1) Start adjustment 20 min- the raster can be seen. 10) Check the high brightness
utes or more after the 5) Input a gray scale signal whites again. If not OK,
power is turned on. into any Video input and repeat steps 6 through 9.
2) Turn the brightness and select that input using the 11) Press the MENU key on
black level OSD to mini- INPUT button on the re- remote to Exit Service
mum by remote control. mote or front control Menu.
3) Receive a tuner signal, panel.
(any channel, B/W would
be best).
4) Set the drive adjustment
Screen VR
VRs (Red R829R and Screen VRs
Green R879G) to their me-
R G B
chanical centers. Focus VR
Focus VRs
Adjustment procedure R G B
played.)
2) Choose SERVICE item
Number [2] of I2C ADJ.
Mode. (Select ON by Cur-
sor Right and the Vertical
will collapses).
PAGE 08-30
DP-0X SUB BRIGHTNESS ADJUSTMENT
Note: When Vertical is collapsed, make adjustments quickly, the image can burn the CRTs.
W Y CY G MG R BL
75% The background is set to black.
Perform the adjustment without
A7 A6 A5 A4 A3 A2 A1
observing the boundary parts.
B
The background is set to lighter
black.
D
Q I W 100% BLK
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 08-31
DP-0X HORIZONTAL POSITIONS (FINE) ADJUSTMENT
Adjustment Preparation: 4) Adjust the data so that the 3) Enter the I 2C Bus align-
1) Video Control: Brightness Left and Right hand side ment menu and select Item
90%, Contrast Max. are equal as noted in the [12] HPOSI
Adjustment Procedure figure on the right. 4) Adjust the data using the
PROGRESSIVE MODE: 5) Press the “MENU” button left and right cursor keys
to exit from the Service and balance the Left and
1) Receive any NTSC circle Menu. Right hand side.
pattern signal. 5) Press the “MENU” button
2) Screen Format is PRO- HD Mode Adjustment: to exit from the Service
GRESSIVE 1) Receive any 2.14H Menu.
3) Enter the I 2C Bus align- 33.75kHZ signal.
ment menu and select 2) Display Format is HD
Item [12] HPOSI mode.
PAGE 08-32
DP-05F OVERLAY DIMENSIONS FOR THE 43 INCH (4 x 3 Aspect) JIG
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence
Unit.
It is important to offset the Red and Blue centering during Magnet Centering. Failure to do
so, could produce a Memory Overrun error. Red Offset = 20mm and Blue Offset = 35mm
for Progressive and HD Mode.
Green is Geometrically centered.
(874)
(72) [874]
[72]
H. SIZE
(46.7)
[41.8]
(93.4)
[83.6]
R B
(656)
[656]
Centering Offset
(1.1)
[35.4]
V. SIZE Progressive ( )
(5)
HD [ ]
[5]
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence
Unit.
It is important to offset the Red and Blue centering during Magnet Centering. Failure to do
so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm
for Progressive and HD Mode.
Green is Geometrically centered.
(1078)
(88.8) [1078]
[88.8]
H. SIZE
(57.5)
[43.5]
(115)
[103]
R B
(808)
[808]
Centering Offset
(1.5)
[43.5]
V. SIZE Progressive ( )
(6.2) HD [ ]
[6.2]
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence
Unit.
It is important to offset the Red and Blue centering during Magnet Centering. Failure to do
so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm
for Progressive and HD Mode.
Green is Geometrically centered.
(1200)
(102.1) [1200]
[102.1]
H. SIZE
(66.2)
[50]
(132.4)
[118.6]
R B
(930)
[930]
Centering Offset
(1.6)
[50]
V. SIZE Progressive ( )
(7.4) HD [ ]
[7.4]
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence
Unit.
It is important to offset the Red and Blue centering during Magnet Centering. Failure to do
so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm
for Progressive and HD Mode.
Green is Geometrically centered.
Grid show is NOT in proper (16X9) aspect, however values are correct. 16X9
(1173.2)
(96.6) [1173.2]
[96.6]
H. SIZE
(46.9)
[42.1]
(94.0)
[84.1]
R B
(660)
[660]
Centering Offset
(1.1)
[35.6]
V. SIZE Progressive ( )
(7.0) HD [ ]
[7.0]
Red and Blue Centering Offset is necessary to free up memory in the Digital Convergence
Unit.
It is important to offset the Red and Blue centering during Magnet Centering. Failure to do
so, could produce a Memory Overrun error. Red Offset = 15mm and Blue Offset = 25mm
for Progressive and HD Mode.
Green is Geometrically centered.
16X9
Grid show is NOT in proper (16X9) aspect, however values are correct.
(1350)
(111.2) [1350]
[111.2]
H. SIZE
(54.2)
[48.6]
(108.5)
[97.1]
R B
(762)
[762]
Centering Offset
(1.3)
[41.1]
V. SIZE Progressive ( )
(7.8)
HD [ ]
[7.8]
3 2 9
5 6 7
MUST USE OVERLAY IN THIS MODE
Press the 0 button on the remote 5 times. The raster will blink and the cursor will flash indicating 5 X 7
MODE.
19 18 17 16 35 34 33
20 10 3 2 9 15 32
21 11 4 1 8 14 31
22 12 5 6 7 13 30
23 24 25 26 27 28 29
PAGE 08-38
DP-0X DIGITAL CONVERGENCE ADJUSTMENT POINT (13X9)
STOPPING POSITIONS
Press the INPUT button on the CLU-572TSI remote 5 times to activate the 117 stopping positions.
The raster will blink and the cursor will flash indicating 13 X 9 MODE.
NOTE:
This is the normal mode when entering the digital convergence adjustment mode.
86 52 36 26 12 11 10 25 24 35 45 72 110
87 53 37 27 13 3 2 9 23 34 44 71 109
88 54 38 28 14 4 1 8 22 33 43 70 108
89 55 39 29 15 5 6 7 21 32 42 69 107
90 56 40 30 16 17 18 19 20 31 41 68 106
91 57 58 59 60 61 62 63 64 65 66 67 105
92 93 94 95 96 97 98 99 100 101 102 103 104
Sometimes during adjustment, S-Distortion can occur. This is when the line has a noticeable wavy
appearance at a certain locatio n. If this is encountered, enter the (5X7) mode and readjust the line. Then
perform Calculation. It may be necessary to return to the (3X3) mode as well.
Note: Store will also perform Calculation.
PAGE 08-39
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Service only
Internal
switch
Digital
is on the Press and hold the SERVICE SWITCH
"Cross Hatch
deflection Button, then press the POWER Button
Signal" is
PWB. simultaneously until the set is on.
projected
When video appears, press SERVICE
SWITCH again.
PAGE 08-40
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Internal Cross
Hatch Signal
selected
Press the Remote FRZ button
(extra lines will appear at top
and bottom )
Extra Lines
appear
indicating
Raster
Mode
Remote
Adjust Color Up
Press the Remote Cursor buttons to
match the selected Crosshatch
Adjust Adjust
(red and blue) to the green. SELE
Color Color
CT
Left Right
B
PAGE 08-41
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
RECALL Button
is used for Green Only
selecting the
3X3 Press the Remote
Adjustment MENU button to
Mode (when project the green
pressed 5 tube only
times).
Remote
ALL
REC
Remote
4 5 6
Lines symmetrically
Moves location of
aligned at Adjustment
Adjustment Point
Points
(Intersection of
blinking cursor)
C
Continue on next page
PAGE 08-42
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
C
Before Calculation
0 Selects RED
Remote
4 5 6
Selects 7 8 9
Mode been
aligned? Press the Remote
No
INPUT button to
Select the Blue
Crosshatch is cyan when the blue Convergence
and green crosshatches align Yes Adjustment Mode
PAGE 08-43
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Remote
4 5 6
7 8 9
Remote
Selects GREEN
35 convergence adjustment
points in 7X5 mode
Remote
Adjust Color Up
Adjust Adjust
Color SEL
Color
Left ECT
Right
PAGE 08-44
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
E
Remote
(Red/Blue Alignment) 7 8 9
0
Press the
Remote INFO
button to
interpolate as
often as
necessary
Cursor blinks red
at intervals of 2
to indicate the Press the Remote INPUT
7x5 mode button to select the Blue
Convergence Adjustment
Mode
Remote
White Internal
Input
Crosshatch
should be
projected Yes
F
PAGE 08-45
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Remote
Remote
INPUT
RECALL Press the Remote RECALL
button to project
the green only
Selects GREEN
Selects the
13X9 mode
117 convergence
adjustment points in
13X9 mode Remote
Adjust Color Up
Adjust Adjust
Color SEL
Color
Left ECT
Right
PAGE 08-46
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press the
Remote INFO
button to
interpolate as
often as
necessary
Cursor blinks red
indicating the
13X9 mode
Press the Remote INPUT
button to select the Blue
Remote Convergence Adjustment
Adjust Color Up Mode
Adjust Adjust
Color SEL Remote
ECT Color
Left Right
Has the Blue INPUT
13X9 Convergence No
Adjust Color Down
Mode been
aligned?
White Internal
Selects Blue for
Crosshatch
adjustment
should be
projected
Yes
PAGE 08-47
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
1
ROM WRITE? 2
I
PAGE 08-48
DP-0X
DP-85 DIGITAL
DIGITAL CONVERGENCE
CONVERGENCE ALIGNMENT
ALIGNMENT PROCEDURES
PROCEDURES
1
ROM WRITE?
3
Screen projects different light
patterns during the
Initialization Mode
PAGE 08-49
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Press and Hold Magic Focus Press and hold the Magic Focus
button for 5 seconds until button for 10 seconds until
CENTER appears on Screen STATIC appears on Screen.
Adjust Adjust
Color SELECT Color
Left Right
CENTER STATIC
Adjust Color ADJUSTMENT
ADJUSTMENT
Down
PAGE 08-50
DP-0X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Convergence Touchup
Overlays NOT required!
1 2
Press the Service Only Switch After HD
to Exit to PROGRESSIVE mode. has been completed
PAGE 08-51
KEY COMPONENT
INFORMATION
SECTION 9
DP-06 KEY COMPONENTS
PAGE 09-01
DP-06 KEY COMPONENTS
PAGE 09-02
DP-06 KEY COMPONENTS
PAGE 09-03