ES LabManual 2011

Embedded Systems
Laboratory Manual
Roll No.:_______________
Exam No.:______________
Name of the student:_________________________________
Government Engineering College, Rajkot

Mavadi-Kankot Road, Near Hanuman Temple, Opp. Kankot Village, Rajkot
www.gecrajkot.org
GOVERNMENT ENGINEERING COLLEGE, RAJKOT
CERTIFICATE
This is to certify that Mr/Miss ________________________________________
Roll No. ______________of B.E. (E.C.) SEM-VIII has satisfactorily completed the
term work of the subject Embedded Systems prescribed by Saurashtra
University during the academic term ___________________________
Date: Signature of the faculty
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INDEX
Sr. Name of Experiment Page
No. No.
1. To understand architecture of ARM7TDMI 4
architecture
2. To understand ARM32 and Thumb instruction set 11
of ARM microcontroller and write simple programs
3. To understand features and block diagram of LPC- 17
2129 ARM processor. To download and execute
program to blink 8 LEDs connected at Port P0 of
LPC-2129 ARM7TDMI chip using LPC2000 flash
utility
4. To understand features of LPC-2294 ARM 24
processor and download programs to flash 8 LEDs
connected at Port P1 of LPC-2294 ARM Processor
5. Write program to blink LEDs one by one. 26
Download and execute program in LPC-2129 chip.
Modify this program according to given instruction
in exercise
6. To write and execute program to display message 29
“display “WELCOME GEC RAJKOT” on LCD screen
for ARM7
7. To read analog input voltage and display it on LCD 33
using LPC-2129
8. To understand architecture of Digital Signal 38
Processor ADSP-2181
9. To understand installation procedure of ADSPLite 44
software and ADSP Kit. To download and run
sample programs on ADSP kit.
10. To generate sine wave, square wave and other 49
complex waveforms using ADSP-2181
11. To filter input signal using FIR filter 53
implementation with ADSP-2181
12. To understand architecture of TMS320C6713 DSP 57
chip and code composer studio
13. To understand features of Cypress Programmable 66
System on Chip (PSoC). To download and execute
demo programs to display vertical bar graph using
LEDs depending on analog input voltage.
14. To read analog voltage and display it on LCD using 70
cypress kit
15. To become familiar with GCC compiler, WinARM 72
and crossware development tools
Assignment 74
3
Experiment No.1
Aim: To understand architecture of ARM7TDMI architecture
Brief Theory:
The ARM7TDMI is a member of the Advanced RISC Machines (ARM)
family of general purpose 32-bit microprocessors, which offer high
performance for very low power consumption and price. The ARM
architecture is based on Reduced Instruction Set Computer (RISC)
principles, and the instruction set and related decode mechanism are much
simpler than those of micro-programmed Complex Instruction Set
Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective chip.
Pipelining is employed so that all parts of the processing and memory

systems can operate continuously. Typically, while one instruction is being
executed, its successor is being decoded, and a third instruction is being
fetched from memory.
The ARM memory interface has been designed to allow the

performance potential to be realized without incurring high costs in the
memory system. Speed-critical control signals are pipelined to allow system
control functions to be implemented in standard low-power logic, and these
control signals facilitate the exploitation of the fast local access modes
offered by industry standard dynamic RAMs.
The ARM7TDMI processor employs a unique architectural strategy

known as THUMB, which makes it ideally suited to high-volume
applications with memory restrictions, or applications where code density is
an issue.
Thumb Concept:
The key idea behind THUMB is that of a super-reduced instruction set.

Essentially, the ARM7TDMI processor has two instruction sets:
• Standard 32-bit ARM set
• 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the
density of standard ARM code while retaining most of the ARM’s
performance advantage over a traditional 16-bit processor using 16-bit
registers. This is possible because THUMB code operates on the same 32-bit
register set as ARM code.
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THUMB code is able to provide up to 65% of the code size of ARM, and 160%
of the performance of an equivalent ARM processor connected to a 16-bit
memory system.
THUMB instructions operate with the standard ARM register configuration,

allowing excellent interoperability between ARM and THUMB states. Each
16-bit THUMB instruction has a corresponding 32-bit ARM instruction with
the same effect on the processor model.
The major advantage of a 32-bit (ARM) architecture over a 16-bit

architecture is its ability to manipulate 32-bit integers with single
instructions, and to address a large address space efficiently. When
processing 32-bit data, a 16-bit architecture will take at least two
instructions to perform the same task as a single ARM instruction. However,
not all the code in a program will process 32-bit data (for example, code that
performs character string handling), and some instructions, like Branches,
do not process any data at all.
If a 16-bit architecture only has 16-bit instructions, and a 32-bit

architecture only has 32-bit instructions, then overall the 16-bit
architecture will have better code density, and better than one half the
performance of the 32-bit architecture. Clearly 32-bit performance comes at
the cost of code density.
THUMB breaks this constraint by implementing a 16-bit instruction length

on a 32-bit architecture, making the processing of 32-bit data efficient with
a compact instruction coding. This provides far better performance than a
16-bit architecture, with better code density than a 32-bit architecture.
THUMB also has a major advantage over other 32-bit architectures with 16-
bit instructions. This is the ability to switch back to full ARM code and
execute at full speed. Thus critical loops for applications such as fast
interrupts and DSP algorithms can be coded using the full ARM instruction
set, and linked with THUMB code. The overhead of switching from THUMB
code to ARM code is folded into sub-routine entry time. Various portions of a
system can be optimized for speed or for code density by switching between
THUMB and ARM execution as appropriate.
Core diagram of the ARM7TDMI is shown in the following figure.
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ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit
registers and six status registers - but these cannot all be seen at once. The
processor state and operating mode dictate which registers are available to
the programmer.
In ARM state, 16 general registers and one or two status registers are
visible at any one time. In privileged (non-User) modes, mode-specific
banked registers are switched in. Register organization shown below. In
ARM state shows which registers are available in each mode: the banked
registers are marked with a shaded triangle. The ARM state register set
contains 16 directly accessible registers: R0 to R15. All of these except R15
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are general-purpose, and may be used to hold either data or address values.
In addition to these, there is a seventeenth register used to store status
information
 Register 14 is used as the subroutine link register. This receives a

copy of R15 when a Branch and Link (BL) instruction is executed. At all
other times it may be treated as a general-purpose register. The
corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and
R14_und are similarly used to hold the return values of R15 when
interrupts and exceptions arise, or when Branch and Link instructions
are executed within interrupt or exception routines.
 Register 15 holds the Program Counter (PC). In ARM state, bits [1:0] of
R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is
zero and bits [31:1] contain the PC.
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 Register 16 is the CPSR (Current Program Status Register). This
contains condition code flags and the current mode bits.
 FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq).

In ARM state, many FIQ handlers do not need to save any registers. That
is the reason for fast execution of interrupts.
 User, IRQ, Supervisor, Abort and Undefined each have two banked
registers mapped to R13 and R14, allowing each of these modes to have a
private stack pointer and link registers.
 Address bus of ARM7TDMI has 32 address If ALE (address latch enable)

is HIGH and APE (Address Pipeline Enable) is LOW, the addresses
become valid during phase 2 of the cycle before the one to which they
refer and remain so during phase 1 of the referenced cycle.
 ABE (Address Bus Enable) pin is LOW, it puts the address bus into a
high impedance state. ABE must be tied HIGH when there is no system
requirement to turn off the address drivers.
 The ARM7TDMI contains a Current Program Status Register (CPSR), plus

five Saved Program Status Registers (SPSRs) for use by exception
handlers. These registers
[1] Hold information about the most recently performed ALU operation
[2] Control the enabling and disabling of interrupts
[3] Set the processor operating mode
 The arrangement of bits is in CPSR is shown below:
Load and Store architecture:
ARM employs load and store architecture. Instruction set will only process
values which are in registers and place result of process into register.
Process may be addition, subtraction, etc. Example: ADD R1,R2,R3 (This
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instruction adds content of registers R2 and R3 and saves result into R1).
Operations related to memory are load and store operations only. Copy
memory values into registers are called load instructions and copy register
values into memory are called store instructions. ARM does not support
memory to memory operations.
ARM Exceptions: ARM architecture supports range of interrupts, traps and

supervisor calls. All these are grouped under general heading “ARM
Exceptions” Exceptions are handled in following ways:
 The current state is saved by copying PC into register R14_Exc
 CPSR (Current Program Status Register) is saved into SPSR (Saved

Program Status Register)
 Processor operating mode is changed to appropriate exception mode
 PC is forced to a value between 00h to 1Ch depending on type of

exception
ARM I/O (Input/output) system: ARM handles input-output peripherals

as memory mapped devices with interrupt support. The internal registers of
these peripheral devices are addressable locations within the ARM’s memory
map. Input and output data transfer is done by same load and store
instructions which are used for memory locations.
WORKSHEET
[1] What is the difference between RISC machine and CISC machine?
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[2] What are the advantages of THUMB mode of ARM microcontroller?
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[3] For what type of applications full arm instructions are better compared to
thumb and switching is required from thumb mode to full arm mode?
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[4] What is load and store architecture? What kind of operations are not
permitted in load and store archictecture?
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[5] List ARM development tools available for the development of ARM
applications.
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Experiment No.2
Aim: To understand ARM32 and Thumb instruction set of ARM
microcontroller and write simple programs
ARM instruction is 32 bit long. All operands are 32 bit wide and come
from registers or are specified as literals in the instruction itself. Thumb
instruction set is 16 bit. It is compressed form of subset of ARM
instructions. It provides more code density. ARM processor which supports
Thumb instruction set, also executes standard 32 bit instruction set.
Instruction stream at particular time is determined by bit 5 of CPSR (T bit).
If T bit is set, ARM processor interprets instruction as 16 bit Thumb
instruction otherwise it interprets as standard 32 bit instruction. ARM core
start up after reset, executes normal 32 bit ARM instructions. The normal
way to switch into Thumb mode is by executing branch and exchange
instruction (BX).
ARM instructions fall into one of following three categories.
1. Data processing instructions: These instructions are used to change

register values by various arithmetic and logical operations
2. Data transfer instructions: Copy memory values into registers (load

instructions) and copy register values into memory (store instructions)
3. Control flow instructions: Control flow instructions cause execution to

switch to different address. Conditional and unconditional jump
instructions, interrupts, supervisor calls falls into this category.
4. Instruction set:
Data processing instructions: Multiply Instructions
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Load and store instructions: Load and store multiple data bytes
Condition code Mnemonics:
Some Examples:
Data transfer instructions (Load and Store)
[1] MOV R1,R2

Explanation: Content of register R2 copied into R1 R1 R2
[2] MOV R1,#0x55
Explanation: Move hexadecimal value 0x55 to register R1
[3] MVN R1,R2
Explanation: Content of R2 complemented and than transferred to R1
R1R2`
[5] MOV PC,R14
Explanation: Copy content of register R14 into PC. Return from subroutine
because R14 is the link register.
[5] LDR R1,[R2]
Explanation: Load R1 from memory address pointed by R2 R1 *R2
Data stored at the address pointed by register R2 is loaded into register R1.
[6] LDR R1,[R2,#8]
Explanation: Load register R2 from the memory address pointed by R2+8.
R1 *(R2+8)
[7] STR(R5,#8),R1
Explanation: Store content of register R1 at the memory location specified by
R5+8. *(R5+8)  R1
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[8] MOVS R0,#0
Explanation: Move value 0 in the register R0. S indicates that it will affect
CPSR also. Zero flag will set, negative flag reset, Carry and overflow flag not
effected.
Data Processing (Arithmetic and logical instructions):
[1] ADD R1,R2,R3

Explanation: Add content of registers R2 and R3, result is stored in R1
R1R2+R3
[2] ADD R1,R2,#0x55
Explanation: Add content of register R2 and immediate value 0x55 and store
result in the register R1. R1R2+0x55
[3] ADDC R1,R2,R3
Explanation: Consider carry during addition. R1=R2+R3+Carry
[4] SUB R1,R2,R3
Explanation: Subtract content of register R3 from R2 and store result in
register R1.
R1 R3-R2
[5] RSB R2,R2,R5
Explanation: Reverse subtraction. Subtract R2 from R5 and store result
back in R2. R2 R5-R2
[6] SBC R1,R2,R3
Explanation: Subtraction with carry. R1=R2-R3-NOT(carry)
[7] RSC R0,R1,R2
Explanation: R0 = R2-R1+C-1 { R2-R1-NOT(carry)}
[8] MUL R1,R2,R3
Explanation: Multiply registers R2 and R3. Store result in the register R1.
[9] ADD R1,R2,R3,LSL #2
Explanation: Addition combined with barrel shifting. It shifts content of
register R3 to the left two times and than adds with the register R2. Store
result in the register R1. Logical shift left multiplies the number by two. Two
time shifting multiplies the number by 4.
R1 R2+4R3
[10] SUB R4,R5,R7,LSR R2
Explanation: Logical right shift R7 by the number in the bottom byte of R2,
subtract result from R5, and put the answer into R4.
[11] MLA R1,R2,R3,R4
Explanation: Multiply and accumulate. R1 R2*R3+R4
Branch Instructions:
[1] B label : Branch unconditionally to label
[2] BCC label : Branch to label if carry flag is cleared
[3] BEQ label : Branch to label if zero flag is set
[4] MOV PC,#0 : Branch to location 0
[5] BL delay : Subroutine call to delay
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Conditional Execution instructions:
[1] MOVCS R0,R1
Explanation: This instruction will move value of register R1 to register R0
only if carry flag is set.
[2] MOVEQ R0,R1
Explanation: This instruction will move value of register R1 to register R0
only if zero flag is set.
[3] Consider following sequence of instructions:

MOVS R0,R1
MOVEQS R0,R2
MOVEQ R0,R3
Explanation:
 The first instruction moves content of register R1 into R0 and change N
and Z flag depending on value stored in R0.
 Second instruction will transfer R2 to R0 only if zero flag is set. That
means if during first instruction R1=0, second instruction will execute. If
second instruction is executed it will change N and Z flag depending on
value stored in R2.
 Third instruction transfer register R3 to R0 only if zero flag is set. That
means R2=0 during second instruction. Thus, third instruction will be
executed only of R1 and R2 both were 0.
CMP R1,#0 ; Compare R1 with 0.

BNE LOOP ; Branch if not equal
Explanation:
The first instruction compares R1 with 0. The second instruction is branch
instruction, program will jump to location specified by label LOOP if R1 is
not equal to 0.
Sequence of instructions to change operating mode of ARM:

MRS R0,CPSR; Take a copy of the CPSR.
BIC R0,R0,#0x1F; Clear the mode bits.
ORR R0,R0,#new_mode; Select new mode
MSR CPSR,R0; Write back the modified CPSR
WORKSHEET
[1] Write instructions for the following operations
[a] Move content of register R6 into R5
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[b] Move immediate data #66 in the register R4
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[c] Add content of register R3 and R4. Save result in register R6
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[d] Multiply content of register R1 and R2. Save result in register R3.
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[e] Write instruction to multiply content of register R4 with 5. Use ADD
instruction in combination with logical shift instruction.
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[f] Write instruction to multiply and accumulate. Use registers R4,R5,R6 and
R7.
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[g] Write instruction to copy CPSR register into register R0.
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[2] Write a program to add elements of array. Consider three elements in the
array. Load data from the array using instruction LDR and add it. Store
the result in register R0.
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[3] Explain execution of following instructions with suitable example:
[a] MOV R0,R1,ASR #2
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[b] MOV R0,R1,ROR #2
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[c] AND R0,R1,R2
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[d] ORR R0,R1,R2
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[e] EOR R0,R1,R2
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[f] BIC R0,R1,R2
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Experiment No.3
Aim: To understand features and block diagram of LPC-2129 ARM
processor. To download and execute program to blink 8 LEDs connected at
Port P0 of LPC-2129 ARM7TDMI chip using LPC2000 flash utility
Brief Theory:
The ARM microcontrollers are high-performance, 16/32 bit RISC Core
devices. The ARM market is one of the fastest growing market for
microcontrollers. TheLPC2119/LPC2129 are based on a 16/32bit
ARM7TDMI-S™ CPU with 256 kB of embedded high speed flash memory. A
128-bit wide memory interface and a unique accelerator architecture enable
32-bit code execution at maximum clock rate. For critical code size
applications, the alternative 16-bit Thumb Mode reduces code by more than
30% with minimal performance penalty.
LPC2129 comes with 64 pin package, low power consumption, various
32-bit timers, 4-channel 10-bitADC, 2 advanced CAN channels, PWM
channels and 46 GPIO lines with up to 9 external interrupt pins these
microcontrollers are particularly suitable for automotive and industrial
control applications as well as medical systems and fault-tolerant
maintenance buses. With a wide range of additional serial communications
interfaces, they are also suited for communication gateways and protocol
converters as well as many other general-purpose applications.
The advantage of ARM microcontrollers are:
 It is very fast: ARM7 core run at 60 MHz and ARM9 runs at 150 MHz
 Low power dissipation: Typical power dissipation for ARM7 is 0.5-1
mA/MHz
 Great range of peripherals: ADC, DAC, USB, SPI,UART, I2C, CAN,
Ethernet, SDRAM
 Internal Flash (32 KB to 1 MB depending on chip) and RAM (4 to 256 KB)
The salient features of LPC-2129 are listed below:
 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. 16kB
on-chip Static RAM. 128/256kB on-chip Flash Program Memory.
 128-bit wide interface/accelerator enables high speed 60MHz operation.
 In-System Programming (ISP) and In-Application Programming (IAP) via
on-chip boot-loader software. Flash programming takes 1 ms per 512
byte line. Single sector or full chip erase takes 400ms.
 Embedded ICE-RT interface enables breakpoints and watch points.
Interrupt service routines can continue to execute whilst the foreground
task is debugged with the on-chip Real Monitor software.
 Embedded Trace Macrocell enables non-intrusive high speed real-time
tracing of instruction execution. Two interconnected CAN interfaces with
advanced acceptance filters.
 Four channel 10-bit A/D converter with conversion time as low as 2.44
µs.
 Multiple serial interfaces including two UARTs (16C550), Fast I2c 400
kbps and two SPIs™.
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 60MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop.
 Vectored Interrupt Controller with configurable priorities and vector
addresses.
Block diagram of the LPC2129 ARM Chip:
 Two 32-bit timers(with 4 capture and 4 compare channels), PWM unit(6

outputs), Real Time Clock and Watchdog.
 Up to forty-six 5V tolerant general purpose I/O pins. Up to 9 edge or level
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sensitive external interrupt pins available.
 On-chip crystal oscillator with an operating range of 1MHz to 30MHz.
 Two low power modes, Idle and Power-down.
 Processor wake-up from Power-down mode via external interrupt.
 Individual enable/disable of peripheral functions for power optimization.
 Dual power supply:
o CPU operating voltage range of 1.65V to 1.95V (1.8V ±0.15V).
o I/O power supply range of 3.0V to 3.6V (3.3V ±10%) with 5V tolerant
I/O pads.
Pin Diagram of LPC2129:
Features of LPC2129:
 It is 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

16kB on-chip Static RAM. 128/256kB on-chip Flash Program Memory.
128-bit wide interface/accelerator enables high speed 60MHz operation.
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 In-System Programming (ISP) and In-Application Programming (IAP) via
on-chip boot-loader software. Flash programming takes 1 ms per 512
byte line. Single sector or full chip erase takes 400ms.
 Embedded ICE-RT interface enables breakpoints and watch points.

Interrupt service routines can continue to execute whilst the foreground
task is debugged with the on-chip Real Monitor software.
 Embedded Trace Macrocell enables non-intrusive high speed real-time

tracing of instruction execution.
 Two interconnected CAN interfaces with advanced acceptance filters.
 4 channel 10-bit A/D converter with conversion time as low as 2.44 µs.
 Multiple serial interfaces including two UARTs (16C550), Fast I2C 400
kbps two SPIs™.
 60MHz maximum CPU clock available from programmable on-chip

Phase-Locked Loop.
 Vectored Interrupt Controller with configurable priorities and vector

addresses.
 Two32 bit timers(with 4 capture and 4 compare channels), PWM unit (6

outputs),
 Real Time Clock and Watchdog.
 Up to 46 general purpose I/O pins.
 Up to 9 edge or level sensitive external interrupt pins available.
 On-chip crystal oscillator with an operating range of 1MHz to 30MHz.
 Two low power modes, Idle and Power-down.
 Processor wake-up from Power-down mode via external interrupt.

Individual enable/disable of peripheral functions for power optimization.
 Dual power supply: CPU operating voltage range of 1.65V to 1.95V (1.8V
±0.15V).
 I/O power supply range of 3.0V to 3.6V (3.3V ±10%) with 5V tolerant I/O
pads.
To download and execute program to blink 8 LEDs connected with

LPC2129 ARM7TDMI using LPC2000 flash utility
LEDs are connected with LPC-2129 chip with port pins P0.2 to P0.7, P0.22
and P0.9. Bit Configuration is shown below. First row is bit position, second
row is corresponding bit and third row is equivalent hexadecimal value.
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31 …. 24 23 22 21 20 ….. 17 16 15 14 …10 9 8 7 6 5 4 3 2 1 0
0 0…0 0 0 1 0 0 ….. 0 0 0 0 ……0 1 0 1 1 1 1 1 1 0 0
00 40 02 FC
Program:
/ *********** Program to blink LEDs **********/

#include <LPC21xx.h> /* LPC21xx definitions in header file */
#include "Timer.h"
extern long volatile timeval;
void wait (void) /* wait function */
{
unsigned long i;
i = timeval;
while ((i +100 ) != timeval); /* wait 100ms */
}
int main (void)
{
unsigned int j; /* LED var */
IODIR0 = 0x004002FC; /* Define I/O pins */
init_timer();
while (1) /* Loop forever */
{
j== 0x004002FC; /* bit pattern for LEDs connected at GPIO port 0*/
IOSET0=j; /* turn LEDs ON */
wait(); /* Delay */
IOCLR0=j; /* turn LEDs OFF */
wait(); /* Delay */
}
}
Downloading program to flash memory of the chip LPC2129:
 Create project and write above program using KEIL IDE tool. (Create New
Project, write C program in new file, Add C file in your project, Add
necessary header files such as LPC21xx.h, timer.c and timer.h in your
project). Build program to generate HEX file.
 Use Philips LPC2000 flash utility to download your program HEX file in
the chip. Screen looks as shown in the figure in the next page
 Philips LPC2000 Flash utility connects PC’s serial port (COM port) to the
serial port of LPC2129 chip and provides in system flash programming
(ISP).
 Select device LPC2129, Change crystal frequency 12000 KHz (12 MHz)
(Or press “Read device Id” command button, it will select device
automatically)
 Select hex file and press button upload to the flash.
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 Before downloading HEX file in the chip, ensure that switch SW5 of the
ARM board is in left position. Press RESET key before downloading
 After downloading the program, make switch SW5 in the right side and
press the reset key to start execution.
 You can use stand-alone Philips LPC2000 Flash utility or it can be

embedded into your KEIL compiler. In Keil compiler use FLASH menu.
WORKSHEET
[1] Modify program of this practical to change blinking interval. Generate
HEX file of modified program, download it and observe the result
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[2] What is use of watchdog timer?
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[2] What is brown out reset?
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[3] Why interrupt execution is fast in ARM processor in FIQ mode?
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[4]Write key features of LPC2129 microcontroller
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23
Experiment No.4
Aim: To understand features of LPC-2294 ARM processor and download
programs to flash 8 LEDs connected at Port P1 of LPC-2294 ARM Processor
Features of LPC-2294:
The LPC-2294 microcontroller is based on a 16-bit/32-bit ARM 7 TDMI-S
It has 256 KB of embedded high - speed flash memory. It has 16 KB on
chip static RAM. A 128-bit wide memory interface and unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb mode reduces
code by more than 30% with minimal performance penalty.
LPC-2294 ARM chip has 144-pin, low power consumption, various 32-bit
timers, 8-channel 10-bit ADC, 2 advanced CAN channels, PWM channels
and up to nine external interrupt pins these microcontrollers are
particularly suitable for automotive and industrial control applications
as well as medical systems and fault-tolerant maintenance buses. The
number of available GPIO's ranges from 76 (with external memory)
through 112 (single-chip). With a wide range of additional serial
communications interfaces, they are also suited for communication
gateways and protocol converters as well as many other general-purpose
applications.
Procedure:
1. To program IC via serial port, short the 1-2 pin of the jumpers J7 &
J6 (left side). Connect the serial cable to any functional COM port of
your PC and SP2 (DB-9 Connector) port of the trainer (in PC interface
& ISP section).
2. To program IC via USB, short the 2-3 pin of the jumpers J7 &
J6 (right side). Connect the USB cable with PC
3. Change the position of Run/ISP switch 'On' the trainer to ISP mode.
4. Connect the power cable to the trainer and switch 'On' the power
switch.
5. Compile program using KEIL compiler and generate hex file LED.hex
6. Start the Philips flash utility LPC210x_ISP.exe
7. Program LED.hex in LPC-2294 using programmer.
8. Switch 'Off’ the power supply and change the position of Run/ISP
switch 'On' the trainer to Run mode.
9. Switch 'On' the supply, then press reset switch.
10. Observe the blinking of LED's according to program.
24
Program:
#include <LPC22xx.h> /* LPC22xx definitions */

#include "LED.h"
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
void main(void)
{
initilise_led();
while (1)
{
blink_led();
}
To compile above program, it is necessary to include library file Nvis2294.LIB where

routines blink_led() and initialize_led() are written.
LEDs are connected with port pins P1.16 to P1.23 of LPC-2294 chip. Following
program will also work without using library file Nvis2294.LIB

#include "Timer.h"
{
unsigned long i;
i = timeval;
}
int main (void)
{
IODIR0 = 0x00FF0000; /* Define I/O pins P1.16 to P1.23 */
init_timer();
while (1) /* Loop forever */
{
j=0x00FF0000; /* bit pattern for LEDs connected at GPIO port 1*/
IOSET0=j; /* turn LEDs ON */
wait(); /* Delay */
IOCLR0=j; /* turn LEDs OFF */
wait(); /* Delay */
}
}
25
Experiment No.5
Aim: Write program to blink LEDs one by one. Download and execute
program in LPC-2129 chip. Modify this program according to given
instruction in exercise
Program:

{
unsigned long i;
i = timeval;
}
int main (void)
{
IODIR0 = 0x000003FC; /* Define I/O pins */
init_timer();
while (1)
{
for (j = 0x00000004; j < 0x00000800; j <<= 1) /* Blink LED one by
one*/
{ IOSET0 = j; /* Turn on LED */
wait (); /* call wait function */
IOCLR0 = j; /* Turn off LED */
wait();
}
}
}
WORKSHEET
Modify above program in such a way that first four LED glow and other four
LEDs remains OFF for a while and then first four LED switched OFF and
other four LEDs becomes ON as shown in following figure (Alternate Nibble
ON-OFF).
26
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Modify program to use pure software delay instead of time delay
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27
Buzzer is connected at pin number P0.20 via buffer at LPC-2129. Write a
program to get beep on the buzzer. Compile and execute program. Change
beep duration
(Hint: IODIR0 = 0x00300000 and short jumper R35 to get beep in buzzer)
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28
Experiment No.6
Aim: To write and execute program to display message “display
“WELCOME GEC RAJKOT” on LCD screen for ARM7
Interfacing details of LCD:

 LCD data lines are connected with port pins P1.16 to P1.23
 RS connected with P0.18
 EN connected with P0.19
 RW pin is grounded (always write operation)
Program:
#include <LPC21XX.H>
#define uchar unsigned char
#define uint unsigned int
#define RS 18
#define EN 19
unsigned char const mcu123[]="WELCOME GEC RAJKOT" ;
void Io_Set(uchar pin)

{
unsigned int io_data=1;
io_data=io_data<<pin;
IOSET0=io_data;
}
void Io_Clr(uchar pin)

{
IOCLR0=io_data;
}
void Io_Set1(uchar pin)

{
IOSET1=io_data;
}
void Io_Clr1(uchar pin)

{
IOCLR1=io_data;
}
void Sent_Byte(unsigned char data)
29
{
unsigned char i;
for(i=0;i<8;i++)
{
if(data&1) {Io_Set1(i+16);}
else {Io_Clr1(i+16);}
data=data>>1;
}
}
void delay(unsigned int i)
{
unsigned int k=1000;
while(i>0)
{
i--;
}
while(k>1)k--;
}
void delayms (unsigned int i) { /* Delay function */

unsigned int n;
while(i>1)
{
for(n=65535;n>1;n--);
i--;
}
}
void delay1s(unsigned char i)

{
while(i>1)
{
i--;
delayms(20);
}
}
void init_port(void)
{
//port initialized
IODIR1=0x00FF0000; //LCD data lines are connected to P1.23 to P1.16
IODIR0=0x000C0000; // RS to P0.18 and EN to P0.19
}
void LcdWrite_CMD( uchar CMD)

{
Io_Clr(RS); /* Select Command Register of LCD*/
delay(1);
Sent_Byte(CMD);
delay(1);
Io_Set(EN); /* Enable LCD*/
delay(1);
Io_Clr(EN); /* Disable LCD */
delay(2);
delayms(10);
}
void LcdWrite_D( char dataW )
{
Io_Set(RS); /* Select Data Register of LCD*/
delay(1);
Sent_Byte(dataW);
30
delay(1);
Io_Set(EN); /* Enable LCD*/
delay(1);
Io_Clr(EN); /* Disable LCD */
delay(2);
delayms(10);
}
void DispOneChar(uchar x,uchar y,uchar Wdata) {
LcdWrite_D( Wdata );
}
void disp(uchar x,uchar y,const unsigned char *ptr) {

uchar i,l=0;
while (ptr[l] >31){l++;};
for (i=0;i<l;i++) {
DispOneChar(x++,y,ptr[i]);
if ( x == 16 ){
x = 0; y ^= 1;
}
}
}
void lcdreset(void)
{
LcdWrite_CMD(0x38); /* Initialize LCD 2 lines, 5X7 matrix*/

delayms(50);
LcdWrite_CMD( 0x08); /* Display OFF cursor OFF */
LcdWrite_CMD( 0x01); /*Clear LCD*/
LcdWrite_CMD( 0x06); /*Shift cursor right*/
LcdWrite_CMD( 0x0c); /* Display ON */
}
int main(void)
{ init_port();
delayms(1);
lcdreset();
delay1s(1);
LcdWrite_CMD( 0x80);
disp(0,0,mcu123);
LcdWrite_CMD( 0xC0);
disp(0,1,"E.C. Department");
while(1)
{
}
}
Compile and build above program with Keil compiler and generate
HEX file. Download HEX file in the chip LPC2129 and execute the program
by pressing RESET key
31
WORKSHEET
[1] What are the pins available on the LCD for interfacing with ARM
processor? Describe functions of the pins.
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[1] Modify LCD program to display character string “Saurashtra” on the first
line and University on the second line. Write modified program again.
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32
Experiment No.7
Aim: To read analog input voltage and display it on LCD using LPC-2129
ADC introduction and interfacing details:
10 bit ADC is interfaced with LPC-2294. It is successive approximation type

analog to digital converter with conversion time greater than 2.44 us.
Basic clocking for the A/D converter is provided by the VPB clock. A
programmable divider is included to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. A fully
accurate conversion requires 11 of these clocks. Seven analog input pins are
in LPC2294. The A/D converter includes two registers ADDR and ADCR.
The ADCR register must be written to select the operating mode
before A/D conversion can occur. This ADDR register contains the end of
conversion bit.
Functions of various bits of ADDR and ADCR registers are explained below:
A/D Control Register (ADCR) :
ADCR Name Description Reset

bit Value
7:0 Sel Select which of the Ain3:0 (LPC2119/2129/2194) or Ain 7: 0 0x01
(LPC2292/2294) pins is (are) to be sampled and converted.
Only bits 3: 0 should be set to 1 in the 48 or 64 pin package. In
software-controlled mode, only one of these bits should be 1. In
hardware scan mode, any value containing 1 to 8 ones (1 to 4
ones in the 48 or 64 pin package) can be used. All zeroes is
equivalent to 0x01.
15.8 CLKDIV The VPB clock (PCLK) is divided by (this value plus one) to 0
produce the clock for the A/D converter, which should be less
than or equal to 4.5 MHz. Typically, software should program the
smallest value in this field that yields a clock of 4.5 MHz or
slightly less, but in certain cases (such as a high -impedance
analog source) a slower clock may be desirable.
16 Burst If this bit is 0, conversions are software controlled and require 11 0
clocks. If this bit is 1, the AD converter does repeated conversions
at the rate selected by the CLKS field, scanning (if necessary)
through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least - significant 1
in the SEL field, then higher numbered 1 -bits (pins) if applicable.
Repeated conversions can be terminated by clearing this bit, but
the conversion that's progress when this bit is cleared will be
completed.
33
19:17 CLKS This field selects the number of clocks used for each conversion 000
in Burst mode, and the number of bits of accuracy of the result in
the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks
(3bits): 000=11 clocks/9 bits.... 111=4 clocks/3 bits
21 PDN 1: the A/D converter is operational 0: the A/D 0

converter is in power down mode
23:22 Test1:0 These bits are used in device testing. 00=normal operation, 0
01= digital test mode, 10=DAC test mode, and 1 1=simple
conversion test mode
When the Burst bit is 0, these bits control whether and when an
A/D conversion is started:000: no start (this value should be
used clearing PDN to 0
001: Start conversion now
26:24 Start 010: Start conversion when the edge selected by bit 27 occurs 000
on P0.16/EINT0/MAT0.2/CAP0.2
011: Start conversion when the edge selected by bit 27 occurs

on P0.22/TD3/CAP0.0/MAT0.0
Note: for choices 100-111 the MAT signal need not be pinned
out:

on MAT0.1

on MAT0.3

on MAT 1.0
27 Edge This bit is significant only when the start field contains 010-111. 0
In there cases:
0: Start conversion on a falling edge on the selected

CAP/MAT signal
1: Start conversion on a rising edge on the selected

CAP/MAT signal
34
A/D Data Register (ADDR) :
ADDR Name Description Reset

bit Value
31 Done This bit is set to 1 when an A/D conversion 0
completes. It is cleared when this registered is read
and when the ADCR is written. If the ADCR is
written while a conversion is still in progress, this bit is
set and a new conversion is started.
30 OVERUN This bit is 1 in burst mode if the results of one or 0
more conversion that produced that the result in the
LS bits. In non -FIFO operation, this is cleared by
reading this register.
29:27 These bits always read as zeroes. They could be used 0
for expansion of the CHN field in future compatible
A/D converters that can convert more channels
26:24 CHN These bits contain the channel from which the LS X
bits were converted
23:16 These bits always read as zeroes. They allow 0
accumulation of successive A/D values without and -
masking, for at least 256 values without overflow
15:6 V/VddA into thedone
When CHNisfield
1, this field contains a binary fraction X
representing the voltage on the Ain pin selected by
the SEL field, divided by the voltage on the VddA
pin. Zero in the field in the indicates that the voltage
on the Ain pin was less than, equal to, or close to that
on VssA, while 0x3 FF indicates that the voltage on Ain
was close to, equal to, or greater than that on VddA
For testing, data written to this field is captured in a

shift register that is clocked by the A/D converter
clock. The MS bit of this register sources the
DINSERI input of the A/D converter which is used is
used only when Test 1:0 are 10.
5:0 These bits always read as zeroes. They provide 0

compatible expansion room for future higher -
resolution A/D converters
35
Procedure:
1. To program IC via serial port, short the 1-2 pin of the jumpers J7 &
J6 (left side). Connect the serial cable to any functional COM port of
your PC and SP2 (DB-9 Connector) port of the trainer (in PC interface
& ISP section).
2. To program IC via USB, short the 2-3 pin of the jumpers J7 &
J6 (right side). Connect the USB cable with PC
3. Change the position of Run/ISP switch 'On' the trainer to ISP mode.
4. Connect the power cable to the trainer and switch 'On' the power
switch.
5. Compile program using KEIL compiler and generate hex file
ADC_Interface.hex
6. Start the Philips flash utility LPC210x_ISP.exe
7. Program ADC_Interface.hex in LPC-2294 using programmer.
8. Switch 'Off’ the power supply and change the position of Run/ISP
switch 'On' the trainer to Run mode.
9. Close 1-2 pin of jumper J1 (left side).
10. Switch ‘On’ the supply, then press reset switch.
11. Observe display coming on LCD.
12. Rotate the DC Voltage potentiometer located in ADC Interface

block and observe the change in readings on LCD also measure the
voltage comes on TP1 test point.
12. Examine the voltage on TP1, when voltage on TP1 is 0V, LCD shows
0000 in decimal and when TP1 is 3.3V, LCD shows 1024 in decimal
on LCD (10 bit ADC).
Pin P0.27 (Pin No. 23 is analog input pin) used for this program. There are
total four ADC input pins are available (P0.27, P0.28, P0.29 and P0.30)
Program:
#include <LPC22xx.H> /* LPC2294 definition */

#include <LCD.h>
#include <ADC.h>
#include <Delay.h>
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
void main(void)
{
adc_initialise();
36
while (1)
{
adc_runmode();
}
}
// Adc.h file
#ifndef ADC_H
#define ADC_H
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
void binbcd(unsigned int );

void adc_initialise(void );
void adc_runmode(void );
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
static unsigned int a,b,c,d,x,y,z;
static unsigned int adcdata;
#endif
:: WORKSHEET ::
[1] What is the advantage of 10 bit ADC over 8 bit ADC?
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[2] How many ADC channels are available in LPC-2294 IC?
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[3] Write decimal value displayed on LCD for following input voltage
0.0 V = _________ 0.1V = _______________ 0.5V = ____________
1 V = ___________ 2V= 3.3V = ____________
Resolution of ADC: ______

37
Experiment No.8
Aim: To understand architecture of Digital Signal Processor ADSP-2181
Brief Theory:
The ADSP-2181 is a single-chip microcomputer optimized for digital
signal processing (DSP) and other high speed numeric processing
applications. The ADSP-2181 combines the ADSP-2100 family base
architecture (three computational units, data address generators and a
program sequencer) with two serial ports, a 16-bit internal DMA port, a byte
DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities,
and on-chip program and data memory.
The ADSP-2181 integrates 80K bytes of on-chip memory configured as

16K words (24-bit) of program RAM, and 16K word (16-bit) of data RAM.
Power-down circuitry is also provided to meet the low power needs of battery
operated portable equipment. The ADSP-2181 is available in 128-lead TQFP
and 128 lead PQFP packages.
In addition, the ADSP-2181 supports new instructions, which include

bit manipulations—bit set, bit clear, bit toggle, bit test, new ALU constants,
new multiplication instruction (x squared), biased rounding, result free ALU
operations, I/O memory transfers and global interrupt masking for
increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS process,

the ADSP-2181 operates with a 25 ns instruction cycle time. Every
instruction can execute in a single processor cycle. The ADSP-2181’s flexible
architecture and comprehensive instruction set allow the processor to
perform multiple operations in parallel.
In one processor cycle the ADSP-2181 can perform following tasks:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
38
Functional block diagram of the ADSP-2181 is shown in the following
figure.
The ADSP-2181 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation) instructions.
Every instruction can be executed in a single processor cycle. The ADSP-
2181 assembly language uses an algebraic syntax for ease of coding and
readability. A comprehensive set of development tools supports program
development.
As shown in the block diagram, ADSP-2181 contains three

independent computational units: the ALU, the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit data directly
and have provisions to support multi-precision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division primitives
are also supported. The MAC performs single-cycle multiply, multiply/add
and multiply/subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormalization and
derive exponent operations. The shifter can be used to efficiently implement
numeric format control including multiword and block floating point
representations. The internal result (R) bus connects the computational
units so that the output of any unit may be the input of any unit on the next
cycle.
A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these computational
units. The sequencer supports conditional jumps, subroutine calls and
39
returns in a single cycle. With internal loop counters and loop stacks, the
ADSP-2181 executes looped code with zero overhead; no explicit jump
instructions are required to maintain loops. Two data address generators
(DAGs) provide addresses for simultaneous dual operand fetches (from data
memory and program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify
registers. A length value may be associated with each pointer to implement
automatic modulo addressing for circular buffers.
Efficient data transfer is achieved with the use of five internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the two data
buses (PMD and DMD) share a single external data bus. Byte memory space
and I/O memory space also share the external buses.
Program memory can store both instructions and data, permitting the
ADSP-2181 to fetch two operands in a single cycle, one from program
40
memory and one from data memory. The ADSP-2181 can fetch an operand
from program memory and the next instruction in the same cycle. In
addition to the address and data bus for external memory connection, the
ADSP-2181 has a 16-bit Internal DMA port (IDMA port) for connection to
external systems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM. An interface to low cost byte-wide
memory is provided by the Byte DMA port (BDMA port). The BDMA port is
bidirectional and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
Interrupts:
The ADSP-2181 can respond to 13 possible interrupts, eleven of which

are accessible at any given time. There can be up to six external interrupts
(one edge-sensitive, two level-sensitive and three configurable) and seven
internal interrupts generated by the timer, the serial ports (SPORTs), the
Byte DMA port and the power-down circuitry. There is also a master signal.
The two serial ports provide a complete synchronous serial interface

with optional companding in hardware and a wide variety of framed or
frameless data transmit and receive modes of operation. Each port can
generate an internal programmable serial clock or accept an external serial
clock.
The ADSP-2181 provides up to 13 general-purpose flag pins. The data

input and output pins on SPORT1 can be alternatively configured as an
input flag and an output flag. In addition, there are eight flags that are
programmable as inputs or outputs and three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A 16-bit count
register (TCOUNT) is decremented every n processor cycles, where n is a
scaling value stored in an 8-bit register (TSCALE). When the value of the
count register reaches zero, an interrupt is generated and the count register
is reloaded from a 16-bit period register (TPERIOD).
Serial Ports:
The ADSP-2181 incorporates two complete synchronous serial ports

(SPORT0 and SPORT1) for serial communications and multiprocessor
communication. Brief list of the capabilities of the ADSP-2181 SPORTs is
given below:
• SPORTs are bidirectional and have a separate, double- buffered

transmit and receive section.
41
• SPORTs can use an external serial clock or generate their own serial
clock internally.
• SPORTs have independent framing for the receive and transmit

sections. Sections run in a frameless mode or with frame synchronization
signals internally or externally generated. Frame sync signals are active high
or inverted, with either of two pulse widths and timings.
QUESTIONS
[1] What is the difference between Digital Signal Processor and General
Purpose Microprocessor?
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[2] How many pins are there in ADSP-2181. What types of packages are
available?
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[3] Which fabrication technology is used for ADSP-2181?
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[4] List five internal bus used for efficient data transfer
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[5]What is DAG and what is importance of DAG?
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[6]What are the interrupts available in ADSP-2181?
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[7] Write features of serial port available in ADSP-2181
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[8] What is function of MAC unit?
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43
Experiment No.9
Aim: To understand installation procedure of ADSPLite software and ADSP
Kit. To download and run sample programs on ADSP kit.
Brief Theory:
ADSP2181 Kit has following features:
• Analog Devices ADSP-2181SK-133 processor

• Operating at an instruction rate of 33MHz (16.667 external clock)
• Analog Audio Interface
- AD1847 – Analog Devices stereo codec
 Analog Inputs
o One stereo pair of 2V RMS AC coupled line-level inputs
o One stereo pair of 20mV RMS AC coupled microphone
inputs
• Analog Outputs
o One stereo pair of 1V RMS AC coupled line-level outputs
• Power Source
o 8 to 10V DC at 300mA
• RS-232 Interface
ADSP Kit System diagram:
44
Board Layout;
Installation of ADSP-2181 Kit :
 Remove the EZ-KIT Lite board from the package. Be careful while
handling the board to avoid the discharge of static electricity, which may
damage some components.
 Connect the RS-232 cable to an available COM Port on the PC and to J3

on the ADSP-2181 evaluation board.
 Plug the provided cord into a 230 Volt AC receptacle and plug the
connector at the other end of the cable into J4 on the evaluation board.
 Visually verify that all of the LEDs light up briefly. The power FL1 blinks.
If the LED does not light (green) LED remains on and up, check the
power connections.
To configure the ADSP-2181 board, we can take advantage of the audio
capabilities of the demos, use the following procedure.
 Plug a set of self-powered computer speakers into jack J1 on the board.

Turn on the speakers and set the volume to an adequate level.
 Connect the line out of an electronic audio device to jack J2 on the

board. Set jumper JP2 to LINE.
 Open Jumper JP2 to GND to enable the AD1847 codec. (This is the board
default).
45
Install EZ-KIT Lite software to download software in the ADSP-2181 chip.
After installation of the software, click on the short cut. Following screen will
appear.
To load the program, we can use following procedure:
 From the File menu, select Load.
The Open a Processor Program dialog box appears.
 Navigate to the folder where your DSP executable file resides.

The demos supplied with the EZ-KIT Lite are located in the
..\218x\EZ-KITs\2181\Examples subdirectory of the harddisk where you

have installed the program
 Select the file and click Open.
The file loads and the Load Complete message appear in the Output window
when the load process has completed.
Procedure to write and execute program:
• Write ADSP program using any text editor and than save it using .dsp
extension.
• Assemble program by giving following command at command prompt.
> asm21 <filename> -2181 -C
After assembly assembler generates three files:
46
- .INT : Initialization data file
- .CDE : Code File
- .OBJ : Object File
If we specify listing option –l it will also generate list file .LST

For example, if we want to assemble test.dsp file
> asm21 test.dsp -2181 -C
After assembly assembler generates three files:
- test.int
- test.cde
- test.obj
If we specify option –l it will also generate test.lst
 asm21 test.dsp -2181 –C –l
 To know more options type asm21 -help
More switch options:
Example program:
{
fixdpadd.dsp - Fixed point double precision addition experiment.
}
.module/RAM/ABS=0 example;
.include <c:\adi_dsp\macros\begin1.dsp>;
ax1 = 0x0005;
ax0 = 0x0001;
ay1 = 0x0000;
ay0 = 0x0005;
AR = AX0+AY0; {Add LSWs}
SR0 = AR,AR = AX1+AY1+C; {Add MSWs}
SR1 = AR;
dm(0) = sr0;
dm(1) = sr1;
rts;
.endmod;
Assemble and link above program to generate ROM image
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WORKSHEET
Write program for addition of two numbers in C language, for 8051 and for
ADSP-2181 and give your comments
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Write steps to generate ROM image from the assembly language file
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How DSP programs are downloaded from PC to ADSP-2181 ?
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Experiment No.10
Aim: To generate sine wave, square wave using ADSP-2181
Brief Theory:
To generate sine wave using DSP, look up table is prepared. Magnitude of
samples of sine wave is stored in the look up table hex format. Hex value is
transferred to output port one by one. Output port is connected to digital to
analog converter which provides analog output. Accuracy of sine wave
depends on how many number of samples are used to create it. To smooth
the sine wave output of DAC is passed through low pass filter.
Program:
{
Sine wave generation program
}
.module/RAM/ABS=0 wavegen;
.include <c:\adi_dsp\macros\wavgen.dsp>;
{--- define sampling rate in Khz: ----------------------------------------}

{0xc850 = 8 | 0xc851 = 5.5125 | 0xc852 = 16 }
{0xc853 = 11.025 | 0xc854 = 27.42857 | 0xc855 = 18.9 }
.const fs = 0xc850; {0xc856 = 32 | 0xc857 = 22.05 | 0xc859 = 37.8 }
{0xc85b = 44.1 | 0xc85c = 48 | 0xc85d = 33.075}
{0xc85e = 9.6 | 0xc85f = 6.615 | }
{-------------------------------------------------------------------------}
.include <c:\adi_dsp\macros\begin.dsp>; { processor initialization.}
{--- define constants, variables, and buffers ----------------------------}
.const D = 4000;
.var/dm/circ sine[D]; { Min frequaency f1 = fs/D = 8/4 = 2Hz}
.init sine: <sinetbl.hex>; { Load one period of the wave table}
.const A = 0x1a00; { A = 0.5 = signal amplitude}
.const c = 1000; { Signal frequency f = c * f1 = 1000Hz}
i6 = ^sine; L6 = %sine; { Pointer for signal generator}

imask = b#0000110000; { Enable rx0 interrupt}
{--- start processing input samples --------------------------------------}
wait: idle; jump wait; {wait for interrupt and loop forever}
49
{interrupt service routine starts here}
input_samples: ena sec_reg; {enable secondary register set}
{--- sample processing algorithm -----------------------------------------}
wavgen(i6, m6, A, c, mx1); {mx1 = A * sin(2*pi*f*t)}
{--- write output samples to codec ---------------------------------------}
dm(tx_buf+1) = mx1; {left output sample}

dm(tx_buf+2) = mx1; {right output sample}
{--- return from interrupt -----------------------------------------------}
rti;
.include <c:\adi_dsp\macros\end.dsp>;
.endmod;
Sine Table:
0000,0033,0067,009a,00ce,0101,0135,0168,019c,01cf,0203,0236,026a,029d,02d1,0304,
0337,036b,039e,03d2,0405,0439,046c,04a0,04d3,0506,053a,056d,05a1,05d4,0608,063b,
066e,06a2,06d5,0709,073c,076f,07a3,07d6,080a,083d,0870,08a4,08d7,090a,093e,0971,0
9a4,09d8,0a0b,0a3e,0a72,0aa5,0ad8,0b0b,0b3f,0b72,0ba5,0bd8,0c0c,0c3f,0c72,0ca5,0cd9
,0d0c,0d3f,0d72,0da5,0dd9,0e0c,0e3f,0e72,0ea5,0ed8,0f0b,0f3f,0f72,0fa5,0fd8,100b,103e,
1071,10a4,10d7,110a,113d,1170,11a3,11d6,1209,123c,126f,12a2,12d5,1308,133b,136d,
13a0,13d3,1406,1439,146c,149f,14d1,1504,1537,156a,159c,15cf,1602,1634,1667,169a,
16cc,16ff,1732,1764,1797,17ca,17fc,182f,1861,1894,18c6,18f9,192b,195e,1990,19c3,19f5,
1a27,1a5a,1a8c,1abe,1af1,1b23,1b55,1b88,1bba,1bec,1c1e,1c51,1c83,1cb5,1ce7,1d19,
1d4b,1d7d,1daf,1de2,1e14,1e46,1e78,1eaa,1edc, 1f0d,1f3f,1f71,1fa3,1fd5,2007,2039,206b
…………….7fff,
7fff,7fff,7ffe,7ffd,7ffd,7ffc,7ffb,7ffa,7ff9,7ff8,7ff7,7ff6,7ff4,7ff3,7ff1,7ff0,7fee,7fec,7feb,7fe9,
7fe7,………..,009a,0067,0033,0000
{
Square.dsp – Square wave generated from a wavetable
}
.module/RAM/ABS=0 wavegen;
.include <c:\adi_dsp\macros\wavgen.dsp>;
{--- define sampling rate in khz: ----------------------------------------}

.const fs = 0xc850;
.include <c:\adi_dsp\macros\begin.dsp>; {processor initialization.}
.const D = 4000;
.var/dm/circ square[D]; {min frequaency f1 = fs/D = 8/4 = 2Hz}
.init square: <squartbl.hex>; {load one period of the wave table}
.const A = 0x5a82; {A = 0.5 = signal amplitude}
.const c = 100; {signal frequency f = c * f1 = 1000Hz}
i6 = ^square; L6 = %square; {pointer for signal generator}

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imask = b#0000110000; {enable rx0 interrupt}
wait: idle; jump wait; {wait for interrupt and loop forever}
{interrupt service routine starts here}
{--- sample processing algorithm -----------------------------------------}
wavgen(i6, m6, A, c, mx1); {mx1 = A * sin(2*pi*f*t)}
dm(tx_buf+1) = mx1; {left output sample}
dm(tx_buf+2) = mx1; {right output sample}

rti;
.include <c:\adi_dsp\macros\end.dsp>;
.endmod;
squartbl.hex file contains ox7fff and 0x8000 (Two levels +V and –V)
WORKSHEET
Observations and waveforms:

Observe sine wave output from the kit at ADC output and plot it in the
following space. Measure amplitude and frequency and mention it on the
waveform.
Observe square output from the kit:
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Change sine wave hex table, assemble and link program file again and
observe change in the waveform. Plot modified waveform in the following
space.
QUESTIONS
[1] Explain following instructions for ADSP-2181 processor.
 AR=AX0+AY0, AX0=MR2;
 AX0=DM(I2,M0), AY0=PM(I4,M6);
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Experiment No.11
Aim: To filter input signal using FIR filter implementation with ADSP-2181
Brief Theory:
In FIR filter, response to impulse becomes zero after a finite number of
samples. Finite duration impulse response filter (FIR) has a system function
of the form:
M 1
H ( z )  b0  b1 z 1  ..........  bM 1 z 1 M   bn z n
n 0
Impulse response of FIR filter is:

h(n)= bn for 0  n M-1
=0 else where
The difference equation representation can be given by
y(n) = b0x(n)+ b1x(n-1)+ …………….+ bM-10x(n-M+1)
Where b0,b1, ......bM-1 are the filter coefficients
x(n), x(n-1), … are input samples.
M is length of filter (Number of filter coefficients)
Order of the FIR filter is M-1 and number of filter coefficients i.e.
length of the filter is M. If we use four coefficients, order of filter is 3. FIR
filter structures are always stable and relatively simple compared to IIR
structures. Furthermore, FIR filters can be designed to have linear phase
response, which is desirable in certain applications.
To implement FIR filter, convolution of filter coefficients is done with
the input signal.
Procedure:
 Assemble FIR filter program lowpass.dsp and link to generate
lowpass.exe file
 Download program into ADSP2181 kit using ADSPLite software
 Connect function generator at the audio input terminal
 Connect C.R.O. at the audio output terminal
 Vary frequency from the function generator and note down amplitude of
the output waveform at different frequency.
 Amplitude of output voltage reduces as frequency increases. Note down
the readings and plot the frequency response
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Program:
{ FIR Low pass filter: lowpass.dsp }
for each input x do:

sD = tap(D, w, p, D) get D-th tap
v0 = a * v1 + sD input to unit delay
u = b0 * v0 + b1 * v1 output of feedback filter
y=x+u filter output
v1 = v0 update unit delay
*p = y input to D-fold delay
cdelay(D, w, &p) update D-fold delay
}
.const fs = 0xc850; { Sampling rate 8 KHz}
.include <c:\adi_dsp\macros\begin.dsp>; {initializations and DSP macros}
{--- define constants, variables, and buffers ----------------------------}
.var/dm v1; {state of first-order feedback filter}
.const a = 0x4000; {a = 0.50}

.const b0 = 0x199a; {b0 = 0.20}
.const b1 = 0x0ccd; {b1 = 0.10}
.const D = 3000; {TD = D/fs = 3/8 = 0.375 sec}

.var/dm/circ w[D+1]; { circular delay line}
i2 = ^w; L2 = %w; { delay-line buffer pointer and length}
ax0 = 0;
dm(v1) = ax0; { clear feedback delay, v1 = 0}
zero(i2, m2, L2); { clear delay line}
wait: idle; jump wait; { wait for interrupt and loop forever}
{ Interrupt service routine starts here}
{--- read input samples from codec ---------------------------------------}
ax1 = dm(rx_buf + 1); {left input sample}

mx1 = dm(rx_buf + 2); {right input sample}
{--- sample processing algorithm --- process right channel only ----------}
tap(i2, m2, D, mr1); {mr1 = sD = D-th tap}
mx0 = a;
my1 = dm(v1); {state v1}
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mr = mr + mx0 * my1 (rnd); {mr = v0 = sD + a * v1}
if mv sat mr;
sr0 = mr1; { Save v0 for later updating v1}
my0 = b0;
mr = mr1 * my0 (ss); {mr = b0 * v0}
mx0 = b1;
mr = mr + mx0 * my1 (rnd); {mr = u = b0 * v0 + b1 * v1}
if mv sat mr;
ay1 = mx1; { ay1 = x = input}

ar = mr1 + ay1; { ar = y = x + u = output}
dm(v1) = sr0; { update lowpass filter, v1 = v0}

tapin(i2, m2, ar); { put y in tap-0}
cdelay(i2, m2); { update delay}
dm(tx_buf + 1) = ar; { left output sample}

dm(tx_buf + 2) = ar; { right output sample}
rti;
.include <c:\adi_dsp\macros\end.dsp>; {wrapup}
WORKSHEET
Observations and waveforms:

Input signal amplitude: Vi = 0.5 Volt
Sr. Input signal Output Voltage Attenuation Attenuation

No. frequency (Vo) (Vo/Vi) in dB
10log(Vo/Vi)
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:: WORKSHEET::
[1] Change filter coefficients in the program:
Instead of b0 = 0.2 and b1=0.1 use b0=0.5 and b1=-0.5. Assemble and link
program again. Download ROM image in ADSP kit and run it. Observe
variation in amplitude with frequency.
As per observation by you answer the following question.
What type of filter is implemented? : __________________________________.
[2] What is the difference between FIR filter and IIR filter?
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[2] What is the advantage of increasing number of filter coefficients? What is

the disadvantage?
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Experiment No.12
Aim: To understand architecture of TMS320C6713 DSP chip
The general purpose DSP processors are available from Intel, Texas
Instruments, Motorola, Analog devices, Agere, DSP groups etc.
TMS320C6713 is manufactured by Texas. DSP systems are embedded into
larger systems to perform specialized DSP functions. Texas Instruments
introduced fixed point and floating point processors. The examples of 16 bit
fixed point DSP processors from the Texas are: TMS320C2000 (C24x and
C28x), TMS320C5000 (C54x and C55x), TMSC6000 (C62x and C64x). 32 Bit
floating point processors are: TMS320C3x (C30, C31, C32 and C33),
TMS320C40 and TMS320C67xx (TMS320C6711, TMS320C6712,
TMS320C6713).
Let us understand brief introduction of TMS320C6000 platform. The
TMS320C6000 has performance of 2000 MIPS (Million instructions per
second) at 250 MHz. TMS320C6000 platform provides good solution for the
multi-channel, multifunction applications such as Audio processing,
Imaging, Pooled modems, Wireless local loop base stations, Beam-forming
base stations, Remote access servers (RAS), Digital subscriber loop (DSL)
systems, Cable modems, Multi-channel telephony systems, Virtual reality 3-
D graphics, Speech recognition, Radar, Atmospheric modeling etc.
TMS320C6000 processors consists of three main parts: CPU (or the
core), peripherals, and memory. The DSP core CPU consists of 32 general-
purpose registers of 32-bit word length and eight functional units:
 Two multipliers
 Six ALUs
Above eight functional units operate in parallel, with two similar sets
of the basic four functional units. The units communicate using a cross
path between two register files, each of which contains 16 32-bit registers.
Program parallelism is defined at compile time because there is no data
dependency checking done in hardware during run time. The 256-bit-wide
program memory fetches eight 32-bit instructions every single cycle.
The general block diagram of TMS320C6000 DSP is shown in the
Fig.1. The C6000 devices comes with on-chip program and data memory,
which may be configured as cache on some devices. Different devices have
varying size of data memory. Peripherals include a direct memory access
(DMA) controller, power-down logic, external memory interface (EMIF), serial
port(s), expansion bus or host port, and timer(s)
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Fig. 1 General Block diagram of TMS320C6000 DSP
Now let us look at the architecture of DSP chip TMS320C6713 which

is based on TMS320C6000 platform. The TMS320C67x Digital Signal
Processors (including the TMS320C6713 and TMS320C6713B devices)
compose the floating-point DSP generation in the TMS320C6000 DSP
platform. The C6713 and C6713B devices are based on the high-
performance, advanced very-long-instruction-word (VLIW) architecture. DSP
TMS320C67x is an excellent choice for multi-channel and multifunction
applications. Operating at 225 MHz, the C6713/13B delivers up to 1350
million floating-point operations per second (MFLOPS), 1800 million
instructions per second (MIPS), and with dual fixed-/floating-point
multipliers up to 45 million multiply-accumulate operations per second
(MMACS).
TMS320C6713 operating at 300 MHz, the C6713B delivers up to 1800
million floating-point operations per second (MFLOPS 2400 million
instructions per second (MIPS), and with dual fixed-/floating-point
multipliers up to 600 million multiply-accumulate operations per second
(MMACS).
The C6713/13B uses a two-level cache-based architecture and has a
powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a
4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte
2-way set-associative cache. The Level 2 memory/cache (L2) consists of a
256K-Byte memory space that is shared between program and data space.
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64K Bytes of the 256K Bytes in L2 memory can be configured as mapped
memory, cache, or combinations of the two. The remaining 192K Bytes in L2
serves as mapped SRAM. The C6713/13B has a rich peripheral set that
includes two Multi-channel Audio Serial Ports (McASPs), two Multi-channel
Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one
dedicated General-Purpose Input/Output (GPIO) module, two general-
purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and
asynchronous peripherals.
The two McASP interface modules each support one transmit and one
receive clock zone. Each of the McASP has eight serial data pins which can
be individually allocated to any of the two zones. The serial port supports
time-division multiplexing on each pin from 2 to 32 time slots. The
C6713/13B has sufficient bandwidth to support all 16 serial data pins
transmitting a 192 kHz stereo signal. Serial data in each zone may be
transmitted and received on multiple serial data pins simultaneously and
formatted in a multitude of variations on the Philips Inter-IC Sound (I2S)
format. In addition, the McASP transmitter may be programmed to output
multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels
simultaneously, with a single RAM containing the full implementation of
user data and channel status fields. The McASP also provides extensive
error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is
within a programmed frequency range.
The two I2C ports on the TMS320C6713/13B allow the DSP to easily
control peripheral devices and communicate with a host processor. In
addition, the standard multi-channel buffered serial port (McBSP) may be
used to communicate with serial peripheral interface (SPI) mode peripheral
devices.
The TMS320C6713/13B device has two bootmodes: one is from the
HPI or other is from external asynchronous ROM.
TMS320C6713 DSP chip comes in 272 ball BGA package and 208 pin
Plastic Quad Flat Pack (PQFP). For the detail ball diagram and pin diagram,
students should refer datasheet of TMS3206713.
The general block diagram of TMS320C6713 is shown in Fig. 2.
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Fig. 2 General block diagram of TMS320C6713 DSP chip
CPU core description:

The CPU features two sets of functional units. Each set contains four
units and a register file. One set contains functional units .L1, .S1, .M1, and
.D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 16 32-bit registers for a total of 32 general-purpose
registers. The two sets of functional units, along with two register files,
compose sides A and B of the CPU. The four functional units on each side of
the CPU can freely share the 16 registers belonging to that side.
Additionally, each side features a single data bus connected to all the
registers on the other side, by which the two sets of functional units can
access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can
service all the units in a single clock cycle, register access using the register
file across the CPU supports one read and one write per cycle. The C67x
CPU executes all C62x instructions. In addition to C62x fixed-point
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instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2,
and .L2) also execute floating-point instructions. The remaining two
functional units (.D1 and .D2) also execute the new LDDW instruction
which loads 64 bits per CPU side for a total of 128 bits per cycle.
Another key feature of the C67x CPU is the load/store architecture,
where all instructions operate on registers (as opposed to data in memory).
Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven
by the .D units allows data addresses generated from one register file to be
used to load or store data to or from the other register file. The C67x CPU
supports a variety of indirect addressing modes using either linear- or
circular-addressing modes with 5- or 15-bit offsets. All instructions are
conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold
the condition for conditional instructions (if the condition is not
automatically “true”). The two .M functional units are dedicated for
multiplies. The two .S and .L functional units perform a general set of
arithmetic, logical, and branch functions with results available every clock
cycle. The processing flow begins when a 256-bit-wide instruction fetch
packet is fetched from a program memory. The 32-bit instructions destined
for the individual functional units are “linked” together by “1” bits in the
least significant bit (LSB) position of the instructions. The instructions that
are “chained” together for simultaneous execution (up to eight in total)
compose an execute packet. A “0” in the LSB of an instruction breaks the
chain, effectively placing the instructions that follow it in the next execute
packet. If an execute packet crosses the fetch-packet boundary (256 bits
wide), the assembler places it in the next fetch packet, while the remainder
of the current fetch packet is padded with NOP instructions. The number of
execute packets within a fetch packet can vary from one to eight. Execute
packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After
decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While
most results are stored in 32-bit registers, they can be subsequently moved
to memory as bytes or half-words as well. All load and store instructions are
byte-, half-word, or word-addressable.
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Fig. 3 TMS320C6713 DSP Core description
The components of the data path for the TMS320C67xCPU are shown
in the Fig. 3. These components consist of:
 Two general-purpose register files (A and B)
 Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2)
 Two load-from-memory data paths (LD1 and LD2)
 Two store-to-memory data paths (ST1 and ST2)
 Two data address paths (DA1 and DA2)
 Two register file data cross paths (1X and 2X)
General purpose registers files:

There are two general-purpose register files (A and B) in the C6713 data
paths. Each of these files contains 16 32-bit registers (A0–A15 for file A and
B0–B15 for file B. The general-purpose registers can be used for data, data
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address pointers, or condition registers. Most data lines in the CPU support
32-bit operands, and some support long (40-bit) and double word (64-bit)
operands. Each functional unit has its own 32-bit write port into a general-
purpose register file.
Functional units:
The eight functional units in the C6713 data paths can be divided into two
groups of four; each functional unit in one data path is almost identical to
the corresponding unit in the other data path. The functional units are
described in the following table.
Most data lines in the CPU support 32-bit operands, and some support long
(40-bit) and double word (64-bit) operands. Each functional unit has its own
32-bit write port into a general-purpose register. All units ending in 1 (for
example, .L1) write to register file A, and all units ending in 2 write to
register file B. Each functional unit has two 32-bit read ports for source
operands src1 and src2. Four units (.L1, .L2, .S1, and .S2) have an extra 8-
bit-wide port for 40-bit long writes, as well as an 8-bit input for 40-bit long
reads. Because each unit has its own 32-bit write port, when performing 32-
bit operations all eight units can be used in parallel every cycle.
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Memory load and store paths:
The C67x DSP has two 32-bit paths for loading data from memory to
the register file: LD1 for register file A, and LD2 for register file B. The
C67x DSP also has a second 32-bit load path for both register files A and
B. This allows the LDDW instruction to simultaneously load two 32-bit
values into register file A and two 32-bit values into register file B. For
side A, LD1a is the load path for the 32 LSBs and LD1b is the load path
for the 32 MSBs. For side B, LD2a is the load path for the 32 LSBs and
LD2b is the load path for the 32 MSBs. There are also two 32-bit paths,
ST1 and ST2, for storing register values to memory from each register
file. On the C6000 architecture, some of the ports for long and
doubleword operands are shared between functional units. This places a
constraint on which long or doubleword operations can be scheduled on
a data path in the same execute packet.
Two data address paths (DA1 and DA2):
The data address paths (DA1 and DA2) are each connected to the .D
units in both data paths. This allows data addresses generated by any
one path to access data to or from any register. The DA1 and DA2
resources and their associated data paths are specified as T1 and T2,
respectively. T1 consists of the DA1 address path and the LD1 and ST1
data paths. For the C67x DSP, LD1 is comprised of LD1a and LD1b to
support 64-bit loads. Similarly, T2 consists of the DA2 address path and
the LD2 and ST2 data paths. For the C67x DSP, LD2 is comprised of
LD2a and LD2b to support 64-bit loads. The T1 and T2 designations
appear in the functional unit fields for load and store instructions. For
example, the following load instruction uses the .D1 unit to generate the
address but is using the LD2 path resource from DA2 to place the data in
the B register file. The use of the DA2 resource is indicated with the T2
designation.
LDW .D1T2 *A0[3],B1
Two register file data cross paths (1X and 2X)
Each functional unit reads directly from and writes directly to the
register file within its own data path. That is, the .L1, .S1, .D1, and .M1
units write to register file A and the .L2, .S2, .D2, and .M2 units write to
register file B. The register files are connected to the opposite-side
register file’s functional units via the 1X and 2X cross paths. These cross
paths allow functional units from one data path to access a 32-bit
operand from the opposite side register file. The 1X cross path allows the
functional units of data path A to read their source from register file B,
and the 2X cross path allows the functional units of data path B to read
their source from register file A. On the C67x DSP, six of the eight
functional units have access to the register file on the opposite side, via a
cross path. The .M1, .M2, .S1, and .S2 units’ src2 units are selectable
between the cross path and the same side register file. In the case of the
.L1 and .L2, both src1 and src2 inputs are also selectable between the
cross path and the same-side register file. Only two cross paths, 1X and
64
2X, exist in the C6000 architecture. Thus, the limit is one source read
from each data path’s opposite register file per cycle, or a total of two
cross path source reads per cycle. In the C67x DSP, only one functional
unit per data path, per execute packet, can get an operand from the
opposite register file.
QUESTIONS
[1] What is the function of following units in DSP chip TMS320C6713?
[a] L unit [b] M unit [c] S unit [d] D unit
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_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
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_____________________________________________________________________
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[2] What is cross path? Why cross path is needed?
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65
Experiment No. 13
Aim: To understand features of Cypress Programmable System on Chip
(PSoC). To download and execute demo programs to display vertical bar
graph using LEDs depending on analog input voltage.
Introduction:
PSoC® is a true programmable embedded system-on-chip integrating

configurable analog and digital peripheral functions, memory and a
microcontroller on a single chip.
It has following features:
 Programmable routing and interconnect:
Using this feature it is possible to re-route signals to user selected pins,

shedding the constraints of a fixed-peripheral controller. In addition, global
buses allow for signal multiplexing and logic operations, eliminating the
need for a complicated digital-logic gate design.
 Configurable analog and digital blocks:
Configurable analog and digital circuitry is the basis of the PSoC platform.
We can configure these blocks using pre-built library functions or by
creating our own. By combining several digital blocks, we can create 16-,
24-, or even 32-bit wide logic resources. The analog blocks are composed of
switch capacitor, op-amp, comparator, ADC, DAC, and digital filter blocks,
allowing complex analog signal flows
 CPU Subsystem:
PSoC has sophisticated CPU subsystem with SRAM , EEPROM, and flash
memory, multiple core options and a variety of essential system resources
including:
 Internal main and low-speed oscillator

 Connectivity to external crystal oscillator for precision, programmable
clocking
 Sleep and watchdog timers
 Multiple clock sources that include a PLL
PSoC devices also have dedicated communication interfaces like I2C, Full-
Speed USB 2.0, CAN 2.0, and on-chip debugging capabilities using JTAG
66
and Serial Wire Debug. The newest members of the PSoC family offer
industry-standard processors like the 8051 and ARM Cortex-M3.
We will use PSoC designer software to execute and download programs into
PSoC Device CY8C24894. Program reads analog input voltage which given
by preset available on the board. Depending on preset value, LEDs as
glowing.
Board Section: Top Right

PSoC Device: CY8C24894
Project Location: \Projects\AnalogInputDriveLEDs.app
Procedure:
Step 1. Create a new Project
1. Click on File->New Project

2. Enter any desired name for the project. Here AnalogInputDriveLEDs.
3. Click Ok
4. Select the target device from Catalog as CY8C24894-24LTXI
5. Click Ok. A new project will be created.
Step 2. Add User Modules

1. Go to the User Module Window.
2. Right Click on Misc Digital->LED. Select Place. This needs to be done six
times for six leds.
3. Right Click on Amplifiers->PGA. Select Place
4. Right Click on ADCs->ADCINC. Select Place. Select Single Stage
Modulator.
Step 3. Set Parameters for User Modules
1. LED_1
Select the Port, Pin and Drive mode
a. PORT -> Port_2
b. PIN -> Port_2_4
c. Drive -> Active High
2. LED_2
a. PORT -> Port_2
b. PIN -> Port_2_0
3. LED_3
a. PORT -> Port_2
b. PIN -> Port_2_1
4. LED_4
67
a. PORT -> Port_2
b. PIN -> Port_2_2
5. LED_5
a. PORT -> Port_2
b. PIN -> Port_2_3
6. LED_6
a. PORT -> Port_2
b. PIN -> Port_2_5
7. ADCINC_1
Select the parameters as below
a. DataFormat -> UnSigned
b. Resolution -> 10bit
c. Data Clock -> VC1
d. ClockPhase -> Normal
e. PosInput -> ACB00
8. PGA_1
a. Gain -> 1.000
b. Input -> AnalogColumnMuxBusSwitch_0
c. Reference -> VSS
d. AnalogBus -> Disable
Step 4. Connecting and Routing
1. In the Chip level Design Window Click on AnalogColumn_InputMux_0
2. Select Input as Port_0_1
Step 5. Add Code to void main(void)
WORD wData;
M8C_EnableGInt; // Enable Global Interrupts
PGA_1_Start(PGA_1_HIGHPOWER); // Apply power to the CT Block
ADCINC_1_Start(ADCINC_1_HIGHPOWER); // Apply power to the SC Block
ADCINC_1_GetSamples(0); // Have ADC run continuously
for(;;)
{
while(ADCINC_1_fIsDataAvailable() == 0); // Loop until value ready
wData = ADCINC_1_iClearFlagGetData(); // Clear ADC flag and get data
if(wData>20) // Decision Control to decide which LEDs to be kept

LED_1_On(); // On or Off
else
LED_1_Off();
if(wData>186)
LED_2_On();
68
else
LED_2_Off();
if(wData>352)
LED_3_On();
else
LED_3_Off();
if(wData>518)
LED_4_On();
else
LED_4_Off();
if(wData>684)
LED_5_On();
else
LED_5_Off();
if(wData>850)
LED_6_On();
else
LED_6_Off();
}
Step 6. Build the Project
1. Click on Build->Generate/Build ‘AnalogInputDriveLED’ Project
Step 7. Programming the PSoC Device
1. Remove the jumpers between J12 and J13
2. Install the MiniProg on J13
3. Click the Programming tab.
4. Click Program at the top of the window. This will open the PSoC
Programmer application.
5. Select MINIProg1/… in the “Port” pull down list
6. Click Power Cycle under “Programming Mode”
7. Click the Program button on the top toolbar
8. Wait for the “Programming Succeeded at ….” status message to be

displayed.
Step 8. Test your project on the Demonstration Board
9. Click Toggle Device Power

The red Target Power LED on the MiniProg will light.
Change the Potentiometer setting to observe the LEDs light up
69
Experiment No. 14
Aim: To read analog voltage and display it on LCD using cypress kit
Description: This project displays a voltage input as a numeric value and as
a bar graph on an LCD display.
Board Section: Bottom Left
PSoC Device: CY8C27643
Project Location: \Projects\AnalogInputDriveLCD
Procedure for experiment:
Step 1. Create a new Project
1. Click on File->New Project

2. Enter any desired name for the project. Here AnalogInputDriveLCD.
3. Click Ok
4. Select the target device from Catalog as CY8C27643-24LFXI
5. Click Ok. A new project will be created.
Step 2. Add User Modules
1. Go to the User Module Window.

2. Right Click on ADCs->ADC. Select Place. Select Single Stage Modulator.
3. Right Click on Misc Digital->LCD. Select Place.
4. Right Click on Amplifiers->PGA. Select Place.
Step 3. Set Parameters for User Modules
1. ADCINC_1
a. DataFormat -> Unsigned
b. Resolution -> 10bit
c. Data Clock -> VC1
d. ClockPhase -> Normal
e. PosInput -> ACB00
2. PGA_1
a. Gain -> 1.000
b. Input -> AnalogColumn_InputMux_0
c. Reference -> VSS
d. AnalogBus -> Disable
3. LCD_1
a. LCDPort -> Port_4
b. BarGraph -> Enable
Step 4. Add Code to void main(void)
WORD wData;
BYTE bBarPos
70
M8C_EnableGInt; // Enable Global Interrupts
PGA_1_Start(PGA_1_LOWPOWER);
ADCINC_1_Start(ADCINC_1_LOWPOWER); // Apply power to the SC Block
ADCINC_1_GetSamples(0); // Have ADC run continuously
LCD_1_Init();
LCD_1_Start(); // Initialize LCD
LCD_1_Position(1,0); // Place LCD cursor at row 0, col 5.
LCD_1_InitBG(LCD_1_SOLID_BG);
while(1)
{
while(ADCINC_1_fIsDataAvailable() == 0); // Loop until value ready
wData = ADCINC_1_iClearFlagGetData(); // Clear ADC flag and get data
bBarPos = ((float)wData/1024)*80;
LCD_1_DrawBG(0,0,16,bBarPos);
LCD_1_Position(1,0); // Place LCD cursor at row 1, col 0.
LCD_1_PrHexInt(wData);
}
Step 5. Build the Project
Click on Build->Generate/Build ‘AnalogInputDriveLCD’ Project
Step 6. Programming the PSoC Device
1. Remove the jumpers between J1 and J2
2. Install the MiniProg on J1
3. Click the Programming tab.
4. Click Program at the top of the window. This will open the PSoC
Programmer application.
5. Select MINIProg1/… in the “Port” pull down list
6. Click Power Cycle under “Programming Mode”
7. Click the Program button on the top toolbar
8. Wait for the “Programming Succeeded at ….” status message to be

displayed.
Step 7. Test your project on the Demonstration Board
Click Toggle Device Power

The red Target Power LED on the MiniProg will light.
Adjust the potentiometer. The input voltage will be displayed as being
presented on a horizontal bar graph.
71
Experiment No.15
Aim: To become familiar with GCC compiler, WinARM and crossware
development tools. To assemble and run programs using crossware
tools
Write your program in the text editor provided in the Linux and save it with
extension .c for C .cpp for C++ and .s for assembly language
Give following command on command line (Dollar sign $ is shell prompt)
$ g++ test.cpp
This command will compile test.cpp file and generates binary file a.out because
we have not specified target file name
To run the program type:
$./a.out
We can also give output file option like following:
$ g++ -o test.o test.cpp
It will generate output file test.o
To run this file in shell prompt:
$ ./test
Write any c++ program and try above commands
Similarly C programs can be compiled by GNU GCC compiler
$ gcc test.c
$ gcc –o test test.c
-c option can be specified to compile only (It will compile but not link)
$ gcc –c test.c
Stop after assembling. Do not link…
(It will not generate executable file. This will check syntax error in the program)
Another option is –S.
$ gcc –s test.c
This will compile but not assemble and link the program.
-Wall option turn on all warning levels.
$ gcc –Wall –W test.c
To turn off all the warning use following command (Actually do not use it because it
will not give any warning which is dangerous during programming)
$ gcc –w test.c
$ g++ -w test.cpp (For C++)
72
$ as test.s
This will generate a.out file
$ as –o test.o test.s (Assembling)
This will generate object file test.o
$ld –o test.elf test.o (Linking)
This will generate HEX file test.elf which can be further programmed into
the chip
$ arm-elf-as –o test.o test.s (Assemble)
$ arm-elf-ld –o test.elf test.o (Link)
We can also define target cpu
$ arm-elf-as –cpu=arm7tdmi –o test.o test.s
Write following sequence in assembly language for ARM processor and

simulate it using Crossware tool and verify the result.
Program 1:
MOV R1,#0x55
MOV R2,#0x33
ADD R3,R1,R2
SUB R4,R1,R2
LOOP: B LOOP
Program 2:
MOV R0,#0x64
MOV R1,#0x10
LOOP: ADD R1,R1,#1
CMP R1,R0
BLT LOOP
HERE: B HERE
Write your comments after executing the above programs

_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
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73
:: ASSIGNMENT ::
[1] What is meaning of load and store architecture?

[2] What are the performance matrices for DSP processors?
[3] Why interrupt response is fast in ARM processor?
[4] What is the meaning of “T” and “M” in ARM7TDMI architecture?
[5]What is the difference between fixed point and floating point
representation? Explain IEEE floating point format.
[6] Explain how three stage pipeline works
[7] What are the variants of ARM processor?
[8] What do you mean by hardwired implementation?
[9] Which technology is used in ARM7TDMI? What is typical die size?
[10] What is CAN?
[11] Which ARM chip you have used in your practical? What is the size of
RAM and ROM in that chip ?
[12] Give example of two data transfer instructions
[13] What is post indexing and pre indexing?
[14]How exception handling is done in ARM?
[15]Explain branch operations in ARM
[16] Explain instructions LDR r4,[r5,#8]! And LDR r4,[r5,#8]
[17] What is difference between ASR and LSR?
[18] What is the difference between real time operating system and
general purpose operating system?
[19] What is the difference between CISC and RISC processor?
[20] ARM processor is based on which architecture?
[21] What is CPSR and SPSR?
[22] What is the difference between ARM processor and DSP processor?
[23] Explain following instructions:
[a] RSC R1,R2 [b] ADD R1,R2,R2,LSL#1 [c] MLA R1,R2,R3,R4
[24] What is real time operating system?
[25] List applications of Embedded systems
[26] What is watchdog timer?
[27] What is brown out reset?
[28] Write commands to compile C language file and assemble assembly
language file using GNU C compiler and GNU assembler.
[29] What is priority inversion? How it occurs?
[30] Explain deadlock situation. How to prevent deadlock situation?
[31] What is round-robbin scheduling? Is it suitable for real time
applications?
[32] What is job of scheduler?
[33] What is context switching?
[34] What is yield?
[35] What are the special functions of R13, R14 and R15 in ARM
processor?
Note: Write answers in separate notebook
74

ES LabManual 2011

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Embedded Systems

Name of the student:_________________________________

Government Engineering College, Rajkot

This is to certify that Mr/Miss ________________________________________

term work of the subject Embedded Systems prescribed by Saurashtra

University during the academic term ___________________________

Date: Signature of the faculty

Pipelining is employed so that all parts of the processing and memory

The ARM memory interface has been designed to allow the

The ARM7TDMI processor employs a unique architectural strategy

The key idea behind THUMB is that of a super-reduced instruction set.

• Standard 32-bit ARM set

• 16-bit THUMB set

THUMB instructions operate with the standard ARM register configuration,

The major advantage of a 32-bit (ARM) architecture over a 16-bit

If a 16-bit architecture only has 16-bit instructions, and a 32-bit

THUMB breaks this constraint by implementing a 16-bit instruction length

Core diagram of the ARM7TDMI is shown in the following figure.

 Register 14 is used as the subroutine link register. This receives a

 FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq).

 Address bus of ARM7TDMI has 32 address If ALE (address latch enable)

 The ARM7TDMI contains a Current Program Status Register (CPSR), plus

[3] Set the processor operating mode

 The arrangement of bits is in CPSR is shown below:

Load and Store architecture:

ARM Exceptions: ARM architecture supports range of interrupts, traps and

 The current state is saved by copying PC into register R14_Exc

 CPSR (Current Program Status Register) is saved into SPSR (Saved

 Processor operating mode is changed to appropriate exception mode

 PC is forced to a value between 00h to 1Ch depending on type of

ARM I/O (Input/output) system: ARM handles input-output peripherals

ARM instructions fall into one of following three categories.

1. Data processing instructions: These instructions are used to change

2. Data transfer instructions: Copy memory values into registers (load

3. Control flow instructions: Control flow instructions cause execution to

Data processing instructions: Multiply Instructions

Condition code Mnemonics:

Data transfer instructions (Load and Store)

[1] MOV R1,R2

Data Processing (Arithmetic and logical instructions):

[1] ADD R1,R2,R3

[3] Consider following sequence of instructions:

CMP R1,#0 ; Compare R1 with 0.

Sequence of instructions to change operating mode of ARM:

[a] MOV R0,R1,ASR #2

[f] BIC R0,R1,R2

Block diagram of the LPC2129 ARM Chip:

 Two 32-bit timers(with 4 capture and 4 compare channels), PWM unit(6

 It is 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

 Embedded ICE-RT interface enables breakpoints and watch points.

 Embedded Trace Macrocell enables non-intrusive high speed real-time

 Two interconnected CAN interfaces with advanced acceptance filters.

 60MHz maximum CPU clock available from programmable on-chip

 Vectored Interrupt Controller with configurable priorities and vector

 Two32 bit timers(with 4 capture and 4 compare channels), PWM unit (6

 Real Time Clock and Watchdog.

 Up to 46 general purpose I/O pins.

 Up to 9 edge or level sensitive external interrupt pins available.

 On-chip crystal oscillator with an operating range of 1MHz to 30MHz.

 Two low power modes, Idle and Power-down.

 Processor wake-up from Power-down mode via external interrupt.

To download and execute program to blink 8 LEDs connected with

/ * Program to blink LEDs /

/ * Program to blink LEDs /

/ * Program to blink LEDs /

0.0 V = _ 0.1V = _ 0.5V = ______

1 V = _ 2V= 3.3V = __