Differences Between VHDL-87 and VHDL-93

In this appendix we summarize the restrictions of VHDL-87 that we mentioned throughout the book. We take
the restrictive approach, rather than describing the way in which VHDL-93 is an extension of VHDL-87, since
VHDL-93 is now the "official" version of the language. We expect most new models to be written in VHDL-93.
Nevertheless, designers must deal with the legacy of models written before adoption of the new version of the
language and with VHDL tools that have yet to be updated to handle the new version.

Lexical Differences
• VHDL-87 uses the ASCII character set, rather than the full ISO character set. ASCII is a subset of the ISO
character set, consisting of just the first 128 characters. This includes all of the unaccented letters, but
excludes letters with diacritical marks.
• VHDL-87 only allows basic identifiers, not extended identifiers. The rules for forming basic identifiers are
the same as those for VHDL-93.
• The following identifiers are not used as reserved words in VHDL-87. They may be used as identifiers for
other purposes, although it is not advisable to do so, as this may cause difficulties in porting the models to
VHDL-93.

group postponed ror sra

impure pure shared srl
inertial reject sla unaffected
literal rol sil xnor

• Bit-string literals may only be used as literals for array types in which the elements are of type bit. The
predefined type bit vector is such a type. However, the standardlogic types std ulogic vector and std logic
vector are not.

Syntactic Differences
• The only sequential statements that may be labeled in VHDL-87 are loop statements. The remaining
sequential statements, which may not be labeled, are variable assignment, signal assignment, wait, if, case,
null, exit, next, assertion, procedure call and return statements.
• The keyword entity may not be repeated at the end of an entity declaration.
• The keyword architecture may not be repeated at the end of an architecture body.
• The keyword configuration may not be repeated at the end of a configuration declaration.
• The keyword package may not be repeated at the end of a package declaration.
• The keywords package body may not be repeated at the end of a package body.
• The keyword procedure may not be repeated at the end of a procedure declaration.
• The keyword function may not be repeated at the end of a function declaration. In a physical type definition,
the type name may not be repeated after the keywords end units.
• In a record type definition, the type name may not be repeated after the keywords end record.
• The keyword is may not be included in the header of a block statement.
• The keyword is may not be included in the header of a process statement.
• The keyword is may not be included in the header of a component declaration and the component name may
not be repeated at the end of the declaration
• A generate statement may not include a declarative part or the keyword begin.
• A component instantiation statement may not directly instantiate an entitv or a configuration. It may only
instantiate a declared component, but may not include the word component.
• A conditional signal assignment statement may not include the keyword else a condition after the last
waveform in the statement.
• The keyword unaffected may not be used in conditional and selected signal assignment statements.
• An alias declaration in VHDL-87 must include a subtype indication.
• The VHDL-87 syntax for file declarations is not a subset of the VHDL-93 syntax. The syntax rule in
VHDL-87 is:
file-declaration ⇐
file identifier : subtype indication is
[in | out] string expression ;

• An attribute specification may not name a character literal as an item rated, nor specify the entity class
literal, units, group or file. An attribute may not include a signature after an item name.

Semantic Differences
• In VHDL-87, the range specified in a slice may have the opposite direction the index range of the array. In
this case, the slice is a null slice.
• The VHDL-87 language definition does not disallow the keyword bus in the specification of a signal
parameter. However, it does not specify whether the kind of signal, guarded or unguarded, is determined by
the formal parameter specification or by the actual signal associated with the parameter. Implementations of
VHDL-87 make different interpretations. Some require the formal parameter specification to include the
keyword bus if the procedure includes a null signal assignment to the parameter. The actual signal
associated with the parameter in a procedure call must then be a guarded signal. Other
implementations follow the approach adopted in VHDL-93, prohibiting the keyword bus in the
parameter specification and determining the kind of the parameter from the kind of the actual signal.
• In VHDL-87, files are of the variable class of objects. Hence file parameters in subprograms are
specified as variable-class parameters. A subprogram that reads a file parameter should declare the
parameter to be of mode in. A subprogram that writes a file parameter should declare the parameter
to be of mode out.

Differences in the Standard Environment

• The types file open kind and file open status, the subtype delay-length and the attribute foreign are not
declared in std.standard.
• The function now returns a value of type time. Since VHDL-87 uses the ASCII character set, the type
character includes only the 128 ASCII characters.
• The predefined attributes 'ascending, 'image, 'value, 'driving, 'driving value, 'simple name, 'path_name and
'instance _name are not provided.
• The logical operator xnor and the shift operators sill, srl, sla, sra, roll and ror are not provided and so cannot
be declared as overloaded operators. Thus, the VHDL-87 version of the standard-logic package std
logic_1164 does not define the xnor operator for standard-logic types.
• In VHDL-87, the 'last _value attribute for a composite signal returns the aggregate of last values for each of
the scalar elements of the signal, as opposed to the last value of the entire composite signal.
• The VHDL-87 version of the textio package declares the function endline, which is not included in the
VHDL-93 version of the package.

VHDL-93 Facilities Not in VHDL-87

• VHDL-87 does not include report statements, labeled sequential statements (and hence decoration of
sequential statements with attributes), postponed processes, shared variables, group templates or groups,
aliases for non-data objects, declarative parts in generate statements or file open and close operations.
• VHDL-87 does not allow specification of a pulse rejection interval in the delay mechanism part of a signal
assignment. Transport delay can be specified using the keyword transport. If it is omitted, inertial delay is
assumed, with a pulse rejection interval equal to the inertial delay interval.
• VHDL-87 does not allow association of an expression with a port in a port map. VHDL-87 does not allow
type conversions in association lists.
• VHDL-87 does not allow direct instantiation of an entity or a configuration. Only declared components can
be instantiated. They must be bound to design entities using configuration specifications or using component
configurations in configuration declarations.
• VHDL-87 does not allow incremental binding. It is an error if a design includes both a configuration
specification and a component configuration for a given component instance.