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Preparation before the lab: Study CORDIC algorithm with MATLAB simulation
The Cordic VHDL code does not include the output signal for the final result of z. Add an
output signal z-n to the code. After changing the VHDL code, show the schematic and click
on Design » Synchronize Sheet Entries and Ports. If there is any unmatched sheet
If you have time, you can add other output signals to observe the intermediate stages of the
pipelined implementation with embedded instruments.
Part 3: Using a button input and a single pulse generator for hardware verification