Acer Swift 3 SF314-57 (Huaqin NB8511-12) Ver 1.0 Schematic

5 4 3 2 1
D D
HuaQin Confidential
NB8511/12_M/B Schematics Document
Intel ICL Lake U-Processor with LPDDR4
C C
REV1.0
2019-02-01
B B
A A
Leo.Liu & Payne.Zhang Huaqin Telecom Technology Com.,Ltd.

Author
Page name:
Cover page
Reviewer Nelosn.Hai & Nemo.Jiang Size: Project REV:
A4 Name: V1.0
NB8511
Approver Lobo_Fan Date: Sheet: of
Monday, July 15, 2019 1 72
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Huaqin Telecom Technology Com.,Ltd.
Page name:
Block Diagram
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 2 72
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5 4 3 2 1
D D
MEM ID
HW_ID3 HW_ID2 HW_ID1 HW_ID0 Description Total
0 0 0 0 SAMSUNG LPDDR4 3733 1GB K4F8E304HB-MGCJ LF+HF D20 4GB
0 0 0 1 HYNIX LPDDR4 3733 1GB H9HCNNN8KUMLHR-NME LF+HF DDP 4GB
0 0 1 0 MICRON LPDDR4 4266 2GB MT53E512M32D2NP-046 WT:E LF+HF Z11N 8GB
0 1 0 0 HYNIX LPDDR4 3733 2GB H9HCNNNBPUMLHR-NME LF+HF DE 8GB
0 1 0 0 16GB
1 0 0 0 HYNIX LPDDR4X 4266 4GB H9HCNNNCPMALHR-NEE LF+HF QDP
C 4x 16Gb(reserve)
C
GPU ID
Description
HW_ID5 HW_ID4
N17-LG-Refresh N17-LG
0 0 NC NC
1 0 Mount
1 1 Mount
B B
KB BL ID
HW_ID6 Description
0 No keyboard Backlignt
1 Keyboard Backlignt
Reserve ID
HW_ID7 Description
0 Reserve
A 1 Reserve
A
Page name:
I2C Table
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 3 72
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Page name:
Blank
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 4 72
5 4 3 2 1
5 4 3 2 1
CHA UU1B ???
M_A_DQ_0[0] CA48 BL48 M_A_CK_DDR0_DN

21 M_A_DQ_0[0] DDRA_DQ0_0/DDR0_DQ0_0 DDRA_CLK_N/DDR0_CLK_N_0 M_A_CK_DDR0_DN 21
M_A_DQ_0[1] CA47 BL47 M_A_CK_DDR0_DP
21 M_A_DQ_0[1] DDRA_DQ0_1/DDR0_DQ0_1 DDRA_CLK_P/DDR0_CLK_P_0 M_A_CK_DDR0_DP 21
M_A_DQ_0[2] CA49 BF42 M_A_CK_DDR1_DN
21 M_A_DQ_0[2] DDRA_DQ0_2/DDR0_DQ0_2 DDRB_CLK_N/DDR0_CLK_N_1 M_A_CK_DDR1_DN 22
M_A_DQ_0[3] BV49 BF43 M_A_CK_DDR1_DP
21 M_A_DQ_0[3] DDRA_DQ0_3/DDR0_DQ0_3 DDRB_CLK_P/DDR0_CLK_P_1 M_A_CK_DDR1_DP 22
BYTE0 M_A_DQ_0[4] CA45
21 M_A_DQ_0[4] DDRA_DQ0_4/DDR0_DQ0_4
M_A_DQ_0[5] BV47 BG49 M_A_LP4_CKE_A0
21 M_A_DQ_0[5] DDRA_DQ0_5/DDR0_DQ0_5 DDRA_CKE0/DDR0_CKE0 M_A_LP4_CKE_A0 21
D M_A_DQ_0[6] BV45 BJ47 M_A_LP4_CKE_A1 D
21 M_A_DQ_0[6] DDRA_DQ0_6/DDR0_DQ0_6 DDRA_CKE1/NC M_A_LP4_CKE_A1 21
M_A_DQ_0[7] BV48 BF38 M_A_LP4_CKE_B0
21 M_A_DQ_0[7] DDRA_DQ0_7/DDR0_DQ0_7 DDRB_CKE0/NC M_A_LP4_CKE_B0 22
M_A_DQ_1[0] CC42 BF41 M_A_LP4_CKE_B1
21 M_A_DQ_1[0] DDRA_DQ1_0/DDR0_DQ1_0 DDRB_CKE1/DDR0_CKE1 M_A_LP4_CKE_B1 22
M_A_DQ_1[1] CC39
M_A_DQ_1[2] CC43 BM38 M_A_LP4_CS_A_R0_N
21 M_A_DQ_1[2] DDRA_DQ1_2/DDR0_DQ1_2 DDRA_CS_0/DDR0_CS_N_0 M_A_LP4_CS_A_R0_N 21
M_A_DQ_1[3] CE38 BM42 M_A_LP4_CS_A_R1_N
21 M_A_DQ_1[3] DDRA_DQ1_3/DDR0_DQ1_3 DDRA_CS_1/NC M_A_LP4_CS_A_R1_N 21
BYTE1 M_A_DQ_1[4] CC38 BP42 M_A_LP4_CS_B_R0_N
21 M_A_DQ_1[4] DDRA_DQ1_4/DDR0_DQ1_4 DDRB_CS_0/NC M_A_LP4_CS_B_R0_N 22
M_A_DQ_1[5] CE39 BG42 M_A_LP4_CS_B_R1_N
21 M_A_DQ_1[5] DDRA_DQ1_5/DDR0_DQ1_5 DDRB_CS_1/DDR0_CS_N_1 M_A_LP4_CS_B_R1_N 22
M_A_DQ_1[6] CE42
M_A_DQ_1[7] CE43 BM43 M_A_LP4_CAB4
21 M_A_DQ_1[7] DDRA_DQ1_7/DDR0_DQ1_7 DDRB_CA4/DDR0_BA0 M_A_LP4_CAB4 22
M_A_DQ_2[0] BT48 BG39
21 M_A_DQ_2[0] DDRA_DQ2_0/DDR0_DQ2_0 NC/DDR0_BA1
M_A_DQ_2[1] BT47
M_A_DQ_2[2] BT49 BB49 M_A_LP4_CAA5 M_A_LP4_CAA5 21
21 M_A_DQ_2[2] DDRA_DQ2_2/DDR0_DQ2_2 DDRA_CA5/DDR0_BG0
M_A_DQ_2[3] BN49 BD47
21 M_A_DQ_2[3] DDRA_DQ2_3/DDR0_DQ2_3 NC/DDR0_BG1
BYTE2 M_A_DQ_2[4] BT45
M_A_DQ_2[5] BN47 BB48
21 M_A_DQ_2[5] DDRA_DQ2_5/DDR0_DQ2_5 NC/DDR0_MA0
M_A_DQ_2[6] BN45 BL49
M_A_DQ_2[7] BN48 BG38 M_A_LP4_CAB5
21 M_A_DQ_2[7] DDRA_DQ2_7/DDR0_DQ2_7 DDRB_CA5/DDR0_MA2 M_A_LP4_CAB5 22
M_A_DQ_3[0] BV42 BL45
M_A_DQ_3[1] BV39 BJ46
M_A_DQ_3[2] BV43 BG48 M_A_LP4_CAA0 M_A_LP4_CAA0 21
21 M_A_DQ_3[2] DDRA_DQ3_2/DDR0_DQ3_2 DDRA_CA0/DDR0_MA5
M_A_DQ_3[3] BW38 BE45 M_A_LP4_CAA2 M_A_LP4_CAA2 21
BYTE3 M_A_DQ_3[4] BV38 BG45 M_A_LP4_CAA4 M_A_LP4_CAA4 21
M_A_DQ_3[5] BW39 BG47 M_A_LP4_CAA3 M_A_LP4_CAA3 21
M_A_DQ_3[6] BW42 BE47 M_A_LP4_CAA1 M_A_LP4_CAA1 21
C 21 M_A_DQ_3[6] DDRA_DQ3_6/DDR0_DQ3_6 DDRA_CA1/DDR0_MA9 C
M_A_DQ_3[7] BW43 BJ38
M_A_DQ_4[0] AY48 BB47
22 M_A_DQ_4[0] DDRB_DQ0_0/DDR0_DQ4_0 NC/DDR0_MA11
M_A_DQ_4[1] AY47 BE48
22 M_A_DQ_4[1] DDRB_DQ0_1/DDR0_DQ4_1 NC/DDR0_MA12
M_A_DQ_4[2] AY49 BM39 M_A_LP4_CAB0 M_A_LP4_CAB0 22
22 M_A_DQ_4[2] DDRB_DQ0_2/DDR0_DQ4_2 DDRB_CA0/DDR0_MA13
M_A_DQ_4[3] AU45 BG43 M_A_LP4_CAB2
22 M_A_DQ_4[3] DDRB_DQ0_3/DDR0_DQ4_3 DDRB_CA2/DDR0_MA14WE_N M_A_LP4_CAB2 22
BYTE4 M_A_DQ_4[4] AY45 BJ42 M_A_LP4_CAB1
22 M_A_DQ_4[4] DDRB_DQ0_4/DDR0_DQ4_4 DDRB_CA1/DDR0_MA15CAS_N M_A_LP4_CAB1 22
M_A_DQ_4[5] AU47 BM41 M_A_LP4_CAB3
22 M_A_DQ_4[5] DDRB_DQ0_5/DDR0_DQ4_5 DDRB_CA3/DDR0_MA16RAS_N M_A_LP4_CAB3 22
M_A_DQ_4[6] AU48
22 M_A_DQ_4[6] DDRB_DQ0_6/DDR0_DQ4_6
M_A_DQ_4[7] AU49 BJ39
22 M_A_DQ_4[7] DDRB_DQ0_7/DDR0_DQ4_7 NC/DDR0_ODT_0
M_A_DQ_5[0] AY42 BB45
22 M_A_DQ_5[0] DDRB_DQ1_0/DDR0_DQ5_0 NC/DDR0_ODT_1
M_A_DQ_5[1] AY38
M_A_DQ_5[2] AY43 BY47 M_A_DQS_0_DN
22 M_A_DQ_5[2] DDRB_DQ1_2/DDR0_DQ5_2 DDRA_DQSN_0/DDR0_DQSN_0 M_A_DQS_0_DN 21
M_A_DQ_5[3] BB39 BY46 M_A_DQS_0_DP
22 M_A_DQ_5[3] DDRB_DQ1_3/DDR0_DQ5_3 DDRA_DQSP_0/DDR0_DQSP_0 M_A_DQS_0_DP 21
BYTE5 M_A_DQ_5[4] AY39 CC41 M_A_DQS_1_DN
M_A_DQ_5[5] BB38 CE41 M_A_DQS_1_DP
M_A_DQ_5[6] BB42 BR47 M_A_DQS_2_DN
M_A_DQ_5[7] BB43 BR46 M_A_DQS_2_DP
M_A_DQ_6[0] AR48 BV41 M_A_DQS_3_DN
M_A_DQ_6[1] AR47 BW41 M_A_DQS_3_DP
M_A_DQ_6[2] AR49 AV46 M_A_DQS_4_DN
22 M_A_DQ_6[2] DDRB_DQ2_2/DDR0_DQ6_2 DDRB_DQSN_0/DDR0_DQSN_4 M_A_DQS_4_DN 22
M_A_DQ_6[3] AM45 AV47 M_A_DQS_4_DP
22 M_A_DQ_6[3] DDRB_DQ2_3/DDR0_DQ6_3 DDRB_DQSP_0/DDR0_DQSP_4 M_A_DQS_4_DP 22
BYTE6 M_A_DQ_6[4] AR45 AY41 M_A_DQS_5_DN
M_A_DQ_6[5] AM47 BB41 M_A_DQS_5_DP
M_A_DQ_6[6] AM48 AN46 M_A_DQS_6_DN
B M_A_DQ_6[7] AM49 AN47 M_A_DQS_6_DP B
M_A_DQ_7[0] AT42 AR41 M_A_DQS_7_DN
M_A_DQ_7[1] AT39 AT41 M_A_DQS_7_DP +VDDQ_CPU
M_A_DQ_7[2] AR43
M_A_DQ_7[3] AT38 BF39
22 M_A_DQ_7[3] DDRB_DQ3_3/DDR0_DQ7_3 NC/DDR0_PAR
BYTE7 M_A_DQ_7[4] AR38 BE49
22 M_A_DQ_7[4] DDRB_DQ3_4/DDR0_DQ7_4 NC/DDR0_ACT_N
M_A_DQ_7[5] AR39 BD46
22 M_A_DQ_7[5] DDRB_DQ3_5/DDR0_DQ7_5 NC/DDR0_ALERT_N
M_A_DQ_7[6] AR42 RD1
M_A_DQ_7[7] AT43 M38 TP_+V_D4CH1_CA_VREF 1
22 M_A_DQ_7[7] DDRB_DQ3_7/DDR0_DQ7_7 RSVD_73 ns TPU1 20MIL 电阻_470R_0201_1/20W_J
C44 TP_+V_D4CH0_CA_VREF 1
DDR0_VREF_CA ns TPU2 20MIL
DDR_RCOMP_0 D47 B45 TP_+V_LPCH0_DQ_VREF 1
DDR_RCOMP_0 DDR1_VREF_CA ns TPU3 20MIL
DDR_RCOMP_1 E46 M39 TP_DDR_VTT_CTRL 1
DDR_RCOMP_1 DDR_VTT_CTL ns TPU4 20MIL
DDR_RCOMP_2 C47 DK47 DRAM_RESET_N RD2 DRAM_RESET_N_R
DDR_RCOMP_2 2 of 19 DRAM_RESET_N 电阻_0R_0201_1/20W_J DRAM_RESET_N_R 21,22,23,24
ICL_U_IP_EXT_WW20 ?
电阻_100R_0201_1/20W_F
电阻_100R_0201_1/20W_F
电阻_100R_0201_1/20W_F
CD1
RU1 RU2 RU3 ns
电容_100nF_0201_X5R_6.3 V_M(±20%)
PLACE RESET COMPONENTS CLOSE TO CPU

A A
Page name:
ICL-U42(CHA)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 5 72
5 4 3 2 1
5 4 3 2 1
CHB
UU1C ???
D M_B_DQ_0[0] AK48 Y48 M_B_CK_DDR0_DN D

23 M_B_DQ_0[0] DDRC_DQ0_0/DDR1_DQ0_0 DDRC_CLK_N/DDR1_CLK_N_0 M_B_CK_DDR0_DN 23
M_B_DQ_0[1] AK45 Y47 M_B_CK_DDR0_DP
23 M_B_DQ_0[1] DDRC_DQ0_1/DDR1_DQ0_1 DDRC_CLK_P/DDR1_CLK_P_0 M_B_CK_DDR0_DP 23
M_B_DQ_0[2] AK49 M43 M_B_CK_DDR1_DN
23 M_B_DQ_0[2] DDRC_DQ0_2/DDR1_DQ0_2 DDRD_CLK_N/DDR1_CLK_N_1 M_B_CK_DDR1_DN 24
M_B_DQ_0[3] AG47 M42 M_B_CK_DDR1_DP
23 M_B_DQ_0[3] DDRC_DQ0_3/DDR1_DQ0_3 DDRD_CLK_P/DDR1_CLK_P_1 M_B_CK_DDR1_DP 24
BYTE0 M_B_DQ_0[4] AK47
23 M_B_DQ_0[4] DDRC_DQ0_4/DDR1_DQ0_4
M_B_DQ_0[5] AG45 U45 M_B_LP4_CKE_A0
23 M_B_DQ_0[5] DDRC_DQ0_5/DDR1_DQ0_5 DDRC_CKE0/DDR1_CKE0 M_B_LP4_CKE_A0 23
M_B_DQ_0[6] AG48 V46 M_B_LP4_CKE_A1
23 M_B_DQ_0[6] DDRC_DQ0_6/DDR1_DQ0_6 DDRC_CKE1/NC M_B_LP4_CKE_A1 23
M_B_DQ_0[7] AG49 M41 M_B_LP4_CKE_B0
23 M_B_DQ_0[7] DDRC_DQ0_7/DDR1_DQ0_7 DDRD_CKE0/NC M_B_LP4_CKE_B0 24
M_B_DQ_1[0] AJ38 P43 M_B_LP4_CKE_B1
23 M_B_DQ_1[0] DDRC_DQ1_0/DDR1_DQ1_0 DDRD_CKE1/DDR1_CKE1 M_B_LP4_CKE_B1 24
M_B_DQ_1[1] AL39
M_B_DQ_1[2] AJ39 V42 M_B_LP4_CS_A_R0_N
23 M_B_DQ_1[2] DDRC_DQ1_2/DDR1_DQ1_2 DDRC_CS_0/DDR1_CS_N_0 M_B_LP4_CS_A_R0_N 23
M_B_DQ_1[3] AL43 V39 M_B_LP4_CS_A_R1_N
23 M_B_DQ_1[3] DDRC_DQ1_3/DDR1_DQ1_3 DDRC_CS_1/NC M_B_LP4_CS_A_R1_N 23
BYTE1 M_B_DQ_1[4] AL38 Y39 M_B_LP4_CS_B_R0_N M_B_LP4_CS_B_R0_N 24
23 M_B_DQ_1[4] DDRC_DQ1_4/DDR1_DQ1_4 DDRD_CS_0/NC
M_B_DQ_1[5] AJ42 T39 M_B_LP4_CS_B_R1_N M_B_LP4_CS_B_R1_N 24
23 M_B_DQ_1[5] DDRC_DQ1_5/DDR1_DQ1_5 DDRD_CS_1/DDR1_CS_N_1
M_B_DQ_1[6] AL42
M_B_DQ_1[7] AJ43 T38 M_B_LP4_CAB4
23 M_B_DQ_1[7] DDRC_DQ1_7/DDR1_DQ1_7 DDRD_CA4/DDR1_BA0 M_B_LP4_CAB4 24
M_B_DQ_2[0] AB49 T42
23 M_B_DQ_2[0] DDRC_DQ2_0/DDR1_DQ2_0 NC/DDR1_BA1
M_B_DQ_2[1] AB48
M_B_DQ_2[2] AE49 R45 M_B_LP4_CAA5 M_B_LP4_CAA5 23
23 M_B_DQ_2[2] DDRC_DQ2_2/DDR1_DQ2_2 DDRC_CA5/DDR1_BG0
M_B_DQ_2[3] AE47 N47
23 M_B_DQ_2[3] DDRC_DQ2_3/DDR1_DQ2_3 NC/DDR1_BG1
BYTE2 M_B_DQ_2[4] AE48
M_B_DQ_2[5] AB47 P42
23 M_B_DQ_2[5] DDRC_DQ2_5/DDR1_DQ2_5 NC/DDR1_MA0
M_B_DQ_2[6] AB45 Y49
M_B_DQ_2[7] AE45 U48 M_B_LP4_CAB5 M_B_LP4_CAB5 24
23 M_B_DQ_2[7] DDRC_DQ2_7/DDR1_DQ2_7 DDRD_CA5/DDR1_MA2
C M_B_DQ_3[0] AD38 Y45 C
M_B_DQ_3[1] AD39 U47
M_B_DQ_3[2] AE39 R49 M_B_LP4_CAA0 M_B_LP4_CAA0 23
23 M_B_DQ_3[2] DDRC_DQ3_2/DDR1_DQ3_2 DDRC_CA0/DDR1_MA5
M_B_DQ_3[3] AE43 U49 M_B_LP4_CAA2 M_B_LP4_CAA2 23
BYTE3 M_B_DQ_3[4] AE38 M47 M_B_LP4_CAA4 M_B_LP4_CAA4 23
M_B_DQ_3[5] AD43 M45 M_B_LP4_CAA3 M_B_LP4_CAA3 23
M_B_DQ_3[6] AD42 R47 M_B_LP4_CAA1 M_B_LP4_CAA1 23
M_B_DQ_3[7] AE42 P39
M_B_DQ_4[0] J48 N46
24 M_B_DQ_4[0] DDRD_DQ0_0/DDR1_DQ4_0 NC/DDR1_MA11
M_B_DQ_4[1] J45 R48
24 M_B_DQ_4[1] DDRD_DQ0_1/DDR1_DQ4_1 NC/DDR1_MA12
M_B_DQ_4[2] J49 Y41 M_B_LP4_CAB0 M_B_LP4_CAB0 24
24 M_B_DQ_4[2] DDRD_DQ0_2/DDR1_DQ4_2 DDRD_CA0/DDR1_MA13
M_B_DQ_4[3] G47 V41 M_B_LP4_CAB2
24 M_B_DQ_4[3] DDRD_DQ0_3/DDR1_DQ4_3 DDRD_CA2/DDR1_MA14WE_N M_B_LP4_CAB2 24
BYTE4 M_B_DQ_4[4] J47 Y42 M_B_LP4_CAB1
24 M_B_DQ_4[4] DDRD_DQ0_4/DDR1_DQ4_4 DDRD_CA1/DDR1_MA15CAS_N M_B_LP4_CAB1 24
M_B_DQ_4[5] G45 V47 M_B_LP4_CAB3
24 M_B_DQ_4[5] DDRD_DQ0_5/DDR1_DQ4_5 DDRD_CA3/DDR1_MA16RAS_N M_B_LP4_CAB3 24
M_B_DQ_4[6] G48
24 M_B_DQ_4[6] DDRD_DQ0_6/DDR1_DQ4_6
M_B_DQ_4[7] E48 V43
24 M_B_DQ_4[7] DDRD_DQ0_7/DDR1_DQ4_7 NC/DDR1_ODT_0
M_B_DQ_5[0] J38 V38
24 M_B_DQ_5[0] DDRD_DQ1_0/DDR1_DQ5_0 NC/DDR1_ODT_1
M_B_DQ_5[1] G39
M_B_DQ_5[2] G38 AH46 M_B_DQS_0_DN
24 M_B_DQ_5[2] DDRD_DQ1_2/DDR1_DQ5_2 DDRC_DQSN_0/DDR1_DQSN_0 M_B_DQS_0_DN 23
M_B_DQ_5[3] G42 AH47 M_B_DQS_0_DP
24 M_B_DQ_5[3] DDRD_DQ1_3/DDR1_DQ5_3 DDRC_DQSP_0/DDR1_DQSP_0 M_B_DQS_0_DP 23
BYTE5 M_B_DQ_5[4] J39 AJ41 M_B_DQS_1_DN
M_B_DQ_5[5] J42 AL41 M_B_DQS_1_DP
M_B_DQ_5[6] G43 AC47 M_B_DQS_2_DN
M_B_DQ_5[7] J43 AC46 M_B_DQS_2_DP
B 24 M_B_DQ_5[7] DDRD_DQ1_7/DDR1_DQ5_7 DDRC_DQSP_2/DDR1_DQSP_2 M_B_DQS_2_DP 23 B
M_B_DQ_6[0] B43 AE41 M_B_DQS_3_DN
M_B_DQ_6[1] D43 AD41 M_B_DQS_3_DP
M_B_DQ_6[2] A43 H47 M_B_DQS_4_DN
24 M_B_DQ_6[2] DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQSN_0/DDR1_DQSN_4 M_B_DQS_4_DN 24
M_B_DQ_6[3] C40 H46 M_B_DQS_4_DP
24 M_B_DQ_6[3] DDRD_DQ2_3/DDR1_DQ6_3 DDRD_DQSP_0/DDR1_DQSP_4 M_B_DQS_4_DP 24
BYTE6 M_B_DQ_6[4] C43 G41 M_B_DQS_5_DN
M_B_DQ_6[5] D40 J41 M_B_DQS_5_DP
M_B_DQ_6[6] B40 C42 M_B_DQS_6_DN
M_B_DQ_6[7] A40 D42 M_B_DQS_6_DP
M_B_DQ_7[0] B35 D36 M_B_DQS_7_DN
M_B_DQ_7[1] D35 C36 M_B_DQS_7_DP
M_B_DQ_7[2] A35
M_B_DQ_7[3] D38 P38
24 M_B_DQ_7[3] DDRD_DQ3_3/DDR1_DQ7_3 NC/DDR1_PAR
BYTE7 M_B_DQ_7[4] C35 M48
24 M_B_DQ_7[4] DDRD_DQ3_4/DDR1_DQ7_4 NC/DDR1_ACT_N
M_B_DQ_7[5] C38 M49
24 M_B_DQ_7[5] DDRD_DQ3_5/DDR1_DQ7_5 NC/DDR1_ALERT_N
M_B_DQ_7[6] B38
M_B_DQ_7[7] A38
ICL_U_IP_EXT_WW20 3 of 19 ?
A A
Page name:
ICL-U42(CHB)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 6 72
5 4 3 2 1
5 4 3 2 1
UU1A ???
EDP_TX0_SOC_DN Y5 BB5 TCP0_TX0_DN

39 EDP_TX0_SOC_DN DDIA_TXN_0 TCP0_TX_N0 TCP0_TX0_DN 45
EDP_TX0_SOC_DP Y3 BB6 TCP0_TX0_DP
39 EDP_TX0_SOC_DP DDIA_TXP_0 TCP0_TX_P0 TCP0_TX0_DP 45
EDP_TX1_SOC_DN Y1 AV6 TCP0_TX1_DN
39 EDP_TX1_SOC_DN DDIA_TXN_1 TCP0_TX_N1 TCP0_TX1_DN 45
D EDP_TX1_SOC_DP Y2 AV5 TCP0_TX1_DP D
eDP 39 EDP_TX1_SOC_DP DDIA_TXP_1 TCP0_TX_P1 TCP0_TX1_DP 45
EDP_TX2_SOC_DN V2 BH2 TCP0_TXRX0_DN
39 EDP_TX2_SOC_DN DDIA_TXN_2 TCP0_TXRX_N0 TCP0_TXRX0_DN 45
EDP_TX2_SOC_DP V1 BH1 TCP0_TXRX0_DP
39 EDP_TX2_SOC_DP DDIA_TXP_2 TCP0_TXRX_P0 TCP0_TXRX0_DP 45
EDP_TX3_SOC_DN V3 BF1 TCP0_TXRX1_DN
39 EDP_TX3_SOC_DN DDIA_TXN_3 TCP0_TXRX_N1 TCP0_TXRX1_DN 45
EDP_TX3_SOC_DP V5 BF2 TCP0_TXRX1_DP
39 EDP_TX3_SOC_DP DDIA_TXP_3 TCP0_TXRX_P1 TCP0_TXRX1_DP 45
EDP_AUX_SOC_DN W4 AY5 TCP0_AUX_DN
39 EDP_AUX_SOC_DN EDP_AUX_SOC_DP W3 DDIA_AUX_N TCP0_AUX_N AY6 TCP0_AUX_DP TCP0_AUX_DN 45
39 EDP_AUX_SOC_DP DDIA_AUX_P TCP0_AUX_P TCP0_AUX_DP 45
DDI1_TX0_DN AE3
40 DDI1_TX0_DN DDI1_TX0_DP AE5 DDIB_TXN_0 AR5
40 DDI1_TX0_DP DDI1_TX1_DN AE2 DDIB_TXP_0 TCP1_TX_N0 AR6
+V3P3A_PCH 40 DDI1_TX1_DN DDI1_TX1_DP AE1 DDIB_TXN_1 TCP1_TX_P0 AL5
HDMI 40 DDI1_TX1_DP DDI1_TX2_DN AC5 DDIB_TXP_1 TCP1_TX_N1 AL3
40 DDI1_TX2_DN DDI1_TX2_DP AC3 DDIB_TXN_2 TCP1_TX_P1 BD2
40 DDI1_TX2_DP DDI1_TX3_DN AC1 DDIB_TXP_2 TCP1_TXRX_N0 BD1
40 DDI1_TX3_DN DDI1_TX3_DP AC2 DDIB_TXN_3 TCP1_TXRX_P0 BB1
RU4 40 DDI1_TX3_DP DDIB_TXP_3 TCP1_TXRX_N1 BB2
AD3 TCP1_TXRX_P1
电阻_2.2K_0201_1/20 W_J(±5%) DDIB_AUX_N
AD4 AN3
DDIB_AUX_P TCP1_AUX_N AN5
BT_RF_KILL_N DP15 TCP1_AUX_P
43 BT_RF_KILL_N DJ17 GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN
GPP_E23/DDPA_CTRLDATA/BK4/SBK4 BF6
DDI1_DDC_SCL DL40 TCP2_TX_N0 BF5
40 DDI1_DDC_SCL GPP_H16/DDPB_CTRLCLK TCP2_TX_P0
40 DDI1_DDC_SDA DDI1_DDC_SDA DP42 BJ5
GPP_H17/DDPB_CTRLDATA TCP2_TX_N1 BJ6
TBT_LSX0_TXD DL17 TCP2_TX_P1 BL1
45 TBT_LSX0_TXD TBT_LSX0_RXD DK17 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP2_TXRX_N0 BL2
45 TBT_LSX0_RXD GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP2_TXRX_P0 BM2
DN17 TCP2_TXRX_N1 BM1
GPP_E21 DP17 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1
C GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD BG6 C
DK34 TCP2_AUX_N BG5
GPP_D10 DL34 GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD TCP2_AUX_P
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
DN33 BP6
GPP_D12 DL33 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TCP3_TX_N0 BP5
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD TCP3_TX_P0 BV5
EDP_HPD DW11 TCP3_TX_N1 BV6
39 EDP_HPD GPP_E14/DPPE_HPDA/DISP_MISCA TCP3_TX_P1
40 DDI1_HPD DDI1_HPD CV42 BR1
HPD_P1 CV39 GPP_A18/DDSP_HPDB/DISP_MISCB TCP3_TXRX_N0 BR2
44 HPD_P1 GPP_A19/DDSP_HPD1/DISP_MISC1 TCP3_TXRX_P0
1 CY43 BT2
20MIL TPU6 ns USB_OC1_N GPP_A20/DDSP_HPD2/DISP_MISC2 TCP3_TXRX_N1
CR41 BT1
1 USB_OC2 CT41 GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 TCP3_TXRX_P1
20MIL TPU7 ns GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4
DV14 BT6
GPP_E17 TCP3_AUX_N BT5
EDP_VDD_EN DN21 TCP3_AUX_P
39 EDP_VDD_EN EDP_VDDEN RU5
EDP_BKLT_EN DL19 AY1 TCRCOMP_DN 电阻_150R_0201_1/20W_F
38,39 EDP_BKLT_EN EDP_BKLT_PWM DU19 EDP_BKLTEN TC_RCOMP_N AY2 TCRCOMP_DP
39 EDP_BKLT_PWM J3 EDP_BKLTCTL TC_RCOMP_P
RSVD_1 CT38
RU6 D2 GPP_A17/DISP_MISCC CV43
DISP_RCOMP R2 DISP_UTILS GPP_A21 CV41
DISP_RCOMP GPP_A22
电阻_150R_0201_1/20W_F 1 0f 19
ICL_U_IP_EXT_WW20 ?
+V3P3A_PCH +V3P3A_PCH
B B
电阻_10K_0201_1/20W_J
电阻_10K_0201_1/20W_J
RU7
RU143
USB_OC1_N USB_OC2
PCH STRAP---VCCIO CONFIGURATION HPD_P1
电阻_100K_0201_1/20W_J
+V3P3A_PCH +V3P3A_PCH +V3P3A_PCH +V3P3A_PCH
电阻_4.7K_0201_1/20W_J
电阻_4.7K_0201_1/20W_J
电阻_4.7K_0201_1/20W_J
电阻_4.7K_0201_1/20W_J
RU12
RU8 RU9 RU10 RU11 ns

ns ns ns ns
TBT_LSX0_RXD GPP_E21 GPP_D12 GPP_D10

电阻_20K_0201_1/20W_J
电阻_20K_0201_1/20W_J
电阻_20K_0201_1/20W_J
电阻_20K_0201_1/20W_J
A A
RU13 RU14 RU15 RU16
TBT_LSX0_RXD GPP_E21 Page name:

0: DDP1 I2C / TBT LSx #0 / BSSB_LS #0 pins at 1.8V 0 = DDP1 I2C / TBT LSx #0 / BSSB_LS #0 pins at 1.8V GPP_D12 GPP_D10 ICL-U42(DISPLAY)
1: DDP1 I2C / TBT LSx #0 / BSSB_LS #0 pins at 3.3V 1 = DDP1 I2C / TBT LSx #0 / BSSB_LS #0 pins at 3.3V 0: DDP4 I2C/TBT LSX #3/BSSB_LS #3 pins at 1.8V 0: DDP3 I2C/TBT LSX #2/BSSB_LS #2 pins at 1.8V Size: Project REV:
A4 Name: V1.0
Internal 20K PD NB8511
Date: Sheet: of
Monday, July 15, 2019 7 72
5 4 3 2 1
5 4 3 2 1
MIPI60_CPU_JTAG_TCLK 1
MIPI60_CPU_JTAG_TDI TP1 20MIL
1
TP2 20MIL
MIPI60_CPU_JTAG_TDO 1 ns
TP3 20MIL
MIPI60_CPU_JTAG_TMS 1 ns
MIPI60_CPU_JTAG_TRST_N TP4 20MIL
1 ns
TP5 20MIL
ns
MIPI60_PCH_JTAG_TRST_N 1 ns
+VCCSTG_TERM
MIPI60_PCH_JTAG_TCLK
MIPI60_PCH_JTAG_TDI
1
1
TP6
TP7
20MIL
20MIL
MIPI_60
+VCCSTG_TERM ns
MIPI60_PCH_JTAG_TDO TP8 20MIL
1 ns TP9 20MIL
PLACE NEAR THE FAR DEVICE MIPI60_PCH_JTAG_TMS 1 ns
MIPI60_PCH_JTAGX TP10 20MIL
1 ns TP11 20MIL
RU17 ns
RU18 MIPI60_PRDY_N 1 ns
TP12 20MIL
电阻_1K_0201_1/20W_J ns 电阻_10K_0201_1/20W_J MIPI60_PREQ_N 1
TP13 20MIL
ns
D ns D
RU19
+V1P0S_VCCST MIPI60_CPU_JTAG_TCLK RU20 电阻_0R_0201_1/20W_J MIPI60_PCH_JTAGX
CPU_PROCHOT_N
CPU_PROCHOT_N 14,38,66
电阻_499Ω_0201_1/20W_F
RU22 电阻_51R_0201_1/20W_J +VCCSTG_TERM
+V1P0S_VCCST
UU1D ???
RU21 RU23
电阻_1K_0201_1/20W_J RU24 电阻_49.9R_0201_1/20W_F CATERR_SOC_N J4 P3 MIPI60_CPU_JTAG_TCLK 电阻_51R_0201_1/20W_J
ns PECI_SOC CD5 CATERR_N PROC_TCK K5 MIPI60_CPU_JTAG_TDI
38 PECI_SOC PECI PROC_TDI MIPI60_CPU_JTAG_TDI RU25 电阻_0R_0201_1/20W_J MIPI60_PCH_JTAG_TDI
PROCHOT_SOC_N C3 K3 MIPI60_CPU_JTAG_TDO
THERMTRIP_SOC_N E3 PROCHOT_N PROC_TDO P4 MIPI60_CPU_JTAG_TMS +VCCSTG_TERM
THRMTRIP_N PROC_TMS N1 MIPI60_CPU_JTAG_TRST_N RU27
PROC_TRST_N
RU26 电阻_49.9R_0201_1/20W_F CPU_POPI_RCOMP CJ41
PROC_POPIRCOMP change RU27 to 51Ω - 02/26
RU28 电阻_49.9R_0201_1/20W_F PCH_POPI_RCOMP DU3 N5 MIPI60_PCH_JTAG_TRST_N
PCH_OPIRCOMP PCH_TRST_N MIPI60_PCH_JTAG_TCLK 电阻_51R_0201_1/20W_J
A14 R5
RSVD_25 PCH_TCK MIPI60_PCH_JTAG_TDI MIPI60_CPU_JTAG_TDO MIPI60_PCH_JTAG_TDO
B14 K1 RU29 电阻_0R_0201_1/20W_J
RSVD_26 PCH_TDI K2 MIPI60_PCH_JTAG_TDO
PCH_TDO +VCCSTG_TERM
DBG_PMODE DL15 N3 MIPI60_PCH_JTAG_TMS
DBG_PMODE PCH_TMS RU30
N2 MIPI60_PCH_JTAGX
1 GPP_E3 DV11 PCH_JTAGX +V1P0S_VCCST
20MIL TP185 GPP_E3/CPU_GP0
1 GPP_E7 DT11 P6 MIPI60_PRDY_N 电阻_51R_0201_1/20W_J
+VCC1P05_OUT_FET 20MIL TP186 GPP_E7/CPU_GP1 PROC_PRDY_N
ns SOC_SCI_N CR38 M6 MIPI60_PREQ_N 电阻_0R_0201_1/20W_J
38 SOC_SCI_N GPP_B3/CPU_GP2 PROC_PREQ_N MIPI60_CPU_JTAG_TMS RU31 MIPI60_PCH_JTAG_TMS
+V3P3SX ns RETIMER_FORCE_PWR CR39
44,45 RETIMER_FORCE_PWR GPP_B4/CPU_GP3
3
电阻_1K_0201_1/20W_J
EC_SLP_S0_CS_N DT12
38,40 EC_SLP_S0_CS_N GPP_E6 D
WAKE_PCIE_N_SOC_H2 DJ38
GPP_H2/CNV_BT_I2S_SDO MIPI60_CPU_JTAG_TRST_N RU33 电阻_0R_0201_1/20W_J MIPI60_PCH_JTAG_TRST_N
UART_BT_WAKE_N_SOC DL38 G
43 UART_BT_WAKE_N_SOC GPP_H19/TIME_SYNC0 1 QU7
38,66 EC_IMVP_PWRGD
RU222 RU32
ICL_U_IP_EXT_WW20 ? RU34
ns 电阻_10K_0201_1/20W_J 4 of 19 S WNM2046-3/TR ns
2
5P0VA_EN 电阻_51R_0201_1/20W_J
38,62 5P0VA_EN
SOC_SCI_N 3P3VA_EN
DBG_PMODE 1 29,38,57,61 3P3VA_EN
TP177 20MIL RSMRST_N_EC RU224
12,38,57 RSMRST_N_EC
ns 电阻_1K_0201_1/20W_J
QU6 QU4 QU5
3
C 1 1 1 C
ns ns +V3P3A_PCH
电阻_100K_0201_1/20W_J
CU168
RU229 LMBT3904LT1G LMBT3904LT1G LMBT3904LT1G
电容_100nF_0201_X5R_6.3 V_M(±20%)
WAKE_PCIE_N_SOC WAKE_PCIE_N_SOC_H2
电阻_2.2K_0201_1/20 W_J(±5%)
电阻_2.2K_0201_1/20 W_J(±5%)
10,43 WAKE_PCIE_N_SOC ns RU232 ns
电阻_0R_0201_1/20W_J
RU35 RU36 +V3P3SX
THERMTRIP_SOC_N
UU1E ???
5
FLASH_SPI_CLK DB42
G
36,37 FLASH_SPI_CLK FLASH_SPI_MOSI DD43 SPI0_CLK DK27 PCH_SMB1_CLK 3 4
36,37 FLASH_SPI_MOSI SPI0_MOSI GPP_C0/SMBCLK ns SMB_EC_SCLK 29,38,56
SMBUS
FLASH_SPI_MISO DF43 DP24 PCH_SMB1_DATA
S
36,37 FLASH_SPI_MISO SPI0_MISO GPP_C1/SMBDATA
SPI 0
FLASH_SPI_IO2 DF42 DL24 GPPC_C2_SMBALERT_N
37 FLASH_SPI_IO2 SPI0_IO2 GPP_C2/SMBALERT_N
FLASH_SPI_IO3 DD41
2
37 FLASH_SPI_IO3 SPI0_IO3 QU1A
FLASH_SPI_CS0_N DB43
G
37 FLASH_SPI_CS0_N DF41 SPI0_CS0_N DK24 SMBUS_CLK0 LBSS139DW1T1G
SPI0_CS1_N GPP_C3/SML0CLK SMBUS_CLK0 45 6 1
FLASH_SPI_CS2_N DB41 DJ24 SMBUS_DAT0 ns SMB_EC_SDATA 29,38,56
SML 0
SMBUS_DAT0 45
S
36 FLASH_SPI_CS2_N SPI0_CS2_N GPP_C4/SML0DATA DP22 GPPC_C5_SML0ALERT_N
GPP_C5/SML0ALERT_N
1 SPI1_CLK DV16 QU1B
20MIL TP183 GPP_E11/SPI1_CLK/BK1/SBK1
1 GPP_E13 DT16 DN22 TYPEC_PD_SOC_CLK LBSS139DW1T1G
SML1
20MIL TP182 GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK TYPEC_PD_SOC_CLK 44

SPI 1
ns 1 GPP_E12 DU18 DL22 TYPEC_PD_SOC_DAT

20MIL TP181 GPP_E12/SPI1_MISO/BK2/SBK2 GPP_C7/SML1DATA/SUSACK_N TYPEC_PD_SOC_DAT 44
ns 1 GPP_E1 DT18
20MIL TP179 GPP_E1/SPI1_IO2
ns 1 GPP_E2 DW18
20MIL TP178 GPP_E2/SPI1_IO3
ns 1 SPI1_CS0_N DW16 CR47 ESPI_CLK RU37 电阻_49.9R_0201_1/20W_F ESPI_CLK_EC
20MIL TP184 GPP_E10/SPI1_CS_N/BK0/SBK0 GPP_A5/ESPI_CLK ESPI_CLK_EC 38
ns 1 GPP_E8 DU16 CN45 ESPI_IO0 RU38 电阻_10R_0201_1/20W_J ESPI_IO0_EC
20MIL TP180 GPP_E8/SATALED_N/SPI1_CS1_N GPP_A0/ESPI_IO0 ESPI_IO0_EC 38
ns CN48 ESPI_IO1 RU39 电阻_10R_0201_1/20W_J ESPI_IO1_EC
GPP_A1/ESPI_IO1 ESPI_IO1_EC 38 +V3P3A_PCH
ns CN49 ESPI_IO2 RU40 电阻_10R_0201_1/20W_J ESPI_IO2_EC
eSPI
GPP_A2/ESPI_IO2 ESPI_IO2_EC 38
CLNK_CLK_SOC DV19 CN47 ESPI_IO3 RU43 电阻_10R_0201_1/20W_J ESPI_IO3_EC
MLINK
43 CLNK_CLK_SOC CLNK_DATA_SOC CL_CLK GPP_A3/ESPI_IO3 ESPI_CS_N ESPI_IO3_EC 38

DW19 CT45
43 CLNK_DATA_SOC CL_DATA GPP_A4/ESPI_CS_N ESPI_CS_N 38
电阻_2.2K_0201_1/20 W_J(±5%)
电阻_2.2K_0201_1/20 W_J(±5%)
CLNK_RESET_SOC DT19 CR46 ESPI_RESET
43 CLNK_RESET_SOC CL_RST_N GPP_A6/ESPI_RESET_N ESPI_RESET 38
RU41
5 of 19 RU42
ICL_U_IP_EXT_WW20 ?
B B
ESPI_CLK_EC
ESPI_IO0_EC
ESPI_IO1_EC
ESPI_IO2_EC SMBUS_CLK0
FLASH_SPI_CLK ESPI_CS_N ESPI_RESET ESPI_IO3_EC
SMBUS_DAT0
电容_22pF_0201_C0G_25 V_J(±5%)
电容_22pF_0201_C0G_25 V_J(±5%)
电容_22pF_0201_C0G_25 V_J(±5%)
电容_22pF_0201_C0G_25 V_J(±5%)
电容_22pF_0201_C0G_25 V_J(±5%)
RU44 RU45 RU46
ns CU1 CU2 CU3 CU4 CU5
电阻_100K_0201_1/20W_J 电阻_75K_0201_1/20 W_F(±1%) 电阻_75K_0201_1/20 W_F(±1%)
ns ns ns ns ns
PCH STRAP
+V3P3A_PCH +V3P3A_SPI_FLASH +V3P3A_SPI_FLASH +V3P3A_PCH XTAL INPUT FREQUENCY
+V3P3A_PCH +V3P3A_PCH +V3P3A_PCH JTAG ODT DISABLE +V3P3A_PCH
BOOT HALT TLS CONFIDENTIALITY ESPI OR EC LESS MAF/SAF STRAP JTAG ODT DISABLE CONSENT STRAP DFXTESTMODE
电阻_100K_0201_1/20W_J
1.SPI1_CS0_N
电阻_20K_0201_1/20W_J
电阻_4.7K_0201_1/20W_J
电阻_100K_0201_1/20W_J
XTAL INPUT FREQUENCY [0]

电阻_4.7K_0201_1/20W_J
电阻_4.7K_0201_1/20W_J 电阻_20K_0201_1/20W_J
2.SPI1_CLK
电阻_10K_0201_1/20W_J
DBG_PMODE XTAL INPUT FREQUENCY [1]
电阻_100K_0201_1/20W_J电阻_4.7K_0201_1/20W_J
电阻_10K_0201_1/20W_J
RU48 RU53
电阻_1K_0201_1/20W_J
RU47
RU49
ns RU50 ns RU51 RU52
RU55 RU56
RU54 ns
A A
FLASH_SPI_MOSI
WAKE_PCIE_N_SOC_H2 EC_SLP_S0_CS_N FLASH_SPI_IO3
FLASH_SPI_IO2 SPI1_CS0_N
电阻_4.7K_0201_1/20W_J
GPPC_C2_SMBALERT_N GPPC_C5_SML0ALERT_N
电阻_4.7K_0201_1/20W_J
电阻_100K_0201_1/20W_J
SPI1_CLK
电阻_20K_0201_1/20W_J
电阻_20K_0201_1/20W_J
RU57
RU61
RU62
RU59 RU60 ns RU63
ns GPPC_C5_SML0ALERT_N RU58 ns ns ns
FLASH_SPI_MOSI 0: Enable eSPI. (Default) GPPC_H2(WAKE_PCIE_N_SOC) FLASH_SPI_IO2 DBG_PMODE ns ns Huaqin Telecom Technology Com.,Ltd.
1: DISABLED GPPC_C2_SMBALERT_N 1: Disable 0: Enable MAFS EC_SLP_S0_CS_N FLASH_SPI_IO3 0: ENABLED 0: DFXTESTMODE ENABLED
0: ENABLED 0: Disable TLS CONFIDENTIALITY DISABLE(Default) Internal 20K PD 1: Enable SAFS 0: JTAG ODT DISABLED 0: ENABLED 1: DISABLED 1: DFXTESTMODE DISABLED(DEFAULT)
00: DIVIDER BYPASS
Page name:
01: DIVIDE BY 2 (HVM: 38.4MHZ INPUT)
WEAK INTERNAL PU
1: Enable TLS CONFIDENTIALITY DISABLE
Internal 20K PD WEAK INTERNAL PD 20K 1: JTAG ODT ENABLED
NO INTERNAL PU/PD
1: DISABLED
NO INTERNAL PU/PD
NO INTERNAL PU/PD WEAK INTERNAL PU 20K 10: DIVIDE BY 10 (HVM: 250MHZ INPUT) ICL-U42(SPI/ESPI/MIPI60)
11: DIVIDE BY 4 (BI: 100MHZ INPUT) Size: Project REV:
( QUALIFIED BY DFXTESTMODE)
A4 Name: V1.0
NO INTERNAL PU/PD NB8511
Date: Sheet: of
Monday, July 15, 2019 8 72
5 4 3 2 1
5 4 3 2 1
PCH STRAP
UU1I ? ?? +V1P8A
电阻_4.7K_0201_1/20W_J
D12 DP27 HW_ID0 XTAL SEL
C12 CSI_E_CLK_N GPP_F8/EMMC_DATA0 DU30 HW_ID1
CSI_E_CLK_P GPP_F9/EMMC_DATA1
B12
A12 CSI_E_DN_0 GPP_F10/EMMC_DATA2
DT30
DT29
HW_ID2
HW_ID3
Memory ID RU64
G13 CSI_E_DP_0 GPP_F11/EMMC_DATA3 DV30 HW_ID4 ns
F13 CSI_E_DN_1 GPP_F12/EMMC_DATA4 DU29 HW_ID5 GPU ID
eMMC
CSI_E_DP_1 GPP_F13/EMMC_DATA5
K10 GPP_F14/EMMC_DATA6
DW30
DW29
HW_ID6
HW_ID7
LCD ID
L10 CSI_F_CLK_N GPP_F15/EMMC_DATA7 DV28 Project ID
L8 CSI_F_CLK_P GPP_F7/EMMC_CMD DW28
D D
CSI_F_DN_0 GPP_F16/EMMC_RCLK CNV_BRI_DT_SOC
M8 DN27
M11 CSI_F_DP_0 GPP_F17/EMMC_CLK DT28 RU65
电阻_20K_0201_1/20W_J
L11 CSI_F_DN_1 GPP_F18/EMMC_RESET_N DU28 EMMC_RCOMP
CSI_F_DP_1 EMMC_RCOMP
电阻_200R_0201_1/20W_F
D9 RU67 CNV_BRI_DT_SOC
C9 CSI_D_CLK_N DV45 CNV_WT_LANE0_DN_R RU66 电阻_0R_0201_1/20W_J CNV_WT_LANE0_DN
CSI_D_CLK_P CNV_WT_D0N CNV_WT_LANE0_DN 43 0: 38.4/19.2MHZ (DEFAULT)
A7 DU45 CNV_WT_LANE0_DP_R RU68 电阻_0R_0201_1/20W_J CNV_WT_LANE0_DP ns 1: 24MHZ (25 MHZ WHEN XTAL
CSI_D_DN_0 CNV_WT_D0P CNV_WT_LANE0_DP 43
B7 DU44 CNV_WT_LANE1_DN_R RU69 电阻_0R_0201_1/20W_J CNV_WT_LANE1_DN FREQ DIVIDER NON ZERO)
CSI_D_DP_0 CNV_WT_D1N CNV_WT_LANE1_DN 43
B9 DT44 CNV_WT_LANE1_DP_R RU70 电阻_0R_0201_1/20W_J CNV_WT_LANE1_DP WEAK INTERNAL PD 20K
CSI_D_DN_1 CNV_WT_D1P CNV_WT_LANE1_DP 43
A9 DL42 CNV_WT_CLK_DN_R RU71 电阻_0R_0201_1/20W_J CNV_WT_CLK_DN
D7 CSI_D_DP_1 CNV_WT_CLKN DK42 CNV_WT_CLK_DP_R RU72 电阻_0R_0201_1/20W_J CNV_WT_CLK_DP CNV_WT_CLK_DN 43
C7 CSI_D_DN_2/CSI_C_DN_0 CNV_WT_CLKP CNV_WT_CLK_DP 43
CSI2
D8 CSI_D_DP_2/CSI_C_DP_0 DP44 CNV_WR_LANE0_DN
CSI_D_DN_3/CSI_C_CLK_N CNV_WR_D0N CNV_WR_LANE0_DN 43
C8 DN44 CNV_WR_LANE0_DP
CSI_D_DP_3/CSI_C_CLK_P CNV_WR_D0P CNV_WR_LANE0_DP 43
DG42 CNV_WR_LANE1_DN
CNV_WR_D1N CNV_WR_LANE1_DN 43
G11 DG44 CNV_WR_LANE1_DP
CSI_H_CLK_N CNV_WR_D1P CNV_WR_LANE1_DP 43
J11 DK44 CNV_WR_CLK_DN
CSI_H_CLK_P CNV_WR_CLKN CNV_WR_CLK_DN 43
F6 DJ44 CNV_WR_CLK_DP
CNV_WR_CLK_DP 43
CNVi
G6 CSI_H_DN_0 CNV_WR_CLKP
G10 CSI_H_DP_0 DT45 CNV_WT_RCOMP RU73 电阻_150R_0201_1/20W_F
F10 CSI_H_DN_1 CNV_WT_RCOMP
G8 CSI_H_DP_1 DL29 CNV_BRI_RSP_SOC
CSI_H_DN_2/CSI_G_DN_0 GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_BRI_RSP_SOC 43
J8 DP31 CNV_RGI_DT_SOC RU74 电阻_33R_0201_1/20W_F CNV_RGI_DT
K6 CSI_H_DP_2/CSI_G_DP_0 GPP_F2/CNV_RGI_DT/UART0_TXD DL31 CNV_BRI_DT_SOC RU75 电阻_33R_0201_1/20W_F CNV_BRI_DT CNV_RGI_DT 43
L6 CSI_H_DN_3/CSI_G_CLK_N GPP_F0/CNV_BRI_DT/UART0_RTS_N DN29 CNV_RGI_RSP_SOC CNV_BRI_DT 43
CSI_H_DP_3/CSI_G_CLK_P GPP_F3/CNV_RGI_RSP/UART0_CTS_N CNV_RGI_RSP_SOC 43
CNV_RGI_DT_SOC
RU76
CSI_COMP B4 DJ29 +V1P8A
CSI_RCOMP GPP_F4/CNV_RF_RESET_N DP29
电阻_100R_0201_1/20W_F GPP_F6/CNV_PA_BLANKING
电阻_100K_0201_1/20W_J
DT34 DL27 A4WP_PRESENT
GPP_D4/IMGCLKOUT0 GPP_F19/A4WP_PRESENT RU223
DP38 DK29
DK36 GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ ns 电阻_4.7K_0201_1/20W_J
GPP_H21/IMGCLKOUT2 RU77
DL36
DN38 GPP_H22/IMGCLKOUT3
GPP_H23/IMGCLKOUT4 ns
C C
ICL_U_IP_EXT_WW20 ?
9 of 19
电阻_100K_0201_1/20W_J
RU78 +V1P8A
电阻_10K_0201_1/20W_J
电阻_20K_0201_1/20W_J
RU79 RU80
ns ns
CNV_RGI_RSP_SOC
CNV_BRI_RSP_SOC
CU6 电容_6.8pF_0201_C0G_50 V_C(±0.25pF)
电阻_10M_0201_1/20 W_J(±5%)
UU1J ?? ?
close to SOC - 07/10
2
RU81 YU1
PCIE_REFCLK_GFX_DN CJ3 CF5
29 PCIE_REFCLK_GFX_DN PCIE_REFCLK_GFX_DP CJ5 CLKOUT_PCIE_N0 CLKOUT_PCIE_N5 CF3 Q13FC1350000200
29 PCIE_REFCLK_GFX_DP PCIE_CLKREQ_VGA_N DK33 CLKOUT_PCIE_P0 CLKOUT_PCIE_P5 DP40
29 PCIE_CLKREQ_VGA_N GPP_D5/SRCCLKREQ0_N GPP_H11/SRCCLKREQ5_N
CL2
1
CLKOUT_PCIE_N1 RTC CRYSTAL
CL1 DL48 XTAL_32K_SOC_IN RU82 电阻_0R_0201_1/20W_J
B
DN34 CLKOUT_PCIE_P1 RTCX1 DL49 XTAL_32K_SOC_OUT RU83 电阻_0R_0201_1/20W_J CU7 电容_6.8pF_0201_C0G_50 V_C(±0.25pF) B
GPP_D6/SRCCLKREQ1_N RTCX2
CL3 DT47 RTC_RST_N
CL5 CLKOUT_PCIE_N2 RTCRST_N DK46 SRTC_RST_N
DP34 CLKOUT_PCIE_P2 SRTCRST_N
GPP_D7/SRCCLKREQ2_N DF49 SUS_CLK RU84 电阻_33R_0201_1/20W_F
PCIE_REFCLK_WLAN_DN CK3 GPD8/SUSCLK SUS_CLK_WLAN 43
43 PCIE_REFCLK_WLAN_DN CLKOUT_PCIE_N3 电容_8.2pF_0201_C0G_50 V_C(±0.25pf)
PCIE_REFCLK_WLAN_DP CK4 电阻_0R_0201_1/20W_J
D
3
43 PCIE_REFCLK_WLAN_DP PCIE_WLAN_CLK_REQ_N DP36 CLKOUT_PCIE_P3 DW8 XTAL_38P4M_SOC_IN RU85
43 PCIE_WLAN_CLK_REQ_N GPP_D8/SRCCLKREQ3_N XTAL_IN DU8 XTAL_38P4M_SOC_OUT RU86
电阻_200K_0201_1/20 W_F(±1%)
XTAL_OUT MAIN 38.4MHZ CRYSTAL QU2 +VCCRTC

41 PCIE_REFCLK_SSD_DN PCIE_REFCLK_SSD_DN CJ2 CU8
CLKOUT_PCIE_N4 电阻_0R_0201_1/20W_J YU2 LMN2500N3T5G
PCIE_REFCLK_SSD_DP CJ1
S
41 PCIE_REFCLK_SSD_DP CLKOUT_PCIE_P4
1 G
PCIE_SSD_CLKREQ1 DN40 DU6 XCLK_BIASREF 2 38.4MHZ 3
41 PCIE_SSD_CLKREQ1 GPP_H10/SRCCLKREQ4_N XCLK_BIASREF GND1 3
电阻_27K_0201_1/20W_F
电阻_27K_0201_1/20W_F
2
EC_RTCRST 38
10 of 19
RU87 RU90 RU91 RU89
ICL_U_IP_EXT_WW20 ? 1 4
1 GND2
RU88
X3S038400BA1H-HS 电阻_10K_0201_1/20W_J
电阻_60.4R_0201_1/20_F(±1%)
CU9
电容_8.2pF_0201_C0G_50 V_C(±0.25pf) SRTC_RST_N

RTC_RST_N
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
20MILTPU8 ns 1
20MILTPU9 ns 1
CU10 CU11
+V3P3SX
+V1P8A
HW ID
A A
RU92 电阻_4.7K_0201_1/20W_J HW_ID0 RU93 电阻_4.7K_0201_1/20W_J
电阻_10K_0201_1/20W_J
电阻_10K_0201_1/20W_J
ns_LP4/X_ID@ LP_4/X_ID@
ns_LP4/X_ID@ LP_4I/X_ID@
ns_LP4/X_ID@ LP_4/X_ID@ RU103 RU101
ns_LP4X_ID@ LP4_ID@
DLG_R_ID@ DLG_ID@ Huaqin Telecom Technology Com.,Ltd.
DGPU_ID@ UMA_ID@
RU107 电阻_4.7K_0201_1/20W_J HW_ID6 RU108 电阻_4.7K_0201_1/20W_J Page name:
LCD4X@ LCD2X@ ICL-U42(CNV1/CSI/CLK)
NB8512@ NB8511@ PCIE_WLAN_CLK_REQ_N Size: Project REV:
PCIE_CLKREQ_VGA_N A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 9 72
5 4 3 2 1
5 4 3 2 1
PCH STRAP
+V3P3SX TOP SWAP OVERRIDE
+V3P3SX
UU1F ???
GPPC_B_14_SPKR
0: Disable Top Swap mode. (Default)
CH48 DV33 1: Enable
GPPC_B18_GSPI0_MOSI CF48 GPP_B16/GSPI0_CLK GPP_D13/ISH_UART0_RXD DW33 RU112 Internal 20K PD
GPP_B18/GSPI0_MOSI GPP_D14/ISH_UART0_TXD RU111
CF47 DT33 CNVI_EN_N ns
GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5 CNVI_EN_N 43 电阻_10K_0201_1/20W_J
PCH_WLAN_OFF_N CH49 DU33 电阻_4.7K_0201_1/20W_J
43 PCH_WLAN_OFF_N GPPC_B_14_SPKR CH47 GPP_B15/GSPI0_CS0_N GPP_D16/ISH_UART0_CTS_N/CNV_WCEN GPU
50 GPPC_B_14_SPKR GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1_N DK22 SSD_RST_N
1 GPSI1_CLK CL47 GPP_C12/UART1_RXD/ISH_UART1_RXD DW24 SSD_RST_N 41 GPPC_B_14_SPKR
20MIL TPU10 ns GPP_B20/GSPI1_CLK GPP_C13/UART1_TXD/ISH_UART1_TXD
1 GPSI1_MOSI CK47 DV24 GPU_EVENT_N
20MIL TPU11 ns GPP_B22/GSPI1_MOSI GPP_C14/UART1_RTS_N/ISH_UART1_RTS_N GPU_EVENT_N 29
1 GPSI1_MISO CK46 DU24 RU113
D 20MIL TPU12 ns GPP_B21/GSPI1_MISO GPP_C15/UART1_CTS_N/ISH_UART1_CTS_N D
TCH_EN_SOC CH45
39 TCH_EN_SOC GPP_B19/GSPI1_CS0_N 电阻_20K_0201_1/20W_J
GPPC_B23_SML1_ALERT_NCL48 CN43 BT_WAKE_N_SOC
GPP_B23/SML1ALERT_N/PCHHOT_N/GSPI1_CS1_N GPP_B5/ISH_I2C0_SDA CN42 BT_WAKE_N_SOC 43
GPP_B6/ISH_I2C0_SCL ns
DP21
DK21 GPP_C8/UART0_RXD CN41
WLAN_RST_N DL21 GPP_C9/UART0_TXD GPP_B7/ISH_I2C1_SDA CL43
43 WLAN_RST_N DJ22 GPP_C10/UART0_RTS_N GPP_B8/ISH_I2C1_SCL
GPP_C11/UART0_CTS_N CL41
UART2_RXD DT22 GPP_B9/I2C5_SDA/ISH_I2C2_SDA CJ39
55 UART2_RXD GPP_C20/UART2_RXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL +V3P3SX
UART2_TXD DW22 DU36 GPU_PWREN NO REBOOT
55 UART2_TXD DV22 GPP_C21/UART2_TXD GPP_D0/ISH_GP0 DV36 PCH_GPU_RST_N_R
DU22 GPP_C22/UART2_RTS_N GPP_D1/ISH_GP1 DW36 GPPC_B18_GSPI0_MOSI
GPP_C23/UART2_CTS_N GPP_D2/ISH_GP2 DT36 FB_GC6_EN_R
0: Disable No Reboot mode. (Default)
FB_GC6_EN_R 29 RU114 1: Enable
RT_TCP0_I2C0_SDA DT24 GPP_D3/ISH_GP3 DU34 Internal 20K PD
45 RT_TCP0_I2C0_SDA GPP_C16/I2C0_SDA GPP_D17/ISH_GP4 ns
RT_TCP0_I2C0_SCL DT23 DW34 GPU_PWROK_R GPU_PWROK
45 RT_TCP0_I2C0_SCL GPP_C17/I2C0_SCL GPP_D18/ISH_GP5 ns 电阻_0R_0201_1/20W_J GPU_PWROK 29,69 电阻_4.7K_0201_1/20W_J
DT14 RU115
TOUCHPAD_I2C_SDA DW23 GPP_E15/ISH_GP6 DU14
52 TOUCHPAD_I2C_SDA GPP_C18/I2C1_SDA GPP_E16/ISH_GP7
TOUCHPAD_I2C_CLK DU23 RU116 GPU_PG_Q GPPC_B18_GSPI0_MOSI
52 TOUCHPAD_I2C_CLK GPP_C19/I2C1_SCL GPU 电阻_0R_0201_1/20W_J GPU_PG_Q 29
DU41
DV41 GPP_H4/I2C2_SDA
GPP_H5/I2C2_SCL RU117
电阻_20K_0201_1/20W_J
DW41
DT41 GPP_H6/I2C3_SDA
GPP_H7/I2C3_SCL ns
DT40
DW40 GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
FLASH DESCRIPTOR SECURITY OVERRIDE
+V3P3A_PCH HDA_SDO_R
0: SECURITY MEASURES NOT OVERRIDEN
1: OVERRIDEN
WEAK INTERNAL PD 20K
C C
RU118 HDA_SDO_R
I2C_PD_SOC_INT_N RU218 电阻_0R_0201_1/20W_J GPPC_B23_SML1_ALERT_N ns 电阻_4.7K_0201_1/20W_J
12,44 I2C_PD_SOC_INT_N ns
+V3P3A_PCH CPUNSSC CLOCK FREQ

+V3P3SX
RU119 电阻_10K_0201_1/20W_J GPU_PWREN

GPU GPU_PWREN 29 RU123
RU120 电阻_10K_0201_1/20W_J PCH_GPU_RST_N_R RU121 ns
ns GPU PCH_GPU_RST_N 29 电阻_4.7K_0201_1/20W_J
电阻_0R_0201_1/20W_J
RU122 电阻_10K_0201_1/20W_J
ns GPPC_B23_SML1_ALERT_N
CU13 电容_10nF_0201_X7R_16V_K PCH_GPU_RST_N
GPU
RU124
ns
电阻_20K_0201_1/20W_J
HDA_SDO_R RU125 EC_ME_UNLOCK GPPC_B23_SML1_ALERT_N
EC_ME_UNLOCK 38
电阻_4.7K_0201_1/20W_J 0: 38.4MHZ CLOCK FROM DIRECT
CRYSTAL (DEFAULT)
1: 19.2MHZ CLOCK FROM DIVIDER
(DERIVED FROM 38.4MHZ CRYSTAL)
WEAK INTERNAL PD 20K
UU1G ???
CE46 SSD1_DET_R RU126 电阻_0R_0201_1/20W_J
GPP_G6/SD_CLK SSD1_DET 11,41
B HDA_BCLK RU127 电阻_33R_0201_1/20W_F HDA_BCLK_R CY46 CC48 RIPQ_N_SOC B
50 HDA_BCLK GPP_R0/HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0 RIPQ_N_SOC 36
HDA_SYNC RU129 电阻_33R_0201_1/20W_F HDA_SYNC_R CV49 CC49 WAKE_PCIE_N_SOC_R RU130 电阻_0R_0201_1/20W_J
50 HDA_SYNC GPP_R1/HDA_SYNC/I2S0_SFRM GPP_G2/SD_DATA1 WAKE_PCIE_N_SOC 8,43
HDA_SDO RU131 电阻_33R_0201_1/20W_F HDA_SDO_R CY47 CC47 CAM_PWR_ON_SOC_R RU132 电阻_0R_0201_1/20W_J
50 HDA_SDO HDA_SDI CV45 GPP_R2/HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2 CF45 CAM_PWR_ON_SOC 39
50 HDA_SDI GPP_R3/HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3
HDA_RST_N RU133 电阻_33R_0201_1/20W_F HDA_RST_N_R DA47 CC45 TOUCHPAD_INT_N
50 HDA_RST_N GPP_R4/HDA_RST_N GPP_G0/SD_CMD TOUCHPAD_INT_N 52
SD3.0 CF49
DP33 GPP_G7/SD_WP CE47
GPP_D19/I2S_MCLK GPP_G5/SD_CD_N
DC45 DK38
DA49 GPP_A23/I2S1_SCLK GPP_H0/CNV_BT_I2S_SDO DG38
DA45 GPP_R5/HDA_SDI1/I2S1_SFRM GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO
RU135 DA48 GPP_R6/I2S1_TXD CJ43 SD3_RCOMP RU134 电阻_200R_0201_1/20W_F
M.2_BT_PCMCLK SOC_BT_PCMCLK CT49 GPP_R7/I2S1_RXD SD3_RCOMP
43 M.2_BT_PCMCLK CNV_RF_RESET_N CT48 GPP_A7/I2S2_SCLK
电阻_33R_0201_1/20W_F 43 CNV_RF_RESET_N GPP_A8/I2S2_SFRM/CNV_RF_RESET_N
43 CNV_MFUART2_RXD CNV_MFUART2_RXD CV47 DG36 RU136 电阻_33R_0201_1/20W_F
CNV_MODEM_CLKREQ CT47 GPP_A10/I2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLK0 DG34 PCH_DMIC1_CLK0 39
43 CNV_MODEM_CLKREQ GPP_A9/I2S2_TXD/MODEM_CLKREQ GPP_S7/SNDW4_DATA/DMIC_DATA0 PCH_DMIC1_DATA0 39
电容_27pF_0201_C0G_25V_J
电容_27pF_0201_C0G_25V_J
Config to 1.8V level CY39 CV38 SNDW_RCOMP
CY38 GPP_S0/SNDW1_CLK SNDW_RCOMP
电阻_200R_0201_1/20W_F
GPP_S1/SNDW1_DATA
AUDIO
DB39 CU14 CU15
DD38 GPP_S2/SNDW2_CLK
GPP_S3/SNDW2_DATA RU137 ns ns
RU138 电阻_33R_0201_1/20W_F DF38
39 PCH_DMIC2_CLK1 ns DD39 GPP_S4/SNDW3_CLK/DMIC_CLK1
39 PCH_DMIC2_DATA1 GPP_S5/SNDW3_DATA/DMIC_DATA1
电容_27pF_0201_C0G_25V_J
电容_27pF_0201_C0G_25V_J
CU16 CU17
CNV_MODEM_CLKREQ
电容_100nF_0201_X5R_6.3 V_M(±20%)
CNV_RF_RESET_N ns ns
RU140
电阻_71.5K_0201_1/20_F(±1%)
RU139
电阻_75K_0201_1/20 W_F(±1%)
CU169
A A
HDA_SYNC_R CU18 电容_2pF_0201_C0G_25V_±0.25pF
ns
HDA_BCLK_R CU19 电容_2pF_0201_C0G_25V_±0.25pF
ns
HDA_SDO_R CU20 电容_2pF_0201_C0G_25V_±0.25pF
ns
HDA_RST_N_R CU21 电容_2pF_0201_C0G_25V_±0.25pF
ns
HDA_SDI CU22 电容_2pF_0201_C0G_25V_±0.25pF
ns
Close to CPU Page name:

Close to CPU ICL-U42(HDA/SD/ISH/GSPI)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 10 72
5 4 3 2 1
5 4 3 2 1
UU1H ???
PCIE_CRX_GTX_N2 CV7 DJ8 USB3_P1_RX_DN

29 PCIE_CRX_GTX_N2 PCIE7_RXN PCIE1_RXN/USB31_1_RXN USB3_P1_RX_DN 49
PCIE_CRX_GTX_P2 CV6 DJ6 USB3_P1_RX_DP
29 PCIE_CRX_GTX_P2 PCIE7_RXP PCIE1_RXP/USB31_1_RXP USB3_P1_RX_DP 49
PCIE_CTX_GRX_N2CU23 电容_220nF_0201_X5R_6.3V_MPCIE_CTX_GRX_N2_C DD3 DJ2 USB3_P1_TX_DN
29 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2CU24 电容_220nF_0201_X5R_6.3V_MPCIE_CTX_GRX_P2_C DD5 PCIE7_TXN PCIE1_TXN/USB31_1_TXN DJ1 USB3_P1_TX_DP USB3_P1_TX_DN 49 USB3.0 TypeA 1 AUO
29 PCIE_CTX_GRX_P2 PCIE7_TXP PCIE1_TXP/USB31_1_TXP USB3_P1_TX_DP 49
GPU
GPU 29 PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
GPU CT6
CT7 PCIE8_RXN PCIE2_RXN/USB31_2_RXN
DG9
DG7
29 PCIE_CRX_GTX_P3
PCIE_CTX_GRX_N3CU25 电容_220nF_0201_X5R_6.3V_MPCIE_CTX_GRX_N3_C DA3 PCIE8_RXP PCIE2_RXP/USB31_2_RXP DJ3 NA
D 29 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3CU26 电容_220nF_0201_X5R_6.3V_MPCIE_CTX_GRX_P3_C DA5 PCIE8_TXN PCIE2_TXN/USB31_2_TXN DJ5 D
29 PCIE_CTX_GRX_P3 PCIE8_TXP PCIE2_TXP/USB31_2_TXP
GPU
GPU CP7 DE7
PCIE9_RXN PCIE3_RXN/USB31_3_RXN
CP6
DA2 PCIE9_RXP PCIE3_RXP/USB31_3_RXP
DE9
DF3
NA
NA DA1 PCIE9_TXN PCIE3_TXN/USB31_3_TXN DF5
PCIE9_TXP PCIE3_TXP/USB31_3_TXP
PCIE_WLAN_RX_DN CM7 DC7
43
43
PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP
PCIE_WLAN_RX_DP CM6 PCIE10_RXN PCIE4_RXN/USB31_4_RXN DC9 NA
PCIE_WLAN_TX_DN CY3 PCIE10_RXP PCIE4_RXP/USB31_4_RXP DF2
WLAN 43 PCIE_WLAN_TX_DN PCIE10_TXN PCIE4_TXN/USB31_4_TXN
PCIE_WLAN_TX_DP CY4 DF1
43 PCIE_WLAN_TX_DP PCIE10_TXP PCIE4_TXP/USB31_4_TXP
CK7 DA6 PCIE_CRX_GTX_N0
PCIE11_RXN/SATA0_RXN PCIE5_RXN/USB31_5_RXN PCIE_CRX_GTX_N0 29
CK6 DA7 PCIE_CRX_GTX_P0
PCIE11_RXP/SATA0_RXP PCIE5_RXP/USB31_5_RXP PCIE_CRX_GTX_P0 29
CW2 DE4 PCIE_CTX_GRX_N0_C CU27 电容_220nF_0201_X5R_6.3V_M PCIE_CTX_GRX_N0
CW1 PCIE11_TXN/SATA0_TXN PCIE5_TXN/USB31_5_TXN DE3 PCIE_CTX_GRX_P0_C CU28 电容_220nF_0201_X5R_6.3V_M PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 29
PCIE11_TXP/SATA0_TXP PCIE5_TXP/USB31_5_TXP PCIE_CTX_GRX_P0 29
GPU
CJ6
CJ7 PCIE12_RXN/SATA1A_RXN PCIE6_RXN/USB31_6_RXN
CY7
CY6
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1
GPU PCIE_CRX_GTX_N1 29 GPU
PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6_RXP PCIE_CRX_GTX_P1 29
CW5 DD1 PCIE_CTX_GRX_N1_C CU29 电容_220nF_0201_X5R_6.3V_M PCIE_CTX_GRX_N1
CW3 PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN DD2 PCIE_CTX_GRX_P1_C CU30 电容_220nF_0201_X5R_6.3V_M PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 29
PCIE12_TXP/SATA1A_TXP PCIE6_TXP/USB31_6_TXP PCIE_CTX_GRX_P1 29
GPU
PCIE13_CRX_DTX_N CG7 DN8 USB2_P1_DN GPU
41 PCIE13_CRX_DTX_N PCIE13_RXN USB2N_1 USB2_P1_DN 49
41 PCIE13_CRX_DTX_P
PCIE13_CRX_DTX_P
PCIE13_CTX_DRX_N
CG6
CT3 PCIE13_RXP USB2P_1
DP8 USB2_P1_DP
USB2_P1_DP 49 USB3.0 Type-A 1 AUO
41 PCIE13_CTX_DRX_N PCIE13_CTX_DRX_P CT5 PCIE13_TXN DK11
41 PCIE13_CTX_DRX_P PCIE13_TXP USB2N_2
PCIE14_CRX_DTX_N CE6 USB2P_2
DJ11 NA
41 PCIE14_CRX_DTX_N PCIE14_RXN
PCIE14_CRX_DTX_P CE7 DP13 USB2_P3_TYPEC_DN
41 PCIE14_CRX_DTX_P PCIE14_RXP USB2N_3 USB2_P3_TYPEC_DN 48
PCIE14_CTX_DRX_N CT2 DN13 USB2_P3_TYPEC_DP
C
41 PCIE14_CTX_DRX_N PCIE14_CTX_DRX_P CT1 PCIE14_TXN USB2P_3 USB2_P3_TYPEC_DP 48 Type-C C
41 PCIE14_CTX_DRX_P PCIE14_TXP DK10 USB2_P4_DN

SSD1 USB2N_4 USB2_P4_DN 54
41 PCIE15_CRX_DTX_N
PCIE15_CRX_DTX_N
PCIE15_CRX_DTX_P
CC5
CC6 PCIE15_RXN/SATA1B_RXN USB2P_4
DJ10 USB2_P4_DP
USB2_P4_DP 54 DB USB2.0 Type-A
41 PCIE15_CRX_DTX_P PCIE15_RXP/SATA1B_RXP
PCIE15_CTX_DRX_N CR3 DL5 USB2_P5_FP_DN
41 PCIE15_CTX_DRX_N PCIE15_TXN/SATA1B_TXN USB2N_5 USB2_P5_FP_DN 52
41 PCIE15_CTX_DRX_P
PCIE15_CTX_DRX_P CR4
PCIE15_TXP/SATA1B_TXP USB2P_5
DL3 USB2_P5_FP_DP
USB2_P5_FP_DP 52 Finger Print
PCIE16_SATA_CRX_DTX_N CA6 DP11 USB_P7_CAM_N
41 PCIE16_SATA_CRX_DTX_N PCIE16_RXN/SATA2_RXN USB2N_6 USB_P7_CAM_N 39
41 PCIE16_SATA_CRX_DTX_P
PCIE16_SATA_CRX_DTX_P
PCIE16_SATA_CTX_DRX_N
CA5
CP1 PCIE16_RXP/SATA2_RXP USB2P_6
DN11 USB_P7_CAM_P
USB_P7_CAM_P 39 Camera
41 PCIE16_SATA_CTX_DRX_N PCIE16_SATA_CTX_DRX_P CP2 PCIE16_TXN/SATA2_TXN DK13
41 PCIE16_SATA_CTX_DRX_P PCIE16_TXP/SATA2_TXP USB2N_7
DW12 USB2P_7
DJ13 NA
CR42 GPP_E0/SATAXPCIE0/SATAGP0 DN6
10,41 SSD1_DET
SSD1_DET CR43 GPP_A12/SATAXPCIE1/SATAGP1 USB2N_8 DP6 NA
GPP_A13/SATAXPCIE2/SATAGP2 USB2P_8
USB_OC0 DW14 DL2 USB2_P9_TS_DN
49 USB_OC0 GPP_E9/USB_OC0_N USB2N_9 USB2_P9_TS_DN 39
54 USB_OC3
USB_OC3 CT43
GPP_A16/USB_OC3_N USB2P_9
DL1 USB2_P9_TS_DP
USB2_P9_TS_DP 39 Touch Panel
DU12 DP10 USB2_P10_BT_DN
GPP_E4/DEVSLP0 USB2N_10 USB2_P10_BT_DN 43
SATA1_DEVSLP
DU11
CV48 GPP_E5/DEVSLP1 USB2P_10
DN10 USB2_P10_BT_DP
USB2_P10_BT_DP 43 BT
41 SATA1_DEVSLP GPP_A11/DEVSLP2 DL6 USB2_OTG_ID
DT38 USB_ID
DW38 GPP_H12/M2_SKT2_CFG0 DL11 USB2_VBUSSENSE
DV38 GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE
DU38 GPP_H14/M2_SKT2_CFG2 DN5 USB2_COMP RU141
RU142 GPP_H15/M2_SKT2_CFG3 USB2_COMP
电阻_113R_0201_1/20 W_F(±1%)
电阻_100R_0201_1/20W_F PCIE_RCOMP_N DN1 CD3
B
PCIE_RCOMP_P DN3 PCIE_RCOMPN RSVD_BSCAN B
PCIE_RCOMPP USB2_COMP2 RESISTOR SHOULD
8 of 19
BE PLACED NEAR TO THE PIN
ICL_U_IP_EXT_WW20 ? LENGHT <450 MILS
PCH STRAP
+V3P3A_PCH RING OSCILLATOR BYPASS
+V3P3A_PCH
电阻_20K_0201_1/20W_J
电阻_10K_0201_1/20W_J
RU145
RU144
USB2_OTG_ID
USB2_VBUSSENSE
电阻_10K_0201_1/20W_J
电阻_10K_0201_1/20W_J
USB_OC0
USB_OC3 RU146 RU147
电阻_4.7K_0201_1/20W_J
A A
RU150
ns
USB_OC0
0: RING OSCILLATOR Huaqin Telecom Technology Com.,Ltd.
1: BYPASS MODE ENABLED
(QUALIFIED BY DFXTESTMODE) Page name:
NO INTERNAL PU/PD ICL-U42(USB/PCIE)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 11 72
5 4 3 2 1
5 4 3 2 1
DSW_PWROK
PCH STRAP
CU170 RU151
RU152 3V SELECT STRAP
I2C_PD_SOC_INT_N_R I2C_PD_SOC_INT_N I2C_PD_SOC_INT_N 10,44
DSW_PWROK_EC DSW_PWROK
38,57 DSW_PWROK_EC 电容_4.7nF_0201_X7R_10v_K +V3P3A_PCH
电阻_0R_0201_1/20W_J
电阻_0R_0201_1/20W_J LOW-> 3.3V +/-5%
HIGH->3.0V +/-5%
RU154
ns
电阻_4.7K_0201_1/20W_J
D 20MIL TPU13 ns 1 D
20MIL TPU14 ns 1 INPUT3VSEL
20MIL TPU15 ns 1 UU1K ???
20MIL TPU18 ns 1 1 ns
TPU16 20MIL +V3P3A
RU153
SLP_SUS_N DM49 CY42 PM_PWRBTN_R_N
电阻_4.7K_0201_1/20W_J
63 SLP_SUS_N SLP_SUS_N GPD3/PWRBTN_N PM_PWRBTN_R_N 38
SLP_S5_N DF45 DE46 PM_AC_PRESENT
45 SLP_S5_N GPD10/SLP_S5_N GPD1/ACPRESENT PM_AC_PRESENT 38 电阻_100K_0201_1/20W_J
SLP_S4_N DC48 DH48 PM_BATLOW_N
38,64 SLP_S4_N GPD5/SLP_S4_N GPD0/BATLOW_N RU155
SLP_S3_N DF47
38,68 SLP_S3_N GPD4/SLP_S3_N
20MIL TPU17 ns SLP_A_N
1 DH47
GPD6/SLP_A_N GPP_B11/PMCALERT
CL39 I2C_PD_SOC_INT_N_R
SLP_S0_N CL45 DU40 CPU_C10_GATE_N
38,68 SLP_S0_N GPP_B12/SLP_S0_N GPP_H18/CPU_C10_GATE_N CPU_C10_GATE_N 38,68
20MIL TPU20 ns 1 GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
DG40
1 ns
SLP_WLAN_N DE49 TPU21 20MIL
43 SLP_WLAN_N GPD9/SLP_WLAN_N
+VCCRTC 20MIL TPU22 ns 1 SLP_LAN_N DN48
SLP_LAN_N WAKE_N
DL45 WAKE_PCH_N WAKE_PCH_N 43
XTAL INPUT MODE
RSMRST_N_EC DG49 DE47 LAN_WAKE_N
8,38,57 RSMRST_N_EC RSMRST_N GPD_2/LAN_WAKE_N +V3P3A_PCH GPD7(TCP_RETIMER_PERST_N)
PM_SYSRST_N DK19 DF48 GPD11 1 ns 0: XTAL IS ATTACHED
SYS_RESET_N GPD11/LANPHYPC/DSWLDO_MON TPU23 20MIL
PLT_RST_SOC_N CM49 1: XTAL INPUT IS SINGLE ENDED
GPP_B13/PLTRST_N CE4 VCCST_OVERRIDE Internal 20K PD
VCCST_OVERRIDE CF2 H_VCCST_PWRGD VCCST_OVERRIDE 68
RU156 VCCST_PWRGD
DSW_PWROK DR48 CE3 VCCSTPWRGOOD_TCSS RU157 电阻_0R_0201_1/20W_J VCCST_OVERRIDE RU158
ns 电阻_1M_0201_1/20W_J PCH_PWROK DN47 DSW_PWROK VCCSTPWRGOOD_TCSS CF1 PROCPWRGD 1 ns ns
38,57 PCH_PWROK PCH_PWROK PROCPWRGD TPU24 20MIL
SYS_PWROK DP19 电阻_4.7K_0201_1/20W_J
38 SYS_PWROK SYS_PWROK DC47 TCP_RETIMER_PERST_N
INPUT3VSEL DN49 GPD7 TCP_RETIMER_PERST_N 45
INPUT3VSEL TCP_RETIMER_PERST_N
SM_INTRUDER_N DR47
INTRUDER_N
电阻_10K_0201_1/20W_J
11 of 19 RU159
RU225
CU31
ns 电容_100nF_0201_16 V_M(±20%)
ICL_U_IP_EXT_WW20 ?
CU32 电容_4.7nF_0201_X7R_10v_K ns电阻_20K_0201_1/20W_J
<Option>
C RU160 C
PROCPWRGD
ns
电阻_100K_0201_1/20W_J
BY DEFAULT 3.3V FLASH SUPPORT.
FOR 1.8V FLASH OPERATION UNSTUFF CH23
+V3P3A +V1P0S_VCCST
+V3P3A
UU2 ns CU33
ns RU161 RU162
1 5 电阻_1K_0201_1/20W_J
NC VCC 电容_100nF_0201_X5R_6.3 V_M(±20%) ns 电阻_2.2K_0201_1/20 W_J(±5%)
PLT_RST_SOC_N 2
A DU1 RU164
RU163
电阻_100K_0201_1/20W_J
EC_VCCST_PWRGD H_VCCST_PWRGD
3 4 PLT_RST_N 38 EC_VCCST_PWRGD ns
GND Y ns PLT_RST_N 29,36,41,43,45 电阻_60.4R_0201_1/20_F(±1%)
电阻_0R_0201_1/20W_J LRB500V-40T1G
74AUP1G07GW 电阻_0R_0201_1/20W_J
CU34 RU166 CU35
RU165
ns 电容_100pF_0201_C0G_50V_J
电容_100pF_0201_C0G_50V_J
B RU167 B
电阻_0R_0201_1/20W_J
BUFFER TO REDUCE LOADING ON PLT_RST_N
+V3P3A_PCH
RTC FOR product line
RTC_VCC
RU169 电阻_100K_0201_1/20W_J SLP_S0_N
+V3P3SX 1 ns
+V3P3A_PCH RU170 电阻_100K_0201_1/20W_J PM_BATLOW_N +VCC3P3_LDO_OUT TP188 40MIL
1 ns
TP190 40MIL
RU226 电阻_100K_0201_1/20W_J
ns +VCCRTC DU2
RU171 电阻_10K_0201_1/20W_J PM_SYSRST_N
RU227 电阻_100K_0201_1/20W_J CPU_C10_GATE_N 2
RU172 电阻_1K_0201_1/20W_J LAN_WAKE_N
JRTCU1
3 RTC_VCC
(Max=3.3 V) LRC LBAT54CWT1 RU174 3
SYS_PWROK RU173 电阻_100K_0201_1/20W_J 1 1 MTG1
1
CU36 电容_100pF_0201_C0G_50V_J CU37 电阻_1K_0201_1/20W_J
ns
PCH_PWROK RU175 电阻_100K_0201_1/20W_J 电容_1uF_0201_X5R_6.3V_M 2
ns 2 4
CU38 电容_2.2nF_0201_X5R_25V_K MTG2
50278-00201-001
A
RSMRST_N_EC RU176 电阻_100K_0201_1/20W_J A
CU39 电容_100pF_0201_C0G_50V_J
ns
SLP_WLAN_N RU177 电阻_100K_0201_1/20W_J
SLP_S3_N RU178 电阻_100K_0201_1/20W_J
SLP_S4_N RU179 电阻_100K_0201_1/20W_J Huaqin Telecom Technology Com.,Ltd.
SLP_S5_N RU180 电阻_100K_0201_1/20W_J Page name:
ns ICL-U42(PMU)
VCCST_OVERRIDE RU181 电阻_100K_0201_1/20W_J
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 12 72
5 4 3 2 1
5 4 3 2 1
+VCCIN +VCCIN
UU1L ???
A19 CJ35
AC12 VCCIN_1 VCCIN_52 CK10
V13 VCCIN_2 VCCIN_53 J32
W12 VCCIN_3 VCCIN_54 CL34
Y13 VCCIN_4 VCCIN_55 CL35
K29 VCCIN_5 VCCIN_56 CN34
K31 VCCIN_6 VCCIN_57 CN35
D D
B19 VCCIN_7 VCCIN_58 CP33
B23 VCCIN_8 VCCIN_59 CR34
B27 VCCIN_9 VCCIN_60 A29
B29 VCCIN_10 VCCIN_61 CR35
BN10 VCCIN_11 VCCIN_62 CT33
BP11 VCCIN_12 VCCIN_63 CT34
BP9 VCCIN_13 VCCIN_64 CT35
BR10 VCCIN_14 VCCIN_65 CU33
BT11 VCCIN_15 VCCIN_66 D19
VCCIN_16 VCCIN_67 +V1P0S_VCCST
A21 D21
BT9 VCCIN_17 VCCIN_68 D23
CLOSE TO CPU
BU10 VCCIN_18 VCCIN_69 D24
BV36 VCCIN_19 VCCIN_70 D27
BV9 VCCIN_20 VCCIN_71 AA12
VCCIN_21 VCCIN_72
电阻_43R_0201_1/20W_F(±1%)
电阻_100R_0201_1/20W_F
电阻_56R_0201_1/20W_F
电容_1uF_0201_X5R_6.3V_M
BW10 D29
BW36 VCCIN_22 VCCIN_73 F19
BW9 VCCIN_23 VCCIN_74 F21
VCCIN_24 VCCIN_75 RU183 RU184 CU40
BY10 F23
C19 VCCIN_25 VCCIN_76 F24
VCCIN_26 VCCIN_77 RU182
C23 F27 ns
A23 VCCIN_27 VCCIN_78 F29
C27 VCCIN_28 VCCIN_79 G1
C29 VCCIN_29 VCCIN_80 G19
C CA36 VCCIN_30 VCCIN_81 G23 C
CA9 VCCIN_31 VCCIN_82 AB1
CB10 VCCIN_32 VCCIN_83 G27
CC11 VCCIN_33 VCCIN_84 G29
CC36 VCCIN_34 VCCIN_85 H19 VCCIN_VIDSCK_R RU185 电阻_0R_0201_1/20W_J
CC9 VCCIN_35 VCCIN_86 H23 VCCIN_VIDSCK 66
CD10 VCCIN_36 VCCIN_87 H27 VCCIN_VIDSOUT_R RU186 电阻_0R_0201_1/20W_J
VCCIN_37 VCCIN_88 VCCIN_VIDSOUT 66
CE11 H29
A24 VCCIN_38 VCCIN_89 J18 VCCIN_VIDALERT_N_R RU187 电阻_0R_0201_1/20W_J
CE34 VCCIN_39 VCCIN_90 J20 VCCIN_VIDALERT_N 66
CE35 VCCIN_40 VCCIN_91 J22
CF10 VCCIN_41 VCCIN_92 J23
CF33 VCCIN_42 VCCIN_93 AB13
CG11 VCCIN_43 VCCIN_94 J26
CG34 VCCIN_44 VCCIN_95 J28
CG35 VCCIN_45 VCCIN_96 K17
CH10 VCCIN_46 VCCIN_97 K19
J30 VCCIN_47 VCCIN_98 K21
CJ11 VCCIN_48 VCCIN_99 K23
A27 VCCIN_49 VCCIN_100 K24
CJ34 VCCIN_50 VCCIN_101 K27
VCCIN_51 VCCIN_102 M1
VCCIN_103 U1
VCCIN_VIDALERT_N_R H1 VCCIN_104
B VCCIN_VIDSCK_R H2 VIDALERT F17 VCC_VCCIN_SENSE_P B
VIDSCK VCCIN_SENSE VCC_VCCIN_SENSE_P 66
VCCIN_VIDSOUT_R H3 G17 VCC_VCCIN_SENSE_N VCC_VCCIN_SENSE_N 66
VIDSOUT VSSIN_SENSE
ICL_U_IP_EXT_WW20 ?
12 of 19
+VCCST +V1P0S_VCCST
SHU1
1 ns 1 2
2
PMR EMPTY
0603
A A
Page name:
ICL-U42(VCCIN)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 13 72
5 4 3 2 1
5 4 3 2 1
+VCCIN_AUX +V3P3A_PCH
UU1N ? ??
D 1.8V/28A Max
AH1
AW10 VCCIN_AUX_1
VCCIN_AUX_2
VCCPRIM_3P3_2
VCCPRIM_3P3_3
DF23
DG26
D
AY11 DG28
AY9 VCCIN_AUX_3 VCCPRIM_3P3_4
+VCCRTC VCCIN_AUX_4 +VCCPRIM_1P8
+VCCPRTC_3P3 BA10
BB9 VCCIN_AUX_5
CH1 VCCIN_AUX_6 DF15
SHU2 VCCIN_AUX_7 VCCPRIM_1P8_2
1 2 CK11 DF17
1
ns 2
CL10 VCCIN_AUX_8 VCCPRIM_1P8_3 DF18

0402 VCCIN_AUX_9 VCCPRIM_1P8_4
CM11 DF20 +VCCLDOSTD_OUT_0P85
CN1 VCCIN_AUX_10 VCCPRIM_1P8_5 DG17
+V1P8A VCCIN_AUX_11 VCCPRIM_1P8_6
+VCCPRIM_1P8 AJ1 DG18
CN10 VCCIN_AUX_12 VCCPRIM_1P8_7 DG20
SHU3 CP11 VCCIN_AUX_13 VCCPRIM_1P8_8 DF34
1 2 VCCIN_AUX_14 VCCPRIM_1P8_9
1
ns 2
CR10
0603 VCCIN_AUX_15 CU41
CT11 Co-lay
VCCIN_AUX_16 电容_2.2uF_0402_X5R_6.3 V_M
CU10
+V3P3A +V3P3A_PCH VCCIN_AUX_17 LU1
CV1 PLACE NEAR DW37 WITHIN 3MM FROM PACKAGE +VCCPRIM_1P8
CV11 VCCIN_AUX_18
VCCIN_AUX_19 +VCCA_CLKLDO_1P8 ns
SHU4 CW10 DW37 (internally) 电感120nH(0402, +/-5%)
1 2 VCCIN_AUX_20 VCCLDOSTD_0P85
1
ns 2
CY11
0805 DC1 VCCIN_AUX_21 DW15 RU190 电阻0R(0402-0.0625W-J)
AL1 VCCIN_AUX_22 VCCA_CLKLDO_1P8 +VCCDPHY_1P24
VCCIN_AUX_23 +VCCDSW_1P05
P13 DW32 (internally)
VCCIN_AUX_24 VCCDPHY_1P24 CU42
R12
VCCIN_AUX_25 电容_1uF_0201_X5R_6.3V_M RU191 电阻0R(0402-0.0625W-J)
T13 DD34 (internally)
U12 VCCIN_AUX_26 VCCDSW_1P05
+VCC1P05_OUT_FET RU221
C DC11
DE12
DF12
VCCIN_AUX_27
VCCIN_AUX_28
VCCIN_AUX_29
VCC1P05_1
VCC1P05_2
BY2
CB2
CC1
(internally) +VCC1P05_OUT_SFR
ns
电阻_100毫欧_0402_1/8W_F(±1%)
C
AM1 VCCIN_AUX_30 VCC1P05_3
VCCIN_AUX_31 +VCC1P05_OUT_PCH Co-lay
电容_22uF_0603_X5R_6.3V_M
电容_22uF_0603_X5R_6.3V_M
+V1P05A_BYPASS_R AN1 CD1
AT11 VCCIN_AUX_32 VCCPLL_2
电阻_100K_0201_1/20W_J
+VNN_BYPASS_R AT9 VCCIN_AUX_33 DG31

AU10 VCCIN_AUX_34 VCCPRIM_1P05_1 Stuffed LU1 RU190 RU191 RU221 CU43 CU44
电阻_100K_0201_1/20W_J
VCCIN_AUX_35 +V3P3A
AV9 DG29 LU1 -- NC 100mΩ
VCCIN_AUX_36 VCCPRIM_1P05_2 SHU5
1 2
RU192 VCCIN_AUX_VCCSENSE BF9 DF29 +VCCPRTC_3P3 1
ns 2
RU190 NC -- 0Ω NC
65 VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE BD9 VCCIN_AUX_VCCSENSE VCCPRIM_1P05_3 0402
RU193 65 VCCIN_AUX_VSSSENSE VCCIN_AUX_VSSSENSE DF31 CU45
VCCPRIM_1P05_4
电容_1uF_0201_X5R_6.3V_M
DG33
DJ15 VCCRTC +V3P3A_PCH
VCC_V1P05EXT_1P05 +VCCPGPPR
DE31
CY34 VCCDSW_3P3
VCC_VNNEXT_1P05 DF26 RU230
+VCCPRIM_1P8 VCCPGPPR
DC33
VCCPRIM_3P3_1 电阻_0R_0201_1/20W_J
CL38 GPPC_B0_CORE_VID_0 GPPC_B0_CORE_VID_0 65
+V3P3A_PCH GPP_B0/CORE_VID0 +VCCPRIM_1P8
DD35 CJ38 GPPC_B1_CORE_VID_1 GPPC_B1_CORE_VID_1 65
VCCPRIM_1P8_1 GPP_B1/CORE_VID1 CN38 GPPC_B2_VRALERT_N
DB34 GPP_B2/VRALERT_N RU231
VCCSPI ns
电阻_0R_0201_1/20W_J
ICL_U_IP_EXT_WW2014 of 19 ?
RU228 BC_PROCHOT_N
BC_PROCHOT_N 44,60
B +VCCPGPPR 电阻_0R_0201_1/20W_J B
电容_1uF_0201_X5R_6.3V_M
+V3P3A
CU171
RU220
电阻_20K_0201_1/20W_J
DU3
BC_PROCHOT_N CPU_PROCHOT_N
CPU_PROCHOT_N 8,38,66
LRB500V-40T1G
+VCCPRTC_3P3 RU219
+VCCPRIM_1P8 +VCCDPHY_1P24 +VCCDSW_1P05 +V3P3A_PCH ns
电阻_0R_0201_1/20W_J
电容_4.7uF_0402_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_100nF_0201_X5R_6.3 V_M(±20%)
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_100nF_0201_X5R_6.3 V_M(±20%)
CU46 CU47 CU48 CU49 CU50 CU53 CU54
CU52
CU51
Close to DW32 Close to DG33
Close to DF18 Close to DD34 Close to DF23
Close to DG26
A A
Page name:
ICL-U42(VCCIN_AUX/PCH PWR1)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 14 72
5 4 3 2 1
5 4 3 2 1
+VDDQ_CPU UU1M ??? +VDDQ_CPU
AA37 BP39
D AG36 VDDQ_1 VDDQ_31 BR37 D
AJ36 VDDQ_2 VDDQ_32 BT38
AL36 VDDQ_3 VDDQ_33 AC35
AL49 VDDQ_4 VDDQ_34 BU37
AN36 VDDQ_5 VDDQ_35 BU49
AP37 VDDQ_6 VDDQ_36 CA39
AR36 VDDQ_7 VDDQ_37 CB49
AR37 VDDQ_8 VDDQ_38 L38
AT36 VDDQ_9 VDDQ_39 L49
AT49 VDDQ_10 VDDQ_40 N36
AA49 VDDQ_11 VDDQ_41 T49
AV36 VDDQ_12 VDDQ_42 AC37
AW37 VDDQ_13 VDDQ_43 AD35
AY36 VDDQ_14 VDDQ_44 AD36
BA37 VDDQ_15 VDDQ_45 AE36
BA49 VDDQ_16 VDDQ_46 AF49
BB36 VDDQ_17 VDDQ_47
BD36 VDDQ_18 C33
BE37 VDDQ_19 RSVD_77
BF36 VDDQ_20 A33
BF37 VDDQ_21 RSVD_2 B33
AB36 VDDQ_22 RSVD_3
BF49 VDDQ_23 BG9
VDDQ_24 VCC1P8A_1 +VCC1P8A
BG36 BJ9
C VDDQ_25 VCC1P8A_2 C
BJ36 BM9
BL37 VDDQ_26 VCC1P8A_3 BW1
BM49 VDDQ_27 VCC1P8A_4 BW2
+V1P0S_VCCST VDDQ_28 VCC1P8A_5
BN37
BP38 VDDQ_29 R35
VDDQ_30 VCCSTG_OUT_3 +VCCFPGM
V34
+VCCSTG_IO VCCSTG_OUT_4
CB1 T34
VCCST VCCSTG_OUT_5 U35
BY1 VCCSTG_OUT_6 AB34
VCCSTG VCCSTG_OUT_7 W35
+VCCSTG_OUT_FUSE RSVD_74 +VCC1P05_OUT_SFR
AA35
RSVD_75 Y34 +VCC1P05_OUT_SFR
+VCCSTG_OUT_LGC RSVD_76
F33
G33 VCCSTG_OUT_1
VCCSTG_OUT_2
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
CD2
E5 VCCPLL_1
电容_1uF_0201_X5R_6.3V_M
VCCSTG_OUT_LGC CG38 CU56 CU57

VCCPLL_OC_1 +VCCSFR_OC
CG41 ns
VCCPLL_OC_2 CG42
CU55 VCCPLL_OC_3 +VCCIO_OUT
CG49 Close to CD2
ns VCCPLL_OC_4
13 of 19 AD7
VCCIO_OUT
B ICL_U_IP_EXT_WW20 ? B
VCCPLL 1x1uf
+V1P1U_VDDQ +VDDQ_CPU
SHU6
+VCCSTG_OUT_FUSE +VCCFPGM
1 2
1
ns 2
0805
SHU8
SHU7 1 2
1 2 1
ns 2
1
ns 2
0402
0805
CU58
+VCCSTG_TERM
+VCCSTG_OUT_LGC
电容_1uF_0201_X5R_6.3V_M
SHU9
1 2
1
ns 2
0402
A A
Page name:
ICL-U42(VCC/VDDQ)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 15 72
5 4 3 2 1
5 4 3 2 1
UU1P ???
UU1O ?? ?
UU1Q ???
BT3 CR37
A11 AF45 VSS_149
VSS_223 DJ33 F11
VSS_1
VSS_75 BT39 CR45 VSS_297
VSS_362
A46 AF47 VSS_150
VSS_224 DJ36 F31
VSS_2
VSS_76 BT41 CR49 VSS_298
VSS_363
BA45 AG1 VSS_151
VSS_225 DJ42 F45
VSS_3
VSS_77 BT42 CT37 VSS_299
VSS_364
BA47 AG11 VSS_152
VSS_226 DK3 F47
VSS_4
VSS_365
BB11 AG3 VSS_153
VSS_227 DK4 F8
D VSS_5
VSS_366 D
BB3 AG38 VSS_154
VSS_228 DK49 G21
VSS_6
VSS_80 BU45 CT9 VSS_302
VSS_367
BB7 AG39 VSS_155
VSS_229 DK6 G24
VSS_7
VSS_81 BU47 CU45 VSS_303
VSS_368
BC37 AG41 VSS_156
VSS_230 DK8 G3
VSS_8
VSS_82 BV1 CU47 VSS_304
VSS_369
BD3 A31 VSS_157
VSS_231 DL10 G31
VSS_9
VSS_83 BV11 CU49 VSS_305
VSS_370
BD38 AG42 VSS_158
VSS_232 DL13 G36
VSS_10
VSS_84 BV2 CV3 VSS_306
VSS_371
BD39 AG43 VSS_159
VSS_233 DL44 G49
VSS_11
VSS_372
BD41 AG5 VSS_160
VSS_234 DL47 G5
VSS_12
VSS_373
A48 AG9 VSS_161
VSS_235 DM47 H17
VSS_13
VSS_87 BW3 CV5 VSS_309
VSS_374
BD42 AH2 VSS_162
VSS_236 DN15 H21
VSS_14
VSS_88 BW37 CV9 VSS_310
VSS_375
BD43 AH37 VSS_163
VSS_237 DN19 H24
VSS_15
VSS_89 BW5 CY41 VSS_311
VSS_376
BD45 AH45 VSS_164
VSS_238 DN24 H31
VSS_16
VSS_377
BD49 AH49 VSS_165
VSS_239 DN31 H33
VSS_17
VSS_378
BD5 AJ2 VSS_166
VSS_240 DN36 H36
VSS_18
VSS_92 BY37 CY9 VSS_314
VSS_379
BD6 AJ3 VSS_167
VSS_241 DN42 H45
VSS_19
VSS_93 BY45 D13 VSS_315
VSS_380
BD7 A34 VSS_168
VSS_242 DP45 H49
VSS_20
VSS_94 BY49 D17 VSS_316
VSS_381
BE1 AK37 VSS_169
VSS_243 DR49 J10
VSS_21
VSS_95 C11 D31 VSS_317
VSS_382
BE2 AL2 VSS_170
VSS_244 DT1 J13
VSS_22
VSS_96 C13 D44 VSS_318
VSS_383
BF3 AL45 VSS_171
VSS_245 DT10 J16
VSS_23
VSS_97 C14 D49 VSS_319
VSS_384
A49 AL47 VSS_172
VSS_246 DT15 J36
VSS_24
VSS_98 C17 DA10 VSS_320
VSS_385
BF45 AL6 VSS_173
VSS_247 DT20 J6
VSS_25
VSS_99 C21 DA33 VSS_321
VSS_386
BF47 AM2 VSS_174
VSS_248 DT27 K11
VSS_26
VSS_100 C24 DA9 VSS_322
VSS_387
BF7 AM37 VSS_175
VSS_249 DT3 K33
VSS_27
VSS_101 C31 DB32 VSS_323
VSS_388
BG3 AN2 VSS_176
VSS_250 DT32 K8
VSS_28
VSS_102 C34 DB35 VSS_324
VSS_389
BG41 AN38 VSS_177
VSS_251 DT37 L36
C VSS_29
VSS_103 C39 DB38 VSS_325
VSS_390 C
BG7 AN39 VSS_178
VSS_252 DT42 L39
VSS_30
VSS_104 C48 DB45 VSS_326
VSS_391
BH37 A36 VSS_179
VSS_253 DT49 L41
VSS_31
VSS_105 C49 DB47 VSS_327
VSS_392
BJ1 AN41 VSS_180
VSS_254 DT6 L42
VSS_32
VSS_106 C6 DB49 VSS_328
VSS_393
BJ2 AN42 VSS_181
VSS_255 DT7 L43
VSS_33
VSS_107 CA3 DC3 VSS_329
VSS_394
BJ3 AN43 VSS_182
VSS_256 DT8 L45
VSS_34
VSS_395
AA45 AN45 VSS_183
VSS_257 DU1 L47
VSS_35
VSS_396
BJ41 AN49 VSS_184
VSS_258 DU10 M10
VSS_36
VSS_397
BJ43 AN6 VSS_185
VSS_259 DU15 M3
VSS_37
VSS_111 CA43 DD37 VSS_333
VSS_398
BJ45 AR1 VSS_186
VSS_260 DU2 M36
VSS_38
VSS_112 CA7 DD42 VSS_334
VSS_399
BJ49 AR11 VSS_187
VSS_261 DU20 M5
VSS_39
VSS_113 CB37 DE10 VSS_335
VSS_400
BJ7 AR2 VSS_188
VSS_262 DU27 N45
VSS_40
VSS_401
BM11 AR3 VSS_189
VSS_263 DU32 N49
VSS_41
VSS_402
BM3 A39 VSS_190
VSS_264 DU37 P11
VSS_42
VSS_116 CC3 DE18 VSS_338
VSS_403
BM45 AR7 VSS_191
VSS_265 DU48 P41
VSS_43
VSS_117 CC7 DE20 VSS_339
VSS_404
BM47 AR9 VSS_192
VSS_266 DU49 P8
VSS_44
VSS_118 CE37 DE22 VSS_340
VSS_405
BM5 AT3 VSS_193
VSS_267 DU7 R3
VSS_45
VSS_406
AA47 AT45 VSS_194
VSS_268 DV2 R37
VSS_46
VSS_407
BM6 AT47 VSS_195
VSS_269 DV44 T11
VSS_47
VSS_408
BM7 AT5 VSS_196
VSS_270 DV48 T36
VSS_48
VSS_122 CG37 DE29 VSS_344
VSS_409
BP1 AT6 VSS_197
VSS_271 DV8 T41
VSS_49
VSS_410
BP2 AT7 VSS_198
VSS_272 DW1 T43
VSS_50
VSS_411
BP3 AU37 VSS_199
VSS_273 DW10 T45
VSS_51
VSS_412
BP43 AV11 VSS_200
VSS_274 DW2 T47
VSS_52
VSS_126 CG47 DF13 VSS_348
VSS_413
B BP7 A42 VSS_201
VSS_275 DW20 U3 B
VSS_53
VSS_127 CG9 DF22 VSS_349
VSS_414
BR45 AV3 VSS_202
VSS_276 DW27 U37
VSS_54
VSS_128 CH3 DF28 VSS_350
VSS_415
BR49 AV38 VSS_203
VSS_277 DW44 U5
VSS_55
VSS_129 CH5 DF33 VSS_351
VSS_416
AB11 AV39 VSS_204
VSS_278 DW46 V11
VSS_56
VSS_130 CJ37 DF35 VSS_352
VSS_417
AB3 AV41 VSS_205
VSS_279 DW48 V36
VSS_57
VSS_131 CJ42 DF39 VSS_353
VSS_418
AB38 AV42 VSS_206
VSS_280 DW49 V45
VSS_58
VSS_132 CJ9 DG10 VSS_354
VSS_419
AB39 AV43 VSS_207
VSS_281 DW7 V49
VSS_59
VSS_133 CK45 DG12 VSS_355
VSS_420
AB41 AV45 VSS_208
VSS_282 E11 V9
VSS_60
VSS_421
A17 AV49 VSS_209
VSS_283 E34 W37
VSS_61
VSS_422
AB42 AV7 VSS_210
VSS_284 E36 Y36
VSS_62
VSS_136 CL37 DG22 VSS_358
VSS_423
AB43 AY3 VSS_211
VSS_285 E39 Y38
VSS_63
VSS_424
AB5 A44 VSS_212
VSS_286 E42 Y43
VSS_64
VSS_425
AB6 AY7 VSS_213
VSS_287 E6 Y9
VSS_65
VSS_139 CM45 DG6 VSS_361
VSS_426
AC45 B17 VSS_214
VSS_288 DE15
VSS_66
VSS_140 CM47 DH1 VSS_427
AC49 B2 VSS_215
VSS_289
VSS_67
VSS_141 CM9 DH3
AD10 B21 VSS_216
VSS_290 ?
VSS_68
VSS_142 CN3 DH45 17 of 19
AD11 B24 VSS_217
VSS_291
VSS_69
VSS_143 CN37 DH5 ICL_U_IP_EXT_WW20
AD34 B3 VSS_218
VSS_292
VSS_70
VSS_144 CN39 DJ19
AD37 B31 VSS_219
VSS_293
VSS_71
VSS_145 CN5 DJ21
A3 B48 VSS_220
VSS_294
VSS_72
VSS_146 CP9 DJ27
AE6 BA1 VSS_221
VSS_295
VSS_73
VSS_147 CR32 DJ31
AF37 BA2 VSS_222
VSS_296
VSS_74
VSS_148
16 of 19 ?
15 of 19 ?
ICL_U_IP_EXT_WW20
A ICL_U_IP_EXT_WW20 A
Page name:
ICL-U42(VSS)
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 16 72
5 4 3 2 1
5 4 3 2 1
UU1S ???
RU194 电阻_1K_0201_1/20W_J CFG0 AG6 A47 1 ns

ns CFG_0 RSVD_TP_1 TPU25 20MIL
RU195 电阻_1K_0201_1/20W_J CFG1 AE7 B47 1 ns
ns CFG_1 RSVD_TP_2 TPU26 20MIL
RU203 电阻_1K_0201_1/20W_J CFG2 AG7
RU196 ns 电阻_1K_0201_1/20W_J CFG3 AD9 CFG_2 C1 1 ns
ns CFG_3 RSVD_57 TPU28 20MIL
RU204 电阻_1K_0201_1/20W_J CFG4 AE9 E1 1 ns
CFG_4 RSVD_58 TPU27 20MIL UU1R ???
RU197 电阻_1K_0201_1/20W_J CFG5 AB9
D RU205 ns 电阻_1K_0201_1/20W_J CFG6 AJ6 CFG_5 CT32 N34 DA11 D
RU200 ns 电阻_1K_0201_1/20W_J CFG7 AB7 CFG_6 RSVD_TP_10 CV32 AK10 RSVD_TP_27 RSVD_TP_35 CL32
RU206 ns 电阻_1K_0201_1/20W_J CFG8 V10 CFG_7 RSVD_TP_11 BT36 RSVD_TP_28 RSVD_TP_36 CN32
RU201 ns 电阻_1K_0201_1/20W_J CFG9 AJ5 CFG_8 G15 AH10 RSVD_7 RSVD_TP_37 CY35
RU198 ns 电阻_1K_0201_1/20W_J CFG10 Y10 CFG_9 RSVD_79 F15 BC10 RSVD_TP_29 RSVD_32 DB37
RU207 ns 电阻_1K_0201_1/20W_J CFG11 AJ7 CFG_10 RSVD_80 CH33 RSVD_TP_30 RSVD_33 DF37
RU199 ns 电阻_1K_0201_1/20W_J CFG12 AB10 CFG_11 BW11 RSVD_TP_31 RSVD_34
RU208 ns 电阻_1K_0201_1/20W_J CFG13 AL7 CFG_12 RSVD_TP_5 CA11 CJ32 BF11
RU202 ns 电阻_1K_0201_1/20W_J CFG14 AL9 CFG_13 RSVD_TP_6 AM10 RSVD_12 IST_TP_0 BD11
RU209 ns 电阻_1K_0201_1/20W_J CFG15 AJ9 CFG_14 C16 BH10 RSVD_TP_32 IST_TP_1 BE10
ns CFG_15 VSS_428 A16 J34 RSVD_TP_33 IST_TRIG_0 BF10
MIPI60_CFG_STB0_DN V6 VSS_429 RSVD_TP_34 IST_TRIG_1
MIPI60_CFG_STB0_DP CFG_16
20MIL TPU29 ns 1 V7
CFG_17 RSVD_55
C2 Y11
RSVD_9 PCH_IST_TP_0
CW33
A4 ns 1 L34 CY32
RSVD_56 20MIL TPU30 RSVD_10 PCH_IST_TP_1
MIPI60_CFG_STB1_DN Y6
MIPI60_CFG_STB1_DP CFG_18
20MIL TPU31 ns 1 Y7
CFG_19 RSVD_65
DP5 AJ11
RSVD_17 RSVD_27
CY37
RU210 DR5 CG32 CV37
CFG_RCOMP AD6 RSVD_66 RSVD_21 RSVD_28
CFG_RCOMP D14
电阻_49.9R_0201_1/20W_F RSVD_59
ns 1 MBP0_N T9 E16 CK33
20MIL TPU73 BPM_N_0 RSVD_60 RSVD_22
ns 1 MBP1_N T7 BP41 G34
20MIL TPU74 BPM_N_1 RSVD_20 RSVD_35
MBP2_N T10 DV6 AL11 H34
MBP3_N T6 BPM_N_2 RSVD_TP_13 DW6 BG11 RSVD_23 RSVD_46 DJ34
BPM_N_3 RSVD_TP_14 AN11 RSVD_24 RSVD_48 DK31
C RSVD_16 RSVD_49 C
BJ11 DP2 M13 DK15
BL10 RSVD_62 RSVD_TP_24 DP1 M34 RSVD_18 RSVD_50 CP3
RSVD_63 RSVD_TP_25 RSVD_19 RSVD_51 CP5
RSVD_52
20MIL TPU32 ns 1 AV1
RSVD_TP_17 RSVD_TP_15
DW4
RSVD_53
AN9
DV4 AN7
RSVD_TP_16 RSVD_54
20MIL TPU33 ns 1 AT2
RSVD_TP_18 RSVD_36
AF10
AT1 CM33 1 ns DU42 AE11
RSVD_TP_20 TP_3 TPU34 20MIL RSVD_42 RSVD_37
AU1 DB10 1 ns DW42 H5
RSVD_TP_19 TP_4 TPU35 20MIL RSVD_43 RSVD_38
AU2 D33 D1
RSVD_TP_21 R1 L13 RSVD_44 RSVD_39 DJ40
AV2 RSVD_TP_12 K13 RSVD_45 RSVD_40 DK40
RSVD_TP_22 DW3 1 ns RSVD_47 RSVD_41
RSVD_TP_7 TPU36 20MIL
20MIL TPU37 ns 1 DP3
RSVD_67 RSVD_TP_8
DV3 1 ns
TPU38 20MIL
20MIL TPU39 ns 1 DT2
RSVD_68 ICL_U_IP_EXT_WW20 ?
DH49
AR10 RSVD_TP_9
AP10 RSVD_69 DL8
BP36 RSVD_71 RSVD_TP_23
BM36 RSVD_70 DW47
RSVD_72 TP_1 DV47
J15 TP_2 DU47
K15 VSS_430 VSS_432
VSS_431 +VCCIO_OUT
P10
SKTOCC_N RSVD_TP_26
B 20MIL TPU40 ns 1 C5
SKTOCC_N B
U42_L_U43E_Z D4
A5 RSVD_78 CFG0 RU233 电阻_1K_0201_1/20W_J
RSVD_64
ICL_U_IP_EXT_WW20
19 of 19 ? CFG1 RU234 电阻_1K_0201_1/20W_J
RU211 CFG8 RU235 电阻_1K_0201_1/20W_J

ns 电阻_10K_0201_1/20W_J
CFG9 RU236 电阻_1K_0201_1/20W_J
CFG10 RU237 电阻_1K_0201_1/20W_J
CFG12 RU238 电阻_1K_0201_1/20W_J
CFG13 RU239 电阻_1K_0201_1/20W_J
+VCCIO_OUT +VCCIO_OUT CFG3 RU240 电阻_1K_0201_1/20W_J

电阻_10K_0201_1/20W_J
电阻_10K_0201_1/20W_J
电阻_10K_0201_1/20W_J
电阻_10K_0201_1/20W_J
RU212
MIPI60_CFG_STB0_DN
电阻_51R_0201_1/20W_J
RU213 RU214 RU215 RU216
RU217
A MIPI60_CFG_STB1_DN A
电阻_51R_0201_1/20W_J
Page name:
MBP0_N MBP2_N
ICL-U42(CFG)
MBP1_N MBP3_N Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 17 72
5 4 3 2 1
A
B
C
D
5
5
+VCCIN
电容_1uF_0201_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M
+V1P0S_VCCST
CU97
电容_1uF_0201_X5R_6.3V_M
CU83
CU69
CU67
CU59
ns
VCCST 1x1uf
CU98
CU84
CU70
CU68
CU60
电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

电容_1uF_0201_X5R_6.3V_M
+VCCSTG_IO
CU85
CU71
CU61
CU99
Place as close as possible to CP33 and CT33
Place as close as possible to each U1 and AB1

电容_1uF_0201_X5R_6.3V_M
ns
VCCSTG 1x1uf
CU86
CU72
CU62
CU100
4
4
PLACE THESE CAPS UNDERNEATH BGA AREA
PLACE CLOSE TO PACKAGE ON PRIMARY SIDE
CU87
CU73
电容_10uF_0402_X5R_6.3V_M
CU63
+VCC1P8A
CU101
CU88
CU74
电容_10uF_0402_X5R_6.3V_M
CU64
电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M
CU102
电容_12pF_0201_COG_25V_J
CU89
CU75
电容_10uF_0402_X5R_6.3V_M
ns
VCC1P8A 1x10uf
CU65
CU103
RF request
电容_100pF_0201_C0G_25V_J
CU90
CU76
CU66
电容_15pF_0201_C0G_25V_J
CU91
CU77
CU104
RF request
ns
电容_100pF_0201_C0G_25V_J
CU162
3
3
电容_15pF_0201_C0G_25V_J
CU92
CU78
CU105
ns
CU163
电容_15pF_0201_C0G_25V_J
CU93
CU79
ns
电容_1uF_0201_X5R_6.3V_M
CU164
CU94
CU80
+VCCSFR_OC
CU106
ns
ns
电容_1uF_0201_X5R_6.3V_M
Reserve，
ns
CU95
CU81
CU107
ns
ns
VCCPLL_OC 1x1uf
CU96
CU82
intel check：Reserve 15pF caps for RF request - 02/26
Positive and negative folding
2
2
PDG:4 x 1uF
3x 47uF
2 x 10uF
10x 22uF
+VCCIN
A4
Size:
Date:
Page name:
Name:
Project
1
1
Monday, July 15, 2019

NB8511
Sheet:
18
of
ICL-U42(DECOUPLING1)
72
REV:
V1.0
A
B
C
D
A
B
C
D
5
5
+VDDQ_CPU
+VCCIN_AUX
电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M
CU152
CU126
CU114
CU142
CU108
CU153
CU127
CU115
CU143
CU109
CU154
CU128
CU116
CU144
CU110
4
4
Place after the TOP DDR signal breakout
CU155
CU129
CU117
CU145
CU111
PLACE CLOSE TO PACKAGE ON PRIMARY SIDE

CU156
CU130
CU118
CU146
CU112
RF request
CU157
CU131
CU147
电容_10uF_0402_X5R_6.3V_M 电容_100pF_0201_C0G_25V_J
ns
CU119
CU113
CU158
CU148
CU132
电容_10uF_0402_X5R_6.3V_M
ns
ns
CU120
CU165
CU159
CU133
CU149
电容_10uF_0402_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M
ns
3
3
ns
CU121
CU166
CU134
CU160
电容_10uF_0402_X5R_6.3V_M
CU150
RF request
电容_10uF_0402_X5R_6.3V_M
ns
电容_100pF_0201_C0G_25V_J
ns
CU122
CU167
CU135
Place as close as possible to BGAs (placeholder)
CU161
电容_10uF_0402_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M
CU151
CU123
CU136
电容_10uF_0402_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M
CU124
CU137
电容_10uF_0402_X5R_6.3V_M
电容_22uF_0603_X5R_6.3V_M
PDG:6 x 1uF
2x 22uF
2 x 10uF
+VDDQ
CU125
CU138
Reserve，
电容_22uF_0603_X5R_6.3V_M
CU139
2
2
电容_22uF_0603_X5R_6.3V_M
Positive and negative folding
CU140
电容_22uF_0603_X5R_6.3V_M
2x 22uF
PDG:25 x 10uF
CU141
+VCCIN_AUX
A4
Size:
Date:
Page name:
Name:
Project
1
1

NB8511
Sheet:
19
of
ICL-U42(DECOUPLING2)
72
REV:
V1.0
A
B
C
D
5 4 3 2 1
D D
C C
B B
A A
Page name:
BLANK
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 20 72
5 4 3 2 1
CHA-1
UD1B
K4F6E3S4HM-MGCJ
+V1P1U_VDDQ +V1P1U_VDDQ
NB_BGA200_15X10X1D2_0D65
U8 A3
VDD2_1 VSS_1
电阻_240R_0201_1/20W_F
电阻_240R_0201_1/20W_F
CD2 U5 Y8
VDD2_2 VSS_2
电容_100nF_0201_X5R_6.3 V_M(±20%) R12 Y5
VDD2_3 VSS_3
UD1A
RD3 RD4 R8 Y1
K4F6E3S4HM-MGCJ VDD2_4 VSS_4
NB_BGA200_15X10X1D2_0D65
R5 W11
VDD2_5 VSS_5
G11 B9 M_A_DQ_3[7]
DNU_G11 DQ15_A M_A_DQ_3[7] 5 R1 W9
VDD2_6 VSS_6
ZQ1_CHA_0 A8 C9 M_A_DQ_3[6]
NC_A8 DQ14_A M_A_DQ_3[6] 5 N12 W4
VDD2_7 VSS_7
ZQ0_CHA_0 A5 E9 M_A_DQ_3[5]
ZQ_A DQ13_A M_A_DQ_3[5] 5 N10 W2
VDD2_8 VSS_8
5,21 M_A_LP4_CAA5 M_A_LP4_CAA5 J11 F9 M_A_DQ_3[3]
CA5_A DQ12_A M_A_DQ_3[3] 5 N3 V12
VDD2_9 VSS_9
5,21 M_A_LP4_CAA4 M_A_LP4_CAA4 H11 F11 M_A_DQ_3[4] BYTE3
CA4_A DQ11_A M_A_DQ_3[4] 5 N1 V8
VDD2_10 VSS_10
5,21 M_A_LP4_CAA3 M_A_LP4_CAA3 H10 E11 M_A_DQ_3[1]
CA3_A DQ10_A M_A_DQ_3[1] 5 K12 V5
VDD2_11 VSS_11
+V1P1U_VDDQ 5,21 M_A_LP4_CAA2 M_A_LP4_CAA2 H9 C11 M_A_DQ_3[0]
CA2_A DQ9_A M_A_DQ_3[0] 5 K10 V1
VDD2_12 VSS_12
M_A_LP4_CAA1 J2 B11 M_A_DQ_3[2]
5,21 M_A_LP4_CAA1 CA1_A DQ8_A M_A_DQ_3[2] 5 K3 T12
VDD2_13 VSS_13
5,21 M_A_LP4_CAA0 M_A_LP4_CAA0 H2 B4 M_A_DQ_2[3]
CA0_A DQ7_A M_A_DQ_2[3] 5 K1 T10
VDD2_14 VSS_14
G2 C4 M_A_DQ_2[7]
ODT_CA_A DQ6_A M_A_DQ_2[7] 5 H12 T8
VDD2_15 VSS_15
K5 E4 M_A_DQ_2[5]
DNU_K5 DQ5_A M_A_DQ_2[5] 5 H8 T5
VDD2_16 VSS_16
M_A_LP4_CS_A_R1_N H3 F4 M_A_DQ_2[4]
5,21 M_A_LP4_CS_A_R1_N NC_H3 DQ4_A M_A_DQ_2[4] 5 H5 T3
BYTE2 VDD2_17 VSS_17
M_A_LP4_CS_A_R0_N H4 F2 M_A_DQ_2[0]
5,21 M_A_LP4_CS_A_R0_N CS_A DQ3_A M_A_DQ_2[0] 5 H1 T1
VDD2_18 VSS_18
K8 E2 M_A_DQ_2[2]
DNU_K8 DQ2_A M_A_DQ_2[2] 5 F8 P12
VDD2_19 VSS_19
M_A_LP4_CKE_A1 J5 C2 M_A_DQ_2[1]
5,21 M_A_LP4_CKE_A1 NC_J5 DQ1_A M_A_DQ_2[1] 5 F5 P10
VDD2_20 VSS_20
M_A_LP4_CKE_A0 J4 B2 M_A_DQ_2[6]
5,21 M_A_LP4_CKE_A0 CKE_A DQ0_A M_A_DQ_2[6] 5 AB9 P3
VDD2_21 VSS_21
M_A_CK_DDR0_DN J9 D10 M_A_DQS_3_DP
5,21 M_A_CK_DDR0_DN CK_C_A DQS1_T_A M_A_DQS_3_DP 5 AB4 P1
VDD2_22 VSS_22
M_A_CK_DDR0_DP J8 E10 M_A_DQS_3_DN
5,21 M_A_CK_DDR0_DP CK_T_A DQS1_C_A M_A_DQS_3_DN 5 A9 N11
VDD2_23 VSS_23
C10 D3 M_A_DQS_2_DP +V1P8U
DMI1_A DQS0_T_A M_A_DQS_2_DP 5 A4 N9
VDD2_24 VSS_24
C3 E3 M_A_DQS_2_DN
DMI0_A DQS0_C_A M_A_DQS_2_DN 5 U12 N4
VDD1_1 VSS_25
5,21 M_A_LP4_CAA5 M_A_LP4_CAA5 P11 AA9 M_A_DQ_1[2]
CA5_B DQ15_B M_A_DQ_1[2] 5 CD3 U1 N2
VDD1_2 VSS_26
M_A_LP4_CAA4 R11 Y9 M_A_DQ_1[0]
5,21 M_A_LP4_CAA4 CA4_B DQ14_B M_A_DQ_1[0] 5 电容_100nF_0201_X5R_6.3 V_M(±20%) T9 K11
VDD1_3 VSS_27
M_A_LP4_CAA3 R10 V9 M_A_DQ_1[1]
5,21 M_A_LP4_CAA3 CA3_B DQ13_B M_A_DQ_1[1] 5 T4 K9
VDD1_4 VSS_28
5,21 M_A_LP4_CAA2 M_A_LP4_CAA2 R9 U9 M_A_DQ_1[4]
CA2_B DQ12_B M_A_DQ_1[4] 5 G9 K4
+V1P1U_VDDQ VDD1_5 VSS_29
5,21 M_A_LP4_CAA1 M_A_LP4_CAA1 P2 U11 M_A_DQ_1[3] BYTE1
CA1_B DQ11_B M_A_DQ_1[3] 5 G4 K2
VDD1_6 VSS_30
5,21 M_A_LP4_CAA0 M_A_LP4_CAA0 R2 V11 M_A_DQ_1[5]
CA0_B DQ10_B M_A_DQ_1[5] 5 F12 J12
VDD1_7 VSS_31
T2 Y11 M_A_DQ_1[6] +VDDQ_LP4X
ODT_CA_B DQ9_B M_A_DQ_1[6] 5 F1 J10
VDD1_8 VSS_32
N5 AA11 M_A_DQ_1[7]
DNU_N5 DQ8_B M_A_DQ_1[7] 5 W12 J3
VDDQ_1 VSS_33
M_A_LP4_CS_A_R1_N R3 AA4 M_A_DQ_0[2]
5,21 M_A_LP4_CS_A_R1_N NC_R3 DQ7_B M_A_DQ_0[2] 5 CD4 W8 J1
VDDQ_2 VSS_34
M_A_LP4_CS_A_R0_N R4 Y4 M_A_DQ_0[0]
5,21 M_A_LP4_CS_A_R0_N CS_B DQ6_B M_A_DQ_0[0] 5 电容_100nF_0201_X5R_6.3 V_M(±20%) W5 G12
VDDQ_3 VSS_35
N8 V4 M_A_DQ_0[1]
DNU_N8 DQ5_B M_A_DQ_0[1] 5 W1 G10
VDDQ_4 VSS_36
M_A_LP4_CKE_A1 P5 U4 M_A_DQ_0[6]
5,21 M_A_LP4_CKE_A1 NC_P5 DQ4_B M_A_DQ_0[6] 5 U10 G8
BYTE0 VDDQ_5 VSS_37
M_A_LP4_CKE_A0 P4 U2 M_A_DQ_0[7]
5,21 M_A_LP4_CKE_A0 CKE_B DQ3_B M_A_DQ_0[7] 5 U3 G5
VDDQ_6 VSS_38
M_A_CK_DDR0_DN P9 V2 M_A_DQ_0[3]
5,21 M_A_CK_DDR0_DN CK_C_B DQ2_B M_A_DQ_0[3] 5 F10 G3
VDDQ_7 VSS_39
M_A_CK_DDR0_DP P8 Y2 M_A_DQ_0[5]
5,21 M_A_CK_DDR0_DP CK_T_B DQ1_B M_A_DQ_0[5] 5 F3 G1
VDDQ_8 VSS_40
Y10 AA2 M_A_DQ_0[4]
DMI1_B DQ0_B M_A_DQ_0[4] 5 D12 E12
VDDQ_9 VSS_41
Y3 V10 M_A_DQS_1_DN
DMI0_B DQS1_C_B M_A_DQS_1_DN 5 D8 E8
VDDQ_10 VSS_42
T11 W10 M_A_DQS_1_DP
5,22,23,24 DRAM_RESET_N_R RESET_N DQS1_T_B M_A_DQS_1_DP 5 D5 E5
VDDQ_11 VSS_43
A1 V3 M_A_DQS_0_DN
DNU_A1 DQS0_C_B M_A_DQS_0_DN 5 D1 E1
VDDQ_12 VSS_44
A2 W3 M_A_DQS_0_DP
DNU_A2 DQS0_T_B M_A_DQS_0_DP 5 B10 D11
CD5 VDDQ_13 VSS_45
A11 AA1
DNU_A11 DNU_AA1 B8 D9
电容_100nF_0201_X5R_6.3 V_M(±20%) ns VDDQ_14 VSS_46
A12 AA12
DNU_A12 DNU_AA12 B5 D4
VDDQ_15 VSS_47
B1 AB1
DNU_B1 DNU_AB1 B3 D2
VDDQ_16 VSS_48
B12 AB2
DNU_B12 DNU_AB2 AA10 C12
VDDQ_17 VSS_49
AB11
DNU_AB11 AA8 C8
VDDQ_18 VSS_50
AB12
DNU_AB12 AA5 C5
VDDQ_19 VSS_51
AA3 C1
VDDQ_20 VSS_52
AB10
VSS_53
AB8
VSS_54
AB5
VSS_55
AB3
VSS_56
A10
VSS_57
Y12
VSS_58
Page name:
LPDDR4 CH-A_1
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 21 72
CHA-2
UD2B
+V1P1U_VDDQ K4F6E3S4HM-MGCJ
NB_BGA200_15X10X1D2_0D65
U8 A3
+V1P1U_VDDQ VDD2_1 VSS_1
CD6 U5 Y8
VDD2_2 VSS_2
电容_100nF_0201_X5R_6.3 V_M(±20%) R12 Y5
VDD2_3 VSS_3
电阻_240R_0201_1/20W_F
电阻_240R_0201_1/20W_F
R8 Y1
VDD2_4 VSS_4
R5 W11
UD2A VDD2_5 VSS_5
RD5 RD6 K4F6E3S4HM-MGCJ
R1 W9
NB_BGA200_15X10X1D2_0D65 VDD2_6 VSS_6
N12 W4
G11 B9 M_A_DQ_7[7] VDD2_7 VSS_7
DNU_G11 DQ15_A M_A_DQ_7[7] 5
N10 W2
ZQ1_CHA_1 A8 C9 M_A_DQ_7[0] VDD2_8 VSS_8
NC_A8 DQ14_A M_A_DQ_7[0] 5
N3 V12
ZQ0_CHA_1 A5 E9 M_A_DQ_7[1] VDD2_9 VSS_9
ZQ_A DQ13_A M_A_DQ_7[1] 5
N1 V8
5,22 M_A_LP4_CAB5 M_A_LP4_CAB5 J11 F9 M_A_DQ_7[3] VDD2_10 VSS_10
CA5_A DQ12_A M_A_DQ_7[3] 5
BYTE7 K12 V5
5,22 M_A_LP4_CAB4 M_A_LP4_CAB4 H11 F11 M_A_DQ_7[4] VDD2_11 VSS_11
CA4_A DQ11_A M_A_DQ_7[4] 5
K10 V1
5,22 M_A_LP4_CAB3 M_A_LP4_CAB3 H10 E11 M_A_DQ_7[5] VDD2_12 VSS_12
CA3_A DQ10_A M_A_DQ_7[5] 5
+V1P1U_VDDQ K3 T12
M_A_LP4_CAB2 H9 C11 M_A_DQ_7[6] VDD2_13 VSS_13
5,22 M_A_LP4_CAB2 CA2_A DQ9_A M_A_DQ_7[6] 5
K1 T10
5,22 M_A_LP4_CAB1 M_A_LP4_CAB1 J2 B11 M_A_DQ_7[2] VDD2_14 VSS_14
CA1_A DQ8_A M_A_DQ_7[2] 5
H12 T8
5,22 M_A_LP4_CAB0 M_A_LP4_CAB0 H2 B4 M_A_DQ_6[7] VDD2_15 VSS_15
CA0_A DQ7_A M_A_DQ_6[7] 5
H8 T5
G2 C4 M_A_DQ_6[6] VDD2_16 VSS_16
ODT_CA_A DQ6_A M_A_DQ_6[6] 5
H5 T3
K5 E4 M_A_DQ_6[5] VDD2_17 VSS_17
DNU_K5 DQ5_A M_A_DQ_6[5] 5
H1 T1
M_A_LP4_CS_B_R1_N H3 F4 M_A_DQ_6[4] VDD2_18 VSS_18
5,22 M_A_LP4_CS_B_R1_N NC_H3 DQ4_A M_A_DQ_6[4] 5
BYTE6 F8 P12
5,22 M_A_LP4_CS_B_R0_N M_A_LP4_CS_B_R0_N H4 F2 M_A_DQ_6[0] VDD2_19 VSS_19
CS_A DQ3_A M_A_DQ_6[0] 5
F5 P10
K8 E2 M_A_DQ_6[2] VDD2_20 VSS_20
DNU_K8 DQ2_A M_A_DQ_6[2] 5
AB9 P3
M_A_LP4_CKE_B1 J5 C2 M_A_DQ_6[1] VDD2_21 VSS_21
5,22 M_A_LP4_CKE_B1 NC_J5 DQ1_A M_A_DQ_6[1] 5
AB4 P1
M_A_LP4_CKE_B0 J4 B2 M_A_DQ_6[3] VDD2_22 VSS_22
5,22 M_A_LP4_CKE_B0 CKE_A DQ0_A M_A_DQ_6[3] 5
A9 N11
M_A_CK_DDR1_DN J9 D10 M_A_DQS_7_DP VDD2_23 VSS_23
5,22 M_A_CK_DDR1_DN CK_C_A DQS1_T_A M_A_DQS_7_DP 5 +V1P8U
A4 N9
M_A_CK_DDR1_DP J8 E10 M_A_DQS_7_DN VDD2_24 VSS_24
5,22 M_A_CK_DDR1_DP CK_T_A DQS1_C_A M_A_DQS_7_DN 5
U12 N4
C10 D3 M_A_DQS_6_DP VDD1_1 VSS_25
DMI1_A DQS0_T_A M_A_DQS_6_DP 5
CD7 U1 N2
C3 E3 M_A_DQS_6_DN VDD1_2 VSS_26
DMI0_A DQS0_C_A M_A_DQS_6_DN 5
电容_100nF_0201_X5R_6.3 V_M(±20%) T9 K11
5,22 M_A_LP4_CAB5 M_A_LP4_CAB5 P11 AA9 M_A_DQ_5[2] VDD1_3 VSS_27
CA5_B DQ15_B M_A_DQ_5[2] 5
T4 K9
M_A_LP4_CAB4 R11 Y9 M_A_DQ_5[0] VDD1_4 VSS_28
5,22 M_A_LP4_CAB4 CA4_B DQ14_B M_A_DQ_5[0] 5
G9 K4
5,22 M_A_LP4_CAB3 M_A_LP4_CAB3 R10 V9 M_A_DQ_5[4] VDD1_5 VSS_29
CA3_B DQ13_B M_A_DQ_5[4] 5
G4 K2
5,22 M_A_LP4_CAB2 M_A_LP4_CAB2 R9 U9 M_A_DQ_5[1] VDD1_6 VSS_30
CA2_B DQ12_B M_A_DQ_5[1] 5
BYTE5 F12 J12
5,22 M_A_LP4_CAB1 M_A_LP4_CAB1 P2 U11 M_A_DQ_5[5] VDD1_7 VSS_31
+V1P1U_VDDQ CA1_B DQ11_B M_A_DQ_5[5] 5
+VDDQ_LP4X
F1 J10
5,22 M_A_LP4_CAB0 M_A_LP4_CAB0 R2 V11 M_A_DQ_5[3] VDD1_8 VSS_32
CA0_B DQ10_B M_A_DQ_5[3] 5
W12 J3
T2 Y11 M_A_DQ_5[6] VDDQ_1 VSS_33
ODT_CA_B DQ9_B M_A_DQ_5[6] 5
CD8 W8 J1
N5 AA11 M_A_DQ_5[7] VDDQ_2 VSS_34
DNU_N5 DQ8_B M_A_DQ_5[7] 5
电容_100nF_0201_X5R_6.3 V_M(±20%) W5 G12
M_A_LP4_CS_B_R1_N R3 AA4 M_A_DQ_4[2] VDDQ_3 VSS_35
5,22 M_A_LP4_CS_B_R1_N NC_R3 DQ7_B M_A_DQ_4[2] 5
W1 G10
M_A_LP4_CS_B_R0_N R4 Y4 M_A_DQ_4[0] VDDQ_4 VSS_36
5,22 M_A_LP4_CS_B_R0_N CS_B DQ6_B M_A_DQ_4[0] 5
U10 G8
N8 V4 M_A_DQ_4[1] VDDQ_5 VSS_37
DNU_N8 DQ5_B M_A_DQ_4[1] 5
U3 G5
M_A_LP4_CKE_B1 P5 U4 M_A_DQ_4[3] VDDQ_6 VSS_38
5,22 M_A_LP4_CKE_B1 NC_P5 DQ4_B M_A_DQ_4[3] 5
BYTE4 F10 G3
M_A_LP4_CKE_B0 P4 U2 M_A_DQ_4[6] VDDQ_7 VSS_39
5,22 M_A_LP4_CKE_B0 CKE_B DQ3_B M_A_DQ_4[6] 5
F3 G1
M_A_CK_DDR1_DN P9 V2 M_A_DQ_4[7] VDDQ_8 VSS_40
5,22 M_A_CK_DDR1_DN CK_C_B DQ2_B M_A_DQ_4[7] 5
D12 E12
M_A_CK_DDR1_DP P8 Y2 M_A_DQ_4[5] VDDQ_9 VSS_41
5,22 M_A_CK_DDR1_DP CK_T_B DQ1_B M_A_DQ_4[5] 5
D8 E8
Y10 AA2 M_A_DQ_4[4] VDDQ_10 VSS_42
DMI1_B DQ0_B M_A_DQ_4[4] 5
D5 E5
Y3 V10 M_A_DQS_5_DN VDDQ_11 VSS_43
DMI0_B DQS1_C_B M_A_DQS_5_DN 5
D1 E1
T11 W10 M_A_DQS_5_DP VDDQ_12 VSS_44
5,21,23,24 DRAM_RESET_N_R RESET_N DQS1_T_B M_A_DQS_5_DP 5
B10 D11
A1 V3 M_A_DQS_4_DN VDDQ_13 VSS_45
DNU_A1 DQS0_C_B M_A_DQS_4_DN 5
B8 D9
A2 W3 M_A_DQS_4_DP VDDQ_14 VSS_46
DNU_A2 DQS0_T_B M_A_DQS_4_DP 5
CD9 B5 D4
A11 AA1 VDDQ_15 VSS_47
DNU_A11 DNU_AA1
电容_100nF_0201_X5R_6.3 V_M(±20%) ns B3 D2
DNU_A12 DNU_AA12
AA10 C12
B1 AB1 VDDQ_17 VSS_49
DNU_B1 DNU_AB1
AA8 C8
DNU_B12 DNU_AB2
AA5 C5
AB11 VDDQ_19 VSS_51
DNU_AB11
AA3 C1
AB12 VDDQ_20 VSS_52
DNU_AB12
AB10
VSS_53
AB8
VSS_54
AB5
VSS_55
AB3
VSS_56
A10
VSS_57
Y12
VSS_58
Page name:
LPDDR4 CH-A_2
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 22 72
CHB-1 +V1P1U_VDDQ
UD3B
电阻_240R_0201_1/20W_F
电阻_240R_0201_1/20W_F
K4F6E3S4HM-MGCJ
+V1P1U_VDDQ
NB_BGA200_15X10X1D2_0D65
RD7 RD8 U8 A3
UD3A VDD2_1 VSS_1
K4F6E3S4HM-MGCJ
CD10 U5 Y8
NB_BGA200_15X10X1D2_0D65 VDD2_2 VSS_2
电容_100nF_0201_X5R_6.3 V_M(±20%) R12 Y5
G11 B9 M_B_DQ_1[4] VDD2_3 VSS_3
DNU_G11 DQ15_A M_B_DQ_1[4] 6
R8 Y1
ZQ1_CHB_0 A8 C9 M_B_DQ_1[1] VDD2_4 VSS_4
NC_A8 DQ14_A M_B_DQ_1[1] 6
R5 W11
ZQ0_CHB_0 A5 E9 M_B_DQ_1[0] VDD2_5 VSS_5
ZQ_A DQ13_A M_B_DQ_1[0] 6
R1 W9
6,23 M_B_LP4_CAA5 M_B_LP4_CAA5 J11 F9 M_B_DQ_1[2] VDD2_6 VSS_6
CA5_A DQ12_A M_B_DQ_1[2] 6
BYTE1 N12 W4
6,23 M_B_LP4_CAA4 M_B_LP4_CAA4 H11 F11 M_B_DQ_1[7] VDD2_7 VSS_7
CA4_A DQ11_A M_B_DQ_1[7] 6
N10 W2
6,23 M_B_LP4_CAA3 M_B_LP4_CAA3 H10 E11 M_B_DQ_1[5] VDD2_8 VSS_8
CA3_A DQ10_A M_B_DQ_1[5] 6
N3 V12
M_B_LP4_CAA2 H9 C11 M_B_DQ_1[3] VDD2_9 VSS_9
6,23 M_B_LP4_CAA2 CA2_A DQ9_A M_B_DQ_1[3] 6
+V1P1U_VDDQ N1 V8
6,23 M_B_LP4_CAA1 M_B_LP4_CAA1 J2 B11 M_B_DQ_1[6] VDD2_10 VSS_10
CA1_A DQ8_A M_B_DQ_1[6] 6
K12 V5
6,23 M_B_LP4_CAA0 M_B_LP4_CAA0 H2 B4 M_B_DQ_3[0] VDD2_11 VSS_11
CA0_A DQ7_A M_B_DQ_3[0] 6
K10 V1
G2 C4 M_B_DQ_3[1] VDD2_12 VSS_12
ODT_CA_A DQ6_A M_B_DQ_3[1] 6
K3 T12
K5 E4 M_B_DQ_3[2] VDD2_13 VSS_13
DNU_K5 DQ5_A M_B_DQ_3[2] 6
K1 T10
M_B_LP4_CS_A_R1_N H3 F4 M_B_DQ_3[4] VDD2_14 VSS_14
6,23 M_B_LP4_CS_A_R1_N NC_H3 DQ4_A M_B_DQ_3[4] 6
BYTE3 H12 T8
M_B_LP4_CS_A_R0_N H4 F2 M_B_DQ_3[7] VDD2_15 VSS_15
6,23 M_B_LP4_CS_A_R0_N CS_A DQ3_A M_B_DQ_3[7] 6
H8 T5
K8 E2 M_B_DQ_3[3] VDD2_16 VSS_16
DNU_K8 DQ2_A M_B_DQ_3[3] 6
H5 T3
M_B_LP4_CKE_A1 J5 C2 M_B_DQ_3[5] VDD2_17 VSS_17
6,23 M_B_LP4_CKE_A1 NC_J5 DQ1_A M_B_DQ_3[5] 6
H1 T1
M_B_LP4_CKE_A0 J4 B2 M_B_DQ_3[6] VDD2_18 VSS_18
6,23 M_B_LP4_CKE_A0 CKE_A DQ0_A M_B_DQ_3[6] 6
F8 P12
M_B_CK_DDR0_DN J9 D10 M_B_DQS_1_DP VDD2_19 VSS_19
6,23 M_B_CK_DDR0_DN CK_C_A DQS1_T_A M_B_DQS_1_DP 6
F5 P10
M_B_CK_DDR0_DP J8 E10 M_B_DQS_1_DN VDD2_20 VSS_20
6,23 M_B_CK_DDR0_DP CK_T_A DQS1_C_A M_B_DQS_1_DN 6
AB9 P3
C10 D3 M_B_DQS_3_DP VDD2_21 VSS_21
DMI1_A DQS0_T_A M_B_DQS_3_DP 6
AB4 P1
C3 E3 M_B_DQS_3_DN VDD2_22 VSS_22
DMI0_A DQS0_C_A M_B_DQS_3_DN 6
A9 N11
6,23 M_B_LP4_CAA5 M_B_LP4_CAA5 P11 AA9 M_B_DQ_0[7] VDD2_23 VSS_23
CA5_B DQ15_B M_B_DQ_0[7] 6
+V1P8U
A4 N9
M_B_LP4_CAA4 R11 Y9 M_B_DQ_0[6] VDD2_24 VSS_24
6,23 M_B_LP4_CAA4 CA4_B DQ14_B M_B_DQ_0[6] 6
U12 N4
6,23 M_B_LP4_CAA3 M_B_LP4_CAA3 R10 V9 M_B_DQ_0[3] VDD1_1 VSS_25
CA3_B DQ13_B M_B_DQ_0[3] 6
CD11 U1 N2
6,23 M_B_LP4_CAA2 M_B_LP4_CAA2 R9 U9 M_B_DQ_0[1] VDD1_2 VSS_26
CA2_B DQ12_B M_B_DQ_0[1] 6
BYTE0 电容_100nF_0201_X5R_6.3 V_M(±20%) T9 K11
6,23 M_B_LP4_CAA1 M_B_LP4_CAA1 P2 U11 M_B_DQ_0[0] VDD1_3 VSS_27
+V1P1U_VDDQ CA1_B DQ11_B M_B_DQ_0[0] 6
T4 K9
6,23 M_B_LP4_CAA0 M_B_LP4_CAA0 R2 V11 M_B_DQ_0[2] VDD1_4 VSS_28
CA0_B DQ10_B M_B_DQ_0[2] 6
G9 K4
T2 Y11 M_B_DQ_0[4] VDD1_5 VSS_29
ODT_CA_B DQ9_B M_B_DQ_0[4] 6
G4 K2
N5 AA11 M_B_DQ_0[5] VDD1_6 VSS_30
DNU_N5 DQ8_B M_B_DQ_0[5] 6
F12 J12
M_B_LP4_CS_A_R1_N R3 AA4 M_B_DQ_2[2] VDD1_7 VSS_31
6,23 M_B_LP4_CS_A_R1_N NC_R3 DQ7_B M_B_DQ_2[2] 6
+VDDQ_LP4X
F1 J10
M_B_LP4_CS_A_R0_N R4 Y4 M_B_DQ_2[4] VDD1_8 VSS_32
6,23 M_B_LP4_CS_A_R0_N CS_B DQ6_B M_B_DQ_2[4] 6
W12 J3
N8 V4 M_B_DQ_2[3] VDDQ_1 VSS_33
DNU_N8 DQ5_B M_B_DQ_2[3] 6
CD12 W8 J1
M_B_LP4_CKE_A1 P5 U4 M_B_DQ_2[6] VDDQ_2 VSS_34
6,23 M_B_LP4_CKE_A1 NC_P5 DQ4_B M_B_DQ_2[6] 6
BYTE2 电容_100nF_0201_X5R_6.3 V_M(±20%) W5 G12
M_B_LP4_CKE_A0 P4 U2 M_B_DQ_2[1] VDDQ_3 VSS_35
6,23 M_B_LP4_CKE_A0 CKE_B DQ3_B M_B_DQ_2[1] 6
W1 G10
M_B_CK_DDR0_DN P9 V2 M_B_DQ_2[0] VDDQ_4 VSS_36
6,23 M_B_CK_DDR0_DN CK_C_B DQ2_B M_B_DQ_2[0] 6
U10 G8
M_B_CK_DDR0_DP P8 Y2 M_B_DQ_2[5] VDDQ_5 VSS_37
6,23 M_B_CK_DDR0_DP CK_T_B DQ1_B M_B_DQ_2[5] 6
U3 G5
Y10 AA2 M_B_DQ_2[7] VDDQ_6 VSS_38
DMI1_B DQ0_B M_B_DQ_2[7] 6
F10 G3
Y3 V10 M_B_DQS_0_DN VDDQ_7 VSS_39
DMI0_B DQS1_C_B M_B_DQS_0_DN 6
F3 G1
T11 W10 M_B_DQS_0_DP VDDQ_8 VSS_40
5,21,22,24 DRAM_RESET_N_R RESET_N DQS1_T_B M_B_DQS_0_DP 6
D12 E12
A1 V3 M_B_DQS_2_DN VDDQ_9 VSS_41
DNU_A1 DQS0_C_B M_B_DQS_2_DN 6
D8 E8
A2 W3 M_B_DQS_2_DP BYTE2 VDDQ_10 VSS_42
CD13 DNU_A2 DQS0_T_B M_B_DQS_2_DP 6
D5 E5
ns A11 AA1 VDDQ_11 VSS_43
电容_100nF_0201_X5R_6.3 V_M(±20%) DNU_A11 DNU_AA1
D1 E1
DNU_A12 DNU_AA12
B10 D11
DNU_B1 DNU_AB1
B8 D9
DNU_B12 DNU_AB2
B5 D4
AB11 VDDQ_15 VSS_47
DNU_AB11
B3 D2
AB12 VDDQ_16 VSS_48
DNU_AB12
AA10 C12
VDDQ_17 VSS_49
AA8 C8
VDDQ_18 VSS_50
AA5 C5
VDDQ_19 VSS_51
AA3 C1
VDDQ_20 VSS_52
AB10
VSS_53
AB8
VSS_54
AB5
VSS_55
AB3
VSS_56
A10
VSS_57
Y12
VSS_58
Page name:
LPDDR4 CH-B_1
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 23 72
CHB-2
UD4B
K4F6E3S4HM-MGCJ
+V1P1U_VDDQ +V1P1U_VDDQ NB_BGA200_15X10X1D2_0D65
U8 A3
VDD2_1 VSS_1
电阻_240R_0201_1/20W_F
电阻_240R_0201_1/20W_F
CD14 U5 Y8
VDD2_2 VSS_2
电容_100nF_0201_X5R_6.3 V_M(±20%) R12 Y5
VDD2_3 VSS_3
RD10
UD4A R8 Y1
RD9 K4F6E3S4HM-MGCJ VDD2_4 VSS_4
NB_BGA200_15X10X1D2_0D65 R5 W11
VDD2_5 VSS_5
G11 B9 M_B_DQ_4[2] R1 W9
DNU_G11 DQ15_A M_B_DQ_4[2] 6 VDD2_6 VSS_6
ZQ1_CHB_1 A8 C9 M_B_DQ_4[0] N12 W4
NC_A8 DQ14_A M_B_DQ_4[0] 6 VDD2_7 VSS_7
ZQ0_CHB_1 A5 E9 M_B_DQ_4[4] N10 W2
ZQ_A DQ13_A M_B_DQ_4[4] 6 VDD2_8 VSS_8
6,24 M_B_LP4_CAB5 M_B_LP4_CAB5 J11 F9 M_B_DQ_4[7] N3 V12
CA5_A DQ12_A M_B_DQ_4[7] 6 VDD2_9 VSS_9
6,24 M_B_LP4_CAB4 M_B_LP4_CAB4 H11 F11 M_B_DQ_4[5] BYTE4 N1 V8
6,24 M_B_LP4_CAB3 M_B_LP4_CAB3 H10 E11 M_B_DQ_4[6] K12 V5
6,24 M_B_LP4_CAB2 M_B_LP4_CAB2 H9 C11 M_B_DQ_4[3] K10 V1
6,24 M_B_LP4_CAB1 M_B_LP4_CAB1 J2 B11 M_B_DQ_4[1] K3 T12
+V1P1U_VDDQ CA1_A DQ8_A M_B_DQ_4[1] 6 VDD2_13 VSS_13
6,24 M_B_LP4_CAB0 M_B_LP4_CAB0 H2 B4 M_B_DQ_5[5] K1 T10
G2 C4 M_B_DQ_5[7] H12 T8
ODT_CA_A DQ6_A M_B_DQ_5[7] 6 VDD2_15 VSS_15
K5 E4 M_B_DQ_5[6] H8 T5
DNU_K5 DQ5_A M_B_DQ_5[6] 6 VDD2_16 VSS_16
M_B_LP4_CS_B_R1_N H3 F4 M_B_DQ_5[3] H5 T3
6,24 M_B_LP4_CS_B_R1_N NC_H3 DQ4_A M_B_DQ_5[3] 6 VDD2_17 VSS_17
BYTE5
M_B_LP4_CS_B_R0_N H4 F2 M_B_DQ_5[1] H1 T1
6,24 M_B_LP4_CS_B_R0_N CS_A DQ3_A M_B_DQ_5[1] 6 VDD2_18 VSS_18
K8 E2 M_B_DQ_5[2] F8 P12
DNU_K8 DQ2_A M_B_DQ_5[2] 6 VDD2_19 VSS_19
M_B_LP4_CKE_B1 J5 C2 M_B_DQ_5[4] F5 P10
6,24 M_B_LP4_CKE_B1 NC_J5 DQ1_A M_B_DQ_5[4] 6 VDD2_20 VSS_20
M_B_LP4_CKE_B0 J4 B2 M_B_DQ_5[0] AB9 P3
6,24 M_B_LP4_CKE_B0 CKE_A DQ0_A M_B_DQ_5[0] 6 VDD2_21 VSS_21
M_B_CK_DDR1_DN J9 D10 M_B_DQS_4_DP AB4 P1
6,24 M_B_CK_DDR1_DN CK_C_A DQS1_T_A M_B_DQS_4_DP 6 VDD2_22 VSS_22
M_B_CK_DDR1_DP J8 E10 M_B_DQS_4_DN A9 N11
6,24 M_B_CK_DDR1_DP CK_T_A DQS1_C_A M_B_DQS_4_DN 6 VDD2_23 VSS_23
+V1P8U
C10 D3 M_B_DQS_5_DP A4 N9
DMI1_A DQS0_T_A M_B_DQS_5_DP 6 VDD2_24 VSS_24
C3 E3 M_B_DQS_5_DN U12 N4
DMI0_A DQS0_C_A M_B_DQS_5_DN 6 VDD1_1 VSS_25
M_B_LP4_CAB5 P11 AA9 M_B_DQ_6[7] CD15 U1 N2
6,24 M_B_LP4_CAB5 CA5_B DQ15_B M_B_DQ_6[7] 6 VDD1_2 VSS_26
6,24 M_B_LP4_CAB4 M_B_LP4_CAB4 R11 Y9 M_B_DQ_6[6] 电容_100nF_0201_X5R_6.3 V_M(±20%) T9 K11
CA4_B DQ14_B M_B_DQ_6[6] 6 VDD1_3 VSS_27
6,24 M_B_LP4_CAB3 M_B_LP4_CAB3 R10 V9 M_B_DQ_6[3] T4 K9
6,24 M_B_LP4_CAB2 M_B_LP4_CAB2 R9 U9 M_B_DQ_6[1] G9 K4
6,24 M_B_LP4_CAB1 M_B_LP4_CAB1 P2 U11 M_B_DQ_6[0] BYTE6 G4 K2
+V1P1U_VDDQ CA1_B DQ11_B M_B_DQ_6[0] 6 VDD1_6 VSS_30
M_B_LP4_CAB0 R2 V11 M_B_DQ_6[2] F12 J12
6,24 M_B_LP4_CAB0 CA0_B DQ10_B M_B_DQ_6[2] 6 VDD1_7 VSS_31
+VDDQ_LP4X
T2 Y11 M_B_DQ_6[4] F1 J10
ODT_CA_B DQ9_B M_B_DQ_6[4] 6 VDD1_8 VSS_32
N5 AA11 M_B_DQ_6[5] W12 J3
DNU_N5 DQ8_B M_B_DQ_6[5] 6 VDDQ_1 VSS_33
M_B_LP4_CS_B_R1_N R3 AA4 M_B_DQ_7[7] CD16 W8 J1
6,24 M_B_LP4_CS_B_R1_N NC_R3 DQ7_B M_B_DQ_7[7] 6 VDDQ_2 VSS_34
M_B_LP4_CS_B_R0_N R4 Y4 M_B_DQ_7[6] 电容_100nF_0201_X5R_6.3 V_M(±20%) W5 G12
6,24 M_B_LP4_CS_B_R0_N CS_B DQ6_B M_B_DQ_7[6] 6 VDDQ_3 VSS_35
N8 V4 M_B_DQ_7[5] W1 G10
DNU_N8 DQ5_B M_B_DQ_7[5] 6 VDDQ_4 VSS_36
M_B_LP4_CKE_B1 P5 U4 M_B_DQ_7[1] U10 G8
6,24 M_B_LP4_CKE_B1 NC_P5 DQ4_B M_B_DQ_7[1] 6 VDDQ_5 VSS_37
BYTE7
M_B_LP4_CKE_B0 P4 U2 M_B_DQ_7[0] U3 G5
6,24 M_B_LP4_CKE_B0 CKE_B DQ3_B M_B_DQ_7[0] 6 VDDQ_6 VSS_38
M_B_CK_DDR1_DN P9 V2 M_B_DQ_7[2] F10 G3
6,24 M_B_CK_DDR1_DN CK_C_B DQ2_B M_B_DQ_7[2] 6 VDDQ_7 VSS_39
M_B_CK_DDR1_DP P8 Y2 M_B_DQ_7[4] F3 G1
6,24 M_B_CK_DDR1_DP CK_T_B DQ1_B M_B_DQ_7[4] 6 VDDQ_8 VSS_40
Y10 AA2 M_B_DQ_7[3] D12 E12
DMI1_B DQ0_B M_B_DQ_7[3] 6 VDDQ_9 VSS_41
Y3 V10 M_B_DQS_6_DN D8 E8
DMI0_B DQS1_C_B M_B_DQS_6_DN 6 VDDQ_10 VSS_42
T11 W10 M_B_DQS_6_DP D5 E5
5,21,22,23 DRAM_RESET_N_R RESET_N DQS1_T_B M_B_DQS_6_DP 6 VDDQ_11 VSS_43
A1 V3 M_B_DQS_7_DN D1 E1
DNU_A1 DQS0_C_B M_B_DQS_7_DN 6 VDDQ_12 VSS_44
A2 W3 M_B_DQS_7_DP B10 D11
DNU_A2 DQS0_T_B M_B_DQS_7_DP 6 VDDQ_13 VSS_45
CD17
A11 AA1 B8 D9
DNU_A11 DNU_AA1 VDDQ_14 VSS_46
电容_100nF_0201_X5R_6.3 V_M(±20%) ns
A12 AA12 B5 D4
DNU_A12 DNU_AA12 VDDQ_15 VSS_47
B1 AB1 B3 D2
DNU_B1 DNU_AB1 VDDQ_16 VSS_48
B12 AB2 AA10 C12
DNU_B12 DNU_AB2 VDDQ_17 VSS_49
AB11 AA8 C8
DNU_AB11 VDDQ_18 VSS_50
AB12 AA5 C5
DNU_AB12 VDDQ_19 VSS_51
AA3 C1
VDDQ_20 VSS_52
AB10
VSS_53
AB8
VSS_54
AB5
VSS_55
AB3
VSS_56
A10
VSS_57
Y12
VSS_58
Page name:
LPDDR4 CH-B_2
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 24 72
D
V1.0
REV:
72
of
25
Sheet:
LPDDR4(DECAPS)
CD37
NB8511
电容_10uF_0402_X5R_6.3V_M
1
1
CD36
CD83
Project
Name:
Page name:
DECOUPLING CAPACITORS FOR LPDDR4 CHANNEL B
Date:
Size:
A4
CD65
电容_10uF_0402_X5R_6.3V_M
CD35
CD82
CD107
CD64
电容_2.2pF_0201_C0G_50V_C 电容_2.2pF_0201_C0G_50V_C
RF request
RF request
CD34
CD81
电容_12pF_0201_COG_25V_J 电容_12pF_0201_COG_25V_J
CD49
电容_10uF_0402_X5R_6.3V_M
CD106
CD33
CD63
CD80
CD48
CD93

CD105
CD32
CD62
CD79
Place as close as possible to UD?

2
2
CD104
CD31
CD47
CD61
CD78
CD92
电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

CD103
CD30
CD46
CD60
CD77
CD91

CD102
CD29
CD45
CD59
CD76
CD90

+V1P1U_VDDQ
+V1P1U_VDDQ
CD101
+VDDQ_LP4X
+VDDQ_LP4X
CD28
CD44
CD58
CD75
CD89
+V1P8U
+V1P8U

3
3
CD27
电容_10uF_0402_X5R_6.3V_M
CD26
CD74
DECOUPLING CAPACITORS FOR LPDDR4 CHANNEL A
CD57
电容_10uF_0402_X5R_6.3V_M
CD25
CD73
CD100
CD56
电容_2.2pF_0201_C0G_50V_C 电容_2.2pF_0201_C0G_50V_C
4
4
RF request
RF request
CD24
CD72
+VDDQ_LP4X
电容_12pF_0201_COG_25V_J 电容_12pF_0201_COG_25V_J
CD43
电容_10uF_0402_X5R_6.3V_M
CD23
CD55
CD71
CD99
CD42
CD88
电阻_0.01R_0805_1/2W_F(±1%)
电阻_0.01R_0805_1/2W_F(±1%)
nb_rtc0805
nb_rtc0805
CD22
CD54
CD70
CD98
2
2 2
4 4
RD11
RD12
4 4
电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 3 3
LPDDR4X@
LPDDR4@
1 3 1 3
CD21
CD41
CD53
CD69
CD87
CD97
1
CD20
CD40
CD52
CD68
CD86
CD96
+V1P1U_VDDQ
+VDDQ_TX
CD19
CD39
CD51
CD67
CD85
CD95
5
5
+V1P1U_VDDQ
+V1P1U_VDDQ
+VDDQ_LP4X
+VDDQ_LP4X
CD18
CD38
CD50
CD66
CD84
CD94
+V1P8U
+V1P8U
A
5 4 3 2 1
D D
C C
B B
A A
Page name:
BLANK
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 26 72
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Page name:
BLANK
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 27 72
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Page name:
BLANK
Size: Project REV:
A4 Name: V1.0
NB8511
Date: Sheet: of
Monday, July 15, 2019 28 72
5 4 3 2 1
5 4 3 2 1
UV2A
INS39945158
?
11 PCIE_CRX_GTX_N[0..3] COMMON
11 PCIE_CRX_GTX_P[0..3]
1/14 PCI_EXPRESS RF Requirement - 03/06
N16:PEX_IOVDD
电容_22uF_0603_X5R_6.3V_M
11 PCIE_CTX_GRX_N[0..3] N17:PEX_DVDD +1.0VGS
电容_4.7uF_0402_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M
电容_4.7uF_0402_X5R_6.3V_M
11 PCIE_CTX_GRX_P[0..3] AA22
200mA
电容_4.7uF_0402_X5R_6.3V_M
PEX_DVDD
电容_1uF_0201_X5R_6.3V_M
电容_22pF_0201_C0G_50V_J
电容_22pF_0201_C0G_50V_J
PLT_RST_VGA_N AC7 PEX_RST PEX_DVDD AB23
PEX_DVDD AC24
CLK_REQ_GPU_N AC6 PEX_CLKREQ PEX_DVDD AD25
CV15 CV4 CV5
PEX_DVDD AE26 CV1 CV16 CV2 CV3 CV207
PLT_RST_VGA_N CV208
PCIE_REFCLK_GFX_DP AE8 PEX_REFCLK PEX_DVDD AE27 GPU GPU GPU GPU GPU GPU GPU ns ns
9 PCIE_REFCLK_GFX_DP
电容_33pF_0201_C0G_25 V_J(±5%)
PCIE_REFCLK_GFX_DN AD8 PEX_REFCLK
9 PCIE_REFCLK_GFX_DN
PCIE_CRX_GTX_P0 GPU CV6 电容_220nF_0201_X5R_6.3V_M PCIE_CRX_C_GTX_P0 AC9 PEX_TX0 +V1P8_V3P3_AON
CV195 +V1P8_V3P3_MAIN
PCIE_CRX_GTX_N0 GPU CV7 电容_220nF_0201_X5R_6.3V_M PCIE_CRX_C_GTX_N0 AB9 PEX_TX0
ns Under GPU Near GPU
PCIE_CTX_GRX_P0 AG6 PEX_RX0 (below 150mils)
PCIE_CTX_GRX_N0 AG7 PEX_RX0 PEX_HVDD AA10
PEX_HVDD AA12 300mA CV17
PCIE_CRX_GTX_P1 GPU CV8 电容_220nF_0201_X5R_6.3V_M PCIE_CRX_C_GTX_P1 AB10 PEX_TX1 PEX_HVDD AA13 CV18 CV19 CV10 CV20 CV21
电容_22pF_0201_C0G_50V_J
电容_22pF_0201_C0G_50V_J
CV22 CV25 GPU
电容_22uF_0603_X5R_6.3V_M
PCIE_CRX_GTX_N1 GPU CV9 电容_220nF_0201_X5R_6.3V_M PCIE_CRX_C_GTX_N1 AC10 PEX_TX1 PEX_HVDD AA16 CV23 CV11
GPU GPU GPU GPU GPU GPU 电容_100nF_0201_X5R_6.3 V_M(±20%)
电容_33pF_0201_C0G_25V_J
PEX_HVDD AA18 ns GPU GPU CV12
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_1uF_0201_X5R_6.3V_M
电容_10uF_0402_X5R_6.3V_M

Acer Swift 3 SF314-57 (Huaqin NB8511-12) Ver 1.0 Schematic

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Acer Swift 3 SF314-57 (Huaqin NB8511-12) Ver 1.0 Schematic

Transféré par

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5 4 3 2 1

Leo.Liu & Payne.Zhang Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

HW_ID3 HW_ID2 HW_ID1 HW_ID0 Description Total

0 0 0 0 SAMSUNG LPDDR4 3733 1GB K4F8E304HB-MGCJ LF+HF D20 4GB

0 0 0 1 HYNIX LPDDR4 3733 1GB H9HCNNN8KUMLHR-NME LF+HF DDP 4GB

0 0 1 0 MICRON LPDDR4 4266 2GB MT53E512M32D2NP-046 WT:E LF+HF Z11N 8GB

0 1 0 0 HYNIX LPDDR4 3733 2GB H9HCNNNBPUMLHR-NME LF+HF DE 8GB

1 0 0 0 HYNIX LPDDR4X 4266 4GB H9HCNNNCPMALHR-NEE LF+HF QDP

Huaqin Telecom Technology Com.,Ltd.

CHA UU1B ???

M_A_DQ_0[0] CA48 BL48 M_A_CK_DDR0_DN

PLACE RESET COMPONENTS CLOSE TO CPU

Huaqin Telecom Technology Com.,Ltd.

D M_B_DQ_0[0] AK48 Y48 M_B_CK_DDR0_DN D

Huaqin Telecom Technology Com.,Ltd.

EDP_TX0_SOC_DN Y5 BB5 TCP0_TX0_DN

PCH STRAP---VCCIO CONFIGURATION HPD_P1

RU8 RU9 RU10 RU11 ns

TBT_LSX0_RXD GPP_E21 GPP_D12 GPP_D10

Huaqin Telecom Technology Com.,Ltd.

TBT_LSX0_RXD GPP_E21 Page name:

20MIL TP182 GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK TYPEC_PD_SOC_CLK 44

ns 1 GPP_E12 DU18 DL22 TYPEC_PD_SOC_DAT

43 CLNK_CLK_SOC CLNK_DATA_SOC CL_CLK GPP_A3/ESPI_IO3 ESPI_CS_N ESPI_IO3_EC 38

XTAL INPUT FREQUENCY [0]

XTAL_OUT MAIN 38.4MHZ CRYSTAL QU2 +VCCRTC

电容_8.2pF_0201_C0G_50 V_C(±0.25pf) SRTC_RST_N

+V3P3A_PCH CPUNSSC CLOCK FREQ

RU119 电阻_10K_0201_1/20W_J GPU_PWREN

Close to CPU Page name:

PCIE_CRX_GTX_N2 CV7 DJ8 USB3_P1_RX_DN

41 PCIE14_CTX_DRX_P PCIE14_TXP DK10 USB2_P4_DN

BUFFER TO REDUCE LOADING ON PLT_RST_N

Huaqin Telecom Technology Com.,Ltd.

CL10 VCCIN_AUX_8 VCCPRIM_1P8_3 DF18

+VNN_BYPASS_R AT9 VCCIN_AUX_33 DG31

+VDDQ_CPU UU1M ??? +VDDQ_CPU

VCCSTG_OUT_LGC CG38 CU56 CU57

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

RU194 电阻_1K_0201_1/20W_J CFG0 AG6 A47 1 ns

RU211 CFG8 RU235 电阻_1K_0201_1/20W_J

CFG10 RU237 电阻_1K_0201_1/20W_J

CFG12 RU238 电阻_1K_0201_1/20W_J

CFG13 RU239 电阻_1K_0201_1/20W_J

+VCCIO_OUT +VCCIO_OUT CFG3 RU240 电阻_1K_0201_1/20W_J

电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

Place as close as possible to each U1 and AB1

PLACE THESE CAPS UNDERNEATH BGA AREA

PLACE CLOSE TO PACKAGE ON PRIMARY SIDE

电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

Positive and negative folding

Monday, July 15, 2019

电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M

Place after the TOP DDR signal breakout

PLACE CLOSE TO PACKAGE ON PRIMARY SIDE

电容_10uF_0402_X5R_6.3V_M 电容_1uF_0201_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M 电容_10uF_0402_X5R_6.3V_M

PLACE THESE CAPS UNDERNEATH BGA AREA