Scaled MOSFETs Physics

Jason C
C.S.
S Woo

University of California, Los Angeles

El
Electrical
i l Engineering
E i i

Jason Woo IWSG2009

 Whyy Scaled MOSFETs
• The best semiconductor active device for advanced
system Field Effect Tansistor (MOSFET)
• Sub-25nm MOSFET has been demonstrated
• Quantum devices generally requires sub 10nm
dimension
• Real Opportunity for 5-25 regime
• Should retains the output characteristics of
MOSFETs
MOSFET

Jason Woo IWSG2009

 Keyy Attributes of MOSFETs

Ion
Ioff
Zin (including Igate)
Parasitics
(G XR t)
Gm (GmXRout)
Noise
Breakdown voltages, Reliability

Jason Woo IWSG2009

 ITRS PIDS Roadmap

Jason Woo IWSG2009

 Long Channel MOSFETs
SiO
Basic
G 2

S D
ND ND
L

NA

Sub
∂φ xi
∫ I D dy = ∫ ∫
L L
q μn Z Fn n( x, y ) dx dy
0 0 ∂y 0

qZ μn |φB |−V n po e β (ψ − βV ) dψ
⇒ ∫ ∫ψ
VD
ID = n dV
L 0 S 2 kT F ( βψ , V , po )
qλ p p po S.M. Sze

• SiO2 Perfect Insulator

• Gate Perfect Conductor
• Band-Bending Approximation
• Gate Modulation on Channel Only
Jason Woo IWSG2009
 Ideal MOSFETs Scaling
• All linear dimensions scale by 1/S (S>1)
• All voltages (VTH, VD, Vsub) scaled by 1/S
• All doping levels scale by S

Device/Circuit Performance Scaling Factor

Dimension: tox, L, W, Xj 1/S
p g NA
Substrate Doping: S
Supply Voltage: V 1/S
Supply Current: I 1/S
Oxide Capacitance: WL/tox 1/S
Grate Delay: 1/S
Power Dissipation: (1/S)2
Power-Delay Product: (1/S)3
Density: S2
Jason Woo IWSG2009
 Fundamental Issues for sub-32nm MOSFETs
• Transport and Kinentics
– Mobility,
M bilit Vsat
V t
– Subthreshold Current Swing
– Rs, Rd, Interface Transport
• Materials
– Breakdown
– Bandgap (Vbi)
– Dopant Incorporation
• Electro-static coupling
– SCE
• Quantum Effetcs
- Tunneling
- Cinv
• Power
• Ioff: DIBL, S, Tunneling
• Ion: Vsat, Power supply
• Rout: DIBL
DIBL, Punchthrough
• Noise: Shot noise, Thermal noise, ...
• Reliability: Thin Film
Jason Woo IWSG2009
 Solutions and limitations
IIncreasing
i substrate
bt t d doping
i tto reduce
d S/D electric
l t i
coupling
⇒ Carrier mobilityy , B-B tunnelingg and junction
j
capacitance - SOI/DG
Reduce gate oxide thickness to enhance gate
controllability
⇒ gate tunneling and breakdown issues – High K
Reduce the power supply (Vdd) aggressively
⇒ reduced
d d gate t overdrive
d i because
b Vth cannott be
b scaled
l d
too fast as a result of un-scalable sub-threshold swing –
STEEP Device
Source/drain engineering is also needed to suppress
SCEs and reduce parasitic resistance.
New contact material to reduce schottky barrier
height (Φ B)
Jason Woo IWSG2009
 Fundamental Issue --- Electrostatic Coupling

I To suppress short channel effects:

Gate
Stack I. Thin effective gate dielectric
silicide silicide
thickness to enhance gate control
II High substrate doping
II. doping, requires
2-D retrograde profile to control
III II
vth?
III. Shallow source/drain extensions,
needs low implanting energy and
tight thermal control

Jason Woo IWSG2009

 2-D potential Profile contour Comparison between 250nm and 35nm BULK FETs
(Vg = 0.1, vd = 0.1) (off state)

Jason Woo IWSG2009

 DIBL : Comparison between 35nm and 250nm @ Vd = 0.1
and 1V for BULK FETs

Conduction Band Edge vs distance along channel

Jason Woo IWSG2009
 Id-Vg for bulk FETs Comparison between 35nm and
250nm FETs (Vd = 0.1 & 1V)
nt (A)
Drain Curren

Blue: 250nm
Red: 35nm

Jason Woo IWSG2009

 SOI CMOS
• Low Junction Capacitances and Leakage
- Low Power and High Speed
• Almost Perfect Isolation
- Higher Density
• Minimized Body Effects
• Suppression of Short Channel Effects
(FDSOI)

Jason Woo IWSG2009

 2-D potential Profile contour Comparison between 250nm and
35nm SOI FETs (Vg = 0.1, vd = 0.1) (off state)

Jason Woo IWSG2009

 General scaling rules in ultrathin SOI MOSFETs

Taur

For given dielectrics εI and εSi, if (tI, tSi) are both scaled by a
ffactor off α,, Lmin will be scaled byy the same factor α

Jason Woo IWSG2009

 Scaling of UTB SOI MOSFETs

• High-κ insulators allow thicker tI for given tSi and Lmin

• For a given εI, same Lmin can be achieved with a thin tSi and
thick tI or with a thin tI and thick tSi

Jason Woo IWSG2009

 Double Gate FETs

P. Wong
Jason Woo IWSG2009
 2-D potential Profile contour Comparison between 250nm and
35nm DG FETs ((VG = 0.1V,, VD = 0.1V)) ((off state))

Jason Woo IWSG2009

 DIBL : Comparison between 35nm and 250nm @ VD = 0.1 and 1V
for DG FETs Conduction Band Edge
g vs distance along
g channel

Jason Woo IWSG2009

 DIBL : Comparison between BULK and DG FETs@ VD = 0.1 and
1V (35nm) Conduction Band Edge vs distance along channel

Jason Woo IWSG2009

ID-VG for 35nm FETs. Comparison between Bulk and DG
FETs (VD = 00.1
1 & 1V)
Draain Curreent (A)

Blue: Bulk FET
Red: DG FET

Jason Woo IWSG2009

 S/D Extension for bulk MOSFETs

• As the MOSFET channel are scaled down to 45 nm and below S/D

extension junction depth must be reduced to 10nm and below nm
to suppress short-channel effects.
• Sheet resistance of the S/D extension may be decreased,
decreased but they
must not add significant resistance to the channel resistance.
• Higher active dopant concentrations must be achieved in the ultra-
shallow
h ll S/D extensioni regions.
i
• Transient Enhanced Diffusion is problematic even with Ultra-low
ion-implantation
p andSpike
p anneal and responsible
p for more than
90% of dopant motion for those anneal steps.
• Note that a raised source-drain structure may help making
contacts but does not by itself satisfy the abruptness
contacts,

Jason Woo IWSG2009

 Solutions and limitations
IIncreasing
i substrate
bt t d doping
i tto reduce
d S/D electric
l t i
coupling
⇒ Carrier mobilityy , B-B tunnelingg and junction
j
capacitance - SOI/DG
Reduce gate oxide thickness to enhance gate
controllability
⇒ gate tunneling and breakdown issues – High K
Reduce the power supply (Vdd) aggressively
⇒ reduced
d d gate t overdrive
d i because
b Vth cannott be
b scaled
l d
too fast as a result of un-scalable sub-threshold swing –
STEEP Device
Source/drain engineering is also needed to suppress
SCEs and reduce parasitic resistance.
New contact material to reduce schottky barrier
height (Φ B)
Jason Woo IWSG2009
 Schematic Diagram
g & Resistance Components
p
Gate

Rcsd Rdp Rext Rov

Rfr,ext
Rsur,dp Rac2
Rcsdd Rsur,extt Rac11
Rsp,dp Rsp,ov
Rsp,ext

R series = R csd + R dp + R ext + R ov

24

Jason Woo IWSG2009

 Advanced Series Resistance Model Formula
Overlap resistance: Deep S/D resistance:
−1 −1
⎛ 1 1 ⎞⎟ ⎛ 1 1 ⎞⎟
Rov = Rac1 + ⎜ + ⎜
d =⎜
Rdp +
⎜R ⎟ ⎟
⎝ ac 2 Rsp ,ov ⎠ ⎝ Rsur , dp Rsp , dp ⎠

Lov dy
Rac1 = ∫ Lsilicide ⎛ Ldp ⎞
Lov −Wov μ ac ( y )Cox (Vgs − V fb ,ov ( y ) − Ψs ( y ) − V p ( y )) Rsp,dp = ρ dp / ln⎜ ⎟
Tsilicide ⎜L −L ⎟
Lov −Wov ddy ⎝ dp
p silicide ⎠
Rac 2 = ∫ Lsw − Ldp ⎛ X jext − Wext − Tsilicide Wext − Wdp ⎞
0 μ ac ( y )Cox (Vgs − V fb ,ov ( y ) − Ψs ( y ) − V p ( y )) Rsp,dp = ρ dp ln⎜ +
Lsw
⋅ ⎟
Wext − Wdp ⎜⎝ X jext − Wdp − Tsilicide Lsw − Ldp X jext − Wdp − Tsilicide ⎟⎠
1 Lov −Wov ρ ov ( y )
Rsp ,ov = ∫
tan α1 0 Lov − Wov + Tc / tan α1 − y
dy

S/D extension resistance: Silicide-diffusion contact resistance:

−1
⎛ 1 1 1 ⎞⎟ ρc ⎛ Lcon ⎞
Rext = ⎜ + + Rcsd = coth⎜⎜ ⎟⎟
⎜R ⎟ LT ⎝ T ⎠
L
⎝ fr ,ext Rsur ,ext Rsp ,ext ⎠

( Lsw − Ldp ) 2
R fr ,ext = Total S/D series resistance:
μ fr ,ext (Vgs − V fb ,ext − Ψs ,ext )C fr ,ext
Lsw − Ldp
Rsur ,ext = ρ ext ( N max,ext ) Rsd = 2 Rseries
X p ,ext
1 X jext −Wdp ρext ( x) = 2( Rov + Rext + Rdp + Rcsd )
Rsp,ext =
tan α 2 ∫X jext −Wext x − X p ,ext
dx

25

Jason Woo IWSG2009

 Relative Contributions of Resistance
Components
NMOSFETs
m]

500 70
S/D Seeries Resisttance [Ωμm

Relattive Contriibution [%]

NMOS scaled by ITRS Rov 60
400 NMOS Rcsd
Rext 50
300 40
Rdp Rext
200 30

Rcsd 20 Rov
100
10
Rdp
0 0
32 nm 53 nm 70 nm 100 nm 32 nm 53 nm 70 nm 100 nm
Physical Gate Length Physical Gate Length

• Assumptions : Scaled according to ITRS projection Gradual doping &

midgap silicide material
• Rcsd will be a dominant component for highly scaled nanometer transistor
(Rcsd/Rseries is rising up to >> ~ 60 % for LG < 53 nm)
Jason Woo IWSG2009
 Relative Contributions of Resistance
Components
PMOSFETs
m]

700 70
S/D Seeries Resisstance [Ωμm

%]
ative Contrribution [%
600 PMOS scaled by ITRS 60 Rcsd PMOS
Rov
500 50
400 Rextt 40
300 30 Rov
200
Rdp 20 Rext
100 Rcsd 10
Rdpp

Rela
0 0
32 nm 53 nm 70 nm 100 nm 32 nm 53 nm 70 nm 100 nm
Physical Gate Length Physical Gate Length

• Relatively large Rov contribution, but still largest in Rcsd

( Rcsd/Rseries : ~ 60 % , Rov/Rseries : 20 ~ 30 % for LG < 53 nm)

27

Jason Woo IWSG2009

 Key S/D Parameters Impact on CMOS Scaling

Sidewall Gate

Silicide
Nov(y)
Rcsdd Rov Rov:
Rdp Rext
• Nov (y)
• Lov
Next(x)
• Xjext

Rcsd: Rdp: Rext:

• ρc(Nif, φb) • Ndp (x) • Next (x)
• Rsh,dp (Ndp, Xjdp, Tsilicide) • Ldp • Ldp - Lsw
• Lcon • Xjdp • Xjext

Jason Woo IWSG2009

 Device Structure

Lg = 45nm
POLY Lm = 30nm
contact contact
Tox,eq = 0.8nm
0 8nm
Source Drain Xje = 15nm
Xjc = 45nm
Lext,sp+ Lext,ov = Lext
Next = 1~5x1019/cm3
Nd = 3x1020/cm3
Si substrate

•Abrupt
Abrupt junction is assumed

Jason Woo IWSG2009

 S/D Extension Doping Effect
900 110
850
100
800
750 90
700
•ρc = 1.2x10-7Ω/μm2

mV/V)
80
A/μm)

650

DIBL (m
600
•Vdd=0.8
08V
Ion (μA

70
550
500 60
450 Ion, Lext,sp = 0nm
•Ioff=10 nA/µm
Ion,L
Lext,sp = 7
7.5nm
5nm 50
400
DIBL,Lext,sp = 0nm
350 40
DIBL,Lext,sp = 7.5nm
300
18 19 20
10 10 10
-3
Extension doping concentration (cm , log)

SCE is very sensitive to SDE doping (5x1018cm-3 ~1x1020cm-3)

SDE doping under sidewall region is critical to series resistance

Jason Woo IWSG2009

 S/D Extension Length
g ((under sidewall)) Effect

750
130
1.10
700 10 A/μm 120
Ioff=10nA/
19 -3
C*V/Ion @ Next=5x10 cm
110 1.05 19 -3
650 C*V/Ion @ Next=1x10 cm
100

Normalized C**Vdd/Ion
1.00
600
90

DIBl (mV/V)
m)
Ion (μA/μm

550 80 0.95

70
500 0.90
60
19 -3
450 Ion,SDE=5x10 cm 0.85
19 -3
3 50
Ion,SDE=1x10 cm
400 19
DIBL,SDE=5x10 cm
-3 40 0.80
19 -3 -10 -5 0 5 10 15 20
DIBL,SDE=1x10 cm 30
350 Extension length under sidewall (nm)
-10 -5 0 5 10 15 20
Extension length under sidewall (nm)

S/D series resistance increased with Lext,sp

DIBL can be decoupled
p from deep
p S/D region
g with large
g spacer
p designg
Device with low SDE doping but zero Lext,sp design can improve Ion ,
DIBL and C*Vdd/Ion
Jason Woo IWSG2009
 SDE-to-Gate Overlap
p Depth
p Effect (@ Lext,sp 0)
ext sp=0

850 110 Gate

19
Ion @Next=1x10
1 10 cm
-3
3 105 Stack
800 19 -3
Ion @Next=5x10 cm 100

95 Source
Drain current (μA/μm)

750
90

DIB
BL (mV/V)
700 85

80
650
75

70
600 19
DIBL @Next=5x10 cm
-3

Ioff=10nA/μm 19
DIBL @Next=1x10 cm
-3 65

550 60
0 5 10 15 20
SDE jjunction depth
p (nm)
( )

Drive current is independent of SDE-to-gate overlap depth due

to the trade-off between Vth and overlap resistance
SDE-to-gate
SDE to gate ooverlap
erlap can be eliminated to suppress
s ppress SCE and
reduce overlap capacitance

Jason Woo IWSG2009

 Zero & Nonzero Gate-to-SDE overlap
Device Performance Comparison (1)
1000
950 with ext. overlap
without ext. overlap 650
900 with ext. overlap
600
without ext. overlap
550
850
Drain currrent (μA/μm)

Drain current (μA/μm)

500
800 450
400
750
350
700 300
250 •Lg=500nm
650
200
600
•Lg=45nm -9
10 10
-8
10
-7 -6
10

550 leakage ( μm))

g current (A/

500
-9 -8 -7 -6
10 10 10 10
Leakage current (A/μm)

Long channel: device with overlap has higher current drive due to
smaller effective channel length, Ion ∝ Leff-1
Short channel: Similar Ion /Ioff
ff performance due to velocity saturation
and SCE limitation

Jason Woo IWSG2009

 Zero & Nonzero Gate-to-SDE Overlap
Device Performance Comparison (2)

1.05

with
ith ext.
t overlap
l
1.00 1.1
without ext. overlap
with ext. overlap
1.0
without ext. overlap
0.95
0.9
normalized C**V/I

normalized C**V/I
0.8
0 90
0.90
0.7

0.85 0.6

0.5
0.80 •Lg=500nm
n

04
0.4

0.3
0.75 •Lg=45nm -9
10 10
-8
10
-7
10
-6

leakage current (A/μm)

0.70
-9 -8 -7 -6
10 10 10 10
leakage current (A/μm)

Long channel: SDE-to-Gate overlap improves device

intrinsic speed due to enhanced drive current
Short channel: SDE-to-Gate overlap degrades device speed
due to increased overlap capacitance
Jason Woo IWSG2009
 Deep S/D Junction Depth
Eff t
Effect
100 800

95 10 A/μm
Ioff=10nA/ Gate
contact Stack
90
750
85
Source
DIBL (mV/V))

IIon (μA/μm)
80
700
75

70
20 -3
DIBL @Nd=3x10 cm 650
65 21 -3
DIBL @Nd=3x10 cm Gate
20 -3
60 Ion @Nd=3x10 cm
21 -3
Stack
Ion @Nd=3x10 cm
55 600 Source
10 20 30 40 50 60
deep S/D junction depth (nm)

•Shallow
Shallow and highly doped Source/Drain region is desired
for high drive current and low DIBL
Jason Woo IWSG2009
 MOSFET with optimized
p S/D region
g

POLY
Conventional contact contact
Source Drain
bulk MOSFET

Si substrate

contact POLY contact

Source Drain
El
Elevated
d S/D
Bury oxide
SOI MOSFET
Si substrate
bt t

Jason Woo IWSG2009

 Silicide Schottky
y Barrier Height
g

400
Controlling ρc :

ontact Resistivitty [Ωcm ]

Midgap Silicide •

2
-77
350 LG = 53
3 nm 10 Midgap silicide →

}
ρc
Ωμm]

low-barrier silicide
300 Rcsd ⇒ ~ 60 % reduction
Resisstance [Ω

250 Rsd -88

10 i Rcsd & Rsd
in
200
Low-barrier Silicide
150 • Schottky barrier height
}

100
RovR -9
10
lowering will be an
ext effective way for Rcsd
50 Rdp reduction
0

Co
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ⎛ qφ ⎞
Schottky Barrier Height, ΦB [eV] ρ c ∝ exp⎜ b ⎟
⎜ N if ⎟
⎝ ⎠

37
 Advanced S/D Engineering
g g

300
Graded Junction
Resistancce [Ωμm]

270 LG = 53 nm Midgap Silicide

• Potential solutions for
240 advanced S/D Engineering:
Rov
210
B Profile
Box P fil Rext ⇒ Box-shaped highly-doped
180 Midgap Silicide R
dp ultrashallow SDE junction
150
Box Profile (i.e., laser annealing)
120
D Series R

Low-Barrier Silicide Rcsd

90
(ΦB = 0.2 eV) ⇒ Schottky Barrier lowering
60 (i.e., ErSi for NMOS, PtSi2
S/D

30 f PMOS
for PMOS, and d llower
0 bandgap Si1-xGex layer)
Source/Drain Engineering

38
Annealing Techniques Investigation
1100 700
TSPIKE TSPER
Spike Anneal 1050 600 tSPER
SPER
Temp (C))
on PAI substrates: 1000 500

Temp (C)
Tsper=650C ,700C
Tspike=1050C ,1075C 950 400
tSPER=1min
Ramp Rate=400C/s. 900 300

850 200
-4 -2 0 2 4 6 8 10 0 150 300 450 600
Time (s) Time (s)

Conv RTA 1000 RTA + SPER

1050 TRTA TSPIKE
Tspike~1075C 900 Tsper=650C ,700C
900 800
tSOAK=5s, 10s 700 TSPER tSPER=10min, 1min
Teemp (C)

750
Teemp (C) 600 tSPER
Max Ramp Rate 600 500 Tspike=850C, 950C
=80C/s.
80C/s 450 400 Max Ramp Rate
300 300
200 =80C/s.
150 100
0 100 200 300 400 0 150 300 450 600 750
Time (s) Time (s)
 Diffusion of As during anneal
1x1023
as-implanted As profile
1x1022 Conventional RTA (1075C, 5sec)
m-3)
Concenttration (cm

1x1021
Spike Anneal (1075C, 400C/s)
1x1020
SPER (650C,1min)
1x1019
Ge profile (PAI)
1x1018

1x1017

1x10160.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
Distance (µm)
SPIKE Annealing MORE SUITABLE THAN CONVENTIONAL RTA
or SPER for controlling
g dopant
p diffusion while maintaining
g an
acceptable degree of activation for arsenic
 Diffusion of B during anneal
1x1023
as-implanted B profile
1x1022 Conventional RTA (1075C, 5sec)
m-3)
Concenttration (cm

1x1021
Spike Anneal (1075C, 400C/s)
1x1020
Ge profile (PAI)
1x1019

1x1018
SPER
1x1017 (650C, 1min)

1x1016
0 00
0.00 0 01 0.02
0.01 0 02 0.03
0 03 0.04
0 04 0.05
0 05 0.06
0 06 0.07
0 07 0.08
0 08 0.09
0 09 0.10
0 10 0.11
0 11 0.12
0 12
Distance (µm)
SPIKE Annealing MORE SUITABLE THAN CONVENTIONAL RTA
OR SPER for controlling
g dopant
p diffusion while maintaining
g an
acceptable degree of activation for boron
 P-n junctions using spike anneal As=5e14

1.00E+22 Boron_as_implanted
As_as_implanted
1.00E+21
00 Activated Profile
D o pi n g (/cc)

1.00E+20

1.00E+19

1.00E+18
p
1.00E+17 Junction n
1.00E+16
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14
depth (um)
SRP results for Spike anneal process (1075C, 400C/s)
performed on PAI samples co-implanted with BF2 and As
(junction in the vertical direction). Very little movement from as
as-
implanted profiles
 Gate Oxide Thickness Scaling
• Reducing gate oxide thickness is known to improve:
- short channel effects
- subthreshold characteristics
- drive current and transconductance
- circuit speed
- reduce body effects
- reduce drain induced barrier lowering g
• Oxide scaling also leads to:
- increased gate leakage current, and standby power
- degraded dielectric reliability
- more severe impurity penetration effects
- oxide thickness uniformity control difficulties
- increased gate induced drain leakage (GIDL) and hot electron
effects
ff t
• High dielectric constant (high-K) thin films might provide solution since
physical thickness can be made thicker while maintaining high
capacitance

Jason Woo IWSG2009

 Thin Oxide Tunneling

Calculated (lines) and experimental (dots) for tunneling

currents from inversion layers through thin oxides.
Jason Woo IWSG2009
 Material requirement for high-K dielectrics

Criteria Requirements
EOT scalability < 10Å Dielectric constant > 15
Negligible FIBL effect Dielectric constant < 60
L k
Leakage currentt < 1A/cm
1A/ 2 B d
Bandgap > 5eV
5 V
Barrier height>1eV
Thermal stability No silicidation and
reduction
Hysteresis
y <20mV
Interface state density <1011/eVcm2
Mobility >85% of SiO2
Reliability >10 years

Jason Woo IWSG2009

 Higher k ⇒ smaller band gap ⇒ Potentially higher JG

Jason Woo IWSG2009

 Degradation in Electrical Performance of the High -k
Gate Stack
G 1.5 nm

S D 25 nm

κ = 3.9

G
19.2 nm

S D 25 nm

κ = 50

High -k Dielectrics => degraded electrical performance.

Gate Stacks,
Stacks High -k k on top of Low -k
k preferred
preferred.
Optimal Dielctric Thickness/Channel Length ratio is
required for better gate coupling.
Jason Woo IWSG2009
 Ratio of the gate-to-source/drain and gate-to-substrate
capacitances
p to the total ggate capacitance
p ((Ctot) vs the TK/L
1.0 CGSU B
CGS +CGD
08
0.8

Cx / Ctot
0.6

0.4

0.2
L=100nm
0
0 0.2 0.4 0.6 0.8
TK / L (Variation in TK)

• High TK/L ratio ⇒ Less CGSUB, Lesser gate control and more SCEs.
Hi h K ⇒ more fringing.
• High f i i

Jason Woo IWSG2009

 Suitable High-k Dielectrics

Jason Woo
Jack Lee IWSG2009
 Hih-k Gate Leakage Current

For the
F h same EOT,
EOT high-K
hi h K samples
l exhibit
hibi
much lower leakage current
Jason Woo IWSG2009
 Issues: Channel Mobility

Jason Woo IWSG2009

 First order Device Model of Scaled Transistors

Sah-Pao model of long channel

G MOS I-V characteristics was
S D W ⎛ VD ⎞
ID ≅ μ n C ox ⎜ VG − VTH − ⎟ VD
L ⎝ 2 ⎠
N+ N+
Linear Region
NA
2
ID ≅ W μn Cox ⎜VG − VTH ⎟
⎛ ⎞
2L ⎝ ⎠
S b
Sub
Saturation Region

This, of course, assumes both gradual channel approximation and

pinch-off approximation. In reality, there is not a pinch-off region,
but ID → IDsat because v ↑ vsat.
Jason Woo IWSG2009
Piecewise approximation of saturation velocity

μeff E
v= E < Esat
1 + ( E / Esat )
= vsat E > Esat

μeff Esat
i.e., vsat =
2
2 sat
2v
or Esat =
μeff

Jason Woo IWSG2009

 With this approximation (again, using gradual channel
approximation and ignoring the variation of the bulk
depletion charge across the channel):
μeff E ( y )
ID = W Cox ⎡⎢VG′ − V ( y ) ⎤⎥
⎣ ⎦ ⎛ E ( y) ⎞
1 + ⎜⎜ E ⎟⎟
⎝ sat ⎠
where
VG′ = VG − VTH

That is
I D Esat
E( y) =
Esat W μeff C ox ⎣⎡VG′ − V ( y ) ⎦⎤ − I D

Jason Woo IWSG2009

To find the I-V in the saturation region, note that ID → IDsat when
velocity approaches vsat near L.
L

⇒ I D = vsat W Cox (VG′ − VDsat )

⎛ V ⎞
W
= μeff Cox ⎜⎜VG − Dsat ⎟⎟V Dsat
′ 1
L
⎝
2 ⎠
1 +V Dsat / Esat L

After some algebra, we get:

Esat LVG′
VDsat =
Esat L + VG′

Jason Woo IWSG2009

 with E(L)=Esat, V(L)=VDsat, and ID=IDsat,

1
I Dsat = W μeff C ox (VG′ − VDsat ) Esat
2 2
⎛ ′ ⎞
⎜ VG ⎟
= W vsat C ox ⎝ ⎠

VG′ + Esat L
⎛ ′ ⎞2
⎜ VG ⎟
⎝ ⎠
= W vsat C ox
′ 2vsat
V + L
G
μeff

i.e., If EsatL is small, I Dsat ∝VG′ i.e., IDsat to first order ∝(V'G)

If EsatL is large, I Dsat ∝ ( ′ 2

VG ) (long channel characteristics)
Jason Woo IWSG2009
 What Can be Done to Improved
Ion while
hil lowering
l i VDD?

Jason Woo IWSG2009

 Limiting Case: Ballistic Transistors

Jason Woo IWSG2009

 In Most Cases Mobility is still important: How to
improve Mobilities?
Strained Silicon

Jason Woo IWSG2009

 III-V Channel FETs

Jason Woo IWSG2009

 InGaAs Channel n-MOSFETs

Jason Woo
Han Zhao, et. Al. APLIWSG2009
2009
 DIGITAL CIRCUIT REQUIREMENTS
High Ion/Ioff ratio
Low intrinsic delay y CgVdd/Ion
Improved DIBL and subthreshold swing (S)
Low parasitic resistances and capacitances

Most of the devices (PDSOI, FDSOI, Double Gate,

UTB) are mainly studied and optimized for digital
requirements
What about their analog performance
Which device is best suited for analog
applications
Alternative Device Architectures?

Jason Woo IWSG2009

 ANALOG CIRCUIT REQUIREMENTS
High Transconductance (gm) and high output
resistance (Routt)
High DC Gain gm x Rout
High Cut
Cut-Off
Off Frequency (fT)
High gm/Id ratio
L Vth mismatch
Low i t h e.g. in
i differential
diff ti l pair
i
High signal swing and Linearity
Low Noise

Jason Woo IWSG2009

 ANALOG DESIGN TRADE-OFFS
Oxide Thickness (Tox)
Reduced Tox ⇒ Increased gate control, Improved SCE.
Higher gm as well as higher Rout
Increases gate leakage
leakage, degrades input resistance
Thinner oxides also limit supply voltages ⇒ signal swing is reduced

Channel Length (Lg)

Lower Lg better gm and fT (ultimately limited by vsat/2Leff)
But worse Short Channel Effects (SCE) ⇒ Reduction in Rout
Bulk Doping(NA)
Higher bulk doping means improved SCE; hence higher Rout
However gm degradation due to reduced effective mobility
Also, low signal swing (high Vth) and higher Vth mismatch

Source Drain Engineering

Rout improvement with reduction in Xj because of improved SCE
gm drops due to increased S/D resistance (specially Rs)

Jason Woo IWSG2009

 Intrinsic Gain vs. fT

100
00
Tox = 1.5nm
Ids = 100μA/μm
80 Vds = 0.8V
Lg = 150nm
ntrinsic Gaiin

60 Lg = 100nm
Lg = 70nm
Lg = 50nm
40
In

N+poly gate
20 Vth=0.15-0.25V
Vth=0.25-0.40V
0
0 50 100 150 200
fT (GHz)

Jason Woo IWSG2009

 Output resistance
Early Voltage :
(1 + ( αLn)/⁄ l)
VV
AA= VAsat + ------------1---------------------------1
-----------------------------------------
⎛------------------- + --------------------- + -----------1---------- )
⎝V
ACLM VADIBL VASCBE

( V ds – V dsat )
ACLM = ( E s attL g ( 1 + θ Vgtt ) + V gtt) --------------------------------------
V
V -
E s at l (1 + θ V gt ))

(EsatLg(1 + θVgt) + Vgt)

VADIBL = ------------------------------------------------------------------------------------------------
′
θ (Lg)(1 + (2EsatLg(1 + θVgt)) ⁄ Vgt))

( (V – Φ ) ⁄ ( V – Φ + V )) ( exp ( L ⁄ l )– 1 ) + ( 1 – exp (–L ⁄ l ))

θ’θ (L g) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
bi s bi s ds
2
g t g t
-
4 sinh (L g ⁄ 2l t )

2
lt = 3Tox (X dep ⁄ η ) llα
l 3 X j T X dep
, ox

Jason Woo IWSG2009

 Effect of Channel Length on gm/Ids vs. Intrinsic Gain
T d ff
Trade-offs

80
8.0
Lg =150nm
7.0 Lg =100nm
Lg =70nm
Lg =50nm
50nm
gm/IIds (V-1)

6.0

Vds=0.8V
50
5.0 Ids=100μ A/μm
Tox =1.5nm
4.0 N+poly gate
Vth=0.15-0.25V
Vth=0.25-0.40V
3.0
0 20 40 60 80 100
Intrinsic Gain

Jason Woo IWSG2009

 Effect of Channel Length on VIP3 vs. fT Trade-
offs
ff
3.0
Vth=0.15-0.25V
Vth=0.25-0.40V
Lg=150nm
150
2.5 Lg=100nm
Lg=70nm
Lg=50nm
VIP3 ((V)

20
2.0 Vds
d =0
0.8V
8V
Ids=100μA/μm
Tox =1.5nm
1.5

1.0
0 50 100 150 200
fT (GHz)
(GH )

Jason Woo IWSG2009

 Impact of oxide thickness on intrinsic gain vs. fT trade-
offs
ff

100
Empty: Tox =2.0nm Lg=150nm
Filled: Tox =1.5nm Lg=100nm
80 Lg=70nm
Lg=50nm
Inntrinsic gainn

60 Vth=0.15-0.25V
Vth=0.25-0.40V
40

20 Vds = 0.8V
μ μ
Ids = 100μA/μm
0
20.0 70.0 120.0 170.0
fT (GHz)

Jason Woo IWSG2009

 Effect of Ids on gain-fT trade-offs for Lg=150nm and
50nm
50

200
Ids = 30μA
Tox =1.5nm Ids = 60μA
Vds =0.8V Ids = 100μA
150 Ids = 150μA
Intrrinsic Gainn

Ids = 200μA

100
Lg=50nm
50

50
Lg=150nm

0
0 50 100 150 200
fT (GHz)

Jason Woo IWSG2009

 DIBL in FDSOI MOSFET
1. Characteristic Length in FDSOI:

(ε T C
lt = si si fbb) ⁄ ( η C ox Cbox )

DIBL depends on silicon thickness. It has very weak dependence on channel doping
unlike in the bulk MOSFET

2. For Sub-100nm FDSOI MOSFETs, Drain acts like a virtual substrate

⎛ ΔV ⎞ C ( 0) C
DIVS B = ⎜ ----------th BD--------------------b------------
---⎟ = ------------------
⎝ ΔVds ⎠ Cox ( C BD( 0 ) + Cb )

Ernst, et. al
 High Frequency Rout in PDSOI MOSFET
DC Kink Effect:
V t h = Vth0 – γ ( 2Φ B – 2Φ B – Vbs)

Ids and gm expressions modified taking into account the change in threshold voltage
with self-body bias
AC Kink Effect:
Effect of Drain-to-Body coupling on output resistance at high operating frequency
I
dsat
V Acou pled = ----------------------------------------------------------- -
⎛∂Ids ∂V th ∂VBS⎞
⎜ • • ⎟
∂
⎝ th V ∂ V ∂V ⎠
BS ds
I
VAcoupled = --------------------------------------------dsat
---------------------------------------------------
⎛ γ C BD ⎞
⎜ g m • --------------------------------------- • ------------------------------- ⎟
⎝ ( 2 2Φ – V ) C BS + C BD ⎠
b bs

Jason Woo IWSG2009

High Frequency Rout in FDSOI MOSFET
AC Kink Effect:
Reduced Drain-to-Body coupling due to interaction between the back-front interfaces

I
dsat
V Acoupled = -----------------------------------------------------------
-
∂I
⎛ ds ∂V th • BS⎞ ∂V
⎜ • ⎟
⎝∂ V th ∂ V BS ∂ Vds ⎠

I
VAcoupled
p = ----
------
------
------
------
------
------
------
------
------
------
------------
----------dsat
------------------------------------------------------------------------------------------
⎛ ⎞
⎜ ⎟
⎜ g • ⎛⎜-----------------------------------------------------
γ Cb ⎞ CBD
- + ------------------------ ⎟ • ------------------------------------------------------------- ⎟
⎜ m ⎝2 2φ – V Cb + Cox ⎠ C ox Cb ⎟
⎜ B bs0 – V bs C + C + ----------------------- ⎟
⎝ BS BD C + C ⎠
ox b
 Effect of Channel Length Scaling of Analog Performance
100
Vth=0.25 - 0.35 V Lg =60nm
Lg =100nm
Vth=0.25 – 0.35 V Lg=150nm
80 For Mid ggapp ggate Lg=250nm
nsic Gain FDSOI MOSFET
Black: Bulk
Green: PDSOI
60 Blue: FDSOI
Ids =100μA/μm
Vds =00.8V
8V
Intrin

40 Xj=10nm
TSi =15nm
Tox =1.5nm
f oper=1GHz
20

0
0 50 100 150 200
fT (GHz)
Channel Doping ↑⇒gm ↓ and Rout ↑ in Bulk MOSFETs
Channel Doping ↑⇒gm ↓ in SOI MOSFET; However Rout ↓ in
PDSOI MOSFET while Rout doesn’t improve much in FDSOI
Gain-fT curves show opposite trends in Bulk and SOI
technologies
Jason Woo IWSG2009
 Effect of Silicon thickness on Rout in FDSOI
80
NA=1e17cm -3 Vds =0.8V Lg=60nm
Tox=1.5nm
1e5
e5 Lg=100nm
60

%Chaange in Routt
Lg =150nm
KΩ-μm)

40 Lg =250nm
Rout (K

20

0
1e4
1 4 15 20 25 30 35
15 20 25 30 35
Tsi (nm) Tsi (nm)
Long g channel FDSOI MOSFET: Rout improves
p for thin
silicon thickness due to reduction in drain-to-body
coupling
Short channel FDSOI MOSFET: Routt improves with
thinning down silicon film due to reduction in DIBL.
Jason Woo IWSG2009
 Excess Low Frequency Noise in
SOI
Gate
Source Drain

1/f
1/f
2qISB
2qIii

Buried Oxide

Jason Woo IWSG2009

 Low Frequency Noise
Characteristics
0.8
10 -9 10-9
Gate Noise

Gate Noise

DS (mA)
10-10 10-10 0.4
N

ID
10-11 10-11
0
10-12 10-12 0 1.0 2.0
Power SVG (V2/Hz))

Power SVG (V2/H

VDS VDS (V)
10-13 VDS 10-13
11. 0.75V
0 75V 1.. 0.75 V 4
5
10-14 2. 1.0V 10-14 2. 1.0 V
3. 1.2V 3. 1.2 V
4. 1.4V 4. 1.4 V
10-15 5. 1.5V 10-15 5. 1.5 V
6. 1.75V 6. 1.75 V
Hz)

1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M

Frequency (Hz)
Frequency (Hz)

PDSOI FDSOI

Jason Woo IWSG2009

 Correlation of LF Noise and DC Kink

10M PD FD nMOS (A)

p
pMOS ((B))
1M PD
Frequency (Hz)

nMOS (B)
100k

10k PD
PD pMOS (A) nMOS (A)
1k
|VGT | = 0.2 V
100 f0 PD
fkink nMOS (A)
10
-3.0 -2.5 -2.0 -1.5 1.0 1.5 2.0

Drain bias, VDS (V)

Jason Woo IWSG2009
 What can we do?

• Backgate bias?
• DG devices?
• Other
Oth d device
i architectures?
hit t ?

Jason Woo IWSG2009

 Comparison of Bulk, DG and UTB MOSFETs

Double Gate devices (thin and low doped Si) show the best performance in terms
of Gain and fT, UTB FETs are worse than Bulk devices for longer
g channel lengths
g
but for lower channel lengths they start showing better performance

Jason Woo IWSG2009

 EFFECT OF ACTIVE BODY BIAS
0.3
NMOS
Tox = 36Å

DTMOS
h(Vbs) (V)
Lg =1μm
0.2
Vth(0)-Vth

0.1

Lg = 0.14μm

0.0
0.0 0.2 0.4 0.6
Vbs (V)
Change in threshold voltage as a function of body bias for two different gate lengths, Tox =
36Å.

Jason Woo IWSG2009

 Output and Subthreshold Characteristics

2.5 10-3
V b = 0V NMOSFET NMOS
V b = 0.3V Lg = 0.14 μm Lg = 0.14 μm
V b = 0.6V
0 6V 10-4
2.0 Vds = 1.6V

Ids (A/ μ m)
10-5
mA/μm)

V gs = 1.2V
1.5
10-6
Ids (m

1.0
10-7
V gs = 0.9V Vb = 0V
0.5 10-8 Vb = 0.3V
Vb = 0.6V
0 6V
0.0 10-9
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V ds (V) Vgs (V)

• Current drive is increased by 50% for Vb=0.6V

• Increased performance gain comes at the cost of increased
off-state current
• Initial Vth and be adjusted accordingly
Jason Woo IWSG2009
 Device Characteristics
0.4
Ids same at same Lg 10 7
V b=0V
Vds = 0.6V V b=0.3V
03
0.3 V b=0.6V
10 6
gm (mS/μ m)

Tox = 36Å

Roout (Ω / μ m)
DTMOS

Rin (Ω / μm
10 5
DTMOS
0.2 10 5
Vb =0V
V b=0.3V
=0 3V

m)
V b=0.6V
0.1 DTMOS NMOS 10 4
10 4 Tox = 36 Å
V ds = 0.6V
0 10 3
0 0.5 1.0 1.5 2.0 0 20 40 60 80
Ids ( μA/ μm)
Lg ( μm)

• Th
The ttransconductance
d t iimproves iin th
the DTMOS case, b
butt nott
with static well bias conditions
• Rin decreases with increasing Vgt, increasing loading on
previous stage
Jason Woo IWSG2009
 Short Channel Characteristics
NMOS 0.5
0.6 Tox = 25Å Vb=0V
0.4
Vb=0.3V
=0 3V 102
0.5 Vb=0.6V
DTMOS

DIBL ((mV /V )
V th,,lin (V)

0.3

Δ V tth (V)
0.4

0.3 02
0.2
10
0.2 Vb=0V 0.1
Vb=0.3V
01
0.1 Vb=00.6V
6V 00
0.0 NMOS
DTMOS Tox = 36Å
0.0 -0.1 1
0.0 0.2 0.4 0.6 0.8 1.0 0.1 1.0
Lg (μm) Lg (μ m)

• Both the Vth roll-off and DIBL are reduced as the active body
bias increases
• Improvement in SCEs due to the resuced drain electric field
coupling
Jason Woo IWSG2009
 INTRINSIC GAIN COMPARISON
1000 Ids same at same Lg
Ids same at same Lg
nsic gain (gm×Rout)

Vds =0.6V Vds = 0.6V

c gain (gm×Rout)
100
100
NMOS
NMOS
Tox =25Å Tox = 36Å

Intrinsic
10
Intrin

10
Vb=0V
Vb=0V
Vb=0.3V Vb=0.3V
Vb=0.6V Vb=0.6V
DTMOS DTMOS
1 1
0.1 1 0.1 1
Lg (μm) Lg (μm)

DTMOS shows the highest improvement (2x), particularly at small channel lengths
due to improved
i gm as well as improved
i Rout (50%)
( 0%) in
i the thick
i Tox devices
i
The Vb = 0.6V case shows improvement upto 50% in the intrinsic gain
Here too Active well bias or DTMOS configuration improves the device
performance
f if the
th original
i i l intrinsic
i t i i device
d i performance
f is
i degraded
d d d by
b severe SCE

Jason Woo IWSG2009

 Summary
• Continued CMOS Scaling Posted Significant
g
Challenges
Gate Leakage
Performance Degradation
SCE Behavior
Much Degraded Analog Characteristics

• Need Innovative solutions --- Great

Opportunities for Research

Jason Woo IWSG2009

Jason Woo IWSG2009
Jason Woo IWSG2009