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Edge connectivity:
Vertex Connectivity:
Separable Graphs:
Planar Graphs:
Kuratwoski’s graphs:
Incidence Matrix A:
Circuit Matrix B:
Path Matrix:
Adjacency Matrix:
Planar Graphs:
A graph G is said to be planar if it can be written on a plane such that no two of its edges
intersect anywhere other then the end vertex. Such a representation of planar graph is
called planar embedding. This planar embedding need not be unique.
Detection of Planarity:
Step 1:
Since the graph in planar if and only if each of its components is planar, it is
sufficient to check for each component. Hence for each component of G go to step 2.
Step 2:
Each graph is planar if and only if each of its block is planar. Hence for each
block of G do the step 3.
Step 3:
Between two vertices if it is possible to write an edge without crossing with each
other, then it is also possible to write more edges between the same pair of vertices
without crossing one another. Hence parallel edges of self-loops do not affect the
planarity. Eliminate edges in parallel by removing all but one edge between pair of
vertex goes to step 4.
Step 4:
Remove all self-loops.
Step 5:
Two edges are said to be in series if they have exactly one vertex of degree two in
common. Merging two parallel edges does not affect the planarity. Therefore eliminate
all edges in series.
Repeated application of the above steps yields one of the following (p, q) graphs
1. a single edge or
2. a complete graph on four vertices or
3. A non-separable, simple graph with p 5 and q 7 .
Check for the planarity of the following graph by the method of elementary
transformation.
Solution:
Step 1:
Does not apply, because the graph is connected.
Step 2:
Separating the blocks of G.
Step 3:
Removing self – loops and parallel edges.
Step 4: Merging the series edges.
The final graph contains three components. Largest component contains 5 vertices.
Other two are K2 and K3. We know that K2 and K3 are planar. We need to verify only
the largest component. If we observe the largest component, it does not contain a graph
isomorphic to K5 or K3, 3. Therefore this block is also planar.
INCIDENCE MATRIX:
Example 1:
e4 e2
e6
v4 e3 v3
e1 e2 e3 e4 e5 e6
v1 1 0 0 1 0 0
v2 1 1 0 0 1 0
A v3 0 1 1 0 0 1
v 4 0 0 1 1 0 0
v5 0 0 0 0 1 1
Example 2:
e5
v2 v4
e6 e7 e3
v1 e4 v5
The incidence matrix of the graph G is given by
e1 e2 e3 e4 e5 e6 e7 e8
v1 0 0 0 1 0 1 0 0
v2 0 0 0 0 1 1 1 1
v 0 0 0 0 0 0 0 1
A 3
v 4 1 1 1 0 1 0 0 0
v5 0 0 1 1 0 0 1 0
v6 1 1 0 0 0 0 0 0
Observations on incidence matrix:
1. We have each edge containing two end vertices (say x and y). Therefore each
column contains 1’s in exactly two places (in rows x and y).
2. The number 1 each row represents the edge incident form the vertex
corresponding to the row. Therefore the sum of 1’s in each row represent the
degree (the number of edges incident with the vertex) of a vertex corresponds to
the row.
4. If a row contains 1’s in exactly one place, then the vertex corresponds to the row
is a pendent vertex and the edge corresponds to the column at which 1 appear is a
pendent edge.
9. Two graphs are isomorphic if and only if the permutation of columns and/or rows
of the incidence matrix of the other can obtain the incidence matrix of one graph.
10. The rank of an incidence matrix of a connected simple graph of order n is n-1.
# Verify that the rank of the incidence matrix of the following graph G is one less
than the order of G.
1 2
3 4 5
Solution:
The order of the given graph G is n = 5. The incidence of the matrix is given by
1 1 0 0 0 1 1 0 0 0
1 0 1 0 0 0 1 1 0 0
A(G ) 0 1 0 1 0 ~ 0 1 0 1 0 ( R 2 R1 R2 )
0 0 1 1 0 0 0 1 1 0
0 0 0 0 1 0 0 0 0 1
1 1 0 0 0
0 1 1 0 0
~ 0 0 1 1 0 ( R 3 R2 R3 )
0 0 1 1 0
0 0 0 0 1
1 1 0 0 0
0 1 1 0 0
~ 0 0 1 1 0 ( R 4 R3 R4 )
0 0 0 0 0
0 0 0 0 1
CIRCUIT MATRIX:
Example 1:
Let G be a graph with the vertex set V (G ) v1 , v2 , v3 , v4 , v5 and
E(G) e1 , e 2 , e 3 , e 4 , e 5 , e 6 . Let the diagrammatic representation of G be as follows.
G:
v1 e1 v2 e5 v5
e4 e2
e6
v4 e3 v3
The circuits of G are:
C1: v1 – e1 – v2 – e2 – v3 – e3 – v4 – e4 – v1
C2: v2 – e5 – v5 – e6 – v3 – e2 – v2
C3: v1 – e1 – v2 – e5 – v5 – e6 – v3 – e3 – v4 – e4 – v1.
1 1 1 1 0 0
B(G ) 0 1 0 0 1 1
1 0 1 1 1 1
Example 2:
G:
v1 e1 v2
e4 e2
e5
v4 e3 v3
4. The number of 1’s in a row is equal to the length of the corresponding circuit.
B (G1 ) 0 0
0 B (G 2 ) 0
B (G )
0 0 B (Gk )
8. Two graphs have the same circuit matrix if and only if there exists a circuit
correspondence between the graphs.
9. For any graph G, A(G )B (G )T B(G )A(G )T =0(mod2), whenever the
columns are arranged in the same order.
# Verify the rank of circuit matrix of the following (p, q) – graph shown in figure
below is q - p + 1 in (mod 2).
Solution:
1 0 1 1 0 1 1 1 0 1 1 0 1 1
B(G ) 1 0 1 0 1 0 1 ~ 0 0 0 1 1 1 0
( R2 R2 R1 )
0 0 0 1 1 1 0 0 0 0 1 1 1 0
1 0 1 1 0 1 1
~ 0 0 0 1 1 1 0 ( R3 R3 R2 )
0 0 0 0 0 0 0
Therefore rank of B(G) = 2.
Now, G contains 6 vertices and 7 edges, hence it is a (6,7) – graph. Consider q- p +1
= 7 -6 +1 = 2= B(G). Hence verified
Example 1:
d e
ab bc bdde ac dc ce
FC1 1 1 0 0 1 0 0
B f (G ) 0 1 1
FC 2 0 0 1 0
FC3 0 1 1 1 0 0 1
# Write down the fundamental circuit matrix B f for the graph of figure shown
below. Also express B f = [ I : Bt ] , by taking any spanning tree T of G.
Solution:
b d
e c
FC1: a – b- c- d – a
FC2: b – c – f – e – b
FC3: c – f – e – c.
ab eb ec da bc cd cf fe
FC1 1 0 0 1 1 1 0 0
B f FC 2 0 1 0 0 1 0 1 1
FC 3 0 0 1 0 0 0 1 1
Adjacency Matrix
2. Diagonal elements of X(G) are all zero if and only if G does not have a loop.
3. We get no information about the parallel edges , thus we avoid parallel edges
in the definition of X(G).
4. Number of vertices having self loop equal to number of 1’s in the diagonal
entries.
7. For every symmetric square binary matrix X there always a graph G such that
X(G) = x.
8. ijth entry of [X(G)]m gives number of walks of length m from ith vertex to the
jth vertex in the graph G.
9. Number of 1’s in a row gives the degree of the vertex corresponds to the row
counting diagonal elements twice. In general, deg (v) = number of 1’s in a off
diagonal row + 2 x diagonal entry.
X (G1 ) 0 0
0 X (G 2 ) 0
X (G )
0 0
X (Gk )