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8 7 6 5 4 3 2 1

m
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION

J16 MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE

.co
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
13 0002231663 ENGINEERING RELEASED 2013-08-10

LAST_MODIFIED=Sat Aug 10 21:13:36 2013

fix
(.csa) Date (.csa) Date

D Page Contents Sync Page Contents Sync D


TABLE_TABLEOFCONTENTS_HEAD

1 10/18/2012 TABLE_TABLEOFCONTENTS_HEAD

55 06/03/2013
1 Table of Contents J16_MAX 49 I and V Sense(Continued) J16_TONY

se TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM
2
3
4
2

4
BOM Configuration
DEBUG LEDS
Holes/PD parts
MASTER

J16_MLB_IG

J16_DG
04/21/2013

05/01/2013

04/21/2013
TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM
50
51
52
56

60

61
Temperature Sensors
System Fan
AUDIO: CODEC/REGULATORS
J16_FIYIN

J16_MLB_IG

J16_MLB_IG
06/11/2013

05/01/2013

05/01/2013
.ro
5 04/21/2013 62 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

5 CPU DMI/PEG/FDI/RSVD J17 53 AUDIO: HEADPHONE AMP J16_MLB_IG


6 04/21/2013 63 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

6 CPU Clock/Misc/JTAG/CFG J17 54 AUDIO: LEFT SPKR AMP J16_MLB_IG


TABLE_TABLEOFCONTENTS_ITEM

7 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

64 05/01/2013
7 CPU DDR3 Interfaces J17 55 AUDIO: RIGHT SPKR AMP J16_MLB_IG
TABLE_TABLEOFCONTENTS_ITEM

8 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

65 05/01/2013
8 CPU Power J17 56 AUDIO: Jack, Mikey, CHS Switch J16_MLB_IG
w

9 04/21/2013 66 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

9 CPU Ground J17 57 Audio: Spkr/Mic Conn. J16_MLB_IG


TABLE_TABLEOFCONTENTS_ITEM

10 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

67 05/01/2013
10 CPU DECOUPLING J17 58 AUDIO: Detects/Grounding J16_MLB_IG
w

11 04/21/2013 68 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

11 PCH RTC/HDA/JTAG/SATA/CLK J17 59 AUDIO: Speaker ID J16_MLB_IG


12 04/21/2013 69 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

12 PCH DMI/FDI/PM/GFX/PCI J17 60 Power Connectors / VReg G3Hot J16_MLB_IG


TABLE_TABLEOFCONTENTS_ITEM

13 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

70 05/01/2013
13 PCH PCI-E/USB 61 VReg CPU VCC Cntl
w

J17 J16_MLB_IG
14 04/21/2013 71 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

14 PCH GPIO/MISC/NCTF J17 62 VReg CPU VCC Phases J16_DG


TABLE_TABLEOFCONTENTS_ITEM

15 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

73 06/17/2013
15 PCH Power J17 63 VReg VDDQ S3 J16_ROSSANA
16 04/21/2013 74 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

16 PCH Grounds J17 64 VReg PCH/GPU/TBT 1V05 S0 J16_DG


17 04/21/2013 76 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

17 PCH DECOUPLING 65 VReg 3.3V S5/5V S4


C TABLE_TABLEOFCONTENTS_ITEM

18
18
CPU & PCH XDP
J17

MASTER
04/21/2013
TABLE_TABLEOFCONTENTS_ITEM

66
77
VReg GPU VDDQ
J16_MLB_IG

J16_DG
04/21/2013 C
TABLE_TABLEOFCONTENTS_ITEM

19 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

78 06/17/2013
19 Chipset Support J17 67 VReg GPU Core J16_ROSSANA
20 04/21/2013 81 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

20 Project Chipset Support MASTER 68 LCD Backlight Driver (LP8561) J16_MLB_IG


21 04/21/2013 84 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

21 CPU Memory S3 Support J17 69 FET-Controlled S0 and S4 MASTER


TABLE_TABLEOFCONTENTS_ITEM

22 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

85 05/01/2013
22 DDR3 VREF MARGINING J17 70 PM Regulator Enables MASTER
23 05/01/2013 86 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

23 DDR3 SO-DIMM Connector A J16_MLB_IG 71 PM Power Good J16_MLB_IG


25 05/01/2013 87 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

24 DDR3 SO-DIMM CONNECTOR B J16_MLB_IG 72 KEPLER PCI-E J16_DG


27 05/01/2013 88 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

25 DDR3 ALIASES AND BITSWAPS J16_MLB_IG 73 KEPLER CORE/FB POWER J16_DG


28 05/01/2013 90 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

26 Thunderbolt Host (1 of 2) J16_MLB_IG 74 KEPLER FRAME BUFFER I/F J16_DG


TABLE_TABLEOFCONTENTS_ITEM

29 05/01/2013 TABLE_TABLEOFCONTENTS_ITEM

92 04/21/2013
27 Thunderbolt Host (2 of 2) J16_MLB_IG 75 GDDR5 Frame Buffer A J16_DG
30 05/01/2013 93 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

28 Thunderbolt Power Support J16_MLB_IG 76 GDDR5 Frame Buffer B J16_DG


32 05/01/2013 96 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

29 Thunderbolt Connector A J16_MLB_IG 77 KEPLER EDP/DP/GPIO J16_DG


33 05/01/2013 97 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

30 Thunderbolt Connector B J16_MLB_IG 78 KEPLER GPIOS,CLK & STRAPS J16_DG


34 04/21/2013 99 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

31 TBT DDC Crossbar J16_DG 79 KEPLER PEX PWR/GNDS J16_DG


35 05/01/2013 100 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

32 AIRPORT/BT J16_MLB_IG 80 Power Connectors/Aliases MASTER


37 05/01/2013 102 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

33 SATA/SSD Connectors MASTER 81 Signal Aliases MASTER


TABLE_TABLEOFCONTENTS_ITEM

38 05/01/2013 TABLE_TABLEOFCONTENTS_ITEM

104 04/21/2013
34 HDD Connector J16_MLB_IG 82 Unused Signal Aliases MASTER

B
39 05/01/2013 105 04/21/2013
B
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

35 ETHERNET PHY (CAESAR IV) J16_MLB_IG 83 Functional / ICT Test J16_DG


40 05/01/2013 110 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

36 Ethernet Support & Connector J16_MLB_IG 84 J16 RULE DEFINITIONS J16_DG


TABLE_TABLEOFCONTENTS_ITEM

41 05/01/2013 TABLE_TABLEOFCONTENTS_ITEM

111 06/03/2013
37 SD READER CONNECTOR J16_MLB_IG 85 DDR3 Constraints J16_NICK
42 05/01/2013 112 06/03/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

38 Camera Controller J16_MLB_IG 86 CPU PCIe Constraints J16_NICK


43 05/01/2013 113 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

39 Camera Controller Support J16_MLB_IG 87 PCH PCIe/DMI Constaints J16_DG


44 05/01/2013 114 05/30/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

40 Internal DP Support J16_MLB_IG 88 SATA/FDI/XDP Constraints J16_NICK


45 04/21/2013 115 05/30/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

41 Internal DP MUXing J16_DG 89 PCH and BR Constraints J16_NICK


TABLE_TABLEOFCONTENTS_ITEM

46 05/01/2013 TABLE_TABLEOFCONTENTS_ITEM

116 05/30/2013
42 EXTERNAL USB PORTS A & B J16_MLB_IG 90 USB/Ethernet/SD Constraints J16_NICK
47 05/01/2013 117 06/03/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

43 EXTERNAL USB PORTS C & D J16_MLB_IG 91 SMBus/Sensor Constraints J16_TONY


TABLE_TABLEOFCONTENTS_ITEM

50 05/01/2013 TABLE_TABLEOFCONTENTS_ITEM

118 04/21/2013
44 SMC J16_MLB_IG 92 VReg Constraints J16_DG
51 06/11/2013 119 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

45 SMC Support J16_TONY 93 CPU VReg Constraints J16_DG


TABLE_TABLEOFCONTENTS_ITEM

52 06/17/2013 TABLE_TABLEOFCONTENTS_ITEM

120 04/21/2013
46 SPI and Debug Connector J16_TONY 94 Platform VReg Constraints MASTER
TABLE_TABLEOFCONTENTS_ITEM

53 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM

121 04/21/2013
47 SMBus Connections J16_DG 95 TBT/DP Constraints MASTER
54 06/11/2013 122 05/30/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

48 I and V Sense J16_TONY 96 GDDR5/GPU Constraints J16_NICK


123 04/21/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM
97 BLC Constraints J16_DG

A A
DRAWING TITLE
SCHEM,MLB,J16
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=J16
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 123
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST_MODIFIED=Sat Aug 10 21:13:36 2013 DRAWING
IV ALL RIGHTS RESERVED 1 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Main BOM Variants Bar Code Labels / EEEE #’s


TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS TABLE_5_HEAD

TABLE_BOMGROUP_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
985-0035 PCBA,MLB,DEV,J16 DEVELOPMENT,J16_DEVEL TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9RR CRITICAL EEEE:F9RR
639-4281 PCBA,MLB,107GX,VRAM_HYNIX,BETTER,J16 J16,J16_COMMON,CPU:BETTER,GPU:107GX,FBA,FBB,FB:BOTH_HYNIX,SSD:Y,EEEE:F9RR TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9T5 CRITICAL EEEE:F9T5
639-4286 PCBA,MLB,107GX,VRAM_ELPIDA,BETTER,J16 J16,J16_COMMON,CPU:BETTER,GPU:107GX,FBA,FBB,FB:BOTH_ELPIDA,SSD:Y,EEEE:F9T5 TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9T3 CRITICAL EEEE:F9T3
639-4282 PCBA,MLB,107GX,VRAM_HYNIX,CTO,J16 J16,J16_COMMON,CPU:CTO,GPU:107GX,FBA,FBB,FB:BOTH_HYNIX,SSD:Y,EEEE:F9T3 TABLE_5_ITEM

825-7896 1 MLB LABEL,2D EEEE_F9RW CRITICAL EEEE:F9RW


D
TABLE_BOMGROUP_ITEM

639-4287 PCBA,MLB,107GX,VRAM_ELPIDA,CTO,J16
D J16,J16_COMMON,CPU:CTO,GPU:107GX,FBA,FBB,FB:BOTH_ELPIDA,SSD:Y,EEEE:F9RW

Schematic / PCB #’s


TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


BOM Groups 051-9889 1 SCH,MLB,J16 SCH CRITICAL J16
TABLE_5_ITEM

TABLE_BOMGROUP_HEAD TABLE_5_ITEM

BOM GROUP BOM OPTIONS 820-3482 1 PCBF,MLB,J16 PCB CRITICAL J16


TABLE_BOMGROUP_ITEM

J16_COMMON COMMON,ALTERNATE,J16_COMMON1,J16_COMMON2,J16_PROGPARTS,J16_PRODUCTION
TABLE_BOMGROUP_ITEM

J16_COMMON1 XDP,SPEAKERID,TBTHV:P12V,CPUVCC:3PHASE,EXT_GPU:YES,VDDQ:P1V5

J16_PROGPARTS SMC:PROG,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG
TABLE_BOMGROUP_ITEM

GPU & VRAM


TABLE_BOMGROUP_ITEM

TABLE_5_HEAD

J16_DEVEL XDP_CONN,LPCPLUS,DDRVREF_DAC,DEVEL_SENSORS,DEVEL_AUDIO ADD ’J16_PRODUCTION’ AT REVA RELEASE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

DEVEL_SENSORS AP_ISNS:Y,HDD_IVSNS:Y,TEMPSNSDEV 337S4427 1 IC,GPU,NV,GK107-GX,PS,926MHZ,2.5GHZ U8700 CRITICAL GPU:107GX


TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

J16_PRODUCTION AP_ISNS:N,HDD_IVSNS:N 333S0630 4 IC,GDDR5,2GBIT,64MX32,5GBPS,GEMMA-DIE U9200,U9250,U9300,U9350 CRITICAL FB:BOTH_HYNIX


TABLE_5_ITEM

333S0695 4 IC,GDDR5,2GBIT,64MX32,5GBPS,B-DIE U9200,U9250,U9300,U9350 CRITICAL FB:BOTH_ELPIDA

C C
CPUs
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM
Alternates
337S4610 1 HSW,SR14J,PRQ,C0,2.9G,65W,4+2,1.15,6M,LGA CPU CRITICAL CPU:BETTER TABLE_ALT_HEAD

TABLE_5_ITEM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
337S4608 1 HSW,SR14H,PRQ,C0,3.1G,65W,4+2,1.2,8M,LGA CPU CRITICAL CPU:CTO PART NUMBER
TABLE_ALT_ITEM

377S0147 377S0126 ALL USB Diode Array


TABLE_ALT_ITEM

377S0124 377S0057 ALL TVS


TABLE_ALT_ITEM

376S0975 376S1081 ALL P/NCh dual FET


TABLE_ALT_ITEM

155S0578 155S0367 ALL 120OHM EMI BEAD


TABLE_ALT_ITEM

128S0368 128S0365 ALL 150UF AL POLY


TABLE_ALT_ITEM

128S0298 128S0293 ALL 330 UF AL POLY


CPU Socket TABLE_ALT_ITEM

TABLE_5_HEAD
138S0681 138S0638 ALL Taiyo 10uf 805 alt
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM

TABLE_5_ITEM
197S0481 197S0480 Y1905 25MHz PCH Xtal
511S0080 1 SOCKET,MOLEX,LGA1150,CPU-LF U0500 CRITICAL TABLE_ALT_ITEM

197S0464 197S0477 Y9700 27 MHz GPU Xtal


TABLE_ALT_ITEM

197S0466 197S0477 Y9700 27 MHz GPU Xtal


TABLE_ALT_ITEM

197S0479 197S0478 Y4200 12 MHz Cam. Xtal


ASIC Parts TABLE_ALT_ITEM

TABLE_5_HEAD
341S3913 341S3912 U3990 Enet ROM,ATMEL,V1.15
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM

B 337S4541 1 IC,LPT-D,SR198Z87,C2,PRQFCBGA708,23X22MM U1100 CRITICAL


TABLE_5_ITEM
377S0155

138S0860
377S0104

138S0775
ALL

ALL
USB Diode

Single-source 1uF 402


TABLE_ALT_ITEM
B
TABLE_5_ITEM

338S1113 1 IC,TBT,CR-4C,B1,PRQ,CIO,288 12X12 FC-CSP U2800 CRITICAL TABLE_ALT_ITEM

TABLE_5_ITEM
138S0859 138S0788 ALL Single-source 10uF
343S0616 1 IC,BCM57766A,CIV+,A0,8X8 U3900 CRITICAL TABLE_ALT_ITEM

TABLE_5_ITEM
107S0251 107S0249 ALL Sense resistor R5400,R5520,R5530
353S3908 1 IC,LP8561,LED BLKT CTLR,LLP24,B0-F U8100 CRITICAL TABLE_ALT_ITEM

138S0648 138S0652 ALL 4.7uF GFX decoupling


TABLE_ALT_ITEM

138S0746 138S0705 ALL 10uF alt;Audio


TABLE_ALT_ITEM

Programmable Parts 138S0715 138S0740 ALL 4.7uF GFX decoupling


TABLE_ALT_ITEM

TABLE_5_HEAD 107S0254 107S0241 ALL 5mOhm Sense Resistor


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM

TABLE_5_ITEM 107S0250 107S0248 ALL 3mOhm Sense Resistor


341S3928 1 IC,EFI,V0112,J16G U5210 CRITICAL BOOTROM:PROG
TABLE_5_ITEM

335S0807 1 IC,64 MBIT SPI SERIAL FLASH U5210 CRITICAL BOOTROM:BLANK


TABLE_5_ITEM
NEED NEW EFI,SMC PROG PARTS
341S3903 1 IC,SMC-A3,V2.16A4,PROTO0,J16G U5000 CRITICAL SMC:PROG
TABLE_5_ITEM

338S1159 1 IC,SMC12-A3,40MHZ/50MIPS,SCPL FW,157BGA U5000 CRITICAL SMC:BLANK


TABLE_5_ITEM

341S3859 1 IC,TBT,EEPROM,CR,V23.10,J16 U2890 CRITICAL T29ROM:PROG


TABLE_5_ITEM

335S0865 1 IC,EEPROM,SERIAL,256KB,MLP8 U2890 CRITICAL T29ROM:BLANK


TABLE_5_ITEM

341S3912 1 IC,ENET SPI ROM,NUMONYX,V1.15,J16/J17 U3990 CRITICAL CIVROM:PROG


TABLE_5_ITEM

335S0862 1 IC,SERIAL FLASH,2MBIT,2.7V,REV F U3990 CRITICAL CIVROM:BLANK


TABLE_5_ITEM

341S3778 1 IC,CAMERA,FLASH,V7230,J16/J17 U4202 CRITICAL CAMROM:PROG


A A
TABLE_5_ITEM

335S0852 1 IC,FLASH,SPI,1MBIT,3V3 U4202 CRITICAL CAMROM:BLANK


SYNC_MASTER=MASTER SYNC_DATE=04/21/2013
PAGE TITLE

BOM Configuration
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

GPU GOOD Led VIDEO ON Led


S5 Led ALL_SYS_PWRGD Led
D =PP3V3_S4_LED
80 3 =PP3V3_S0_LED 80 3 =PP3V3_S0_LED
D
80 =PP3V3_S5_LED
80

1
R0302 R0303
1

1K
R0304
1

1
R0301
1K
1K
5%
1/16W
5%
1/16W
MF-LF
1K
5%
1/16W
MF-LF
5% MF-LF 2 402 2 402
1/16W 2 402 GPU_PRESENT_R
MF-LF
2 402
CORE_VOLTAGES_ON_R LCD_SHOULD_ON_R
A SILK_PART=3
ITS_PLUGGED_IN A SILK_PART=2 CRITICAL LE0303 CRITICAL
A
SILK_PART=1 CRITICAL LE0302 GREEN-3.6MCD CRITICAL
LE0301 K
GREEN-3.6MCD
2.0X1.25MM-SM
K 2.0X1.25MM-SM
A SILK_PART=4
GREEN-3.6MCD
K
2.0X1.25MM-SM
CORE_VOLTAGES_ON
GPU_PRESENT_DRAIN
LE0304
GREEN-3.6MCD
6 K 2.0X1.25MM-SM
3 CRITICAL This LED is a GPIO driven from
D the southbridge that indicates
that chipset has enumerated graphics
D CRITICAL Q0302
Q0302 2
2N7002DW-X-G VIDEO_ON_L
2N7002DW-X-G 18 14 IN GPU_GOOD G S SOT-363 IN 40

71 44 21 ALL_SYS_PWRGD 5 G S SOT-363
IN
1
4

C C

B B

A SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
PAGE TITLE

DEBUG LEDS
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU Heatsink WIRELESS CARD MTG HOLES

4mm Plated Holes (998-0850) 998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)

OMIT OMIT OMIT OMIT


ZH0400 ZH0401 ZH0402 ZH0403
8P5R5-NSP 8P5R5-NSP 8P5R5-NSP 8P5R5-NSP
1 1 1 1
ZH0421 ZH0422 D
D 5P5R1P9-4P3B-NSP
1
5P5R1P9-4P3B-NSP
1

GPU HEATSINK MOUNTING FEATURES


(860-1532)

CRITICAL
CRITICAL
SH0477 SH0479
STDOFF-4.5OD.98H-1.1-3.40-TH
STDOFF-4.5OD.98H-1.1-3.40-TH CRITICAL
1
1 SH0478
STDOFF-4.5OD.98H-1.1-3.40-TH
1

C C

Rear Cover
998-4559 (Plated holes, 4mm inner diameter, 8mm pad)
998-5089 (ZH0414) near BLC has slightly larger hole to allow for grommet
ZH0413 ZH0415 ZH0416 ZH0414
7P0R4P0-8P0B-NSP 7P0R4P0-8P0B-NSP
1 7P0R4P0-8P0B-NSP 7P0R4P6-8P0B-NSP
1 1 1

B B

SSD STANDOFF
APN: 860-1624
SSD:Y
CRITICAL
NUT0413
STDOFF-4.5OD2.2ID-6.5H-SM
1

A SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013 A
PAGE TITLE

Holes/PD parts
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 4 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PPVCOMP_S0_CPU 5 8

PLACE_NEAR=U0500.P3:12.7MM
1
OMIT_TABLE R0510
24.9
U0500 1%

D HASWELL
LGA 2
1/16W
MF-LF
402 D
87 12 DMI_S2N_N<0> T3 DMI_RXN0 SYM 1 OF 11 PEG_RCOMP P3 86 CPU_PEG_RCOMP
IN
87 12 IN DMI_S2N_N<1> V1 DMI_RXN1
87 12 DMI_S2N_N<2> V2 DMI_RXN2 PEG_RXN0 F15 =PEG_D2R_N<0> 81
IN IN
87 12 IN DMI_S2N_N<3> W3 DMI_RXN3 PEG_RXN1 E14 =PEG_D2R_N<1> IN 81
F13 OMIT_TABLE
PEG_RXN2 =PEG_D2R_N<2> IN 81

87 12 IN DMI_S2N_P<0> U3 DMI_RXP0 PEG_RXN3 E12 =PEG_D2R_N<3> IN 81 U0500


87 12 IN DMI_S2N_P<1> U1 DMI_RXP1 PEG_RXN4 F11 =PEG_D2R_N<4> IN 81 HASWELL
87 12 IN DMI_S2N_P<2> W2 DMI_RXP2 PEG_RXN5 G10 =PEG_D2R_N<5> IN 81
LGA
SYM 10 OF 11
87 12 IN DMI_S2N_P<3> Y3 DMI_RXP3 PEG_RXN6 F9 =PEG_D2R_N<6> IN 81 82 TP_DP_IG_B_MLN<0> F17 DDIB_TXBN0
PEG_RXN7 G8 =PEG_D2R_N<7> TP_DP_IG_B_MLP<0> E17 DDIB_TXBP0

DMI
IN 81 82

87 12 OUT DMI_N2S_N<0> AA5 DMI_TXN0 PEG_RXN8 D4 =PEG_D2R_N<8> IN 81 82 TP_DP_IG_B_MLN<1> G18 DDIB_TXBN1


87 12 OUT DMI_N2S_N<1> AB4 DMI_TXN1 PEG_RXN9 E5 =PEG_D2R_N<9> IN 81 82 TP_DP_IG_B_MLP<1> F18 DDIB_TXBP1
DMI_N2S_N<2> AC4 DMI_TXN2 PEG_RXN10 F6 =PEG_D2R_N<10> TP_DP_IG_B_MLN<2> H19 DDIB_TXBN2

EDP
87 12 OUT IN 81 82

87 12 OUT DMI_N2S_N<3> AC2 DMI_TXN3 PEG_RXN11 G5 =PEG_D2R_N<11> IN 81 82 TP_DP_IG_B_MLP<2> G19 DDIB_TXBP2


PEG_RXN12 H6 =PEG_D2R_N<12> 81 82 TP_DP_IG_B_MLN<3> G20 DDIB_TXBN3
IN
DMI_N2S_P<0> AA4 DMI_TXP0 PEG_RXN13 J5 =PEG_D2R_N<13> TP_DP_IG_B_MLP<3> F20 DDIB_TXBP3

DIGITAL DISPLAY INTERFACES


87 12 OUT IN 81 82

87 12 OUT DMI_N2S_P<1> AB3 DMI_TXP1 PEG_RXN14 K6 =PEG_D2R_N<14> IN 81

87 12 OUT DMI_N2S_P<2> AC5 DMI_TXP2 PEG_RXN15 L5 =PEG_D2R_N<15> IN 81 82 TP_DP_IG_C_MLN<0> E19 DDIC_TXCN0 PPVCOMP_S0_CPU 5 8

87 12 OUT DMI_N2S_P<3> AC1 DMI_TXP3 82 TP_DP_IG_C_MLP<0> D19 DDIC_TXCP0 PLACE_NEAR=U0500.R4:12.7MM

PEG_RXP0 E15 =PEG_D2R_P<0> TP_DP_IG_C_MLN<1> D20 DDIC_TXCN1 1


IN 81 82 R0530
PEG_RXP1 D14 =PEG_D2R_P<1> IN 81 82 TP_DP_IG_C_MLP<1> C20 DDIC_TXCP1 24.9
88 12 FDI_CSYNC D16 FDI_CSYNC 1%
IN E13 =PEG_D2R_P<2> TP_DP_IG_C_MLN<2> E21
PEG_RXP2 DDIC_TXCN2

FDI
IN 81 82 1/16W
MF-LF
PEG_RXP3 D12 =PEG_D2R_P<3> IN 81 82 TP_DP_IG_C_MLP<2> D21 DDIC_TXCP2 402
2
88 12 FDI_INT D18 DISP_INT PEG_RXP4 E11 =PEG_D2R_P<4> 81 82 TP_DP_IG_C_MLN<3> D22 DDIC_TXCN3
IN IN
F10 C22 DP_RCOMP R4 86 CPU_EDP_RCOMP
PEG_RXP5 =PEG_D2R_P<5> 81 82 TP_DP_IG_C_MLP<3> DDIC_TXCP3
C
IN
EDP_DISP_UTIL E16
C Though FDI unused, these are
to be connected per PDG (10.6)
PEG_RXP6
PEG_RXP7
E9
F8
=PEG_D2R_P<6>
=PEG_D2R_P<7>
IN 81

81 82 TP_DP_IG_D_MLN<2> C17 DDID_TXDN2


TP_EDP_DISP_UTIL

IN
PEG_RXP8 D3 =PEG_D2R_P<8> 81 82 TP_DP_IG_D_MLP<2> B17 DDID_TXDP2
IN B14
E4 B18 FDI0_TX0N0 NC
PEG_RXP9 =PEG_D2R_P<9> IN 81 82 TP_DP_IG_D_MLN<3> DDID_TXDN3 A14
PCI EXPRESS BASED INTERFACE SIGNALS FDI0_TX0P0

FDI
PEG_RXP10 F5 =PEG_D2R_P<10> IN 81 82 TP_DP_IG_D_MLP<3> A18 DDID_TXDP3 NC
FDI0_TX0N1 C13
PEG_RXP11 G4 =PEG_D2R_P<11> IN 81
NC
TP_DP_IG_D_MLN<0> C15 DDID_TXDN0 FDI0_TX0P1 B13
PEG_RXP12 H5 =PEG_D2R_P<12> IN 81
82
NC
82 TP_DP_IG_D_MLP<0> B15 DDID_TXDP0
PEG_RXP13 J4 =PEG_D2R_P<13> 81
IN TP_DP_IG_D_MLN<1> B16
K5 82 DDID_TXDN1
PEG_RXP14 =PEG_D2R_P<14> IN 81
82 TP_DP_IG_D_MLP<1> A16 DDID_TXDP1
PEG_RXP15 L4 =PEG_D2R_P<15> IN 81
Port D pins out of order
B12 to match Intel symbol.
PEG_TXN0 =PEG_R2D_C_N<0> OUT 81

PEG_TXN1 C11 =PEG_R2D_C_N<1> 81


OUT
PEG_TXN2 D10 =PEG_R2D_C_N<2> 81
OUT
PEG_TXN3 C9 =PEG_R2D_C_N<3> 81
OUT
PEG_TXN4 D8 =PEG_R2D_C_N<4> 81
OUT
PEG_TXN5 C7 =PEG_R2D_C_N<5> OUT 81

PEG_TXN6 B6 =PEG_R2D_C_N<6> OUT 81

PEG_TXN7 C5 =PEG_R2D_C_N<7> OUT 81

PEG_TXN8 E2 =PEG_R2D_C_N<8> OUT 81

PEG_TXN9 F3 =PEG_R2D_C_N<9> 81
OUT
PEG_TXN10 G2 =PEG_R2D_C_N<10> 81
OUT
PEG_TXN11 H3 =PEG_R2D_C_N<11> OUT 81

PEG_TXN12 J2 =PEG_R2D_C_N<12> OUT 81

PEG_TXN13 K3 =PEG_R2D_C_N<13> OUT 81

PEG_TXN14 M3 =PEG_R2D_C_N<14> OUT 81

B PEG_TXN15 L2 =PEG_R2D_C_N<15> OUT 81


B
PEG_TXP0 A12 =PEG_R2D_C_P<0> 81
OUT
PEG_TXP1 B11 =PEG_R2D_C_P<1> OUT 81

PEG_TXP2 C10 =PEG_R2D_C_P<2> 81


OUT
PEG_TXP3 B9 =PEG_R2D_C_P<3> OUT 81

PEG_TXP4 C8 =PEG_R2D_C_P<4> OUT 81

PEG_TXP5 B7 =PEG_R2D_C_P<5> OUT 81

PEG_TXP6 A6 =PEG_R2D_C_P<6> OUT 81

PEG_TXP7 B5 =PEG_R2D_C_P<7> OUT 81

PEG_TXP8 E1 =PEG_R2D_C_P<8> 81
OUT
PEG_TXP9 F2 =PEG_R2D_C_P<9> 81
OUT
PEG_TXP10 G1 =PEG_R2D_C_P<10> OUT 81

PEG_TXP11 H2 =PEG_R2D_C_P<11> OUT 81

PEG_TXP12 J1 =PEG_R2D_C_P<12> OUT 81

PEG_TXP13 K2 =PEG_R2D_C_P<13> OUT 81

PEG_TXP14 M2 =PEG_R2D_C_P<14> OUT 81

PEG_TXP15 L1 =PEG_R2D_C_P<15> 81
OUT

A SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE

CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 5 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE

U0500
HASWELL
LGA
61 18 8 PPVCCIO_S0_CPU SYM 2 OF 11
86 18 14 IN CPU_RESET_L M39 RESET* SM_RCOMP0 R1 85 CPU_SM_RCOMP<0>
PLACE_NEAR=U0500.R1:12.7mm
SM_RCOMP1 P1 CPU_SM_RCOMP<1>
D
PLACE_NEAR=R0603.2:1mm 1 85

DDR3
D R0601
51
5%
86 45 OUT CPU_CATERR_L M36 CATERR* SM_RCOMP2 R2 85 CPU_SM_RCOMP<2>
PLACE_NEAR=U0500.P1:12.7mm

PLACE_NEAR=U0500.R2:12.7mm

SM_DRAMRST* AK22 =MEM_RESET_L

THERMAL
1/16W OUT 21
CPU_PECI N37 PECI 1 1 1
MF-LF PLACE_NEAR=U0500.K38:38MM 86 45 44 14 BI R0614 R0613 R0612
402
2 R0603 100 75 100
56
K38 PROCHOT* (IPU) PRDY* L39 XDP_CPU_PRDY_L OUT 18 1% 1% 1%
86 61 45 44 BI CPU_PROCHOT_L 2 1 86 CPU_PROCHOT_R_L 1/16W 1/16W 1/16W
(IPU) PREQ* L37 XDP_CPU_PREQ_L IN 18 MF-LF MF-LF MF-LF
5% 402 402 402
80 10 8 =PP1V5_S0_CPU_MEM 1/16W 2 2 2
MF-LF 45 OUT CPU_THRMTRIP_L F37 THERMTRIP*
402 (IPD) TCK D39 XDP_CPU_TCK IN 18 88

R0620 1 P36 PM_SYNC (IPU) TMS E39 XDP_CPU_TMS IN 18 88


86 12 IN PM_SYNC
1.82K (IPU) TRST* E37 XDP_CPU_TRST_L IN 18
1%
1/16W
MF-LF 86 18 14 IN CPU_PWRGD AB35 PWRGOOD
TDI F38 XDP_CPU_TDI

PWR
402 (IPU) IN 18 88
2
PLACE_NEAR=R0621.2:1mm
AK21 SM_DRAMPWROK TDO F39 XDP_CPU_TDO OUT 18 88
21 12 IN PM_MEM_PWRGD

JTAG
PLACE_NEAR=U0500.AK21:25.4mm
D38 SKTOCC* DBR* G40 XDP_DBRESET_L OUT 18 19
R0621 1 70 OUT CPU_SKTOCC_L
2.55K
1% (IPU) BPM0* G39 XDP_BPM_L<0> BI 18 86
1/16W 87 11 IN CPU_CLK135M_DPLLREF_N W6 DPLL_REF_CLKN
MF-LF (IPU) BPM1* J39 XDP_BPM_L<1> BI 18 86
402 87 11 IN CPU_CLK135M_DPLLREF_P W5 DPLL_REF_CLKP
2
(IPU) BPM2* G38 XDP_BPM_L<2> BI 18 88

BPM3* H37 XDP_BPM_L<3>

CLOCK
(IPU) BI 18 88
87 11 CPU_CLK135M_DPLLSS_N U5 SSC_DPLL_REF_CLKN
IN H38 XDP_BPM_L<4>
U6 SSC_DPLL_REF_CLKP (IPU) BPM4* BI 18 88
87 11 IN CPU_CLK135M_DPLLSS_P
(IPU) BPM5* J38 XDP_BPM_L<5> BI 18 88

(IPU) BPM6* K39 XDP_BPM_L<6> BI 18 88


87 11 DMI_CLK100M_CPU_N V4 BCLKN
IN K37 XDP_BPM_L<7>
V5 BCLKP (IPU) BPM7* BI 18 88
87 11 IN DMI_CLK100M_CPU_P
PLACE_NEAR=U0500.AB35:25mm

R0611 1
C DPLL_REF_CLK needs to be connected as it provides
some bootstrap function during startup
10K
5%
1/16W
MF-LF
C
402
2

OMIT_TABLE

U0500
HASWELL
LGA
TP_CPU_RSVD_TP1 H16 RSVD_TP SYM 11 OF 11 RSVD_TP J12 TP_CPU_RSVD_TP12
D1 RSVD_TP RESERVED J10
TP_CPU_RSVD_TP2 RSVD_TP TP_CPU_RSVD_TP13
RSVD_TP C2 TP_CPU_RSVD_TP14
TP_CPU_RSVD_TP3 J13 RSVD_TP
RSVD_TP C39 TP_CPU_RSVD_TP15
TP_CPU_RSVD_TP4 K11 RSVD_TP
PLACE_NEAR=U0500.H40:10mm
TP_CPU_RSVD_TP5 K8 RSVD_TP CFG_RCOMP H40 86 CPU_CFG_RCOMP
TP_CPU_RSVD_TP6 N36 RSVD_TP
(IPU) CFG16 Y37 CPU_CFG<16> 18 88
CPU_TESTLO_P6 P6 TESTLO_P6 1
CFG18 W36 CPU_CFG<18> 18
R0690
B8 VSS 49.9
(IPU) CFG17 Y36 CPU_CFG<17> 18 88 1%
1 B23 VSS
R0680 CFG19 V36 CPU_CFG<19> 18
1/16W
MF-LF
49.9 80 61 48 10 8 =PPCPUVCC_S0_CPU B10 VSS 402
2
1%
1/16W P8 VCC
MF-LF
402
2 TP_CPU_RSVD_TP7 P37 RSVD_TP
TP_CPU_RSVD_TP8 R36 RSVD_TP

TP_CPU_RSVD_TP9 N38 RSVD_TP


RSVD U8
B TESTLO_X pins to be individually connected to GND
via a resistor matching the nominal trace impedance +/-20%
TP_CPU_RSVD_TP10
TP_CPU_RSVD_TP11
J16 RSVD_TP
J8 RSVD_TP RSVD H12
H15
NC
NC B
N5 TESTLO_N5 RSVD NC
CPU_TESTLO_N5
RSVD J9
NC
1 CPU_CFG<0> AA37 CFG0 (IPU)
R0685 88 18

49.9 CPU_CFG<1> Y38 CFG1 (IPU) RSVD M10 INTEL’S HASWELL DT EDS SAYS THAT ALL RSVD AND RSVD_NCTF SHOULD BE NC’D
1%
88 18
NC
1/16W 88 18 CPU_CFG<2> AA36 CFG2 (IPU)
MF-LF
402 88 18 CPU_CFG<3> W38 CFG3 (IPU)
2
V39 RSVD H14 NC
88 18 CPU_CFG<4> CFG4 (IPU)
88 18 CPU_CFG<5> U39 CFG5 (IPU)
1
R0642 88 18 CPU_CFG<6> U40 CFG6 (IPU)
1K
5% 88 18 CPU_CFG<7> V38 CFG7 (IPU)
1/16W
MF-LF 88 18 CPU_CFG<8> T40 CFG8 (IPU)
402
Y35 RSVD_TP K13 TP_CPU_RSVD_TP16
2
88 18 CPU_CFG<9> CFG9 (IPU)
AA34 RSVD_TP K12 TP_CPU_RSVD_TP17
88 18 CPU_CFG<10> CFG10 (IPU)
88 18 CPU_CFG<11> V37 CFG11 (IPU)
Y34 VSS B30
88 82 18 CPU_CFG<12> CFG12 (IPU)
U38 VSS B28
88 82 18 CPU_CFG<13> CFG13 (IPU)
88 82 18 CPU_CFG<14> W34 CFG14 (IPU) VSS B24
88 82 18 CPU_CFG<15> V35 CFG15 (IPU) VSS B26

Y8 RSVD
NC
W8 RSVD
NC
M11 RSVD
NC

A CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE
CFG [6:5] :PCIE BIFURCATION

CFG [4] :eDP ENABLE/DISABLE


11 = 1 X16 (default)

1 = DISABLED(default)
10 = 2 X8

0 = ENABLED
01 = RSVD 00 = X8, X4, X4
CPU Clock/Misc/JTAG/CFG
DRAWING NUMBER SIZE
CFG [3] :PCIE x4 LANE REVERSAL

CFG [2] :PCIE x16 LANE REVERSAL


1 = NORMAL OPERATION(default)

1 = NORMAL OPERATION(default)
0 = LANES REVERSED

0 = LANES REVERSED Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE OMIT_TABLE

85 25 BI MEM_A_DQ<0> AD38 SA_DQ0 U0500 RSVD N35 NC 85 25 BI MEM_B_DQ<0> AE34 SB_DQ0 U0500 RSVD AB8 NC
85 25 BI MEM_A_DQ<1> AD39 SA_DQ1 HASWELL SA_CKN0 AY16 MEM_A_CLK_N<0>
85 25 BI MEM_B_DQ<1> AE35 SB_DQ1 HASWELL SB_CKN0 AM21 MEM_B_CLK_N<0>
85 25 BI MEM_A_DQ<2> AF38 SA_DQ2 LGA OUT 23 85
85 25 BI MEM_B_DQ<2> AG35 SB_DQ2 LGA OUT 24 85

AF39 SYM 3 OF 11 SA_CK0 AY15 MEM_A_CLK_P<0> OUT 23 85


AH35 SYM 4 OF 11 SB_CK0 AM20 MEM_B_CLK_P<0> OUT 24 85
85 25 BI MEM_A_DQ<3> SA_DQ3 85 25 BI MEM_B_DQ<3> SB_DQ3
AD37 SA_CKE0 AV22 MEM_A_CKE<0> OUT 23 85
AD34 SB_CKE0 AW29 MEM_B_CKE<0> OUT 24 85
85 25 BI MEM_A_DQ<4> SA_DQ4 85 25 BI MEM_B_DQ<4> SB_DQ4
85 25 BI MEM_A_DQ<5> AD40 SA_DQ5 SA_CKN1 AV15 MEM_A_CLK_N<1> OUT 23 85 85 25 BI MEM_B_DQ<5> AD35 SB_DQ5 SB_CKN1 AP21 MEM_B_CLK_N<1> OUT 24 85

85 25 BI MEM_A_DQ<6> AF37 SA_DQ6 SA_CK1 AW15 MEM_A_CLK_P<1> OUT 23 85 85 25 BI MEM_B_DQ<6> AG34 SB_DQ6 SB_CK1 AP22 MEM_B_CLK_P<1> OUT 24 85

MEM_A_DQ<7> AF40 SA_DQ7 SA_CKE1 AT23 MEM_A_CKE<1> MEM_B_DQ<7> AH34 SB_DQ7 SB_CKE1 AY29 MEM_B_CKE<1>

D
85 25

85 25
BI
BI MEM_A_DQ<8> AH40
AH39
SA_DQ8
SA_CKN2 AW14 MEM_A_CLK_N<2>
OUT

OUT
23 85

82 85
85 25

85 25
BI
BI MEM_B_DQ<8> AL34
AL35
SB_DQ8
SB_CKN2 AN21 MEM_B_CLK_N<2>
OUT

OUT
24 85

82 85
D
85 25 BI MEM_A_DQ<9> SA_DQ9 85 25 BI MEM_B_DQ<9> SB_DQ9
AK38 SA_CK2 AV14 MEM_A_CLK_P<2> OUT 82 85
AK31 SB_CK2 AN20 MEM_B_CLK_P<2> OUT 82 85
85 25 BI MEM_A_DQ<10> SA_DQ10 85 25 BI MEM_B_DQ<10> SB_DQ10
AK39 SA_CKE2 AU22 MEM_A_CKE<2> OUT 82 85
AL31 SB_CKE2 AU28 MEM_B_CKE<2> OUT 82 85
85 25 BI MEM_A_DQ<11> SA_DQ11 85 25 BI MEM_B_DQ<11> SB_DQ11
85 25 MEM_A_DQ<12> AH37 SA_DQ12 SA_CKN3 AY13 MEM_A_CLK_N<3> 82 85 85 25 MEM_B_DQ<12> AK34 SB_DQ12 SB_CKN3 AP20 MEM_B_CLK_N<3> 82 85
BI OUT BI OUT
85 25 BI MEM_A_DQ<13> AH38 SA_DQ13 SA_CK3 AW13 MEM_A_CLK_P<3> OUT 82 85 85 25 BI MEM_B_DQ<13> AK35 SB_DQ13 SB_CK3 AP19 MEM_B_CLK_P<3> OUT 82 85

85 25 BI MEM_A_DQ<14> AK37 SA_DQ14 SA_CKE3 AU23 MEM_A_CKE<3> OUT 82 85 85 25 BI MEM_B_DQ<14> AK32 SB_DQ14 SB_CKE3 AU29 MEM_B_CKE<3> OUT 82 85

85 25 MEM_A_DQ<15> AK40 SA_DQ15 85 25 MEM_B_DQ<15> AL32 SB_DQ15


BI BI
85 25 BI MEM_A_DQ<16> AM40 SA_DQ16 SA_CS0* AU14 MEM_A_CS_L<0> OUT 23 85 85 25 BI MEM_B_DQ<16> AN34 SB_DQ16 SB_CS0* AP17 MEM_B_CS_L<0> OUT 24 85

85 25 BI MEM_A_DQ<17> AM39 SA_DQ17 SA_CS1* AV9 MEM_A_CS_L<1> OUT 23 85 85 25 BI MEM_B_DQ<17> AP34 SB_DQ17 SB_CS1* AN15 MEM_B_CS_L<1> OUT 24 85

85 25 BI MEM_A_DQ<18> AP38 SA_DQ18 SA_CS2* AU10 MEM_A_CS_L<2> OUT 82 85 85 25 BI MEM_B_DQ<18> AN31 SB_DQ18 SB_CS2* AN17 MEM_B_CS_L<2> OUT 82 85

85 25 BI MEM_A_DQ<19> AP39 SA_DQ19 SA_CS3* AW8 MEM_A_CS_L<3> OUT 82 85 85 25 BI MEM_B_DQ<19> AP31 SB_DQ19 SB_CS3* AL15 MEM_B_CS_L<3> OUT 82 85

85 25 MEM_A_DQ<20> AM37 SA_DQ20 85 25 MEM_B_DQ<20> AN35 SB_DQ20


BI AW10 MEM_A_ODT<0> BI AM17 MEM_B_ODT<0>
AM38 SA_ODT0 OUT 23 85
AP35 SB_ODT0 OUT 24 85

MEMORY CHANNEL A

MEMORY CHANNEL B
85 25 BI MEM_A_DQ<21> SA_DQ21 85 25 BI MEM_B_DQ<21> SB_DQ21
SA_ODT1 AY8 MEM_A_ODT<1> OUT 23 85 SB_ODT1 AL16 MEM_B_ODT<1> OUT 24 85
85 25 BI MEM_A_DQ<22> AP37 SA_DQ22 85 25 BI MEM_B_DQ<22> AN32 SB_DQ22
SA_ODT2 AW9 MEM_A_ODT<2> OUT 82 85 SB_ODT2 AM16 MEM_B_ODT<2> OUT 82 85
85 25 MEM_A_DQ<23> AP40 SA_DQ23 85 25 MEM_B_DQ<23> AP32 SB_DQ23
BI AU8 MEM_A_ODT<3> BI AK15 MEM_B_ODT<3>
AV37 SA_ODT3 OUT 82 85
AM29 SB_ODT3 OUT 82 85
85 25 BI MEM_A_DQ<24> SA_DQ24 85 25 BI MEM_B_DQ<24> SB_DQ24
85 25 BI MEM_A_DQ<25> AW37 SA_DQ25 SA_BS0 AV12 MEM_A_BA<0> OUT 23 85 85 25 BI MEM_B_DQ<25> AM28 SB_DQ25 SB_BS0 AK17 MEM_B_BA<0> OUT 24 85

85 25 BI MEM_A_DQ<26> AU35 SA_DQ26 SA_BS1 AY11 MEM_A_BA<1> OUT 23 85 85 25 BI MEM_B_DQ<26> AR29 SB_DQ26 SB_BS1 AL18 MEM_B_BA<1> OUT 24 85

85 25 MEM_A_DQ<27> AV35 SA_DQ27 SA_BS2 AT21 MEM_A_BA<2> 23 85 85 25 MEM_B_DQ<27> AR28 SB_DQ27 SB_BS2 AW28 MEM_B_BA<2> 24 85
BI OUT BI OUT
85 25 MEM_A_DQ<28> AT37 SA_DQ28 85 25 MEM_B_DQ<28> AL29 SB_DQ28
BI BI
85 25 BI MEM_A_DQ<29> AU37 SA_DQ29 VSS AW3 85 25 BI MEM_B_DQ<29> AL28 SB_DQ29 VSS AU30
85 25 MEM_A_DQ<30> AT35 SA_DQ30 85 25 MEM_B_DQ<30> AP29 SB_DQ30
BI BI
AW35 SA_RAS* AU12 MEM_A_RAS_L OUT 23 85
AP28 SB_RAS* AM18 MEM_B_RAS_L OUT 24 85
85 25 BI MEM_A_DQ<31> SA_DQ31 85 25 BI MEM_B_DQ<31> SB_DQ31
AY6 SA_WE* AU11 MEM_A_WE_L OUT 23 85
AR12 SB_WE* AK16 MEM_B_WE_L OUT 24 85
85 25 BI MEM_A_DQ<32> SA_DQ32 85 25 BI MEM_B_DQ<32> SB_DQ32
AU6 SA_CAS* AU9 MEM_A_CAS_L OUT 23 85
AP12 SB_CAS* AP16 MEM_B_CAS_L OUT 24 85
85 25 BI MEM_A_DQ<33> SA_DQ33 85 25 BI MEM_B_DQ<33> SB_DQ33

C 85 25

85 25
BI
BI
MEM_A_DQ<34>
MEM_A_DQ<35>
AV4
AU4
SA_DQ34
SA_DQ35
SA_MA0
SA_MA1
AU13
AV16
MEM_A_A<0>
MEM_A_A<1>
OUT 23 85

23 85
85 25

85 25
BI
BI
MEM_B_DQ<34>
MEM_B_DQ<35>
AL13
AL12
SB_DQ34
SB_DQ35
SB_MA0
SB_MA1
AL19
AK23
MEM_B_A<0>
MEM_B_A<1>
OUT 24 85

24 85
C
MEM_A_DQ<36> AW6 OUT MEM_B_DQ<36> AR13 OUT
85 25 BI SA_DQ36 AU16 85 25 BI SB_DQ36 AM22
SA_MA2 MEM_A_A<2> OUT 23 85 SB_MA2 MEM_B_A<2> OUT 24 85
85 25 BI MEM_A_DQ<37> AV6 SA_DQ37 85 25 BI MEM_B_DQ<37> AP13 SB_DQ37
SA_MA3 AW17 MEM_A_A<3> 23 85 SB_MA3 AM23 MEM_B_A<3> 24 85
MEM_A_DQ<38> AW4 OUT MEM_B_DQ<38> AM13 OUT
85 25 BI SA_DQ38 AU17 85 25 BI SB_DQ38 AP23
SA_MA4 MEM_A_A<4> OUT 23 85 SB_MA4 MEM_B_A<4> OUT 24 85
85 25 MEM_A_DQ<39> AY4 SA_DQ39 85 25 MEM_B_DQ<39> AM12 SB_DQ39
BI AW18 MEM_A_A<5> BI AL23 MEM_B_A<5>
AR1 SA_MA5 OUT 23 85
AR9 SB_MA5 OUT 24 85
85 25 BI MEM_A_DQ<40> SA_DQ40 85 25 BI MEM_B_DQ<40> SB_DQ40
SA_MA6 AV17 MEM_A_A<6> 23 85 SB_MA6 AY24 MEM_B_A<6> 24 85
MEM_A_DQ<41> AR4 OUT MEM_B_DQ<41> AP9 OUT
85 25 BI SA_DQ41 AT18 85 25 BI SB_DQ41 AV25
SA_MA7 MEM_A_A<7> OUT 23 85 SB_MA7 MEM_B_A<7> OUT 24 85
85 25 BI MEM_A_DQ<42> AN3 SA_DQ42 85 25 BI MEM_B_DQ<42> AR6 SB_DQ42
SA_MA8 AU18 MEM_A_A<8> 23 85 SB_MA8 AU26 MEM_B_A<8> 24 85
MEM_A_DQ<43> AN4 OUT MEM_B_DQ<43> AP6 OUT
85 25 BI SA_DQ43 AT19 85 25 BI SB_DQ43 AW25
SA_MA9 MEM_A_A<9> OUT 23 85 SB_MA9 MEM_B_A<9> OUT 24 85
85 25 MEM_A_DQ<44> AR2 SA_DQ44 85 25 MEM_B_DQ<44> AR10 SB_DQ44
BI AW11 MEM_A_A<10> BI AP18 MEM_B_A<10>
AR3 SA_MA10 OUT 23 85
AP10 SB_MA10 OUT 24 85
85 25 BI MEM_A_DQ<45> SA_DQ45 85 25 BI MEM_B_DQ<45> SB_DQ45
SA_MA11 AV19 MEM_A_A<11> OUT 23 85 SB_MA11 AY25 MEM_B_A<11> OUT 24 85
85 25 MEM_A_DQ<46> AN2 SA_DQ46 85 25 MEM_B_DQ<46> AR7 SB_DQ46
BI AU19 MEM_A_A<12> BI AV26 MEM_B_A<12>
AN1 SA_MA12 OUT 23 85
AP7 SB_MA12 OUT 24 85
85 25 BI MEM_A_DQ<47> SA_DQ47 85 25 BI MEM_B_DQ<47> SB_DQ47
SA_MA13 AY10 MEM_A_A<13> 23 85 SB_MA13 AR15 MEM_B_A<13> 24 85
MEM_A_DQ<48> AL1 OUT MEM_B_DQ<48> AM9 OUT
85 25 BI SA_DQ48 AT20 85 25 BI SB_DQ48 AV27
SA_MA14 MEM_A_A<14> OUT 23 85 SB_MA14 MEM_B_A<14> OUT 24 85
85 25 BI MEM_A_DQ<49> AL4 SA_DQ49 85 25 BI MEM_B_DQ<49> AL9 SB_DQ49
SA_MA15 AU21 MEM_A_A<15> 23 85 SB_MA15 AY28 MEM_B_A<15> 24 85
MEM_A_DQ<50> AJ3 OUT MEM_B_DQ<50> AL6 OUT
85 25 BI SA_DQ50 85 25 BI SB_DQ50
85 25 MEM_A_DQ<51> AJ4 SA_DQ51 SA_DQSN0 AE38 MEM_A_DQS_N<0> 25 85 85 25 MEM_B_DQ<51> AL7 SB_DQ51
BI BI BI AF34 MEM_B_DQS_N<0>
AL2 AJ38 AM10 SB_DQSN0 BI 25 85
85 25 BI MEM_A_DQ<52> SA_DQ52 SA_DQSN1 MEM_A_DQS_N<1> BI 25 85 85 25 BI MEM_B_DQ<52> SB_DQ52
SB_DQSN1 AK33 MEM_B_DQS_N<1> BI 25 85
85 25 BI MEM_A_DQ<53> AL3 SA_DQ53 SA_DQSN2 AN38 MEM_A_DQS_N<2> BI 25 85 85 25 BI MEM_B_DQ<53> AL10 SB_DQ53
SB_DQSN2 AN33 MEM_B_DQS_N<2> BI 25 85
85 25 BI MEM_A_DQ<54> AJ2 SA_DQ54 SA_DQSN3 AU36 MEM_A_DQS_N<3> BI 25 85 85 25 BI MEM_B_DQ<54> AM6 SB_DQ54
SB_DQSN3 AN29 MEM_B_DQS_N<3> BI 25 85
85 25 BI MEM_A_DQ<55> AJ1 SA_DQ55 SA_DQSN4 AW5 MEM_A_DQS_N<4> BI 25 85 85 25 BI MEM_B_DQ<55> AM7 SB_DQ55
SB_DQSN4 AN13 MEM_B_DQS_N<4> BI 25 85
85 25 MEM_A_DQ<56> AG1 SA_DQ56 SA_DQSN5 AP2 MEM_A_DQS_N<5> 25 85 85 25 MEM_B_DQ<56> AH6 SB_DQ56
BI BI BI AR8 MEM_B_DQS_N<5>
AG4 AK2 AH7 SB_DQSN5 BI 25 85
85 25 BI MEM_A_DQ<57> SA_DQ57 SA_DQSN6 MEM_A_DQS_N<6> BI 25 85 85 25 BI MEM_B_DQ<57> SB_DQ57
SB_DQSN6 AM8 MEM_B_DQS_N<6> BI 25 85
85 25 MEM_A_DQ<58> AE3 SA_DQ58 SA_DQSN7 AF2 MEM_A_DQS_N<7> 25 85 85 25 MEM_B_DQ<58> AE6 SB_DQ58
BI BI BI AG6 MEM_B_DQS_N<7>
AE4 AU32 AE7 SB_DQSN7 BI 25 85
85 25 BI MEM_A_DQ<59> SA_DQ59 SA_DQSN8 TP_MEM_A_DQS_N<8> 82 85 25 BI MEM_B_DQ<59> SB_DQ59
SB_DQSN8 AN26 TP_MEM_B_DQS_N<8> 82
MEM_A_DQ<60> AG2 SA_DQ60 MEM_B_DQ<60> AJ6 SB_DQ60
B
85 25

85 25
BI
BI MEM_A_DQ<61> AG3
AE2
SA_DQ61 SA_DQSP0 AE39
AJ39
MEM_A_DQS_P<0> BI 25 85
85 25

85 25
BI
BI MEM_B_DQ<61> AJ7
AF6
SB_DQ61
SB_DQS0 AF35 MEM_B_DQS_P<0> BI 25 85
B
85 25 BI MEM_A_DQ<62> SA_DQ62 SA_DQSP1 MEM_A_DQS_P<1> BI 25 85 85 25 BI MEM_B_DQ<62> SB_DQ62
SB_DQS1 AL33 MEM_B_DQS_P<1> 25 85
MEM_A_DQ<63> AE1 AN39 MEM_A_DQS_P<2> MEM_B_DQ<63> AF7 BI
85 25 BI SA_DQ63 SA_DQSP2 BI 25 85 85 25 BI SB_DQ63 AP33
SB_DQS2 MEM_B_DQS_P<2> BI 25 85
SA_DQSP3 AV36 MEM_A_DQS_P<3> BI 25 85
AW33 SA_ECC_CB0 AM26 SB_ECC_CB0 SB_DQS3 AN28 MEM_B_DQS_P<3>
NC SA_DQSP4 AV5 MEM_A_DQS_P<4> BI 25 85
NC BI 25 85
AV33 SA_ECC_CB1 AM25 SB_ECC_CB1 SB_DQS4 AN12 MEM_B_DQS_P<4>
NC SA_DQSP5 AP3 MEM_A_DQS_P<5> BI 25 85
NC BI 25 85
AU31 SA_ECC_CB2 AP25 SB_ECC_CB2 SB_DQS5 AP8 MEM_B_DQS_P<5>
NC SA_DQSP6 AK3 MEM_A_DQS_P<6> 25 85
NC BI 25 85
AV31 BI AP26 AL8 MEM_B_DQS_P<6>
NC SA_ECC_CB3 AF3 NC SB_ECC_CB3 SB_DQS6 BI 25 85
SA_DQSP7 MEM_A_DQS_P<7> BI 25 85
AT33 SA_ECC_CB4 AL26 SB_ECC_CB4 SB_DQS7 AG7 MEM_B_DQS_P<7>
NC SA_DQSP8 AV32 TP_MEM_A_DQS_P<8> 82
NC BI 25 85
AU33 SA_ECC_CB5 AL25 SB_ECC_CB5 SB_DQS8 AN25 TP_MEM_B_DQS_P<8>
NC NC 82
AT31 SA_ECC_CB6 AR26 SB_ECC_CB6
NC RSVD J40 NC
AW31 SA_ECC_CB7 NC AR25 SB_ECC_CB7 RSVD R34
NC RSVD L12 NC NC
NC RSVD T8
CPU_DIMM_VREFCA AB38 SM_VREF RSVD L10 NC
22 OUT NC RSVD T34
RSVD R33 NC
NC RSVD AT40
CPU_DIMMA_VREFDQ AB39 SA_DIMM_VREFDQ RSVD J15 NC
22 OUT NC RSVD AL20
RSVD T35 NC
CPU_DIMMB_VREFDQ AB40 SB_DIMM_VREFDQ NC RSVD AB36
22 OUT
RSVD J17 NC
NC RSVD AB33
RSVD M38 NC
P33 RSVD NC RSVD AC8
NC NC

INTEL’S HASWELL DT EDS SAYS THAT ALL RSVD AND RSVD_NCTF SHOULD BE NC’D

A SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE

CPU DDR3 Interfaces


DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 7 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 7 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE
=PPCPUVCC_S0_CPU 6 8 10 48 61 80

NC
AW12 RSVD U0500 C28

NC
AW23 RSVD HASWELL C29
AW24 RSVD LGA C30
NC
AW27 RSVD SYM 5 OF 11 C31
NC
80 10 6 =PP1V5_S0_CPU_MEM C32
AJ12 C33

D
AJ13
AJ15
C34
C35
D
AJ17 D25
AJ20 D27
AJ21 D29
80 61 48 10 8 6 =PPCPUVCC_S0_CPU OMIT_TABLE
AJ24 D31
AJ25 D33 M33 U0500
AJ28 D35 M29 HASWELL
AJ29 E24 M27 LGA
AJ9 E25 M25 SYM 6 OF 11
AT17 E26 M23 POWER
VDDQ
AT22 E27 M21
AU15 E28 M19
AU20 E29 M17
AU24 E30 M15
AV10 E31 M13
AV11 E32 M8
AV13 E33 L34
AV18 E34 L33
AV23 E35 L32
AV8 F23 L31 VCC
AW16 F25 L30
AY12 F27 L29
AY14 F29 L28
AY9 F31 L27
F33 L26
F35 L25

C G22
G23
L24
A28
C
G24 A27
80 61 48 10 8 6 =PPCPUVCC_S0_CPU G25 A26
G26 A25
AU39 RSVD G27 A24
NC
1 L22 VCC G28
R0800
PLACE_NEAR=U0500.E40:50.8mm 100 L23 VCC G29
5%
AU27 RSVD G30
PLACE_SIDE=BOTTOM
1/16W
MF-LF
NC
NOTE: Aliases not used on CPU supply outputs AU1 RSVD G31
402
2 NC VCC
to avoid any extraneous connections. G32
93 61 CPU_VCCSENSE_P E40 VCC_SENSE
OUT G33
PPVCCIO_S0_CPU AK20 RSVD
61 18 6
MIN_LINE_WIDTH=0.4 mm
NC G34
Max load: 300mA MIN_NECK_WIDTH=0.2 mm L40 VCCIO_OUT
VOLTAGE=1.05V G35
PPVCOMP_S0_CPU AV24 RSVD
5
MIN_LINE_WIDTH=0.4 mm
NC H23
P4
R0801 1 1
R0804 Max load: 300mA MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
VCOMP_OUT H25
75 110 AV2 RSVD
1% 1%
NC H27
AY18 RSVD
1/16W
MF-LF
1/16W
MF-LF
NC H29
AV29 RSVD
402
2 R0802 2
402
NC H31
43 AV20 RSVD
93 61 IN CPU_VIDALERT_L 1 2 NC H33
5% H35
1/16W 93 CPU_VIDALERT_R_L B37 VIDALERT*
MF-LF J21
R0803 402 93 CPU_VIDSCLK_R C38 VIDSCLK
0 J22
93 61 OUT CPU_VIDSCLK 1 2 93 CPU_VIDSOUT_R C37 VIDSOUT
J23
5%
1/16W R0804.2: PLACE_NEAR=U0500.C37:12.7mm J24
MF-LF AY5 VSS
402 R0805 R0802.2: PLACE_NEAR=U0500.B37:12.7mm J25
0 CPU_PWR_DEBUG N40 PWR_DEBUG
B 93 61 BI CPU_VIDSOUT 1

5%
2 R0801.2: PLACE_NEAR=R0802.1:25.4mm
18 IN
AY7
AW2
VSS
J26
J27
B
1/16W
NC RSVD J28
MF-LF
402 AV1 RSVD
NC J29
A4 RSVD
NC J30
B3 RSVD
NC J31
B4 VSS J32
AY26 VSS J33
AW34 VSS J34
AW32 VSS J35
AY17 VSS K19
AW36 VSS K21
AY27 VSS K23
AW26 VSS K25
AY30 VSS K27
AW30 VSS K29
AY23 VSS K31
K33
A29
K35
A30
L15
B25
L16
B27
L17
B29
L18
B31
L19
B33 VCC
L20
B35
L21
C26
A C27 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
C24 FC_Y7 Y7 TP_CPU_VCCST_PWRGD PAGE TITLE
C25 FC_K9 K9 TP_CPU_VCCST CPU Power
DRAWING NUMBER SIZE

Y7,K9 FOR FUTURE CPU COMPATIBILITY Apple Inc. 051-9889 D


REVISION
NC FOR NOW BUT NEEDED FOR 2014 CPUS R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 8 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE
OMIT_TABLE OMIT_TABLE B32 VSS U0500 VSS K24
A11 U0500 AH1 AL40 U0500 AR24 B34 VSS HASWELL VSS K26
A13 HASWELL AH2 AM1 HASWELL AR16 B36 VSS LGA VSS K28
A15 LGA AH3 AM11 LGA AR30 C3 VSS SYM 9 OF 11 VSS K30
A17 SYM 7 OF 11 AH5 AM14 SYM 8 OF 11 AR31 C4 VSS VSS K32
A23 GROUND AH33 AM15 GROUND AR32 C6 K34
VSS VSS
D A5
A7
AH8
AH36
AM19
AM2
AR33
AR34
C12
C14
VSS VSS K36
K40
D
VSS VSS
AA3 AH4 AL36 AR35 C16 VSS VSS L3
AA33 AJ11 AM24 AR36 C18 VSS VSS L6
AA35 AJ14 AM27 AR37 C19 VSS VSS L7
AA38 AJ19 AM3 AR38 C21 VSS VSS L8
AA6 AJ16 AM30 AR39 C23 VSS VSS L9
AA7 AJ18 AM31 AR40 C36 VSS VSS L11
AA8 AJ22 AL37 AR27 D2 VSS VSS L13
AB5 AJ26 AL38 AT11 D5 VSS VSS L14
AB34 AJ27 AL39 AT12 D6 VSS VSS L35
AB37 AJ30 AM34 AT13 D7 VSS VSS L36
AB6 AJ31 AM35 AT14 D9 VSS VSS L38
AC33 AJ23 AM36 AT15 D11 VSS VSS M1
AC34 AJ32 AM4 AT16 D13 VSS VSS M4
AC35 AJ33 AM5 AT2 D15 VSS VSS M5
AC36 AJ34 AN10 AR5 D17 VSS VSS M6
AB7 AJ35 AN11 AT24 D23 VSS VSS M7
AC3 AJ40 AN14 AT1 D24 VSS VSS M9
AC39 AJ36 AM32 AT25 D26 VSS VSS M12
AC37 AJ5 AM33 AT26 D28 VSS VSS M14
AC40 AJ37 AN16 AT27 D30 VSS VSS M16
AC38 AK1 AN27 AT28 D32 VSS VSS M18
AD1 AK10 AN30 AT10 D34 VSS VSS M20
AD2 AJ8 AN18 AT34 D36 VSS VSS M22
AD3 VSS VSS AK18 AN36 AT36 D37 VSS VSS M24
E3 M26
C AC6
AC7
AK19
AK24
AN37
AN40
AT38
AT39 E6
VSS
VSS
VSS
VSS M28 C
AD33 AK25 AN19 AT4 E7 VSS VSS M30
AD36 AK26 AN5 AT5 E8 VSS VSS M32
AD4 AK27 AN22 AT6 E10 VSS VSS M34
AD5 AK28 AN6 AT7 E18 VSS VSS M35
AD8 AK29 AN23 AT8 E20 VSS VSS M37
AD6 AK11 AN7 AT9 E22 VSS VSS M40
AE33 AK30 AN24 VSS VSS AU2 E23 VSS VSS N1
AD7 AK12 AP1 AU25 E36 VSS VSS N2
AE36 AK13 AP11 AU3 E38 VSS VSS N3
AE37 AK14 AP14 AW7 F1 VSS VSS N4
AE40 AK36 AP15 AU34 F4 VSS VSS N6
AF33 AK5 AP24 AU38 F7 VSS VSS N7
AE5 AK6 AP27 AU5 F12 VSS VSS N8
AF36 AK7 AP30 AU7 F14 VSS VSS N33
AF4 AK8 AP36 AV21 F16 VSS VSS N34
AF5 AK9 AP4 AV28 F19 VSS VSS N39
AF8 AL11 AN8 AV3 F21 VSS VSS P2
AE8 AL14 AP5 AV30 F22 VSS VSS P5
AF1 AL17 AR11 AV34 F24 VSS VSS P7
AG33 AL21 AR14 AV38 F26 VSS VSS P34
AG36 AL22 AN9 AV7 F28 VSS VSS P35
AG37 AL24 AR17 AT29 F30 VSS VSS P38
AG38 AL27 AR18 AT3 F32 VSS VSS P39
AG5 AL30 AR19 AT30 F34 VSS VSS P40
AG39 AL5 AR20 AT32 F36 VSS VSS R3
B AG8
AG40
AK4 AR21
AR22
U34
U35
G3
G6
VSS VSS R5
R6
B
VSS VSS
AR23 U36 G7 VSS VSS R7
H39 U37 G9 VSS VSS R8
J3 V3 G11 VSS VSS R35
J6 V6 G12 VSS VSS R37
J7 V7 G13 VSS VSS R38
J11 V8 G14 VSS VSS R39
J14 V33 G15 VSS VSS R40
J18 V34 G16 VSS VSS T1
J19 V40 G17 VSS VSS T2
J20 W1 G21 VSS VSS T4
J36 W4 G36 VSS VSS T5
J37 W7 G37 VSS VSS T6
K1 W33 H1 VSS VSS T7
K4 W35 H4 VSS VSS T33 CPU_VCCSENSE_N 61 93
OUT
K7 W37 H7 VSS VSS T36
K10 Y4 H8 VSS VSS T37
K14 Y5 H9 T38 PLACE_NEAR=U0500.F40:50.8mm 1
VSS VSS R0960
K15 Y6 H10 T39 PLACE_SIDE=BOTTOM
VSS VSS 100
K16 Y33 H11 U2 5%
VSS VSS 1/16W
K17 K20 H13 U4 MF-LF
VSS VSS 2
402
K18 K22 H17 VSS VSS U7
H18 VSS VSS U33
H20 VSS
H21
A H22
VSS
VSS
VSS_NCTF
VSS_NCTF
AU40
AV39 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
H24 VSS PAGE TITLE
VSS_NCTF AW38
H26 VSS
VSS_NCTF AY3 CPU Ground
H28 VSS DRAWING NUMBER SIZE
VSS_NCTF B38
H30 VSS
VSS_NCTF B39 Apple Inc. 051-9889 D
H32 VSS REVISION
VSS_NCTF C40
H34 VSS
R
13.0.0
VSS_NCTF D40
H36 VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH
VSS_SENSE F40 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 9 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 9 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING
Intel Recommendation:22x 22UF 0805,topside (18 inside cavity, 4 north of processor),8x 470uF bulk caps(5 stuffed,3 no-stuffed)
Apple Implementation:28x 22UF 0603 per Harold
18x 10UF 0603 placed inside socket cavity

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.
BULK CAPS ON CPU VREG PAGE 71

D 80 61 48 8 6 =PPCPUVCC_S0_CPU
D
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1000 1 C1001 1 C1002 1 C1003 1 C1004 1 C1005 1 C1006 1 C1007 1 C1008 1 C1009 1 C1010
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1011 1 C1012 1 C1013 1 C1014 1 C1015 1 C1016 1 C1017 1 C1018 1 C1019 1 C1020 1 C1021
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL


1 C1022 1 C1023 1 C1024 1 C1025 1 C1026 1 C1027
22UF 22UF 22UF 22UF 22UF 22UF ADDED CRITICAL PROPERTY TO CPU CORE DECOUPLING
20% 20% 20% 20% 20% 20% DUE TO ACOUSTICS CONCERNS
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2

C 0603 0603 0603 0603 0603 0603


C

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL


1 C1030 1 C1031 1 C1032 1 C1033 1 C1034 1 C1035 1 C1036 1 C1037 1 C1038
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL


1 C1039 1 C1040 1 C1041 1 C1042 1 C1043 1 C1044 1 C1045 1 C1046 1 C1047
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
603 603 603 603 603 603 603 603 603

B B
Memory (CPU VCCDDR) DECOUPLING
Intel Recommendation:9x 22UF 0805 near CPU power pins
Apple Implementation:9x 22UF 0603 per Harold
Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

80 8 6 =PP1V5_S0_CPU_MEM

1 C1050 1 C1051 1 C1052 1 C1053 1 C1054 1 C1055 1 C1056 1 C1057 1 C1058


22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2
0603 0603 0603 0603 0603 0603 0603 0603 0603

NOSTUFF NOSTUFF NOSTUFF


1 C1060 1 C1061 1 C1062
22UF 22UF 22UF
20% 20% 20%
2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2
0603 0603 0603

A SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE

CPU DECOUPLING
DRAWING NUMBER SIZE

NOSTUFF Apple Inc. 051-9889 D


CRITICAL REVISION
1
C1059
R
13.0.0
330UF-0.0045OHM NOTICE OF PROPRIETARY PROPERTY: BRANCH
20%
2 2V THE INFORMATION CONTAINED HEREIN IS THE
POLY PROPRIETARY PROPERTY OF APPLE INC.
CASE-D2-SM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 10 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
SATA Port assignments:
89 19 IN PCH_CLK32K_RTCX1 AN40 RTCX1 U1100 SATA_RXN0 B28 SATA_HDD_D2R_N IN 33 88

89 19 PCH_CLK32K_RTCX2 AN39 RTCX2 LYNX SATA_RXP0 A28 SATA_HDD_D2R_P 33 88


OUT IN
FCBGA F31 PRIMARY HDD
SATA_TXN0 SATA_HDD_R2D_C_N OUT 33 88
DESKTOP H31
AR39 SRTCRST* SATA_TXP0 SATA_HDD_R2D_C_P OUT 33 88
11 PCH_SRTCRST_L SYM 1 OF 11
SATA_RXN1 D30
11 PCH_INTRUDER_L AR41 INTRUDER* NC
SATA_RXP1 C30
NC

RTC
PCH_INTVRMEN_L AV36 INTVRMEN SATA_TXN1 B34
11
NC
SATA_TXP1 C34
45 19 11 RTC_RESET_L AR38 RTCRST* NC
SATA_RXN2 A31
NC
D R1110 33 AV23 HDA_BCLK SATA_RXP2 B31
NC D

SATA
89 52 OUT HDA_BIT_CLK 1 2 89 HDA_BIT_CLK_R
SATA_TXN2 B35
5% 1/20W MF 201
PLACE_NEAR=U1100.AV23:5MM NC
SATA_TXP2 D35
89 52 OUT HDA_SYNC R1111 33 1 2 89 HDA_SYNC_R AV24 HDA_SYNC (IPD-boot) NC
5% 1/20W MF 201
SATA_RXN3 B32
PLACE_NEAR=U1100.AV24:5MM
NC
PCH_SPKR R32 SPKR SATA_RXP3 C32
11 (IPD-PLTRST#)
NC
SATA_TXN3 G33
NC

AZALIA
HDA_RST_L R1112 33 1 2 89 HDA_RST_R_L AU24 HDA_RST* SATA_TXP3 F33
89 52 OUT
5% 1/20W MF 201 NC
PLACE_NEAR=U1100.AU24:7MM
SATA_RXN4/PERN1 A26 SSD_D2R_N<0>
89 52 HDA_SDIN0 AT26 HDA_SDI0 (IPD)
IN 33 88
IN B26 SSD_D2R_P<0>
AV22 SATA_RXP4/PERP1 IN 33 88
82 TP_HDA_SDIN1 HDA_SDI1 (IPD) SSD
SATA_TXN4/PETN1 L28 SSD_R2D_N<0> =PP1V5_S0_PCH_SATA
82 TP_HDA_SDIN2 AT22 HDA_SDI2 (IPD)
OUT 33 88 80

SATA_TXP4/PETP1 K28 SSD_R2D_P<0>


82 TP_HDA_SDIN3 AW23 HDA_SDI3 (IPD)
OUT 33 88

SATA_RXN5/PERN2 C27 SSD_D2R_N<1> 33 88


IN
89 52 HDA_SDOUT R1113 33 1 2 89 19 HDA_SDOUT_R AU22 HDA_SDO (IPD-boot) SATA_RXP5/PERP2 B27 SSD_D2R_P<1> 33 88
R1130 1
OUT IN
5% 1/20W MF 201
G28 7.5K
PLACE_NEAR=U1100.AU22:6MM SATA_TXN5/PETN2 SSD_R2D_N<1> OUT 33 88 1%
(IPD-DOCKEN#?)
AV26 DOCKEN*/GPIO33 1/20W
=PP3V3_G3_PCH 12 80 58 41 11 DP_TBT_SEL SATA_TXP5/PETP2 F28 SSD_R2D_P<1> 33 88 MF
OUT OUT
AN22 HDA_DOCK_RST*/GPIO13 201
90 35 11 IN ENET_MEDIA_SENSE 2
PLACE_NEAR=U1100.D33:2.54MM
SATA_RCOMP D33 88 PCH_SATA_RCOMP
R1102 1
1
R1103 88 18 IN XDP_PCH_TCK Y40 JTAG_TCK (IPD)
1
20K 20K SATALED* J39 PCH_SATALED_L 11 33
R1100 1
R1101 5% 5% W40 JTAG_TMS
390K 1/20W 1/20W 88 18 IN XDP_PCH_TMS (IPU)
1M MF MF
SATA0GP/GPIO21 M37

JTAG
5%
5% 201 201 W39 JTAG_TDI DP_AUXIO_EN OUT 11 18 29 30
1/20W 1/20W 2 2 88 18 IN XDP_PCH_TDI (IPU)
MF MF SATA1GP/GPIO19 J40 SATARDRVR_EN OUT 11 18
201
2 2 201
PCH_SRTCRST_L 11 Y38 JTAG_TDO (IPU-PLTRST#)
88 18 OUT XDP_PCH_TDO
PCH_INTRUDER_L
SATA_IREF A33
11

PCH_INTVRMEN_L 11 AM34
NC TP25
RTC_RESET_L 11 19 45
AH24 TP22
C C1102 1 1
C1103
NC
NC
W37 TP20
TP9 K34
TP8 K33
NC
NC
C
1UF 1UF
10% 10%
10V 10V
X5R 2 2 X5R OMIT_TABLE
402 402
87 33 OUT PCIE_CLK100M_SSD_N AE10 CLKOUT_PCIE_N0
U1100 CLKOUT_PEG_A_N AA3 NC
87 33 OUT PCIE_CLK100M_SSD_P AE11 CLKOUT_PCIE_P0
LYNX CLKOUT_PEG_A_P AA2 NC
W34 PCIECLKRQ0*/GPIO73 FCBGA
33 11 IN SSD_CLKREQ_L DESKTOP
SYM 2 OF 11
87 35 OUT PCIE_CLK100M_ENET_N AC6 CLKOUT_PCIE_N1 CLKOUT_PEG_B_N AE6 NC
87 35 OUT PCIE_CLK100M_ENET_P AC7 CLKOUT_PCIE_P1 CLKOUT_PEG_B_P AE7 NC
35 18 11 ENET_CLKREQ_L P39 PCIECLKRQ1*/GPIO18
IN

87 32 OUT PCIE_CLK100M_AP_N AC11 CLKOUT_PCIE_N2 CLKOUT_DMI_N R2 DMI_CLK100M_CPU_N OUT 6 87

87 32 OUT PCIE_CLK100M_AP_P AC10 CLKOUT_PCIE_P2 CLKOUT_DMI_P T2 DMI_CLK100M_CPU_P OUT 6 87

AP_CLKREQ_L P37 PCIECLKRQ2*/GPIO20/SMI*


CLKOUT_DP_N T3
32 18 11 IN CPU_CLK135M_DPLLSS_N OUT 6 87

W11 CLKOUT_PCIE_N3 CLKOUT_DP_P T5 CPU_CLK135M_DPLLSS_P OUT 6 87


87 26 OUT PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P W10 CLKOUT_PCIE_P3
CLKOUT_DPNS_N W2
87 26 OUT CPU_CLK135M_DPLLREF_N OUT 6 87

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks. 11 PCH_CLKRQ3_L_GPIO25 AA39 PCIECLKRQ3*/GPIO25 CLKOUT_DPNS_P U2 CPU_CLK135M_DPLLREF_P OUT 6 87

CLOCKS
PEG-attached (CPU) PCIe devices must use one set, Unused clock terminations for FCIM Mode
while PCH-attached PCIe devices use the other set. 82 TP_PCIE_CLK100M_PE4N Y4 CLKOUT_PCIE_N4 CLKIN_DMI_N G22 PCIE_CLK100M_PCHN R1196 10K 1 2
5% 1/20W MF 201
If 2 or less devices are attached to PEG the 82 TP_PCIE_CLK100M_PE4P Y2 CLKOUT_PCIE_P4 CLKIN_DMI_P F22 PCIE_CLK100M_PCHP R1195 10K 1 2
5% 1/20W MF 201
CLKOUT_PEG outputs can be used for those devices. W35 PCIECLKRQ4*/GPIO26
28 11 IN TBT_CLKREQ_L
CLKIN_GND_N G16 PCH_CLKIN_GNDN R1171 10K 1 2

B 82 TP_PCIE_CLK100M_PE5N W7 CLKOUT_PCIE_N5 CLKIN_GND_P F16 PCH_CLKIN_GNDP R1170 10K 1 2


5%

5%
1/20W

1/20W
MF

MF
201

201
B
82 TP_PCIE_CLK100M_PE5P W6 CLKOUT_PCIE_P5
CLKIN_DOT96_N AP11 PCH_CLK96M_DOTN R1192 10K 1 2
5% 1/20W MF 201
11 PCH_CLKRQ5_L_GPIO44 AA36 PCIECLKRQ5*/GPIO44 CLKIN_DOT96_P AM11 PCH_CLK96M_DOTP R1191 10K 1 2
(IPU-RSMRST#) 5% 1/20W MF 201

86 72 OUT PEG_CLK100M_N AA7 CLKOUT_PCIE_N6 CLKIN_SATA_N H35 PCH_CLK100M_SATAN R1194 10K 1 2


5% 1/20W MF 201
86 72 OUT PEG_CLK100M_P AA6 CLKOUT_PCIE_P6 CLKIN_SATA_P H36 PCH_CLK100M_SATAP R1193 10K 1 2
5% 1/20W MF 201

72 11 PEG_CLKREQ_L W32 PCIECLKRQ6*/GPIO45


REFCLK14IN AR7
IN PCH_CLK14P3M_REFCLK R1197 10K 1 2
5% 1/20W MF 201

82 TP_PCIE_CLK100M_PE7N R6 CLKOUT_PCIE_N7 CLKIN_33MHZLOOPBACK AM22 PCH_CLK33M_PCIIN IN 19 89

82 TP_PCIE_CLK100M_PE7P R7 CLKOUT_PCIE_P7 R1172


340
AA40 PCIECLKRQ7*/GPIO46 XTAL25_IN N7 89 SYSCLK_CLK25M_SB_R 1 2 SYSCLK_CLK25M_SB IN 19 89
11 PCH_CLKRQ7_L_GPIO46
(IPU-RSMRST#) XTAL25_OUT N6 NC PLACE_NEAR=U1100.N7:5MM 1%
1/16W
1
=PP3V3_S5_PCH_VCCSUS_GPIO 12 13 14 15 17 80
R1173 MF-LF
402
(IPD-PWROK) CLKOUTFLEX0/GPIO64 AV8 TP_PCH_GPIO64_CLKOUTFLEX0 82 1K
=PP3V3_S0_PCH_VCC3_3_GPIO 12 13 14 15 17 80 1%
88 82 OUT ITPXDP_CLK100M_N U6 CLKOUT_ITPXDP_N (IPD-PWROK) CLKOUTFLEX1/GPIO65 AT9 TP_PCH_GPIO65_CLKOUTFLEX1 82 1/20W
MF
88 82 ITPXDP_CLK100M_P U7 CLKOUT_ITPXDP_P (IPD-PWROK) CLKOUTFLEX2/GPIO66 AV9 TP_PCH_GPIO66_CLKOUTFLEX2 82 201
R1177 4.7K 1 2 PCH_SPKR OUT 2
11
5% 1/20W MF 201 (IPD-PWROK) CLKOUTFLEX3/GPIO67 AU8 TP_PCH_GPIO67_CLKOUTFLEX3 82
R1176 10K 1 2 DP_TBT_SEL 11 41 58
5% 1/20W MF 201 =PP1V5_S0_PCH_CLK 19 80
R1178 10K 1 2 PCH_SATALED_L 11 33
5% 1/20W MF 201 ICLK_IREF N10
R1134 10K 1 2 DP_AUXIO_EN 11 18 29 30 89 19 OUT LPC_CLK33M_SMC_R AV5 CLKOUT_33MHZ0 (IPD-PWROK)
5% 1/20W MF 201
R1133 10K 1 2 SATARDRVR_EN 11 18 89 19 OUT LPC_CLK33M_LPCPLUS_R AV7 CLKOUT_33MHZ1 (IPD-PWROK) TP19 U11 NC
5% 1/20W MF 201
TP_PCI_CLK33M_OUT2 AU2 CLKOUT_33MHZ2 TP18 U10
R1143 10K 1 2 SSD_CLKREQ_L
82 (IPD-PWROK)
NC
5% 1/20W MF 201
11 33
82 TP_PCI_CLK33M_OUT3 AN9 CLKOUT_33MHZ3 (IPD-PWROK)
R1190 =PP1V5_S0_PCH_VCCVRM_BIAS 17
R1142 10K 1 2 ENET_CLKREQ_L 7.5K
DIFFCLK_BIASREF R11
11 18 35
5% 1/20W MF 201 89 19 OUT PCH_CLK33M_PCIOUT AU5 CLKOUT_33MHZ4 (IPD-PWROK) PCH_DIFFCLK_BIASREF 2 1
R1169 10K
A R1144 10K
1

1
2

2
5%
5%
1/20W
1/20W
MF
MF
201
201
AP_CLKREQ_L
PCH_CLKRQ3_L_GPIO25
11 18 32

11
PLACE_NEAR=U1100.R11:2.54MM 1%
1/20W
MF
SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
R1145 10K 1 2 TBT_CLKREQ_L 11 28 201 PAGE TITLE
R1147 10K 1 2
5%

5%
1/20W

1/20W
MF

MF
201

201
PCH_CLKRQ5_L_GPIO44 11 PCH RTC/HDA/JTAG/SATA/CLK
R1114 10K 2 1 PEG_CLKREQ_L 11 72 DRAWING NUMBER SIZE
R1115 10K 1 2
5%

5%
1/20W

1/20W
MF

MF
201

201
PCH_CLKRQ7_L_GPIO46 11
Apple Inc. 051-9889 D
REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1179 10K 1 2 ENET_MEDIA_SENSE 11 35 90 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 11 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 11 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE

87 5 IN DMI_N2S_N<0> L24 DMI_RXN0 U1100 FDI_RXN0 N1 NC


DMI_N2S_N<1> G24 DMI_RXN1 LYNX FDI_RXN1 P2
87 5 IN NC
87 5 DMI_N2S_N<2> F26 DMI_RXN2 FCBGA
FDI_RXP0 N2
IN
K26 DESKTOP NC
87 5 DMI_N2S_N<3> DMI_RXN3
IN SYM 4 OF 11 FDI_RXP1 P3 NC
87 5 DMI_N2S_P<0> K24 DMI_RXP0
IN
87 5 DMI_N2S_P<1> H24 DMI_RXP1
IN
87 5 DMI_N2S_P<2> G26 DMI_RXP2
IN
DMI_N2S_P<3> L26 DMI_RXP3 TP16 R4
87 5 IN NC
TP5 K5
C20 P5
NC
DMI_S2N_N<0> DMI_TXN0 TP15
D
87 5

87 5
OUT
OUT DMI_S2N_N<1> D21
B22
DMI_TXN1 TP10 L5
NC
NC D
87 5 OUT DMI_S2N_N<2> DMI_TXN2

DMI
FDI
87 5 DMI_S2N_N<3> A24 DMI_TXN3
OUT

87 5 DMI_S2N_P<0> B20 DMI_TXP0 FDI_CSYNC L2 FDI_CSYNC 5 88


OUT OUT
87 5 DMI_S2N_P<1> B21 DMI_TXP1 FDI_INT L3 FDI_INT 5 88
OUT OUT
87 5 DMI_S2N_P<2> C22 DMI_TXP2
=PP1V5_S0_PCH_RCOMP OUT =PP1V5_S0_PCH_RCOMP
80 13 12
87 5 DMI_S2N_P<3> B24 DMI_TXP3
12 13 80
OUT

A19 DMI_IREF FDI_IREF N11


R1200 1 R1210 1
7.5K L22 TP12 7.5K =PP3V3_G3_PCH 11 80
1%
NC TP17 R12 NC 1%
1/20W K22 TP7 TP13 N12
1/20W
MF
NC NC MF
1
201
2
PLACE_NEAR=U1100.K2:12.7MM
201
2 R1215
PLACE_NEAR=U1100.B19:12.7MM B19 DMI_RCOMP 390K
87 PCH_DMI_RCOMP FDI_RCOMP K2 88 PCH_FDI_RCOMP 5%
1/20W
MF
2 201
PCH_SUSACK_L AJ37 SUSACK* (IPU)
DSWVRMEN AM41 PCH_DSWVRMEN

SYSTEM POWER
MANAGEMENT
44 19 PM_SYSRST_L N36 SYS_RESET*
IN
DPWROK AV38 PM_RSMRST_PCH_L IN 12 18 71

PM_PCH_SYS_PWROK W31 SYS_PWROK


WAKE* AK34
71 45 18 IN
1
PCIE_WAKE_L IN 12 32 36
1
R1286 PM_PCH_PWROK AT40 PWROK (IPD-DeepSx) R1209
GPIO32 N32
71 39 20 18 IN
0 PCH_GPIO32 BI 12 10K
5% AA32 APWROK 5%
1/20W PM_PCH_APWROK 1/20W
SUS_STAT*/GPIO61 AD37
71 IN
MF LPC_PWRDWN_L OUT 20 44 46 MF
0201
2 PM_MEM_PWRGD AE38 DRAMPWROK 2 201
SUSCLK/GPIO62 W36
21 6 OUT
(OD) PM_CLK32K_SUSCLK_R OUT 45 89
AM40 RSMRST* (IPU-RSMRST#)
71 18 12 IN PM_RSMRST_PCH_L AA35
SLP_S5*/GPIO63 PM_SLP_S5_L 12 32 44 70

C
OUT
C 80 17 15 14 13 12 11 =PP3V3_S5_PCH_VCCSUS_GPIO
PCH_SUSWARN_L AG41 SUSWARN*/SUSPWRNACK/GPIO30
SLP_S4* AT35 PM_SLP_S4_L OUT 12 44 70

PM_PWRBTN_L AK41
R1205 1 44 18 12 IN PWRBTN* (IPU)
SLP_S3* AK40 PM_SLP_S3_L 12 21 36 44 45 70 71
OUT
10K AM36
5% 12 IN PCH_GPIO31 ACPRESENT/GPIO31 AN37
1/20W (IPD-DeepSx) SLP_A* TP_PM_SLP_A_L
MF AJ40
201 12 IN PCH_GPIO72 GPIO72 AK38
2
SLP_SUS* PM_SLP_SUS_L OUT 12

PCH_RI_L AE36 RI*


PMSYNCH F40 PM_SYNC 6 86
OUT
AC35 TP21
NC SLP_LAN* AU36 TP_PCH_SLP_LAN_L
TP_PCH_SLP_WLAN_L AL39 SLP_WLAN*/GPIO29

OMIT_TABLE

NC
AC3 VGA_BLUE U1100
NC
AE2 VGA_GREEN LYNX
AC2 VGA_RED FCBGA
NC DESKTOP AM1
SYM 5 OF 11 DDPB_CTRLCLK NC
AL2 VGA_DDC_CLK DDPB_CTRLDATA AJ5
VGA DAC Disabled per SB NC (IPD-PLTRST#)
NC
AL3 VGA_DDC_DATA
NC DDPC_CTRLCLK AN3
DG v1.0 (Table 11-11). NC
AH3 DDPC_CTRLDATA AM2 NC
NC VGA_HSYNC (IPD-PLTRST#)
AH2 VGA_VSYNC DDPD_CTRLCLK AN4
NC NC
DDPD_CTRLDATA AN2

CRT
(IPD-PLTRST#)
NC

DISPLAY
AF5 DAC_IREF
AG4 VGA_IRTN DDPB_AUXN AK6 NC
DDPC_AUXN AG7 NC
B NC
AP2 EDP_BKLTCTL DDPD_AUXN AG11 NC B

EDP
AT2 EDP_BKLTEN DDPB_AUXP AK8 NC
NC DDPC_AUXP AG6 NC
AP1 EDP_VDDEN DDPD_AUXP AG10
NC NC
80 17 15 14 13 12 11 =PP3V3_S0_PCH_VCC3_3_GPIO
DDPB_HPD AJ2 NC
R1260 10K 1 2 PCI_INTA_L AU29 PIRQA*
5% 1/20W MF 201 DDPC_HPD AH5 NC
=PP3V3_S5_PCH_VCCSUS_GPIO R1261 10K 1 2 PCI_INTB_L AU27 PIRQB*
DDPD_HPD AJ4
11 12 13 14 15 17 80

R1262 10K 1 2
5% 1/20W MF 201
PCI_INTC_L AW28 PIRQC* NC
5% 1/20W MF 201
=PP3V3_S0_PCH_VCC3_3_GPIO 11 12 13 14 15 17 80 R1263 10K 1 2 PCI_INTD_L AV27 PIRQD*
5% 1/20W MF 201 AR30

PCI
PIRQE*/GPIO2 SDCONN_OC_L IN 12 37

20 12 ENET_LOW_PWR_PCH AH26 GPIO50 PIRQF*/GPIO3 AV29 AUD_IP_PERIPHERAL_DET 12 58


R1226 10K 2 1 PCH_GPIO31 OUT IN
12 AV28
5% 1/20W MF 201 20 12 OUT AUD_IPHS_SWITCH_EN_PCH AJ26 GPIO52 PIRQG*/GPIO4 TBT_PWR_REQ_L IN 12 26

R1240 10K 2 1 PCH_GPIO72 12 32 12 BT_PWR_RST_L AW33 GPIO54 PIRQH*/GPIO5 AT27 AUD_I2C_INT_L 12 56


OUT IN
5% 1/20W MF 201
R1291 10K 1 2 PCH_GPIO32 12
AU31 GPIO51 AA31
5% 1/20W MF 201 TP_PCH_STRP_BBS1 (IPU)PME* TP_PCI_PME_L
R1216 10K 1 2 ENET_LOW_PWR_PCH 12 20 TP_PCH_STRP_ESI_L AV31 GPIO53
5% 1/20W MF 201
R1217 100K 1 2 AUD_IPHS_SWITCH_EN_PCH 12 20 45 OUT PCH_STRP_TOPBLK_SWP_L R30 GPIO55 PLTRST* AA37 PLT_RESET_L OUT 20
5% 1/20W MF 201 (IPU-PWROK&PCIRST#)
R1218 10K 1 2 BT_PWR_RST_L 12 32
5% 1/20W MF 201
R1230 10K 1 2 SDCONN_OC_L 12 37
5% 1/20W MF 201

NOSTUFF Redundant to pull-up on audio page


R1214 100K 1 2 AUD_IP_PERIPHERAL_DET 12 58
5% 1/20W MF 201
R1231 10K 1 2 TBT_PWR_REQ_L 12 26
5% 1/20W MF 201

NOSTUFF Redundant to pull-up on audio page


R1233 10K
A R1225 1K
1

1
2

2
5% 1/20W MF
AUD_I2C_INT_L
201
12 56

12 32 36
SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
5% 1/20W MF 201
PAGE TITLE
PCIE_WAKE_L
MAKE_BASE=TRUE
=TBT_WAKE_L 26 PCH DMI/FDI/PM/GFX/PCI
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


R1227 3.0K 1 2 PM_PWRBTN_L 12 18 44 REVISION
5% 1/20W MF 201 R
13.0.0
R1224 100K 2 1 PM_SLP_S3_L
NOTICE OF PROPRIETARY PROPERTY: BRANCH
12 21 36 44 45 70 71
5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE
R1221 100K 2 1 PM_SLP_S4_L 12 44 70 PROPRIETARY PROPERTY OF APPLE INC.
5% 1/20W MF 201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
R1222 100K 2 1 PM_SLP_S5_L 12 32 44 70
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
R1223 100K 2 1
5% 1/20W MF 201
PM_SLP_SUS_L
12 OF 123
12 II NOT TO REPRODUCE OR COPY IT
5% 1/20W MF 201
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE USB Port Assignments:

U1100 USB2N0 AV10 USB_EXTA_0_N BI 42 90


Ext A (LS/FS/HS)
LYNX USB2P0 AU10 USB_EXTA_0_P BI 42 90
FCBGA
DESKTOP USB2N1 AV11 USB_EXTC_1_N BI 43 90
Ext C (LS/FS/HS)
SYM 9 OF 11 USB2P1 AW11 USB_EXTC_1_P BI 43 90

L14 PERN1_USB3RN3 USB2N2 AN14


NC NC
K14 PERP1_USB3RP3 USB2P2 AP14
NC NC
B12 PETN1_USB3TN3 USB2N3 AJ16
NC NC
B11 PETP1_USB3TP3 USB2P3 AK16
NC NC

D NC
F14 PERN2_USB3RN4
USB2N4 AU15
USB2P4 AV15
NC
NC
D
G14 PERP2_USB3RP4
NC USB2N5 AU12 NC
D11 PETN2_USB3TN4 USB2P5 AT12
NC NC
C11 PETP2_USB3TP4
NC USB2N6 AV14 NC
USB2P6 AW14 NC
87 32 PCIE_AP_D2R_N F11 PERN3
IN
H11 PERP3 USB2N7 AU17 NC
87 32 PCIE_AP_D2R_P
USB2P7 AT17
IN
AirPort NC
87 32 PCIE_AP_R2D_C_N B9 PETN3
OUT
A9 PETP3 USB2N8 AW16 USB_EXTB_8_N BI 42 90
87 32 OUT PCIE_AP_R2D_C_P Ext B (LS/FS/HS)
USB2P8 AV16 USB_EXTB_8_P BI 42 90

J11 PERN4 USB2N9 AN16 USB_EXTD_9_N BI 43 90


PCIE_ENET_D2R_N Ext D (LS/FS/HS)
USB2P9 AP16
87 35 IN
L11 PERP4 USB_EXTD_9_P BI 43 90
87 35 IN PCIE_ENET_D2R_P
ENET
B8 PETN4 USB2N10 AJ18 USB_CAMERA_N BI 38 90
87 35 PCIE_ENET_R2D_C_N CAMERA
OUT
C8 PETP4 USB2P10 AK18 USB_CAMERA_P BI 38 90
87 35 OUT PCIE_ENET_R2D_C_P
USB2N11 AP18 USB_BT_N BI 32 90
BT
G9 PERN5 USB2P11 AN18 USB_BT_P BI 32 90
87 26 IN PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<0> F9 PERP5 USB2N12 AW18
87 26 IN NC
B7 PETN5 USB2P12 AV18 NC
87 26 OUT PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_P<0> A7 PETP5 USB2N13 AP20
87 26 OUT NC
USB2P13 AN20 NC
(IPD)
F7 PERN6 USB3 Port Assignments:
87 26 IN PCIE_TBT_D2R_N<1> F20 USB3_EXTA_RX_F_N

PCI-E
H7 PERP6 USB3RN1 IN 42 90
PCIE_TBT_D2R_P<1>

USB
87 26

C
IN G20
C 87 26 OUT PCIE_TBT_R2D_C_N<1> E1 PETN6
USB3RP1
USB3TN1 B18
USB3_EXTA_RX_F_P
USB3_EXTA_TX_N
IN
OUT
42 90

42 90
Ext A (SS)

87 26 PCIE_TBT_R2D_C_P<1> D2 PETP6 USB3TP1 C18 USB3_EXTA_TX_P 42 90


OUT OUT
TBT
USB3RN2 G18 USB3_EXTB_RX_F_N 42 90
IN
87 26 PCIE_TBT_D2R_N<2> K6 PERN7 USB3RP2 H18 USB3_EXTB_RX_F_P 42 90
IN IN
K8 PERP7 B15 Ext B (SS)
87 26 IN PCIE_TBT_D2R_P<2> USB3TN2 USB3_EXTB_TX_N OUT 42 90

USB3TP2 B16 USB3_EXTB_TX_P


87 26 PCIE_TBT_R2D_C_N<2> G3 PETN7 OUT 42 90
OUT
87 26 PCIE_TBT_R2D_C_P<2> G5 PETP7 USB3RN5 K20 USB3_EXTC_RX_F_N 43 90
OUT IN
USB3RP5 L20 USB3_EXTC_RX_F_P 43 90
IN
D15 Ext C (SS)
J2 PERN8 USB3TN5 USB3_EXTC_TX_N OUT 43 90
87 26 IN PCIE_TBT_D2R_N<3> C15
J3 PERP8 USB3TP5 USB3_EXTC_TX_P OUT 43 90
87 26 IN PCIE_TBT_D2R_P<3> 90 PCH_USB_RBIAS
USB3RN6 L18 USB3_EXTD_RX_F_N PLACE_NEAR=U1100.AV20:11.4MM
87 26 PCIE_TBT_R2D_C_N<3> H2 PETN8 IN 43 90
OUT
USB3RP6 K18 USB3_EXTD_RX_F_P 1
87 26 OUT PCIE_TBT_R2D_C_P<3> H1 PETP8 IN 43 90
Ext D (SS) R1370
USB3TN6 B14 USB3_EXTD_TX_N 43 90 22.6
OUT
A14 1%
USB3TP6 USB3_EXTD_TX_P OUT 43 90 1/20W
MF
2 201
USBRBIAS* AV20
USBRBIAS AU20

TP24 AK14 NC
TP23 AJ14 NC
80 12 =PP1V5_S0_PCH_RCOMP AE40
OC0*/GPIO59 USB_EXTA_OC_L IN 13 18 42

OC1*/GPIO40 AF37 USB_EXTC_OC_L 13 18 43


IN
B13 PCIE_IREF OC2*/GPIO41 AD39 PCH_GPIO41 13 18
1 OUT
R1300
B 7.5K
1%
NC
L16 TP11
OC3*/GPIO42
OC4*/GPIO43
AD40
AF39
PCH_GPIO42
USB_EXTB_OC_L
OUT
IN
13 18

13 18 42
B
1/20W K16 TP6 AC41
OC5*/GPIO9 USB_EXTD_OC_L
MF
201
NC AF40
IN 13 18 43
2
PLACE_NEAR=U1100.C13:12.7MM OC6*/GPIO10 PCH_GPIO10 OUT 13 18

87 PCH_PCIE_RCOMP C13 PCIE_RCOMP OC7*/GPIO14 AG40 SDCONN_STATE_CHANGE 13 18 37


IN

OMIT_TABLE

89 46 44 BI LPC_AD<0> R1340 33 1 2
5% 1/20W MF 201
89 LPC_AD_R<0> AN24 LAD0 (IPU) U1100 SMBALERT*/GPIO11 AG31 PCH_SMBALERT_L 13

89 46 44 BI LPC_AD<1> R1341 33 1 2
5% 1/20W MF 201
89 LPC_AD_R<1> AP26 LAD1 (IPU) LYNX SMBCLK AG36 SMBUS_PCH_CLK 47 91
LPC_AD<2> R1342 33 LPC_AD_R<2> AJ24 FCBGA OUT
89 46 44 1 2 89 LAD2 (IPU)
BI
5% 1/20W MF 201 DESKTOP SMBDATA AG32 SMBUS_PCH_DATA BI 47 91
89 46 44 BI LPC_AD<3> R1343 33 1 2 89 LPC_AD_R<3> AN26 LAD3 (IPU)
5% 1/20W MF 201 SYM 3 OF 11
89 46 44 OUT LPC_FRAME_L R1344 33 1 2 89 LPC_FRAME_R_L AP24 LFRAME* SML0ALERT*/GPIO60 AG35 PCH_SML0ALERT_L 13

SMBUS
5% 1/20W MF 201
TP_LPC_DREQ0_L AK22 LDRQ0* (IPU) SML0CLK AE32 SML_PCH_0_CLK

LPC
82 OUT 47 91

20 13 OUT TBT_PWR_EN_PCH AK26 LDRQ1*/GPIO23 SML0DATA AE35 SML_PCH_0_DATA BI 47 91


(IPU-LDRQ1#?)

46 44 13 LPC_SERIRQ G39 SERIRQ


=PP3V3_S5_PCH_VCCSUS_GPIO 11 12 14 15 17 80
BI
SML1ALERT*/PCHHOT*/GPIO74 AJ39 PCH_SML1ALERT_L 13

SML1CLK/GPIO58 AK36 SML_PCH_1_CLK IN 47 91


=PP3V3_S4_PCH 80
SML1DATA/GPIO75 AK33 SML_PCH_1_DATA BI 47 91
=PP3V3_S0_PCH_VCC3_3_GPIO 11 12 14 15 17 80

89 46 SPI_CLK_R U39 SPI_CLK


OUT

C-LINK
SPI
R1350 10K 1 2 LPC_SERIRQ 13 44 46
R38 SPI_CS0* (IPU/IPD) CL_CLK U36 TP_CLINK_CLK
5% 1/20W MF 201 89 46 OUT SPI_CS0_R_L (IPU)
R1351 10K 1 2 TBT_PWR_EN_PCH 13 20
R35 SPI_CS1* (IPU/IPD) CL_DATA U35 TP_CLINK_DATA
5% 1/20W MF 201 NC (IPU)
R1360 10K 1 2 USB_EXTA_OC_L 13 18 42
R40 SPI_CS2* CL_RST* U34 TP_CLINK_RESET_L
R1361 10K 5% 1/20W MF 201 NC (IPU)

A R1362 10K
1

1
2

2
5% 1/20W MF 201
USB_EXTC_OC_L
PCH_GPIO41
13 18 43

13 18 89 46 BI SPI_MOSI_R P40 SPI_MOSI (IPD)


TP1 A2 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
R1368 10K 1 2
5% 1/20W MF 201
PCH_GPIO42 NC PAGE TITLE
13 18
SPI_MISO R36 SPI_MISO TP2 A3
R1320 10K 1 2
5% 1/20W MF 201
USB_EXTB_OC_L 13 18 42
89 46 BI (IPU)

TP4 B2
NC PCH PCI-E/USB
R1321 10K 1 2
5% 1/20W MF 201
USB_EXTD_OC_L U40 SPI_IO2 NC DRAWING NUMBER SIZE
13 18 43
NC (IPU)
TP3 B1
R1367 10K 2 1
5% 1/20W MF 201
PCH_GPIO10 13 18
U37 SPI_IO3 TD_IREF C3
NC
PCH_TD_IREF Apple Inc. 051-9889 D
R1369 10K 1 2
5% 1/20W MF 201
SDCONN_STATE_CHANGE 13 18 37
NC (IPU)
REVISION
5% 1/20W MF 201 PLACE_NEAR=U1100.C3:11.4MM R
1
13.0.0
R1380 NOTICE OF PROPRIETARY PROPERTY: BRANCH
8.2K
1% THE INFORMATION CONTAINED HEREIN IS THE
1/20W PROPRIETARY PROPERTY OF APPLE INC.
R1353 10K 1 2 PCH_SMBALERT_L 13 MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 201
R1354 10K 1 2 PCH_SML0ALERT_L 13
2 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 13 OF 123
5% 1/20W MF 201 II NOT TO REPRODUCE OR COPY IT
R1355 10K 1 2 PCH_SML1ALERT_L 13
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
5% 1/20W MF 201
IV ALL RIGHTS RESERVED 13 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D OMIT_TABLE D
TBT_CIO_PLUG_EVENT_ISOL G38 BMBUSY*/GPIO0
20 IN
U1100 =PP1V05_S0_PCH_V_PROC_IO
14 FW_PME_L AT31 TACH1/GPIO1 LYNX 15 17 80

FCBGA
DPMUX_UC_IRQ AM28 TACH2/GPIO6 DESKTOP PWM0 AL31 NOSTUFF
14
NC
AM31
91 44 14 IN SMC_RUNTIME_SCI_L AV34 TACH3/GPIO7 SYM 6 OF 11 PWM1 NC
1
R1457
PWM2 AP31
NC 1K
AC40 GPIO8 5%
HDD_PWR_EN (IPU-RSMRST#) PWM3 AV30 1/16W
69 18 OUT NC MF-LF
WOL_EN AL40 LAN_PHY_PWR_CTRL/GPIO12 SST AJ31 2 402
36 14 OUT NC
14 MEM_VDD_SEL_1V5_L AC32 GPIO15 TP14 N30 PCH_A20GATE 14

M39 SATA4GP/GPIO16 NOSTUFF


18 14 PCH_GPIO16 (IPD)
IN
(IPU-Boot/SATA4GP?) PECI G40 PCH_PECI R1470 43 1 2 CPU_PECI BI 6 44 45 86
AP28 TACH0/GPIO17 5% 1/20W

CPU/MISC
46 14 BI LPCPLUS_GPIO MF 201

L38 SCLOCK/GPIO22 RCIN* K36 PCH_RCIN_L 14


20 14 OUT JTAG_TBT_TMS_PCH

26 14 TBT_GO2SX_BIDIR AE34 GPIO24 PROCPWRGD D40 86 PCH_PROCPWRGD R1440 0 1 2 CPU_PWRGD 6 18 86


BI OUT
5% 1/20W
AU34 GPIO27 MF 0201
91 44 14 SMC_WAKE_SCI_L (IPU-DeepSx)
THRMTRIP* C40
IN 86 PM_THRMTRIP_L_R R1456 390 1 2 PM_THRMTRIP_L IN 45 86
V41 GPIO28 5% 1/20W
21 OUT ISOLATE_CPU_MEM_L MF 201

N34 GPIO34 PLTRST_PROC* F41 CPU_RESET_L OUT 6 18 86


28 OUT TBT_SW_RESET_L

18 3 GPU_GOOD M40 GPIO35/NMI* VSS AV33


OUT

GPIO
18 14 PCH_GPIO36 H40 SATA2GP/GPIO36
OUT
(IPD-PLTRST#)

80 28 =PP3V3_S0_PCH_GPIO 20 18 14 JTAG_ISP_TCK N41 SATA3GP/GPIO37


AT20
C
OUT
C 20 14 IN JTAG_ISP_TDO
(IPD-PLTRST#)
H41 SLOAD/GPIO38
VSS
VSS AT21
VSS AT23
20 14 JTAG_ISP_TDI R31 SDATAOUT0/GPIO39
OUT AT24
VSS
14 FW_PWR_EN_PCH L40 SDATAOUT1/GPIO48 VSS AT28
VSS AT29
18 14 PCH_GPIO49 N40 SATA5GP/GPIO49
IN AT33
1 (IPU-Boot/SATA5GP?) VSS
R1426 1 SPIROM_USE_MLB AC36 GPIO57 VSS AT36
R1427 89 46 BI
10K 10K 33.2 VSS AT38
5%
5% PCH_CAM_EXT_BOOT_R_L 1 2 R1461 14 PCH_CAM_EXT_BOOT_L AT30 TACH4/GPIO68
1/20W
1/20W
39 OUT 1% 1/20W MF 201 VSS AT41
MF 33.2
MF
201
2 201 39 PCH_CAM_RESET_R 1 2 R1462 14 PCH_CAM_RESET AV35 TACH5/GPIO69 VSS AT7
2 OUT 1% 1/20W MF 201
PLACE_NEAR=U1100.AT30:10MM VSS AT8
PLACE_NEAR=U1100.AV35:10MM PCH_BLC_MCU_RESET_R AK28 TACH6/GPIO70
(IPU-Boot?) VSS AU1
PCH_BLC_EXT_BOOT_R AT34 TACH7/GPIO71 VSS AU3
(IPU-Boot?) AU39
VSS
VSS AV1
AT14 VSS
VSS AV12
AT15 VSS
VSS AV17
AT16 VSS
VSS AV2
AT18 VSS
VSS AV21

B B

14 PCH_CAM_EXT_BOOT_L
14 PCH_CAM_RESET
=PP3V3_S5_PCH_VCCSUS_GPIO 11 12 13 15 17 80

=PP3V3_S0_PCH_VCC3_3_GPIO 11 12 13 15 17 80

R1422 1 1
R1423
R1485 10K 1 2 FW_PME_L 14 1K 1K
5% 1/20W MF 201
R1411 20K 2 1 DPMUX_UC_IRQ 14
5%
1/20W
5%
1/20W
5% 1/20W MF 201
R1496 10K 1 2 SMC_RUNTIME_SCI_L 14 44 91
MF
201
MF
201
5% 1/20W MF 201 2 2
R1494 10K 1 2 WOL_EN 14 36
5% 1/20W MF 201
R1489 10K 1 2 MEM_VDD_SEL_1V5_L 14
5% 1/20W MF 201
R1495 10K 1 2 PCH_GPIO16 14 18
5% 1/20W MF 201
R1490 100K 1 2 LPCPLUS_GPIO 14 46
5% 1/20W MF 201
R1412 10K 2 1 JTAG_TBT_TMS_PCH 14 20
5% 1/20W MF 201
R1492 10K 1 2 TBT_GO2SX_BIDIR 14 26
5% 1/20W MF 201
R1491 10K
A R1498 10K
1

2
2

1
5%
5%
1/20W
1/20W
MF
MF
201
201
SMC_WAKE_SCI_L
PCH_GPIO36
14 44 91

14 18 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
R1413 10K 2 1 JTAG_ISP_TCK 14 18 20
PAGE TITLE
R1486 10K 1 2
5%

5%
1/20W

1/20W
MF

MF
201

201
JTAG_ISP_TDO 14 20 PCH GPIO/MISC/NCTF
R1499 10K 1 2 JTAG_ISP_TDI 14 20 DRAWING NUMBER SIZE
R1484 10K 1 2
5%

5%
1/20W

1/20W
MF

MF
201

201
FW_PWR_EN_PCH 14
Apple Inc. 051-9889 D
R1497 10K 1 2 PCH_GPIO49 14 18 REVISION
5% 1/20W MF 201 R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1450 10K 1 2 PCH_A20GATE 14 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
R1455 10K 1 2 PCH_RCIN_L 14 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 14 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE

U1100
LYNX
FCBGA
DESKTOP
80 17 =PP1V05_S0_PCH_VCC
V20 SYM 7 OF 11 CKPLUS_WAIVE=PWRTERM2GND
VCC: 1312mA Max, 130mA Idle VCC VCCADAC1_5 AF2
V22 VCC VGA DAC Disabled per LPT
VSS AV40

CRT
V23 VCC DG v1.0 (Table 12-18).
V25 VCC VCCADACBG3_3 AE1 CKPLUS_WAIVE=PWRTERM2GND
W17 VCC
W19 =PP1V5_S0_PCH_VCCVRM_FDI 17
VCC VCCVRM: 158mA Max, 43mA Idle
VCCVRM B39
D
W23 VCC
D

FDI
W25 =PP1V05_S0_PCH_VCCIO 15 17 80
VCC VCCIO: 3491mA Max, 199mA Idle
AA19 VCCIO AC12
VCC
AA20 VCCIO AF19 =PP1V05_S0_PCH_VCCIO_USB2 15 17 80
VCC
17 PP1V05_S0_PCH_VCC_CLK_F AB1 VCC

HVCMOS
AB16 VCC VCC3_3 AG1 =PP3V3_S0_PCH_VCC3_3_HVCMOS 17 80
AB17 VCC3_3: 133mA Max, 3mA Idle
VCC
AB19 VCC
AB20 VCC
AD16 VCC DCPSUS1 AE30 NC
=PP3V3_S5_PCH_VCCSUS_GPIO 11 12 13 14 15 17 80
VCCSUS3_3: 261mA Max, 6mA Idle
R1550 VCCSUS3_3 AN33
PLACE_NEAR=R1550.1:2.54mm PLACE_NEAR=U1100.AU40:2.54MM
5.11 AU40 DCPSUSBYP VCCSUS3_3 P20 =PP3V3_S5_PCH_VCCSUS_USB3 80
PPVOUT_S5_PCH_DCPSUSBYP 1 2 PPVOUT_S5_PCH_DCPSUSBYP_R

CORE
MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm

USB3
MIN_NECK_WIDTH=0.2 mm 1% MIN_NECK_WIDTH=0.2 mm Powered in DeepSx AU41 DCPSUSBYP
1VOLTAGE=1.05V
1/20W VOLTAGE=1.05V DCPSUS3 P19 NC
C1550 MF-LF
201 C1 VCCVRM
1UF
10% C2 VCCVRM =PP1V05_S0_PCH_VCCIO 15 17 80
6.3V
2 VCCIO: 3491mA Max, 199mA Idle
CERM
402
K1 VCCVRM VCCIO P25
17 15 =PP1V5_S0_PCH_VCCVRM_CLK T14 VCCVRM =PP1V5_S0_PCH_VCCVRM_USB3 17
VCCVRM: 158mA Max, 43mA Idle VCCVRM: 158mA Max, 43mA Idle
VCCVRM A39
VCCVRM A4

=PP1V5_S0_PCH_VCCVRM_PCIE 17

PCIE/DMI
VCCVRM: 158mA Max, 43mA Idle
VCCVRM B4

80 17 15 =PP1V05_S0_PCH_VCCASW AF25 VCCASW VCCIO P23


VCCASW: 670mA Max, 34mA Idle AA25 VCCASW
AA26 =PP1V5_S0_PCH_VCCVRM_SATA 17
VCCASW VCCVRM: 158mA Max, 43mA Idle
C VCCVRM A40
C

SATA
AB22 VCCASW
AB23 VCCASW
AB25 VCCIO P26
VCCASW
AB26 VCCASW
AD17 VCCASW VCCIO P28

VCCMPHY
AD19 VCCASW VCCIO T19
AD20 VCCASW VCCIO T20
AD22 VCCASW VCCIO AF20 =PP1V05_S0_PCH_VCCIO_USB2 15 17 80
AD23 VCCASW VCCIO AF22
AD25 VCCASW VCCIO AF23

OMIT_TABLE

U1100
LYNX
FCBGA
DESKTOP VCCSUS3_3 AH18 =PP3V3_S5_PCH_VCCSUS_USB 15 17 80
80 17 15 =PP3V3_S5_PCH_VCCSUS_USB VCCSUS3_3: 261mA Max, 6mA Idle
VCCSUS3_3: 261mA Max, 6mA Idle AH22 VCCSUS3_3 SYM 8 OF 11 VCCSUS3_3 AH20
AJ20 VCCSUS3_3 VCCDSW3_3 AV39 =PP3V3_S5_PCH_VCCDSW 17 80
AK20 VCCSUS3_3 VCCDSW3_3: 15mA Max, 1mA Idle
VCCDSW3_3 AW38
80 17 15 14 13 12 11 =PP3V3_S5_PCH_VCCSUS_GPIO AM33 VCCSUS3_3 VCCDSW3_3 AW39

GPIO/LPC
AV41 VSS BYPASS=U1100.AH28:6.35MM
DCPSST AH28 PPVOUT_S0_PCH_DCPSST
MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm

80 17 =PP1V05_S0_PCH_VCCUSBPLL AP22 VCCUSBPLL VCC3_3 AF26 =PP3V3_S0_PCH_VCC_FUSE 17 80


1
C1580
VCC3_3 U30 =PP3V3_S0_PCH_VCC3_3_GPIO 11 12 13 14 15 17 80
0.1UF
20%
VCC3_3 AW21 =PP3V3_S0_PCH_VCC3_3_USB 10V

B M14 VCCIO
VCC3_3 W30 =PP3V3_S0_PCH_VCC3_3_GPIO
17 80

11 12 13 14 15 17 80
2 CERM
402 B
VCCIO P14

USB
80 17 =PP1V05_S0_PCH_VCCIO_FDI =PP1V05_S0_PCH_VCCIO 15 17 80
P16 VCCIO VCCIO: 3491mA Max, 199mA Idle
80 17 15 =PP1V05_S0_PCH_VCCIO
VCCIO: 3491mA Max, 199mA Idle P17 VCCIO

HDA
P22 VCCIO
VCCSUSHDA AW26 =PP3V3_S5_PCH_VCCSUS_HDA 17 80
VCCSUSHDA: 10mA Max, 1mA Idle
AJ22 DCPSUS2
NC

VCCSUS3_3 AP35 =PP3V3_S5_PCH_VCCSUS_RTC 17 80

RTC
A38 VCCVRM =PP3V3_G3_PCH_RTC 80
17 15 =PP1V5_S0_PCH_VCCVRM_CLK
VCCVRM: 158mA Max, 43mA Idle VCCRTC AP33
6uA Max (3.0V, room temperature)
BYPASS=U1100.AW35:6.35MM
DCPRTC AW35 PPVOUT_S0_PCH_DCPRTC C1533 1
C1532 1 1
C1531
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
0.1UF 0.1UF 1UF
80 17 =PP1V05_S0_PCH_VCCCLK_SSC T16 VCCCLK VOLTAGE=1.05V 20% 20% 10%
10V 10V 6.3V
VCCCLK: 306mA Max, 89mA Idle CERM 2 CERM 2 2 CERM
402 402 402
=PP3V3_S0_PCH_VCCCLK3_3 AM9 VCCCLK3_3 CPU 1
C1590
CLK/MISC
80 17
VCCCLK3_3: 55mA Max, 11mA Idle AK11 BYPASS=U1100.AP33:6.35MM
VCCCLK3_3 V_PROC_IO C39 =PP1V05_S0_PCH_V_PROC_IO 14 17 80
0.1UF
20%
BYPASS=U1100.AP33:6.35MM
AG12 V_PROC_IO: 4mA Max, 2mA Idle 10V BYPASS=U1100.AP33:6.35MM
VCCCLK3_3 2 CERM
AM7 VCCCLK3_3 402

AP5 VCCCLK3_3
SPI

AP7 VCCCLK3_3
AW3 VCCSPI R41 =PP3V3_S5_PCH_VCC_SPI 17 80
VCCCLK3_3 VCCSPI: 22mA Max, 1mA Idle
AW4 VCCCLK3_3
AW9 VCCCLK3_3
AR4 VCCCLK3_3 VCC V17 =PP1V05_S0_PCH_VCCIO 15 17 80

A AT5
AV3
VCCCLK3_3
VCCCLK3_3
VCC V19
SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE
AV4 VCCCLK3_3 VCCASW W26 =PP1V05_S0_PCH_VCCASW
VCCASW: 670mA Max, 34mA Idle
15 17 80
PCH Power
V16 DRAWING NUMBER SIZE
VCCCLK VCCASW AA23 =PP1V05_S0_PCH_VCCASW
80 17 =PP1V05_S0_PCH_VCCCLK_CLK100 U12 VCCCLK
VCCASW: 670mA Max, 34mA Idle
15 17 80

Apple Inc. 051-9889 D


VCCCLK: 306mA Max, 89mA Idle V14 REVISION
VCCCLK R
THERMAL

=PP1V05_S0_PCH_VCCCLK_CLK135 W14 13.0.0


80 17 VCCCLK
VCCCLK: 306mA Max, 89mA Idle W16 VCCVRM B37 =PP1V5_S0_PCH_VCCVRM_THRM 17 NOTICE OF PROPRIETARY PROPERTY: BRANCH
VCCCLK VCCVRM: 158mA Max, 43mA Idle
AA16 THE INFORMATION CONTAINED HEREIN IS THE
80 17 =PP1V05_S0_PCH_VCCCLK_SSC100 VCCCLK PROPRIETARY PROPERTY OF APPLE INC.
VCCCLK: 306mA Max, 89mA Idle AB2 VCC3_3 B6 =PP3V3_S0_PCH_VCC3_3_THRM 17 80 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VCCCLK VCC3_3: 133mA Max, 3mA Idle I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 15 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
Current data from LPT EDS (doc #486708, Rev 1.0).
IV ALL RIGHTS RESERVED 15 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

OMIT_TABLE
OMIT_TABLE
A12 VSS U1100 VSS F18
T23 VSS U1100 VSS AE12
A16 VSS LYNX VSS F24
A21 VSS FCBGA VSS F35
T25 VSS LYNX VSS AE31
DESKTOP T26 VSS FCBGA VSS AE4
A35 VSS VSS F37 DESKTOP
SYM 10 OF 11 T28 VSS VSS AE41
B25 VSS VSS F38 SYM 11 OF 11
U1 AE8
B3 VSS VSS VSS G2 VSS VSS
AF14
B30 VSS VSS H14
U31 VSS VSS VSS
U32 VSS VSS AF16
B33 VSS VSS H16
U4 VSS VSS AF17
B38 VSS VSS H20
U8 VSS VSS AF28
B40 VSS VSS H22
V26 VSS VSS AF3
B41 VSS VSS H26
V28 VSS VSS AG2
C25 VSS VSS H28
V38 VSS VSS AG30
C37 VSS VSS H33
V40 VSS VSS AG34
C41 VSS VSS H34
W12 VSS VSS AG38
C6 VSS VSS H38
W20 VSS VSS AG8
D1 VSS VSS H4
AH14
C D12
D13
VSS
VSS
VSS
VSS
H6
H8
W22
W28
VSS
VSS
VSS
VSS AH16 C
W3 VSS VSS AJ1
D14 VSS VSS H9
W5 VSS VSS AJ28
D16 VSS VSS J31
W8 VSS VSS AK24
D18 VSS VSS J37
Y1 VSS VSS AK37
D19 VSS VSS J5
Y41 VSS VSS AK9
D20 VSS VSS K31
AA10 VSS VSS AL11
D22 VSS VSS K4
AA11 VSS VSS AL37
D24 VSS VSS K9
AA12 VSS VSS AL5
D25 VSS VSS L37
AA14 VSS VSS AM14
D26 VSS VSS L41
AA17 VSS VSS AM16
D27 VSS VSS M16
AA22 VSS VSS AM18
D28 VSS VSS M18
AA28 VSS VSS AM20
D31 VSS VSS M20
AA30 VSS VSS AM24
D32 VSS VSS M22
AA34 VSS VSS AM26
D34 VSS VSS M24
AA5 VSS VSS AM35
D37 VSS VSS M26
AA8 VSS VSS AM38
D4 VSS VSS M28
AB14 VSS VSS AM4
D41 VSS VSS N31
AB28 VSS VSS AM6
D6 VSS VSS N35
AB4 VSS VSS AM8
D7 VSS VSS N38
AC30 VSS VSS AN28
D8 VSS VSS N4
AC31 VSS VSS AP4
D9 VSS VSS N8
AC34 VSS VSS AP9
E12 VSS VSS R1
AC38 VSS VSS AR11
E3 VSS VSS R10
AC5 VSS VSS AR35
E31 VSS VSS R34
AC8 VSS VSS AR37
B E35
E38
VSS
VSS
VSS
VSS
R8
T17
AD14
AD26
VSS VSS AT1
AT10
B
E4 T22 VSS VSS
VSS VSS AD28 AT11
E5 AW2 VSS VSS
VSS VSS
E7 VSS VSS AW30
VSS AW40
VSS AW7

A SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE

PCH Grounds
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 16 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCCLK3_3 BYPASS 55mA Max, 11mA Idle PCH VCCASW BYPASS
PCH VCCDSW3_3 BYPASS (PCH 3.3V CLK PWR) INTEL:4X 1UF(402) (PCH 1.05V ME CORE PWR) INTEL:1X10UF(805), 1X1UF(402)
(PCH 3.3V DSW PWR) INTEL:1X 0.1UF(402) 80 15 =PP3V3_S0_PCH_VCCCLK3_3 80 15 =PP1V05_S0_PCH_VCCASW
80 15 =PP3V3_S5_PCH_VCCDSW 670mA Max, 34mA Idle
15mA Max, 1mA Idle
C1700 1
C1720 1
C1721 1
C1722 1
C1723 1
C1750 1 1
C1751 1
C1752
0.1UF 1UF 1UF 1UF 1UF 10UF 1UF 1UF
20% 10% 10% 10% 10% 20% 10% 10%
10V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 X5R 2 2 CERM 2 CERM
402 402 402 402 402 603 402 402
BYPASS=U1100.AW39:6.35MM
BYPASS=U1100.AP5:6.35MM place_near=U1100.AD17:2.54MM
BYPASS=U1100.AV4:6.35MM place_near=U1100.AD17:2.54MM
BYPASS=U1100.AR4:6.35MM place_near=U1100.AD19:2.54MM

D PCH VCCSPI BYPASS PCH VCC3_3 BYPASS


BYPASS=U1100.AT5:6.35MM

PCH VCC BYPASS D


(PCH 3.3V SPI PWR) INTEL:1X 1UF(402) (PCH 3.3V HVCMOS PWR) INTEL:1X 0.1UF(402) (PCH 1.05V CORE PWR)
THESE 4X1UF ARE EXTRA BYPASS
80 15 =PP3V3_S5_PCH_VCC_SPI 80 15 =PP3V3_S0_PCH_VCC3_3_HVCMOS 80 15 =PP1V05_S0_PCH_VCC
22mA Max, 1mA Idle 133mA Max, 3mA Idle 1312mA Max, 130mA Idle
C1702 1
C1726 1

1UF 0.1UF 1
C1761 1
C1756 1
C1757 1
C1758
10% 20%
6.3V
2
10V
2 1UF 1UF 1UF 1UF
CERM CERM 10% 10% 10% 10%
402 402 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM
BYPASS=U1100.R41:6.35MM BYPASS=U1100.AG1:6.35MM 402 402 402 402

BYPASS=U1100.P14:6.35MM
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS BYPASS=U1100.V22:6.35MM
INTEL:1X 0.1UF(402) BYPASS=U1100.V25:6.35MM
(PCH 3.3V SUSPEND PWR) (PCH 3.3V GPIO/LPC PWR) INTEL:1X 0.1UF(402) BYPASS=U1100.AA19:6.35MM

80 15 14 13 12 11 =PP3V3_S5_PCH_VCCSUS_GPIO 80 15 14 13 12 11 =PP3V3_S0_PCH_VCC3_3_GPIO PCH VCCIO BYPASS


261mA Max, 6mA Idle 133mA Max, 3mA Idle (PCH 1.05V PCIe/DMI/SATA/USB3 PWR) INTEL:2X10UF(805), 3X1UF(402)
C1704 1
C1728 1
80 15 =PP1V05_S0_PCH_VCCIO
0.1UF 0.1UF 3491mA Max, 114mA Idle
20% 20%
10V 10V
CERM 2 CERM 2
402
BYPASS=U1100.AN33:6.35MM BYPASS=U1100.W30:6.35MM
402
C1760 1 C1755 1 1
C1762 1
C1763 1
C1764
10UF 10UF 1UF 1UF 1UF
20% 20% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 X5R 2 2 CERM 2 CERM 2 CERM
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS 603 603 402 402 402
(PCH 3.3V SUSPEND USB PWR) INTEL:1X 0.1UF(402) (PCH 3.3V USB2 PWR) INTEL:1X 1UF(402)
BYPASS=U1100.P14:12.7MM
80 15 =PP3V3_S5_PCH_VCCSUS_USB 80 15 =PP3V3_S0_PCH_VCC3_3_USB BYPASS=U1100.P28:12.7MM
BYPASS=U1100.P16:6.35MM
261mA Max, 6mA Idle 133mA Max, 3mA Idle BYPASS=U1100.P17:6.35MM
BYPASS=U1100.P26:6.35MM PCH VCCCLK BYPASS
C1706 1
C1730 1
PCH VCCUSBPLL BYPASS
0.1UF 1UF (PCH 1.05V SSC100 PWR) INTEL:2X 1UF(402)
(PCH 1.05V USB2 PLL PWR) INTEL:1X 1UF(402)
20%
10V
10%
6.3V 80 15 =PP1V05_S0_PCH_VCCCLK_SSC100
CERM 2 CERM 2 80 15 =PP1V05_S0_PCH_VCCUSBPLL
306mA Max, 89mA Idle
C
402
BYPASS=U1100.AK20:6.35MM
402
BYPASS=U1100.AW21:6.35MM
C1770 1
C1776 1
C1777 1
C
1UF
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS 10% 1UF 1UF
6.3V 10% 10%
CERM 2 6.3V 6.3V
(PCH 3.3V DSW RTC PWR) INTEL:1X 1UF(402) (PCH 3.3V THERMAL PWR) INTEL:1X 0.1UF(402) 402 CERM 2 CERM 2
=PP3V3_S5_PCH_VCCSUS_RTC =PP3V3_S0_PCH_VCC3_3_THRM 402 402
80 15 80 15 BYPASS=U1100.AP22:6.35MM

133mA Max, 3mA Idle BYPASS=U1100.AA16:6.35MM


BYPASS=U1100.W16:6.35MM
C1708 1
C1732 1
PCH VCCIO BYPASS
1UF 0.1UF INTEL:1X 1UF(402)
10% 20%
(PCH 1.05V FDI PWR)
6.3V 10V =PP1V05_S0_PCH_VCCIO_FDI
CERM 2 CERM 2 80 15 PCH VCCCLK BYPASS
402 402 INTEL:2X 1UF(402)
3491mA Max, 114mA Idle (PCH 1.05V DIFFCLK PWR)
BYPASS=U1100.AP35:6.35MM BYPASS=U1100.B6:6.35MM
C1772 1
80 15 =PP1V05_S0_PCH_VCCCLK_CLK100
1UF
10%
PCH VCC BYPASS 306mA Max, 89mA Idle
6.3V
CERM 2 C1778 1
C1783 1
(PCH 3.3V FUSE PWR) INTEL:1X 1UF(402) 402 1UF 1UF
80 15 =PP3V3_S0_PCH_VCC_FUSE BYPASS=U1100.M14:6.35MM 10%
6.3V
10%
6.3V
CERM 2 CERM 2
133mA Max, 3mA Idle 402 402
C1734 1
PCH VCCIO BYPASS BYPASS=U1100.U12:6.35MM
BYPASS=U1100.AB2:6.35MM
1UF (PCH 1.05V USB2 PWR) INTEL:1X 1UF(402)
10%
6.3V =PP1V05_S0_PCH_VCCIO_USB2
CERM 2 80 15 PCH VCCCLK BYPASS
402 INTEL:1X 1UF(402)
3491mA Max, 114mA Idle (PCH 1.05V DIFFCLK135 PWR)
BYPASS=U1100.AF26:6.35MM
C1774 1
80 15 =PP1V05_S0_PCH_VCCCLK_CLK135
1UF
10%
306mA Max, 89mA Idle
6.3V
CERM 2 C1780 1
402 1UF
10%
BYPASS=U1100.AF19:6.35MM 6.3V
CERM 2
402
PCH VCCSUSHDA BYPASS PCH VCCVRM BYPASS PCH V_PROC_IO BYPASS BYPASS=U1100.W14:6.35MM
INTEL:1X 0.1UF(402)
B 80 15
(PCH 3.3V HDA PWR)
=PP3V3_S5_PCH_VCCSUS_HDA
INTEL:1X 0.1UF(402)
80
(PCH 1.5V VCCVRM PWR)
=PP1V5_S0_PCH_VCCVRM 80 15 14
(PCH 1.05V CPU I/F PWR)
=PP1V05_S0_PCH_V_PROC_IO
INTEL:1X1UF(603), 2X0.1UF(402)
PCH VCCCLK BYPASS
B
158mA Max, 43mA Idle
10mA Max, 1mA Idle 4mA Max, 2mA Idle (PCH 1.05V SSC PWR) INTEL:1X 1UF(402)
C1710 1
11 =PP1V5_S0_PCH_VCCVRM_BIAS 80 15 =PP1V05_S0_PCH_VCCCLK_SSC
0.1UF 15 =PP1V5_S0_PCH_VCCVRM_FDI C1785 1 1
C1786 1
C1787
20% 306mA Max, 89mA Idle
10V
2 15 =PP1V5_S0_PCH_VCCVRM_USB3 1UF 0.1UF 0.1UF C1782 1
CERM 10% 20% 20%
402
15 =PP1V5_S0_PCH_VCCVRM_PCIE 6.3V
2 2
10V
2
10V 1UF
CERM CERM CERM 10%
BYPASS=U1100.AW26:6.35MM 402 402 402 6.3V
15 =PP1V5_S0_PCH_VCCVRM_SATA CERM 2
=PP1V5_S0_PCH_VCCVRM_CLK 402
15 BYPASS=U1100.C39:12.7MM
BYPASS=U1100.C39:6.35MM BYPASS=U1100.V16:6.35MM
15 =PP1V5_S0_PCH_VCCVRM_THRM BYPASS=U1100.C39:6.35MM

C1740 1 PCH CLK VCC BYPASS INTEL:1X10UF(603), 1X1UF(402)


0.1UF (PCH 1.05V CLK PLL PWR. NOSTUFF 10UF IF IDG NO USED)
20%
16V
CERM 2 L1790 PP1V05_S0_PCH_VCC_CLK_F 15
603
=PP1V05_S0_PCH_VCC_CLK 1
0 2
MIN_LINE_WIDTH=0.2 MM
BYPASS=U1100.T14:12.7MM 80 MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
5% 1/10W MF-LF 603
306mA Max, 89mA Idle
C1790 1 1
C1791
NOSTUFF 10UF
20%
1UF
10%
6.3V 10V
X5R 2 2 X5R
603 402

BYPASS=U1100.AB1:12.7mm
BYPASS=U1100.AB1:6.35mm

A SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE

PCH DECOUPLING
DRAWING NUMBER SIZE

Apple Inc. 051-9889 D


REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 17 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
Current data from LPT EDS (doc #486708, Rev 1.0).
IV ALL RIGHTS RESERVED 17 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Extra BPM Testpoints 61 8 6 PPVCCIO_S0_CPU CPU Micro2-XDP 80 18 =PP1V05_S0_XDP

CRITICAL NOTE: This is not the standard XDP pinout. XDP


88 6 IN XDP_BPM_L<2> 1
TP XDP_CONN Use with 921-0133 Adapter Flex to 88 18 6 XDP_CPU_TDO R1820 51 2 1
TP1802 =PP1V05_S0_XDP
PLACE_NEAR=J1800.51:5MM 5% 1/20W MF 201
TP-P6 80 18 J1800 support chipset debug.
88 6 IN XDP_BPM_L<3> 1
TP XDP
TP-P6
TP1803 DF40RC-60DP-0.4V
XDP_CPU_TCK R1823 51 2 1
M-ST-SM1 88 18 6
88 6 IN XDP_BPM_L<4> 1
TP R1830 1 5% 1/20W MF 201
TP1804 150 62 61
TP-P6 XDP
88 6 IN XDP_BPM_L<5> 1 5%
TP
TP-P6
TP1805 1/16W 18 6 XDP_CPU_TRST_L R1824 51 2 1
MF-LF 5% 1/20W MF 201
88 6 IN XDP_BPM_L<6> 1
TP 402
TP-P6
TP1806 2 2 1
TDI and TMS are terminated in CPU.
XDP_BPM_L<7> XDP_CPU_PREQ_L OBSFN_A0 4 3
OBSFN_C0 CPU_CFG<17>
D
88 6 IN 1 6 BI IN 6 88
TP TP1807
D TP-P6 6 IN XDP_CPU_PRDY_L OBSFN_A1 6

8
5

7
OBSFN_C1 CPU_CFG<16> IN 6 88

88 6 IN CPU_CFG<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<8> IN 6 88

CPU_CFG<1> 12 11 CPU_CFG<9>
88 6 IN OBSDATA_A1 OBSDATA_C1 IN 6 88
14 13

88 6 IN CPU_CFG<2> OBSDATA_A2 16 15 OBSDATA_C2 CPU_CFG<10> IN 6 88

CPU_CFG<3> 18 17 CPU_CFG<11>
88 6 IN OBSDATA_A3 OBSDATA_C3 IN 6 88
20 19

86 6 IN XDP_BPM_L<0> OBSFN_B0 22 21
OBSFN_D0 CPU_CFG<19> IN 6

86 6 XDP_BPM_L<1> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<18> 6


IN IN
26 25

88 6 IN CPU_CFG<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<12> IN 6 82 88

88 6 IN CPU_CFG<5> OBSDATA_B1 30 29
OBSDATA_D1 CPU_CFG<13> IN 6 82 88
32 31

CPU_CFG<6> 34 33 CPU_CFG<14>
88 6 IN OBSDATA_B2 OBSDATA_D2 IN 6 82 88
XDP
88 6 IN CPU_CFG<7> OBSDATA_B3 36 35 OBSDATA_D3 CPU_CFG<15> IN 6 82 88
86 14 6 IN CPU_PWRGD R1800 1K 1 2
38 37
PLACE_NEAR=U0500.AB35:16.5mm 5% 1/20W MF 201
XDP 86 XDP_CPU_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 NC
44 18 12 OUT PM_PWRBTN_L R1802 0 1 2 XDP_CPU_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 NC NC per Intel DPDG.
5% 1/20W MF 0201
VCC_OBS_AB 44 43 VCC_OBS_CD XDP
WF: SB DPDG says HOOK1 is BP_PWRGD_RST#
XDP 8 OUT CPU_PWR_DEBUG HOOK2 46 45
RESET#/HOOK6 86 XDP_CPURST_L R1805 1K 1 2 CPU_RESET_L IN 6 14 86

71 45 12 OUT PM_PCH_SYS_PWROK R1804 220 1 2 XDP_VR_READY HOOK3 48 47


DBR#/HOOK7 XDP_DBRESET_L OUT 6 18 19
5% 1/20W MF 201
5% 1/20W MF 201
50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
47 18 BI =SMBUS_XDP_SDA SDA 52 51
TDO XDP_CPU_TDO IN 6 18 88
47 18 IN =SMBUS_XDP_SCL SCL 54 53
TRSTn XDP_CPU_TRST_L OUT 6 18 CPU-PCH JTAG Chain Support
56 55 XDP_CPU_TDI
TCK1 NC TDI OUT 6 88
To link CPU and PCH JTAG pull ICT_JTAG_EN to 5V (must be in S0)
C 88 18 6 OUT XDP_CPU_TCK TCK0 58

60
57

59
TMS
XDP_PRESENT#
XDP_CPU_TMS OUT 6 18 88
TP1845 TP
TP-P6
1 C
XDP SIGNALS XDP 1
XDP XDP XDP XDP Q1840 ICT_JTAG_EN
Q1846
OMIT

5
PCH SIGNALS (All 18 R’s) R1831 C1804 1
C1800 1 1
C1801 1
C1806 DMN5L06VK-7 DMN5L06VK-7

G
1K 64 63 SOT-563 SOT-563
0.1UF 0.1UF 0.1UF 0.1UF
42 13 IN USB_EXTA_OC_L R1890 SHORT 1 2 XDP_DA0_USB_EXTA_OC_L 18
5%
1/16W
20%
10V
20%
10V
20%
10V
20%
10V
R1893 NONE NONE NONE 402 MF-LF 2 2 2 2

D
43 13 IN USB_EXTC_OC_L SHORT 1 2 XDP_DA1_USB_EXTC_OC_L 18 402 2
CERM
402
CERM
402 998-2516 CERM
402
CERM
402 88 18 6 XDP_CPU_TMS XDP_CPU_PCH_TMS XDP_PCH_TMS 11 18 88
R1894 NONE NONE NONE 402 PLACE_NEAR=J1800.57:5.08mm PLACE_NEAR=J1850.57:6mm

3
4

4
13 IN PCH_GPIO41 SHORT 1 2 XDP_DA2_PCH_GPIO41 18

13 IN PCH_GPIO42 R1895 SHORT 1 2


NONE NONE NONE 402
XDP_DA3_PCH_GPIO42 18 TP1840 TP 1

USB_EXTB_OC_L R1880 NONE NONE NONE 402


XDP_DB0_USB_EXTB_OC_L
Q1840 TP-P6 Q1846
SHORT 1 2

2
42 13 IN 18
DMN5L06VK-7 DMN5L06VK-7
R1881 NONE NONE NONE 402

G
43 13 IN USB_EXTD_OC_L SHORT 1 2 XDP_DB1_USB_EXTD_OC_L 18 XDP_CPU_PRESENT_L SOT-563 SOT-563

13 IN PCH_GPIO10 R1896 SHORT 1 2


NONE NONE NONE 402
XDP_DB2_PCH_GPIO10 18
R1897 NONE NONE NONE 402

D
37 13 OUT SDCONN_STATE_CHANGE SHORT 1 2 XDP_DB3_SDCONN_STATE_CHANGE_L 18 88 18 6 XDP_CPU_TCK XDP_CPU_PCH_TCK XDP_PCH_TCK 11 18 88
R1872 NONE NONE NONE 402 PLACE_NEAR=J1800.58:5.08mm PLACE_NEAR=J1850.58:5.08mm

6
1

1
30 29 11 IN DP_AUXIO_EN SHORT 1 2 XDP_DC0_DP_AUXCH_ISOL_L 18

11 IN SATARDRVR_EN R1873 SHORT 1 2


NONE NONE NONE 402
XDP_DC1_SATARDRVR_EN 18 TP1841 TP 1

R1874 NONE NONE NONE 402 Q1842 TP-P6 Q1848


PCH_GPIO36 SHORT 1 2 XDP_DC2_PCH_GPIO36

1
14 IN 18 DMN32D2LFB4 DMN32D2LFB4
R1875 NONE NONE NONE 402

G
DFN1006H4-3 DFN1006H4-3
20 14 IN JTAG_ISP_TCK SHORT 1 2 XDP_DC3_JTAG_ISP_TCK 18 SYM_VER_3 SYM_VER_3
14 OUT PCH_GPIO16 R1878 SHORT 1 2
NONE NONE NONE 402
XDP_DD0_PCH_GPIO16 18
R1879 NONE NONE NONE 402

D
PCH_GPIO49 SHORT 1 2 XDP_DD1_PCH_GPIO49 XDP_CPU_TDO XDP_CPU_TDO_PCH_TDI XDP_PCH_TDI
14 OUT
R1882 NONE NONE NONE 402
18
PCH Micro2-XDP =PP3V3_S5_XDP
88 18 6
PLACE_NEAR=J1800.51:5.08mm PLACE_NEAR=J1850.55:5.08mm
11 18 88

3
18 80

2
35 11 OUT ENET_CLKREQ_L SHORT 1 2 XDP_DD2_ENET_CLKREQ_L 18

32 11 OUT AP_CLKREQ_L R1883 SHORT 1 2


NONE NONE NONE 402
XDP_DD3_AP_CLKREQ_L 18
R1886 NONE NONE NONE 402 CRITICAL
69 14 OUT HDD_PWR_EN SHORT 1 2 XDP_FC0_HDD_PWR_EN 18

14 3 GPU_GOOD R1887 SHORT 1 2


NONE NONE NONE 402
XDP_FC1_GPU_GOOD 18
XDP_CONN R1842 1 1
R1841 1
R1840 R1845 1
OUT NONE NONE NONE 402
J1850 1M 1M 1M 1K
5% 5% 5% 5%
DF40RC-60DP-0.4V NOTE: This is not the standard XDP pinout. 1/20W 1/20W 1/20W 1/20W
M-ST-SM1 MF MF MF MF
Use with 921-0133 Adapter Flex to 201
2 2
201
2
201 201
2
62 61 support chipset debug.

B 2 1
NOSTUFF
B
OBSFN_A0 4 3
OBSFN_C0 XDP_FC0_HDD_PWR_EN R1892
NC 18
0
OBSFN_A1 6 5
OBSFN_C1 XDP_FC1_GPU_GOOD =PP3V3_S5_XDP 1 2 PP3V3_S5_XDP_R
NC 18 80 18
8 7 5% VOLTAGE=3.3V
1/16W MIN_LINE_WIDTH=0.2MM
18 XDP_DA0_USB_EXTA_OC_L OBSDATA_A0 10 9
OBSDATA_C0 XDP_DC0_DP_AUXCH_ISOL_L 18 MF-LF MIN_NECK_WIDTH=0.15MM
402 MAX_NECK_LENGTH=3MM
18 XDP_DA1_USB_EXTC_OC_L OBSDATA_A1 12 11
OBSDATA_C1 XDP_DC1_SATARDRVR_EN 18
PCH/XDP Signal Isolation Notes: 14 13

’Output’ non-XDP signals require pulls. 18 XDP_DA2_PCH_GPIO41 OBSDATA_A2 16 15


OBSDATA_C2 XDP_DC2_PCH_GPIO36 18
XDP XDP XDP
’Output’ PCH/XDP signals require pulls. XDP_DA3_PCH_GPIO42 OBSDATA_A3 18 17
OBSDATA_C3 XDP_DC3_JTAG_ISP_TCK 1 1 1
18 18
R1860 R1861 R1862
20 19 210 210 210
22 21 1% 1% 1%
R187x and R189x should be placed where OBSFN_B0 NC NC OBSFN_D0 1/20W 1/20W 1/20W
24 23
MF MF MF
signal path needs to split between route OBSFN_B1 NC NC OBSFN_D1 2 201 2 201 2 201
from PCH to J1850 and path to non-XDP 26 25 88 18 11 XDP_PCH_TDO U1100.W40:21mm
J1850.51:2.54mm U1100.W39:21mm
signal destination (to minimize stub). 18 XDP_DB0_USB_EXTB_OC_L OBSDATA_B0 28 27 OBSDATA_D0 XDP_DD0_PCH_GPIO16 18 88 18 11 XDP_PCH_TDI
XDP_DB1_USB_EXTD_OC_L 30 29 XDP_DD1_PCH_GPIO49 XDP_PCH_TMS
18 OBSDATA_B1 OBSDATA_D1 18 88 18 11
32 31 88 18 11 XDP_PCH_TCK
18 XDP_DB2_PCH_GPIO10 OBSDATA_B2 34 33
OBSDATA_D2 XDP_DD2_ENET_CLKREQ_L 18

XDP_DB3_SDCONN_STATE_CHANGE_L 36 35 XDP_DD3_AP_CLKREQ_L
18 OBSDATA_B3 OBSDATA_D3 18 XDP XDP
38 37
XDP XDP
XDP 1 J1850.51:5mm
1 U1100.W40:20MM 1
PLACE_NEAR=J1850.40:2.54mm R1867 1 U1100.W39:21MM R1869 R1866
71 12 IN PM_RSMRST_PCH_L R1884 1K 1 2 XDP_PCH_S5_PWRGD PWRGD/HOOK0 40 39
NC ITPCLK/HOOK4 R1868
5% 1/20W MF 201
42 41 XDP 100 100 100 51
XDP_PCH_PWRBTN_L HOOK1 NC ITPCLK#/HOOK5 5% 5% 5%
XDP 44 43
R1870 1K 1 2 PM_PCH_PWROK IN 12 20 39 71 1/20W
5%
1/20W 1/20W 1/20W
VCC_OBS_AB VCC_OBS_CD MF MF MF
44 18 12 OUT PM_PWRBTN_L R1885 0 1 2 5% 1/20W MF 201
2 201
MF
2 201 2 201
HOOK2 46 45 RESET#/HOOK6 XDP_PM_PCH_PWROK 2 201
PLACE_NEAR=U5000.J3:2.54mm 5% 1/20W MF 0201
NC
HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L
NC OUT 6 18 19
50 49
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 47 18

47 18
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52

54
51

53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
IN 11 18 88
SYNC_MASTER=MASTER SYNC_DATE=04/21/2013 A
IN PAGE TITLE
TCK1 56 55 TDI XDP_PCH_TDI
88 18 11 XDP_PCH_TCK TCK0
NC
58 57
TMS XDP_PCH_TMS
OUT 11 18 88

11 18 88
CPU & PCH XDP
OUT OUT
60 59
DRAWING NUMBER SIZE
XDP_PRESENT#
XDP XDP Apple Inc. 051-9889 D
REVISION
C1880 1 1
C1881 R
0.1UF
64 63
0.1UF 13.0.0
20%
10V
20%
10V NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 2
CERM
402 998-2516 CERM
402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 18 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 97

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PCH Reset Button


System 25MHz Clock Generator 80 =PP3V3_S0_PCH

1
R1995
VDD must be powered if any VDDIO is. 4.7K
5%
ENET > S0 > TBT, so ENET is used here. XDP 1/16W
MF-LF
GreenClk 25MHz Power =PP3V3_ENET_SYSCLK
80
R1996 2
402

0
18 6 IN XDP_DBRESET_L 1 2 PM_SYSRST_L OUT 12 44

D Ethernet XTAL Power


SB XTAL Power
80

80 11
=PPVDDIO_ENET_CLK
=PP1V5_S0_PCH_CLK
5%
1/16W
MF-LF 1
OMIT
R1997
D
402
TBT XTAL Power 80 =PPVDDIO_TBT_CLK 0
5%
1/16W
MF-LF
402
2
C1924 1
C1922 1
C1920 1 1
C1902 SILK_PART=SYS RESET

VDD 2

VDDIO_A 6
VDDIO_B 3
VDDIO_C 7
0.1UF 0.1UF 0.1UF 1UF
20% 20% 20% 10%
10V 10V 10V 6.3V
CERM 2 CERM 2 CERM 2 2 CERM
402 402 402 402

U1900
C1905 SLG3NB146V
12PF R1905 TDFN
0 CRITICAL
1 2 89 SYSCLK_CLK25M_X2 1 2 89 SYSCLK_CLK25M_X2_R 10 XOUT

5%
5% NOSTUFF 1 XIN 25MHZ_A 5 SYSCLK_CLK25M_SB OUT 11 89
1/16W
50V MF-LF 1
R1906 25MHZ_B 4 SYSCLK_CLK25M_ENET_R
1

19 89
C0G-CERM CRITICAL 402
0402 NC 1M 25MHZ_C 8 SYSCLK_CLK25M_TBT
Y1905
2 4

OUT 26 89
NC 5%
1/16W
25.000MHZ-20PPM-12PF-85C
C1906 MF-LF
3