Apple Imac 21.5 A1418 Apple J16 820-3482, 051-9889 r13.0.0 - Electronicforum

8 7 6 5 4 3 2 1
m
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
J16 MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
.co
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
13 0002231663 ENGINEERING RELEASED 2013-08-10
LAST_MODIFIED=Sat Aug 10 21:13:36 2013
fix
(.csa) Date (.csa) Date
D Page Contents Sync Page Contents Sync D

TABLE_TABLEOFCONTENTS_HEAD
1 10/18/2012 TABLE_TABLEOFCONTENTS_HEAD
55 06/03/2013
1 Table of Contents J16_MAX 49 I and V Sense(Continued) J16_TONY
se TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
2
3
4
2
4
BOM Configuration
DEBUG LEDS
Holes/PD parts
MASTER
J16_MLB_IG
J16_DG
04/21/2013
05/01/2013
04/21/2013
50
51
52
56
60
61
Temperature Sensors
System Fan
AUDIO: CODEC/REGULATORS
J16_FIYIN
J16_MLB_IG
J16_MLB_IG
06/11/2013
05/01/2013
05/01/2013
.ro
5 04/21/2013 62 05/01/2013
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
5 CPU DMI/PEG/FDI/RSVD J17 53 AUDIO: HEADPHONE AMP J16_MLB_IG

6 04/21/2013 63 05/01/2013
6 CPU Clock/Misc/JTAG/CFG J17 54 AUDIO: LEFT SPKR AMP J16_MLB_IG

7 04/21/2013 TABLE_TABLEOFCONTENTS_ITEM
64 05/01/2013
7 CPU DDR3 Interfaces J17 55 AUDIO: RIGHT SPKR AMP J16_MLB_IG
65 05/01/2013
8 CPU Power J17 56 AUDIO: Jack, Mikey, CHS Switch J16_MLB_IG
w
9 04/21/2013 66 05/01/2013
9 CPU Ground J17 57 Audio: Spkr/Mic Conn. J16_MLB_IG

67 05/01/2013
10 CPU DECOUPLING J17 58 AUDIO: Detects/Grounding J16_MLB_IG
w
11 04/21/2013 68 05/01/2013
11 PCH RTC/HDA/JTAG/SATA/CLK J17 59 AUDIO: Speaker ID J16_MLB_IG

12 04/21/2013 69 05/01/2013
12 PCH DMI/FDI/PM/GFX/PCI J17 60 Power Connectors / VReg G3Hot J16_MLB_IG

70 05/01/2013
13 PCH PCI-E/USB 61 VReg CPU VCC Cntl
w
J17 J16_MLB_IG
14 04/21/2013 71 04/21/2013
14 PCH GPIO/MISC/NCTF J17 62 VReg CPU VCC Phases J16_DG

73 06/17/2013
15 PCH Power J17 63 VReg VDDQ S3 J16_ROSSANA
16 04/21/2013 74 04/21/2013
16 PCH Grounds J17 64 VReg PCH/GPU/TBT 1V05 S0 J16_DG

17 04/21/2013 76 05/01/2013
17 PCH DECOUPLING 65 VReg 3.3V S5/5V S4

C TABLE_TABLEOFCONTENTS_ITEM
18
18
CPU & PCH XDP
J17
MASTER
04/21/2013
66
77
VReg GPU VDDQ
J16_MLB_IG
J16_DG
04/21/2013 C
78 06/17/2013
19 Chipset Support J17 67 VReg GPU Core J16_ROSSANA
20 04/21/2013 81 05/01/2013
20 Project Chipset Support MASTER 68 LCD Backlight Driver (LP8561) J16_MLB_IG

21 04/21/2013 84 05/01/2013
21 CPU Memory S3 Support J17 69 FET-Controlled S0 and S4 MASTER

85 05/01/2013
22 DDR3 VREF MARGINING J17 70 PM Regulator Enables MASTER
23 05/01/2013 86 05/01/2013
23 DDR3 SO-DIMM Connector A J16_MLB_IG 71 PM Power Good J16_MLB_IG

25 05/01/2013 87 04/21/2013
24 DDR3 SO-DIMM CONNECTOR B J16_MLB_IG 72 KEPLER PCI-E J16_DG

27 05/01/2013 88 04/21/2013
25 DDR3 ALIASES AND BITSWAPS J16_MLB_IG 73 KEPLER CORE/FB POWER J16_DG

28 05/01/2013 90 04/21/2013
26 Thunderbolt Host (1 of 2) J16_MLB_IG 74 KEPLER FRAME BUFFER I/F J16_DG

92 04/21/2013
27 Thunderbolt Host (2 of 2) J16_MLB_IG 75 GDDR5 Frame Buffer A J16_DG
30 05/01/2013 93 04/21/2013
28 Thunderbolt Power Support J16_MLB_IG 76 GDDR5 Frame Buffer B J16_DG

32 05/01/2013 96 04/21/2013
29 Thunderbolt Connector A J16_MLB_IG 77 KEPLER EDP/DP/GPIO J16_DG

33 05/01/2013 97 04/21/2013
30 Thunderbolt Connector B J16_MLB_IG 78 KEPLER GPIOS,CLK & STRAPS J16_DG

34 04/21/2013 99 04/21/2013
31 TBT DDC Crossbar J16_DG 79 KEPLER PEX PWR/GNDS J16_DG

35 05/01/2013 100 04/21/2013
32 AIRPORT/BT J16_MLB_IG 80 Power Connectors/Aliases MASTER

37 05/01/2013 102 04/21/2013
33 SATA/SSD Connectors MASTER 81 Signal Aliases MASTER

104 04/21/2013
34 HDD Connector J16_MLB_IG 82 Unused Signal Aliases MASTER
B
39 05/01/2013 105 04/21/2013
B
35 ETHERNET PHY (CAESAR IV) J16_MLB_IG 83 Functional / ICT Test J16_DG

40 05/01/2013 110 04/21/2013
36 Ethernet Support & Connector J16_MLB_IG 84 J16 RULE DEFINITIONS J16_DG

111 06/03/2013
37 SD READER CONNECTOR J16_MLB_IG 85 DDR3 Constraints J16_NICK
42 05/01/2013 112 06/03/2013
38 Camera Controller J16_MLB_IG 86 CPU PCIe Constraints J16_NICK

43 05/01/2013 113 04/21/2013
39 Camera Controller Support J16_MLB_IG 87 PCH PCIe/DMI Constaints J16_DG

44 05/01/2013 114 05/30/2013
40 Internal DP Support J16_MLB_IG 88 SATA/FDI/XDP Constraints J16_NICK

45 04/21/2013 115 05/30/2013
41 Internal DP MUXing J16_DG 89 PCH and BR Constraints J16_NICK

116 05/30/2013
42 EXTERNAL USB PORTS A & B J16_MLB_IG 90 USB/Ethernet/SD Constraints J16_NICK
47 05/01/2013 117 06/03/2013
43 EXTERNAL USB PORTS C & D J16_MLB_IG 91 SMBus/Sensor Constraints J16_TONY

118 04/21/2013
44 SMC J16_MLB_IG 92 VReg Constraints J16_DG
51 06/11/2013 119 04/21/2013
45 SMC Support J16_TONY 93 CPU VReg Constraints J16_DG

120 04/21/2013
46 SPI and Debug Connector J16_TONY 94 Platform VReg Constraints MASTER
121 04/21/2013
47 SMBus Connections J16_DG 95 TBT/DP Constraints MASTER
54 06/11/2013 122 05/30/2013
48 I and V Sense J16_TONY 96 GDDR5/GPU Constraints J16_NICK

123 04/21/2013
97 BLC Constraints J16_DG
A A
DRAWING TITLE
SCHEM,MLB,J16
DRAWING NUMBER SIZE
Apple Inc. 051-9889 D

REVISION
R
13.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=J16
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 123
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST_MODIFIED=Sat Aug 10 21:13:36 2013 DRAWING
IV ALL RIGHTS RESERVED 1 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Main BOM Variants Bar Code Labels / EEEE #’s

TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS TABLE_5_HEAD
TABLE_BOMGROUP_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
985-0035 PCBA,MLB,DEV,J16 DEVELOPMENT,J16_DEVEL TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9RR CRITICAL EEEE:F9RR
639-4281 PCBA,MLB,107GX,VRAM_HYNIX,BETTER,J16 J16,J16_COMMON,CPU:BETTER,GPU:107GX,FBA,FBB,FB:BOTH_HYNIX,SSD:Y,EEEE:F9RR TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9T5 CRITICAL EEEE:F9T5
639-4286 PCBA,MLB,107GX,VRAM_ELPIDA,BETTER,J16 J16,J16_COMMON,CPU:BETTER,GPU:107GX,FBA,FBB,FB:BOTH_ELPIDA,SSD:Y,EEEE:F9T5 TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9T3 CRITICAL EEEE:F9T3
639-4282 PCBA,MLB,107GX,VRAM_HYNIX,CTO,J16 J16,J16_COMMON,CPU:CTO,GPU:107GX,FBA,FBB,FB:BOTH_HYNIX,SSD:Y,EEEE:F9T3 TABLE_5_ITEM
825-7896 1 MLB LABEL,2D EEEE_F9RW CRITICAL EEEE:F9RW

D
TABLE_BOMGROUP_ITEM
639-4287 PCBA,MLB,107GX,VRAM_ELPIDA,CTO,J16
D J16,J16_COMMON,CPU:CTO,GPU:107GX,FBA,FBB,FB:BOTH_ELPIDA,SSD:Y,EEEE:F9RW
Schematic / PCB #’s

TABLE_5_HEAD

BOM Groups 051-9889 1 SCH,MLB,J16 SCH CRITICAL J16
TABLE_5_ITEM
TABLE_BOMGROUP_HEAD TABLE_5_ITEM
BOM GROUP BOM OPTIONS 820-3482 1 PCBF,MLB,J16 PCB CRITICAL J16

TABLE_BOMGROUP_ITEM
J16_COMMON COMMON,ALTERNATE,J16_COMMON1,J16_COMMON2,J16_PROGPARTS,J16_PRODUCTION
TABLE_BOMGROUP_ITEM
J16_COMMON1 XDP,SPEAKERID,TBTHV:P12V,CPUVCC:3PHASE,EXT_GPU:YES,VDDQ:P1V5
J16_PROGPARTS SMC:PROG,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG
TABLE_BOMGROUP_ITEM
GPU & VRAM

TABLE_BOMGROUP_ITEM
TABLE_5_HEAD
J16_DEVEL XDP_CONN,LPCPLUS,DDRVREF_DAC,DEVEL_SENSORS,DEVEL_AUDIO ADD ’J16_PRODUCTION’ AT REVA RELEASE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
DEVEL_SENSORS AP_ISNS:Y,HDD_IVSNS:Y,TEMPSNSDEV 337S4427 1 IC,GPU,NV,GK107-GX,PS,926MHZ,2.5GHZ U8700 CRITICAL GPU:107GX

TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
J16_PRODUCTION AP_ISNS:N,HDD_IVSNS:N 333S0630 4 IC,GDDR5,2GBIT,64MX32,5GBPS,GEMMA-DIE U9200,U9250,U9300,U9350 CRITICAL FB:BOTH_HYNIX

TABLE_5_ITEM
333S0695 4 IC,GDDR5,2GBIT,64MX32,5GBPS,B-DIE U9200,U9250,U9300,U9350 CRITICAL FB:BOTH_ELPIDA
C C
CPUs
TABLE_5_HEAD

TABLE_5_ITEM
Alternates
337S4610 1 HSW,SR14J,PRQ,C0,2.9G,65W,4+2,1.15,6M,LGA CPU CRITICAL CPU:BETTER TABLE_ALT_HEAD
TABLE_5_ITEM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
337S4608 1 HSW,SR14H,PRQ,C0,3.1G,65W,4+2,1.2,8M,LGA CPU CRITICAL CPU:CTO PART NUMBER
TABLE_ALT_ITEM
377S0147 377S0126 ALL USB Diode Array

TABLE_ALT_ITEM
377S0124 377S0057 ALL TVS

TABLE_ALT_ITEM
376S0975 376S1081 ALL P/NCh dual FET

TABLE_ALT_ITEM
155S0578 155S0367 ALL 120OHM EMI BEAD

TABLE_ALT_ITEM
128S0368 128S0365 ALL 150UF AL POLY

TABLE_ALT_ITEM
128S0298 128S0293 ALL 330 UF AL POLY

CPU Socket TABLE_ALT_ITEM
TABLE_5_HEAD
138S0681 138S0638 ALL Taiyo 10uf 805 alt
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM
TABLE_5_ITEM
197S0481 197S0480 Y1905 25MHz PCH Xtal
511S0080 1 SOCKET,MOLEX,LGA1150,CPU-LF U0500 CRITICAL TABLE_ALT_ITEM
197S0464 197S0477 Y9700 27 MHz GPU Xtal

TABLE_ALT_ITEM
197S0466 197S0477 Y9700 27 MHz GPU Xtal

TABLE_ALT_ITEM
197S0479 197S0478 Y4200 12 MHz Cam. Xtal

ASIC Parts TABLE_ALT_ITEM
TABLE_5_HEAD
341S3913 341S3912 U3990 Enet ROM,ATMEL,V1.15
B 337S4541 1 IC,LPT-D,SR198Z87,C2,PRQFCBGA708,23X22MM U1100 CRITICAL

TABLE_5_ITEM
377S0155
138S0860
377S0104
138S0775
ALL
ALL
USB Diode
Single-source 1uF 402

TABLE_ALT_ITEM
B
TABLE_5_ITEM
338S1113 1 IC,TBT,CR-4C,B1,PRQ,CIO,288 12X12 FC-CSP U2800 CRITICAL TABLE_ALT_ITEM
TABLE_5_ITEM
138S0859 138S0788 ALL Single-source 10uF
343S0616 1 IC,BCM57766A,CIV+,A0,8X8 U3900 CRITICAL TABLE_ALT_ITEM
TABLE_5_ITEM
107S0251 107S0249 ALL Sense resistor R5400,R5520,R5530
353S3908 1 IC,LP8561,LED BLKT CTLR,LLP24,B0-F U8100 CRITICAL TABLE_ALT_ITEM
138S0648 138S0652 ALL 4.7uF GFX decoupling

TABLE_ALT_ITEM
138S0746 138S0705 ALL 10uF alt;Audio

TABLE_ALT_ITEM
Programmable Parts 138S0715 138S0740 ALL 4.7uF GFX decoupling

TABLE_ALT_ITEM
TABLE_5_HEAD 107S0254 107S0241 ALL 5mOhm Sense Resistor

TABLE_5_ITEM 107S0250 107S0248 ALL 3mOhm Sense Resistor

341S3928 1 IC,EFI,V0112,J16G U5210 CRITICAL BOOTROM:PROG
TABLE_5_ITEM
335S0807 1 IC,64 MBIT SPI SERIAL FLASH U5210 CRITICAL BOOTROM:BLANK

TABLE_5_ITEM
NEED NEW EFI,SMC PROG PARTS
341S3903 1 IC,SMC-A3,V2.16A4,PROTO0,J16G U5000 CRITICAL SMC:PROG
TABLE_5_ITEM
338S1159 1 IC,SMC12-A3,40MHZ/50MIPS,SCPL FW,157BGA U5000 CRITICAL SMC:BLANK

TABLE_5_ITEM
341S3859 1 IC,TBT,EEPROM,CR,V23.10,J16 U2890 CRITICAL T29ROM:PROG

TABLE_5_ITEM
335S0865 1 IC,EEPROM,SERIAL,256KB,MLP8 U2890 CRITICAL T29ROM:BLANK

TABLE_5_ITEM
341S3912 1 IC,ENET SPI ROM,NUMONYX,V1.15,J16/J17 U3990 CRITICAL CIVROM:PROG

TABLE_5_ITEM
335S0862 1 IC,SERIAL FLASH,2MBIT,2.7V,REV F U3990 CRITICAL CIVROM:BLANK

TABLE_5_ITEM
341S3778 1 IC,CAMERA,FLASH,V7230,J16/J17 U4202 CRITICAL CAMROM:PROG

A A
TABLE_5_ITEM
335S0852 1 IC,FLASH,SPI,1MBIT,3V3 U4202 CRITICAL CAMROM:BLANK

SYNC_MASTER=MASTER SYNC_DATE=04/21/2013
PAGE TITLE
BOM Configuration
DRAWING NUMBER SIZE

REVISION
R
13.0.0
2 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
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8 7 6 5 4 3 2 1
GPU GOOD Led VIDEO ON Led

S5 Led ALL_SYS_PWRGD Led
D =PP3V3_S4_LED
80 3 =PP3V3_S0_LED 80 3 =PP3V3_S0_LED
D
80 =PP3V3_S5_LED
80
1
R0302 R0303
1
1K
R0304
1
1
R0301
1K
1K
5%
1/16W
5%
1/16W
MF-LF
1K
5%
1/16W
MF-LF
5% MF-LF 2 402 2 402
1/16W 2 402 GPU_PRESENT_R
MF-LF
2 402
CORE_VOLTAGES_ON_R LCD_SHOULD_ON_R
A SILK_PART=3
ITS_PLUGGED_IN A SILK_PART=2 CRITICAL LE0303 CRITICAL
A
SILK_PART=1 CRITICAL LE0302 GREEN-3.6MCD CRITICAL
LE0301 K
GREEN-3.6MCD
2.0X1.25MM-SM
K 2.0X1.25MM-SM
A SILK_PART=4
GREEN-3.6MCD
K
2.0X1.25MM-SM
CORE_VOLTAGES_ON
GPU_PRESENT_DRAIN
LE0304
GREEN-3.6MCD
6 K 2.0X1.25MM-SM
3 CRITICAL This LED is a GPIO driven from
D the southbridge that indicates
that chipset has enumerated graphics
D CRITICAL Q0302
Q0302 2
2N7002DW-X-G VIDEO_ON_L
2N7002DW-X-G 18 14 IN GPU_GOOD G S SOT-363 IN 40
71 44 21 ALL_SYS_PWRGD 5 G S SOT-363
IN
1
4
C C
B B
A SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
PAGE TITLE
DEBUG LEDS
DRAWING NUMBER SIZE

REVISION
R
13.0.0
3 OF 123
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8 7 6 5 4 3 2 1
CPU Heatsink WIRELESS CARD MTG HOLES
4mm Plated Holes (998-0850) 998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)
OMIT OMIT OMIT OMIT

ZH0400 ZH0401 ZH0402 ZH0403
8P5R5-NSP 8P5R5-NSP 8P5R5-NSP 8P5R5-NSP
1 1 1 1
ZH0421 ZH0422 D
D 5P5R1P9-4P3B-NSP
1
5P5R1P9-4P3B-NSP
1
GPU HEATSINK MOUNTING FEATURES

(860-1532)
CRITICAL
CRITICAL
SH0477 SH0479
STDOFF-4.5OD.98H-1.1-3.40-TH
STDOFF-4.5OD.98H-1.1-3.40-TH CRITICAL
1
1 SH0478
STDOFF-4.5OD.98H-1.1-3.40-TH
1
C C
Rear Cover
998-4559 (Plated holes, 4mm inner diameter, 8mm pad)
998-5089 (ZH0414) near BLC has slightly larger hole to allow for grommet
ZH0413 ZH0415 ZH0416 ZH0414
7P0R4P0-8P0B-NSP 7P0R4P0-8P0B-NSP
1 7P0R4P0-8P0B-NSP 7P0R4P6-8P0B-NSP
1 1 1
B B
SSD STANDOFF
APN: 860-1624
SSD:Y
CRITICAL
NUT0413
STDOFF-4.5OD2.2ID-6.5H-SM
1
A SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013 A
PAGE TITLE
Holes/PD parts
DRAWING NUMBER SIZE

REVISION
R
13.0.0
4 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVCOMP_S0_CPU 5 8
PLACE_NEAR=U0500.P3:12.7MM
1
OMIT_TABLE R0510
24.9
U0500 1%
D HASWELL
LGA 2
1/16W
MF-LF
402 D
87 12 DMI_S2N_N<0> T3 DMI_RXN0 SYM 1 OF 11 PEG_RCOMP P3 86 CPU_PEG_RCOMP
IN
87 12 IN DMI_S2N_N<1> V1 DMI_RXN1
87 12 DMI_S2N_N<2> V2 DMI_RXN2 PEG_RXN0 F15 =PEG_D2R_N<0> 81
IN IN
87 12 IN DMI_S2N_N<3> W3 DMI_RXN3 PEG_RXN1 E14 =PEG_D2R_N<1> IN 81
F13 OMIT_TABLE
PEG_RXN2 =PEG_D2R_N<2> IN 81
87 12 IN DMI_S2N_P<0> U3 DMI_RXP0 PEG_RXN3 E12 =PEG_D2R_N<3> IN 81 U0500

87 12 IN DMI_S2N_P<1> U1 DMI_RXP1 PEG_RXN4 F11 =PEG_D2R_N<4> IN 81 HASWELL
87 12 IN DMI_S2N_P<2> W2 DMI_RXP2 PEG_RXN5 G10 =PEG_D2R_N<5> IN 81
LGA
SYM 10 OF 11
87 12 IN DMI_S2N_P<3> Y3 DMI_RXP3 PEG_RXN6 F9 =PEG_D2R_N<6> IN 81 82 TP_DP_IG_B_MLN<0> F17 DDIB_TXBN0
PEG_RXN7 G8 =PEG_D2R_N<7> TP_DP_IG_B_MLP<0> E17 DDIB_TXBP0
DMI
IN 81 82
87 12 OUT DMI_N2S_N<0> AA5 DMI_TXN0 PEG_RXN8 D4 =PEG_D2R_N<8> IN 81 82 TP_DP_IG_B_MLN<1> G18 DDIB_TXBN1

87 12 OUT DMI_N2S_N<1> AB4 DMI_TXN1 PEG_RXN9 E5 =PEG_D2R_N<9> IN 81 82 TP_DP_IG_B_MLP<1> F18 DDIB_TXBP1
DMI_N2S_N<2> AC4 DMI_TXN2 PEG_RXN10 F6 =PEG_D2R_N<10> TP_DP_IG_B_MLN<2> H19 DDIB_TXBN2
EDP
87 12 OUT IN 81 82
87 12 OUT DMI_N2S_N<3> AC2 DMI_TXN3 PEG_RXN11 G5 =PEG_D2R_N<11> IN 81 82 TP_DP_IG_B_MLP<2> G19 DDIB_TXBP2

PEG_RXN12 H6 =PEG_D2R_N<12> 81 82 TP_DP_IG_B_MLN<3> G20 DDIB_TXBN3
IN
DMI_N2S_P<0> AA4 DMI_TXP0 PEG_RXN13 J5 =PEG_D2R_N<13> TP_DP_IG_B_MLP<3> F20 DDIB_TXBP3
DIGITAL DISPLAY INTERFACES

87 12 OUT IN 81 82
87 12 OUT DMI_N2S_P<1> AB3 DMI_TXP1 PEG_RXN14 K6 =PEG_D2R_N<14> IN 81
87 12 OUT DMI_N2S_P<2> AC5 DMI_TXP2 PEG_RXN15 L5 =PEG_D2R_N<15> IN 81 82 TP_DP_IG_C_MLN<0> E19 DDIC_TXCN0 PPVCOMP_S0_CPU 5 8
87 12 OUT DMI_N2S_P<3> AC1 DMI_TXP3 82 TP_DP_IG_C_MLP<0> D19 DDIC_TXCP0 PLACE_NEAR=U0500.R4:12.7MM
PEG_RXP0 E15 =PEG_D2R_P<0> TP_DP_IG_C_MLN<1> D20 DDIC_TXCN1 1

IN 81 82 R0530
PEG_RXP1 D14 =PEG_D2R_P<1> IN 81 82 TP_DP_IG_C_MLP<1> C20 DDIC_TXCP1 24.9
88 12 FDI_CSYNC D16 FDI_CSYNC 1%
IN E13 =PEG_D2R_P<2> TP_DP_IG_C_MLN<2> E21
PEG_RXP2 DDIC_TXCN2
FDI
IN 81 82 1/16W
MF-LF
PEG_RXP3 D12 =PEG_D2R_P<3> IN 81 82 TP_DP_IG_C_MLP<2> D21 DDIC_TXCP2 402
2
88 12 FDI_INT D18 DISP_INT PEG_RXP4 E11 =PEG_D2R_P<4> 81 82 TP_DP_IG_C_MLN<3> D22 DDIC_TXCN3
IN IN
F10 C22 DP_RCOMP R4 86 CPU_EDP_RCOMP
PEG_RXP5 =PEG_D2R_P<5> 81 82 TP_DP_IG_C_MLP<3> DDIC_TXCP3
C
IN
EDP_DISP_UTIL E16
C Though FDI unused, these are
to be connected per PDG (10.6)
PEG_RXP6
PEG_RXP7
E9
F8
=PEG_D2R_P<6>
=PEG_D2R_P<7>
IN 81
81 82 TP_DP_IG_D_MLN<2> C17 DDID_TXDN2

TP_EDP_DISP_UTIL
IN
PEG_RXP8 D3 =PEG_D2R_P<8> 81 82 TP_DP_IG_D_MLP<2> B17 DDID_TXDP2
IN B14
E4 B18 FDI0_TX0N0 NC
PEG_RXP9 =PEG_D2R_P<9> IN 81 82 TP_DP_IG_D_MLN<3> DDID_TXDN3 A14
PCI EXPRESS BASED INTERFACE SIGNALS FDI0_TX0P0
FDI
PEG_RXP10 F5 =PEG_D2R_P<10> IN 81 82 TP_DP_IG_D_MLP<3> A18 DDID_TXDP3 NC
FDI0_TX0N1 C13
PEG_RXP11 G4 =PEG_D2R_P<11> IN 81
NC
TP_DP_IG_D_MLN<0> C15 DDID_TXDN0 FDI0_TX0P1 B13
PEG_RXP12 H5 =PEG_D2R_P<12> IN 81
82
NC
82 TP_DP_IG_D_MLP<0> B15 DDID_TXDP0
PEG_RXP13 J4 =PEG_D2R_P<13> 81
IN TP_DP_IG_D_MLN<1> B16
K5 82 DDID_TXDN1
PEG_RXP14 =PEG_D2R_P<14> IN 81
82 TP_DP_IG_D_MLP<1> A16 DDID_TXDP1
PEG_RXP15 L4 =PEG_D2R_P<15> IN 81
Port D pins out of order
B12 to match Intel symbol.
PEG_TXN0 =PEG_R2D_C_N<0> OUT 81
PEG_TXN1 C11 =PEG_R2D_C_N<1> 81

OUT
PEG_TXN2 D10 =PEG_R2D_C_N<2> 81
OUT
PEG_TXN3 C9 =PEG_R2D_C_N<3> 81
OUT
PEG_TXN4 D8 =PEG_R2D_C_N<4> 81
OUT
PEG_TXN5 C7 =PEG_R2D_C_N<5> OUT 81
PEG_TXN6 B6 =PEG_R2D_C_N<6> OUT 81
PEG_TXN7 C5 =PEG_R2D_C_N<7> OUT 81
PEG_TXN8 E2 =PEG_R2D_C_N<8> OUT 81
PEG_TXN9 F3 =PEG_R2D_C_N<9> 81
OUT
PEG_TXN10 G2 =PEG_R2D_C_N<10> 81
OUT
PEG_TXN11 H3 =PEG_R2D_C_N<11> OUT 81
PEG_TXN12 J2 =PEG_R2D_C_N<12> OUT 81
PEG_TXN13 K3 =PEG_R2D_C_N<13> OUT 81
PEG_TXN14 M3 =PEG_R2D_C_N<14> OUT 81
B PEG_TXN15 L2 =PEG_R2D_C_N<15> OUT 81

B
PEG_TXP0 A12 =PEG_R2D_C_P<0> 81
OUT
PEG_TXP1 B11 =PEG_R2D_C_P<1> OUT 81
PEG_TXP2 C10 =PEG_R2D_C_P<2> 81

OUT
PEG_TXP4 C8 =PEG_R2D_C_P<4> OUT 81
PEG_TXP6 A6 =PEG_R2D_C_P<6> OUT 81
PEG_TXP8 E1 =PEG_R2D_C_P<8> 81
OUT
PEG_TXP9 F2 =PEG_R2D_C_P<9> 81
OUT
PEG_TXP10 G1 =PEG_R2D_C_P<10> OUT 81
PEG_TXP11 H2 =PEG_R2D_C_P<11> OUT 81
PEG_TXP12 J1 =PEG_R2D_C_P<12> OUT 81
PEG_TXP13 K2 =PEG_R2D_C_P<13> OUT 81
PEG_TXP14 M2 =PEG_R2D_C_P<14> OUT 81
PEG_TXP15 L1 =PEG_R2D_C_P<15> 81
OUT
A SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

REVISION
R
13.0.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U0500
HASWELL
LGA
61 18 8 PPVCCIO_S0_CPU SYM 2 OF 11
86 18 14 IN CPU_RESET_L M39 RESET* SM_RCOMP0 R1 85 CPU_SM_RCOMP<0>
PLACE_NEAR=U0500.R1:12.7mm
SM_RCOMP1 P1 CPU_SM_RCOMP<1>
D
PLACE_NEAR=R0603.2:1mm 1 85
DDR3
D R0601
51
5%
86 45 OUT CPU_CATERR_L M36 CATERR* SM_RCOMP2 R2 85 CPU_SM_RCOMP<2>
PLACE_NEAR=U0500.P1:12.7mm
PLACE_NEAR=U0500.R2:12.7mm
SM_DRAMRST* AK22 =MEM_RESET_L
THERMAL
1/16W OUT 21
CPU_PECI N37 PECI 1 1 1
MF-LF PLACE_NEAR=U0500.K38:38MM 86 45 44 14 BI R0614 R0613 R0612
402
2 R0603 100 75 100
56
K38 PROCHOT* (IPU) PRDY* L39 XDP_CPU_PRDY_L OUT 18 1% 1% 1%
86 61 45 44 BI CPU_PROCHOT_L 2 1 86 CPU_PROCHOT_R_L 1/16W 1/16W 1/16W
(IPU) PREQ* L37 XDP_CPU_PREQ_L IN 18 MF-LF MF-LF MF-LF
5% 402 402 402
80 10 8 =PP1V5_S0_CPU_MEM 1/16W 2 2 2
MF-LF 45 OUT CPU_THRMTRIP_L F37 THERMTRIP*
402 (IPD) TCK D39 XDP_CPU_TCK IN 18 88
R0620 1 P36 PM_SYNC (IPU) TMS E39 XDP_CPU_TMS IN 18 88

86 12 IN PM_SYNC
1.82K (IPU) TRST* E37 XDP_CPU_TRST_L IN 18
1%
1/16W
MF-LF 86 18 14 IN CPU_PWRGD AB35 PWRGOOD
TDI F38 XDP_CPU_TDI
PWR
402 (IPU) IN 18 88
2
PLACE_NEAR=R0621.2:1mm
AK21 SM_DRAMPWROK TDO F39 XDP_CPU_TDO OUT 18 88
21 12 IN PM_MEM_PWRGD
JTAG
PLACE_NEAR=U0500.AK21:25.4mm
D38 SKTOCC* DBR* G40 XDP_DBRESET_L OUT 18 19
R0621 1 70 OUT CPU_SKTOCC_L
2.55K
1% (IPU) BPM0* G39 XDP_BPM_L<0> BI 18 86
1/16W 87 11 IN CPU_CLK135M_DPLLREF_N W6 DPLL_REF_CLKN
MF-LF (IPU) BPM1* J39 XDP_BPM_L<1> BI 18 86
402 87 11 IN CPU_CLK135M_DPLLREF_P W5 DPLL_REF_CLKP
2
(IPU) BPM2* G38 XDP_BPM_L<2> BI 18 88
BPM3* H37 XDP_BPM_L<3>
CLOCK
(IPU) BI 18 88
87 11 CPU_CLK135M_DPLLSS_N U5 SSC_DPLL_REF_CLKN
IN H38 XDP_BPM_L<4>
U6 SSC_DPLL_REF_CLKP (IPU) BPM4* BI 18 88
87 11 IN CPU_CLK135M_DPLLSS_P
(IPU) BPM5* J38 XDP_BPM_L<5> BI 18 88
(IPU) BPM6* K39 XDP_BPM_L<6> BI 18 88

87 11 DMI_CLK100M_CPU_N V4 BCLKN
IN K37 XDP_BPM_L<7>
V5 BCLKP (IPU) BPM7* BI 18 88
87 11 IN DMI_CLK100M_CPU_P
PLACE_NEAR=U0500.AB35:25mm
R0611 1
C DPLL_REF_CLK needs to be connected as it provides
some bootstrap function during startup
10K
5%
1/16W
MF-LF
C
402
2
OMIT_TABLE
U0500
HASWELL
LGA
TP_CPU_RSVD_TP1 H16 RSVD_TP SYM 11 OF 11 RSVD_TP J12 TP_CPU_RSVD_TP12
D1 RSVD_TP RESERVED J10
TP_CPU_RSVD_TP2 RSVD_TP TP_CPU_RSVD_TP13
RSVD_TP C2 TP_CPU_RSVD_TP14
TP_CPU_RSVD_TP3 J13 RSVD_TP
RSVD_TP C39 TP_CPU_RSVD_TP15
TP_CPU_RSVD_TP4 K11 RSVD_TP
PLACE_NEAR=U0500.H40:10mm
TP_CPU_RSVD_TP5 K8 RSVD_TP CFG_RCOMP H40 86 CPU_CFG_RCOMP
TP_CPU_RSVD_TP6 N36 RSVD_TP
(IPU) CFG16 Y37 CPU_CFG<16> 18 88
CPU_TESTLO_P6 P6 TESTLO_P6 1
CFG18 W36 CPU_CFG<18> 18
R0690
B8 VSS 49.9
(IPU) CFG17 Y36 CPU_CFG<17> 18 88 1%
1 B23 VSS
R0680 CFG19 V36 CPU_CFG<19> 18
1/16W
MF-LF
49.9 80 61 48 10 8 =PPCPUVCC_S0_CPU B10 VSS 402
2
1%
1/16W P8 VCC
MF-LF
402
2 TP_CPU_RSVD_TP7 P37 RSVD_TP
TP_CPU_RSVD_TP8 R36 RSVD_TP
TP_CPU_RSVD_TP9 N38 RSVD_TP

RSVD U8
B TESTLO_X pins to be individually connected to GND
via a resistor matching the nominal trace impedance +/-20%
TP_CPU_RSVD_TP10
TP_CPU_RSVD_TP11
J16 RSVD_TP
J8 RSVD_TP RSVD H12
H15
NC
NC B
N5 TESTLO_N5 RSVD NC
CPU_TESTLO_N5
RSVD J9
NC
1 CPU_CFG<0> AA37 CFG0 (IPU)
R0685 88 18
49.9 CPU_CFG<1> Y38 CFG1 (IPU) RSVD M10 INTEL’S HASWELL DT EDS SAYS THAT ALL RSVD AND RSVD_NCTF SHOULD BE NC’D
1%
88 18
NC
1/16W 88 18 CPU_CFG<2> AA36 CFG2 (IPU)
MF-LF
402 88 18 CPU_CFG<3> W38 CFG3 (IPU)
2
V39 RSVD H14 NC
88 18 CPU_CFG<4> CFG4 (IPU)
88 18 CPU_CFG<5> U39 CFG5 (IPU)
1
R0642 88 18 CPU_CFG<6> U40 CFG6 (IPU)
1K
5% 88 18 CPU_CFG<7> V38 CFG7 (IPU)
1/16W
MF-LF 88 18 CPU_CFG<8> T40 CFG8 (IPU)
402
Y35 RSVD_TP K13 TP_CPU_RSVD_TP16
2
AA34 RSVD_TP K12 TP_CPU_RSVD_TP17
88 18 CPU_CFG<11> V37 CFG11 (IPU)
Y34 VSS B30
88 82 18 CPU_CFG<12> CFG12 (IPU)
U38 VSS B28
88 82 18 CPU_CFG<13> CFG13 (IPU)
88 82 18 CPU_CFG<14> W34 CFG14 (IPU) VSS B24
88 82 18 CPU_CFG<15> V35 CFG15 (IPU) VSS B26
Y8 RSVD
NC
W8 RSVD
NC
M11 RSVD
NC
A CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
PAGE TITLE
CFG [6:5] :PCIE BIFURCATION
CFG [4] :eDP ENABLE/DISABLE

11 = 1 X16 (default)
1 = DISABLED(default)
10 = 2 X8
0 = ENABLED
01 = RSVD 00 = X8, X4, X4
CPU Clock/Misc/JTAG/CFG
DRAWING NUMBER SIZE
CFG [3] :PCIE x4 LANE REVERSAL
CFG [2] :PCIE x16 LANE REVERSAL

1 = NORMAL OPERATION(default)
1 = NORMAL OPERATION(default)
0 = LANES REVERSED
0 = LANES REVERSED Apple Inc. 051-9889 D

REVISION
R
13.0.0
6 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE OMIT_TABLE
85 25 BI MEM_A_DQ<0> AD38 SA_DQ0 U0500 RSVD N35 NC 85 25 BI MEM_B_DQ<0> AE34 SB_DQ0 U0500 RSVD AB8 NC
85 25 BI MEM_A_DQ<1> AD39 SA_DQ1 HASWELL SA_CKN0 AY16 MEM_A_CLK_N<0>
85 25 BI MEM_B_DQ<1> AE35 SB_DQ1 HASWELL SB_CKN0 AM21 MEM_B_CLK_N<0>
85 25 BI MEM_A_DQ<2> AF38 SA_DQ2 LGA OUT 23 85
85 25 BI MEM_B_DQ<2> AG35 SB_DQ2 LGA OUT 24 85
AF39 SYM 3 OF 11 SA_CK0 AY15 MEM_A_CLK_P<0> OUT 23 85

AH35 SYM 4 OF 11 SB_CK0 AM20 MEM_B_CLK_P<0> OUT 24 85
85 25 BI MEM_A_DQ<3> SA_DQ3 85 25 BI MEM_B_DQ<3> SB_DQ3
AD37 SA_CKE0 AV22 MEM_A_CKE<0> OUT 23 85
AD34 SB_CKE0 AW29 MEM_B_CKE<0> OUT 24 85
85 25 BI MEM_A_DQ<5> AD40 SA_DQ5 SA_CKN1 AV15 MEM_A_CLK_N<1> OUT 23 85 85 25 BI MEM_B_DQ<5> AD35 SB_DQ5 SB_CKN1 AP21 MEM_B_CLK_N<1> OUT 24 85
85 25 BI MEM_A_DQ<6> AF37 SA_DQ6 SA_CK1 AW15 MEM_A_CLK_P<1> OUT 23 85 85 25 BI MEM_B_DQ<6> AG34 SB_DQ6 SB_CK1 AP22 MEM_B_CLK_P<1> OUT 24 85
MEM_A_DQ<7> AF40 SA_DQ7 SA_CKE1 AT23 MEM_A_CKE<1> MEM_B_DQ<7> AH34 SB_DQ7 SB_CKE1 AY29 MEM_B_CKE<1>
D
85 25
85 25
BI
BI MEM_A_DQ<8> AH40
AH39
SA_DQ8
SA_CKN2 AW14 MEM_A_CLK_N<2>
OUT
OUT
23 85
82 85
85 25
85 25
BI
BI MEM_B_DQ<8> AL34
AL35
SB_DQ8
SB_CKN2 AN21 MEM_B_CLK_N<2>
OUT
OUT
24 85
82 85
D
AK38 SA_CK2 AV14 MEM_A_CLK_P<2> OUT 82 85
AK31 SB_CK2 AN20 MEM_B_CLK_P<2> OUT 82 85
AK39 SA_CKE2 AU22 MEM_A_CKE<2> OUT 82 85
AL31 SB_CKE2 AU28 MEM_B_CKE<2> OUT 82 85
85 25 MEM_A_DQ<12> AH37 SA_DQ12 SA_CKN3 AY13 MEM_A_CLK_N<3> 82 85 85 25 MEM_B_DQ<12> AK34 SB_DQ12 SB_CKN3 AP20 MEM_B_CLK_N<3> 82 85
BI OUT BI OUT
85 25 BI MEM_A_DQ<13> AH38 SA_DQ13 SA_CK3 AW13 MEM_A_CLK_P<3> OUT 82 85 85 25 BI MEM_B_DQ<13> AK35 SB_DQ13 SB_CK3 AP19 MEM_B_CLK_P<3> OUT 82 85
85 25 BI MEM_A_DQ<14> AK37 SA_DQ14 SA_CKE3 AU23 MEM_A_CKE<3> OUT 82 85 85 25 BI MEM_B_DQ<14> AK32 SB_DQ14 SB_CKE3 AU29 MEM_B_CKE<3> OUT 82 85
85 25 MEM_A_DQ<15> AK40 SA_DQ15 85 25 MEM_B_DQ<15> AL32 SB_DQ15

BI BI
85 25 BI MEM_A_DQ<16> AM40 SA_DQ16 SA_CS0* AU14 MEM_A_CS_L<0> OUT 23 85 85 25 BI MEM_B_DQ<16> AN34 SB_DQ16 SB_CS0* AP17 MEM_B_CS_L<0> OUT 24 85
85 25 BI MEM_A_DQ<17> AM39 SA_DQ17 SA_CS1* AV9 MEM_A_CS_L<1> OUT 23 85 85 25 BI MEM_B_DQ<17> AP34 SB_DQ17 SB_CS1* AN15 MEM_B_CS_L<1> OUT 24 85
85 25 BI MEM_A_DQ<18> AP38 SA_DQ18 SA_CS2* AU10 MEM_A_CS_L<2> OUT 82 85 85 25 BI MEM_B_DQ<18> AN31 SB_DQ18 SB_CS2* AN17 MEM_B_CS_L<2> OUT 82 85
85 25 BI MEM_A_DQ<19> AP39 SA_DQ19 SA_CS3* AW8 MEM_A_CS_L<3> OUT 82 85 85 25 BI MEM_B_DQ<19> AP31 SB_DQ19 SB_CS3* AL15 MEM_B_CS_L<3> OUT 82 85
85 25 MEM_A_DQ<20> AM37 SA_DQ20 85 25 MEM_B_DQ<20> AN35 SB_DQ20

BI AW10 MEM_A_ODT<0> BI AM17 MEM_B_ODT<0>
AM38 SA_ODT0 OUT 23 85
AP35 SB_ODT0 OUT 24 85
MEMORY CHANNEL A
MEMORY CHANNEL B
SA_ODT1 AY8 MEM_A_ODT<1> OUT 23 85 SB_ODT1 AL16 MEM_B_ODT<1> OUT 24 85
85 25 BI MEM_A_DQ<22> AP37 SA_DQ22 85 25 BI MEM_B_DQ<22> AN32 SB_DQ22
SA_ODT2 AW9 MEM_A_ODT<2> OUT 82 85 SB_ODT2 AM16 MEM_B_ODT<2> OUT 82 85
85 25 MEM_A_DQ<23> AP40 SA_DQ23 85 25 MEM_B_DQ<23> AP32 SB_DQ23
BI AU8 MEM_A_ODT<3> BI AK15 MEM_B_ODT<3>
AV37 SA_ODT3 OUT 82 85
AM29 SB_ODT3 OUT 82 85
85 25 BI MEM_A_DQ<25> AW37 SA_DQ25 SA_BS0 AV12 MEM_A_BA<0> OUT 23 85 85 25 BI MEM_B_DQ<25> AM28 SB_DQ25 SB_BS0 AK17 MEM_B_BA<0> OUT 24 85
85 25 BI MEM_A_DQ<26> AU35 SA_DQ26 SA_BS1 AY11 MEM_A_BA<1> OUT 23 85 85 25 BI MEM_B_DQ<26> AR29 SB_DQ26 SB_BS1 AL18 MEM_B_BA<1> OUT 24 85
85 25 MEM_A_DQ<27> AV35 SA_DQ27 SA_BS2 AT21 MEM_A_BA<2> 23 85 85 25 MEM_B_DQ<27> AR28 SB_DQ27 SB_BS2 AW28 MEM_B_BA<2> 24 85
BI OUT BI OUT
85 25 MEM_A_DQ<28> AT37 SA_DQ28 85 25 MEM_B_DQ<28> AL29 SB_DQ28
BI BI
85 25 BI MEM_A_DQ<29> AU37 SA_DQ29 VSS AW3 85 25 BI MEM_B_DQ<29> AL28 SB_DQ29 VSS AU30
85 25 MEM_A_DQ<30> AT35 SA_DQ30 85 25 MEM_B_DQ<30> AP29 SB_DQ30
BI BI
AW35 SA_RAS* AU12 MEM_A_RAS_L OUT 23 85
AP28 SB_RAS* AM18 MEM_B_RAS_L OUT 24 85
AY6 SA_WE* AU11 MEM_A_WE_L OUT 23 85
AR12 SB_WE* AK16 MEM_B_WE_L OUT 24 85
AU6 SA_CAS* AU9 MEM_A_CAS_L OUT 23 85
AP12 SB_CAS* AP16 MEM_B_CAS_L OUT 24 85
C 85 25
85 25
BI
BI
MEM_A_DQ<34>
MEM_A_DQ<35>
AV4
AU4
SA_DQ34
SA_DQ35
SA_MA0
SA_MA1
AU13
AV16
MEM_A_A<0>
MEM_A_A<1>
OUT 23 85
23 85
85 25
85 25
BI
BI
MEM_B_DQ<34>
MEM_B_DQ<35>
AL13
AL12
SB_DQ34
SB_DQ35
SB_MA0
SB_MA1
AL19
AK23
MEM_B_A<0>
MEM_B_A<1>
OUT 24 85
24 85
C
MEM_A_DQ<36> AW6 OUT MEM_B_DQ<36> AR13 OUT
85 25 BI SA_DQ36 AU16 85 25 BI SB_DQ36 AM22
SA_MA2 MEM_A_A<2> OUT 23 85 SB_MA2 MEM_B_A<2> OUT 24 85
85 25 BI MEM_A_DQ<37> AV6 SA_DQ37 85 25 BI MEM_B_DQ<37> AP13 SB_DQ37
SA_MA3 AW17 MEM_A_A<3> 23 85 SB_MA3 AM23 MEM_B_A<3> 24 85
MEM_A_DQ<38> AW4 OUT MEM_B_DQ<38> AM13 OUT
85 25 BI SA_DQ38 AU17 85 25 BI SB_DQ38 AP23
85 25 MEM_A_DQ<39> AY4 SA_DQ39 85 25 MEM_B_DQ<39> AM12 SB_DQ39
BI AW18 MEM_A_A<5> BI AL23 MEM_B_A<5>
AR1 SA_MA5 OUT 23 85
AR9 SB_MA5 OUT 24 85
SA_MA6 AV17 MEM_A_A<6> 23 85 SB_MA6 AY24 MEM_B_A<6> 24 85
MEM_A_DQ<41> AR4 OUT MEM_B_DQ<41> AP9 OUT
85 25 BI SA_DQ41 AT18 85 25 BI SB_DQ41 AV25
85 25 BI MEM_A_DQ<42> AN3 SA_DQ42 85 25 BI MEM_B_DQ<42> AR6 SB_DQ42
SA_MA8 AU18 MEM_A_A<8> 23 85 SB_MA8 AU26 MEM_B_A<8> 24 85
MEM_A_DQ<43> AN4 OUT MEM_B_DQ<43> AP6 OUT
85 25 BI SA_DQ43 AT19 85 25 BI SB_DQ43 AW25
85 25 MEM_A_DQ<44> AR2 SA_DQ44 85 25 MEM_B_DQ<44> AR10 SB_DQ44
BI AW11 MEM_A_A<10> BI AP18 MEM_B_A<10>
AR3 SA_MA10 OUT 23 85
AP10 SB_MA10 OUT 24 85
SA_MA11 AV19 MEM_A_A<11> OUT 23 85 SB_MA11 AY25 MEM_B_A<11> OUT 24 85
85 25 MEM_A_DQ<46> AN2 SA_DQ46 85 25 MEM_B_DQ<46> AR7 SB_DQ46
BI AU19 MEM_A_A<12> BI AV26 MEM_B_A<12>
AN1 SA_MA12 OUT 23 85
AP7 SB_MA12 OUT 24 85
SA_MA13 AY10 MEM_A_A<13> 23 85 SB_MA13 AR15 MEM_B_A<13> 24 85
MEM_A_DQ<48> AL1 OUT MEM_B_DQ<48> AM9 OUT
85 25 BI SA_DQ48 AT20 85 25 BI SB_DQ48 AV27
85 25 BI MEM_A_DQ<49> AL4 SA_DQ49 85 25 BI MEM_B_DQ<49> AL9 SB_DQ49
SA_MA15 AU21 MEM_A_A<15> 23 85 SB_MA15 AY28 MEM_B_A<15> 24 85
MEM_A_DQ<50> AJ3 OUT MEM_B_DQ<50> AL6 OUT
85 25 BI SA_DQ50 85 25 BI SB_DQ50
85 25 MEM_A_DQ<51> AJ4 SA_DQ51 SA_DQSN0 AE38 MEM_A_DQS_N<0> 25 85 85 25 MEM_B_DQ<51> AL7 SB_DQ51
BI BI BI AF34 MEM_B_DQS_N<0>
AL2 AJ38 AM10 SB_DQSN0 BI 25 85
85 25 BI MEM_A_DQ<52> SA_DQ52 SA_DQSN1 MEM_A_DQS_N<1> BI 25 85 85 25 BI MEM_B_DQ<52> SB_DQ52
SB_DQSN1 AK33 MEM_B_DQS_N<1> BI 25 85
85 25 BI MEM_A_DQ<53> AL3 SA_DQ53 SA_DQSN2 AN38 MEM_A_DQS_N<2> BI 25 85 85 25 BI MEM_B_DQ<53> AL10 SB_DQ53
SB_DQSN2 AN33 MEM_B_DQS_N<2> BI 25 85
85 25 BI MEM_A_DQ<54> AJ2 SA_DQ54 SA_DQSN3 AU36 MEM_A_DQS_N<3> BI 25 85 85 25 BI MEM_B_DQ<54> AM6 SB_DQ54
85 25 BI MEM_A_DQ<55> AJ1 SA_DQ55 SA_DQSN4 AW5 MEM_A_DQS_N<4> BI 25 85 85 25 BI MEM_B_DQ<55> AM7 SB_DQ55
85 25 MEM_A_DQ<56> AG1 SA_DQ56 SA_DQSN5 AP2 MEM_A_DQS_N<5> 25 85 85 25 MEM_B_DQ<56> AH6 SB_DQ56
BI BI BI AR8 MEM_B_DQS_N<5>
AG4 AK2 AH7 SB_DQSN5 BI 25 85
85 25 BI MEM_A_DQ<57> SA_DQ57 SA_DQSN6 MEM_A_DQS_N<6> BI 25 85 85 25 BI MEM_B_DQ<57> SB_DQ57
SB_DQSN6 AM8 MEM_B_DQS_N<6> BI 25 85
85 25 MEM_A_DQ<58> AE3 SA_DQ58 SA_DQSN7 AF2 MEM_A_DQS_N<7> 25 85 85 25 MEM_B_DQ<58> AE6 SB_DQ58
BI BI BI AG6 MEM_B_DQS_N<7>
AE4 AU32 AE7 SB_DQSN7 BI 25 85
85 25 BI MEM_A_DQ<59> SA_DQ59 SA_DQSN8 TP_MEM_A_DQS_N<8> 82 85 25 BI MEM_B_DQ<59> SB_DQ59
SB_DQSN8 AN26 TP_MEM_B_DQS_N<8> 82
MEM_A_DQ<60> AG2 SA_DQ60 MEM_B_DQ<60> AJ6 SB_DQ60
B
85 25
85 25
BI
BI MEM_A_DQ<61> AG3
AE2
SA_DQ61 SA_DQSP0 AE39
AJ39
MEM_A_DQS_P<0> BI 25 85
85 25
85 25
BI
BI MEM_B_DQ<61> AJ7
AF6
SB_DQ61
SB_DQS0 AF35 MEM_B_DQS_P<0> BI 25 85
B
85 25 BI MEM_A_DQ<62> SA_DQ62 SA_DQSP1 MEM_A_DQS_P<1> BI 25 85 85 25 BI MEM_B_DQ<62> SB_DQ62
SB_DQS1 AL33 MEM_B_DQS_P<1> 25 85
MEM_A_DQ<63> AE1 AN39 MEM_A_DQS_P<2> MEM_B_DQ<63> AF7 BI
85 25 BI SA_DQ63 SA_DQSP2 BI 25 85 85 25 BI SB_DQ63 AP33
SB_DQS2 MEM_B_DQS_P<2> BI 25 85
SA_DQSP3 AV36 MEM_A_DQS_P<3> BI 25 85
AW33 SA_ECC_CB0 AM26 SB_ECC_CB0 SB_DQS3 AN28 MEM_B_DQS_P<3>
NC SA_DQSP4 AV5 MEM_A_DQS_P<4> BI 25 85
NC BI 25 85
AV33 SA_ECC_CB1 AM25 SB_ECC_CB1 SB_DQS4 AN12 MEM_B_DQS_P<4>
NC SA_DQSP5 AP3 MEM_A_DQS_P<5> BI 25 85
NC BI 25 85
AU31 SA_ECC_CB2 AP25 SB_ECC_CB2 SB_DQS5 AP8 MEM_B_DQS_P<5>
NC SA_DQSP6 AK3 MEM_A_DQS_P<6> 25 85
NC BI 25 85
AV31 BI AP26 AL8 MEM_B_DQS_P<6>
NC SA_ECC_CB3 AF3 NC SB_ECC_CB3 SB_DQS6 BI 25 85
SA_DQSP7 MEM_A_DQS_P<7> BI 25 85
AT33 SA_ECC_CB4 AL26 SB_ECC_CB4 SB_DQS7 AG7 MEM_B_DQS_P<7>
NC SA_DQSP8 AV32 TP_MEM_A_DQS_P<8> 82
NC BI 25 85
AU33 SA_ECC_CB5 AL25 SB_ECC_CB5 SB_DQS8 AN25 TP_MEM_B_DQS_P<8>
NC NC 82
AT31 SA_ECC_CB6 AR26 SB_ECC_CB6
NC RSVD J40 NC
AW31 SA_ECC_CB7 NC AR25 SB_ECC_CB7 RSVD R34
NC RSVD L12 NC NC
NC RSVD T8
CPU_DIMM_VREFCA AB38 SM_VREF RSVD L10 NC
22 OUT NC RSVD T34
RSVD R33 NC
NC RSVD AT40
CPU_DIMMA_VREFDQ AB39 SA_DIMM_VREFDQ RSVD J15 NC
22 OUT NC RSVD AL20
RSVD T35 NC
CPU_DIMMB_VREFDQ AB40 SB_DIMM_VREFDQ NC RSVD AB36
22 OUT
RSVD J17 NC
NC RSVD AB33
RSVD M38 NC
P33 RSVD NC RSVD AC8
NC NC
INTEL’S HASWELL DT EDS SAYS THAT ALL RSVD AND RSVD_NCTF SHOULD BE NC’D
PAGE TITLE
CPU DDR3 Interfaces

DRAWING NUMBER SIZE

REVISION
R
13.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
=PPCPUVCC_S0_CPU 6 8 10 48 61 80
NC
AW12 RSVD U0500 C28
NC
AW23 RSVD HASWELL C29
AW24 RSVD LGA C30
NC
AW27 RSVD SYM 5 OF 11 C31
NC
80 10 6 =PP1V5_S0_CPU_MEM C32
AJ12 C33
D
AJ13
AJ15
C34
C35
D
AJ17 D25
AJ20 D27
AJ21 D29
80 61 48 10 8 6 =PPCPUVCC_S0_CPU OMIT_TABLE
AJ24 D31
AJ25 D33 M33 U0500
AJ28 D35 M29 HASWELL
AJ29 E24 M27 LGA
AJ9 E25 M25 SYM 6 OF 11
AT17 E26 M23 POWER
VDDQ
AT22 E27 M21
AU15 E28 M19
AU20 E29 M17
AU24 E30 M15
AV10 E31 M13
AV11 E32 M8
AV13 E33 L34
AV18 E34 L33
AV23 E35 L32
AV8 F23 L31 VCC
AW16 F25 L30
AY12 F27 L29
AY14 F29 L28
AY9 F31 L27
F33 L26
F35 L25
C G22
G23
L24
A28
C
G24 A27
80 61 48 10 8 6 =PPCPUVCC_S0_CPU G25 A26
G26 A25
AU39 RSVD G27 A24
NC
1 L22 VCC G28
R0800
PLACE_NEAR=U0500.E40:50.8mm 100 L23 VCC G29
5%
AU27 RSVD G30
PLACE_SIDE=BOTTOM
1/16W
MF-LF
NC
NOTE: Aliases not used on CPU supply outputs AU1 RSVD G31
402
2 NC VCC
to avoid any extraneous connections. G32
93 61 CPU_VCCSENSE_P E40 VCC_SENSE
OUT G33
PPVCCIO_S0_CPU AK20 RSVD
61 18 6
MIN_LINE_WIDTH=0.4 mm
NC G34
Max load: 300mA MIN_NECK_WIDTH=0.2 mm L40 VCCIO_OUT
VOLTAGE=1.05V G35
PPVCOMP_S0_CPU AV24 RSVD
5
NC H23
P4
R0801 1 1
R0804 Max load: 300mA MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
VCOMP_OUT H25
75 110 AV2 RSVD
1% 1%
NC H27
AY18 RSVD
1/16W
MF-LF
1/16W
MF-LF
NC H29
AV29 RSVD
402
2 R0802 2
402
NC H31
43 AV20 RSVD
93 61 IN CPU_VIDALERT_L 1 2 NC H33
5% H35
1/16W 93 CPU_VIDALERT_R_L B37 VIDALERT*
MF-LF J21
R0803 402 93 CPU_VIDSCLK_R C38 VIDSCLK
0 J22
93 61 OUT CPU_VIDSCLK 1 2 93 CPU_VIDSOUT_R C37 VIDSOUT
J23
5%
1/16W R0804.2: PLACE_NEAR=U0500.C37:12.7mm J24
MF-LF AY5 VSS
402 R0805 R0802.2: PLACE_NEAR=U0500.B37:12.7mm J25
0 CPU_PWR_DEBUG N40 PWR_DEBUG
B 93 61 BI CPU_VIDSOUT 1
5%
2 R0801.2: PLACE_NEAR=R0802.1:25.4mm
18 IN
AY7
AW2
VSS
J26
J27
B
1/16W
NC RSVD J28
MF-LF
402 AV1 RSVD
NC J29
A4 RSVD
NC J30
B3 RSVD
NC J31
B4 VSS J32
AY26 VSS J33
AW34 VSS J34
AW32 VSS J35
AY17 VSS K19
AW36 VSS K21
AY27 VSS K23
AW26 VSS K25
AY30 VSS K27
AW30 VSS K29
AY23 VSS K31
K33
A29
K35
A30
L15
B25
L16
B27
L17
B29
L18
B31
L19
B33 VCC
L20
B35
L21
C26
A C27 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
C24 FC_Y7 Y7 TP_CPU_VCCST_PWRGD PAGE TITLE
C25 FC_K9 K9 TP_CPU_VCCST CPU Power
DRAWING NUMBER SIZE
Y7,K9 FOR FUTURE CPU COMPATIBILITY Apple Inc. 051-9889 D

REVISION
NC FOR NOW BUT NEEDED FOR 2014 CPUS R
13.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
OMIT_TABLE OMIT_TABLE B32 VSS U0500 VSS K24
A11 U0500 AH1 AL40 U0500 AR24 B34 VSS HASWELL VSS K26
A13 HASWELL AH2 AM1 HASWELL AR16 B36 VSS LGA VSS K28
A15 LGA AH3 AM11 LGA AR30 C3 VSS SYM 9 OF 11 VSS K30
A17 SYM 7 OF 11 AH5 AM14 SYM 8 OF 11 AR31 C4 VSS VSS K32
A23 GROUND AH33 AM15 GROUND AR32 C6 K34
VSS VSS
D A5
A7
AH8
AH36
AM19
AM2
AR33
AR34
C12
C14
VSS VSS K36
K40
D
VSS VSS
AA3 AH4 AL36 AR35 C16 VSS VSS L3
AA33 AJ11 AM24 AR36 C18 VSS VSS L6
AA8 AJ22 AL37 AR27 D2 VSS VSS L13
AB5 AJ26 AL38 AT11 D5 VSS VSS L14
AB34 AJ27 AL39 AT12 D6 VSS VSS L35
AB37 AJ30 AM34 AT13 D7 VSS VSS L36
AB6 AJ31 AM35 AT14 D9 VSS VSS L38
AC33 AJ23 AM36 AT15 D11 VSS VSS M1
AC36 AJ34 AN10 AR5 D17 VSS VSS M6
AB7 AJ35 AN11 AT24 D23 VSS VSS M7
AC3 AJ40 AN14 AT1 D24 VSS VSS M9
AC40 AJ37 AN16 AT27 D30 VSS VSS M16
AC38 AK1 AN27 AT28 D32 VSS VSS M18
AD1 AK10 AN30 AT10 D34 VSS VSS M20
AD2 AJ8 AN18 AT34 D36 VSS VSS M22
AD3 VSS VSS AK18 AN36 AT36 D37 VSS VSS M24
E3 M26
C AC6
AC7
AK19
AK24
AN37
AN40
AT38
AT39 E6
VSS
VSS
VSS
VSS M28 C
AD33 AK25 AN19 AT4 E7 VSS VSS M30
AE33 AK30 AN24 VSS VSS AU2 E23 VSS VSS N1
AD7 AK12 AP1 AU25 E36 VSS VSS N2
AE36 AK13 AP11 AU3 E38 VSS VSS N3
AE37 AK14 AP14 AW7 F1 VSS VSS N4
AE40 AK36 AP15 AU34 F4 VSS VSS N6
AF33 AK5 AP24 AU38 F7 VSS VSS N7
AE5 AK6 AP27 AU5 F12 VSS VSS N8
AF36 AK7 AP30 AU7 F14 VSS VSS N33
AF4 AK8 AP36 AV21 F16 VSS VSS N34
AF5 AK9 AP4 AV28 F19 VSS VSS N39
AF8 AL11 AN8 AV3 F21 VSS VSS P2
AE8 AL14 AP5 AV30 F22 VSS VSS P5
AF1 AL17 AR11 AV34 F24 VSS VSS P7
AG33 AL21 AR14 AV38 F26 VSS VSS P34
AG36 AL22 AN9 AV7 F28 VSS VSS P35
AG37 AL24 AR17 AT29 F30 VSS VSS P38
AG39 AL5 AR20 AT32 F36 VSS VSS R3
B AG8
AG40
AK4 AR21
AR22
U34
U35
G3
G6
VSS VSS R5
R6
B
VSS VSS
AR23 U36 G7 VSS VSS R7
H39 U37 G9 VSS VSS R8
J3 V3 G11 VSS VSS R35
J18 V34 G16 VSS VSS T1
J19 V40 G17 VSS VSS T2
J20 W1 G21 VSS VSS T4
K1 W33 H1 VSS VSS T7
K4 W35 H4 VSS VSS T33 CPU_VCCSENSE_N 61 93
OUT
K7 W37 H7 VSS VSS T36
K10 Y4 H8 VSS VSS T37
K14 Y5 H9 T38 PLACE_NEAR=U0500.F40:50.8mm 1
VSS VSS R0960
K15 Y6 H10 T39 PLACE_SIDE=BOTTOM
VSS VSS 100
K16 Y33 H11 U2 5%
VSS VSS 1/16W
K17 K20 H13 U4 MF-LF
VSS VSS 2
402
K18 K22 H17 VSS VSS U7
H18 VSS VSS U33
H20 VSS
H21
A H22
VSS
VSS
VSS_NCTF
VSS_NCTF
AU40
AV39 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
H24 VSS PAGE TITLE
VSS_NCTF AW38
H26 VSS
VSS_NCTF AY3 CPU Ground
H28 VSS DRAWING NUMBER SIZE
VSS_NCTF B38
H30 VSS
VSS_NCTF B39 Apple Inc. 051-9889 D
H32 VSS REVISION
VSS_NCTF C40
H34 VSS
R
13.0.0
VSS_NCTF D40
H36 VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH
VSS_SENSE F40 THE INFORMATION CONTAINED HEREIN IS THE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING
Intel Recommendation:22x 22UF 0805,topside (18 inside cavity, 4 north of processor),8x 470uF bulk caps(5 stuffed,3 no-stuffed)
Apple Implementation:28x 22UF 0603 per Harold
18x 10UF 0603 placed inside socket cavity
Layout Note: These caps should be placed symmetrically on Top and Bottom sides.
BULK CAPS ON CPU VREG PAGE 71
D 80 61 48 8 6 =PPCPUVCC_S0_CPU
D
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1000 1 C1001 1 C1002 1 C1003 1 C1004 1 C1005 1 C1006 1 C1007 1 C1008 1 C1009 1 C1010
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1011 1 C1012 1 C1013 1 C1014 1 C1015 1 C1016 1 C1017 1 C1018 1 C1019 1 C1020 1 C1021
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1 C1022 1 C1023 1 C1024 1 C1025 1 C1026 1 C1027
22UF 22UF 22UF 22UF 22UF 22UF ADDED CRITICAL PROPERTY TO CPU CORE DECOUPLING
20% 20% 20% 20% 20% 20% DUE TO ACOUSTICS CONCERNS
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2 2 X5R-CERM2
C 0603 0603 0603 0603 0603 0603

C
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1 C1030 1 C1031 1 C1032 1 C1033 1 C1034 1 C1035 1 C1036 1 C1037 1 C1038
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1 C1039 1 C1040 1 C1041 1 C1042 1 C1043 1 C1044 1 C1045 1 C1046 1 C1047
20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
603 603 603 603 603 603 603 603 603
B B
Memory (CPU VCCDDR) DECOUPLING
Intel Recommendation:9x 22UF 0805 near CPU power pins
Apple Implementation:9x 22UF 0603 per Harold
Layout Note: These caps should be placed symmetrically on Top and Bottom sides.
80 8 6 =PP1V5_S0_CPU_MEM
1 C1050 1 C1051 1 C1052 1 C1053 1 C1054 1 C1055 1 C1056 1 C1057 1 C1058

20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2
6.3V
2 X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2
0603 0603 0603 0603 0603 0603 0603 0603 0603
NOSTUFF NOSTUFF NOSTUFF

1 C1060 1 C1061 1 C1062
22UF 22UF 22UF
20% 20% 20%
2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2 2 6.3V
X5R-CERM2
0603 0603 0603
PAGE TITLE
CPU DECOUPLING
DRAWING NUMBER SIZE
NOSTUFF Apple Inc. 051-9889 D

CRITICAL REVISION
1
C1059
R
13.0.0
330UF-0.0045OHM NOTICE OF PROPRIETARY PROPERTY: BRANCH
20%
2 2V THE INFORMATION CONTAINED HEREIN IS THE
POLY PROPRIETARY PROPERTY OF APPLE INC.
CASE-D2-SM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
SATA Port assignments:
89 19 IN PCH_CLK32K_RTCX1 AN40 RTCX1 U1100 SATA_RXN0 B28 SATA_HDD_D2R_N IN 33 88
89 19 PCH_CLK32K_RTCX2 AN39 RTCX2 LYNX SATA_RXP0 A28 SATA_HDD_D2R_P 33 88

OUT IN
FCBGA F31 PRIMARY HDD
SATA_TXN0 SATA_HDD_R2D_C_N OUT 33 88
DESKTOP H31
AR39 SRTCRST* SATA_TXP0 SATA_HDD_R2D_C_P OUT 33 88
11 PCH_SRTCRST_L SYM 1 OF 11
SATA_RXN1 D30
11 PCH_INTRUDER_L AR41 INTRUDER* NC
SATA_RXP1 C30
NC
RTC
PCH_INTVRMEN_L AV36 INTVRMEN SATA_TXN1 B34
11
NC
SATA_TXP1 C34
45 19 11 RTC_RESET_L AR38 RTCRST* NC
SATA_RXN2 A31
NC
D R1110 33 AV23 HDA_BCLK SATA_RXP2 B31
NC D
SATA
89 52 OUT HDA_BIT_CLK 1 2 89 HDA_BIT_CLK_R
SATA_TXN2 B35
5% 1/20W MF 201
PLACE_NEAR=U1100.AV23:5MM NC
SATA_TXP2 D35
89 52 OUT HDA_SYNC R1111 33 1 2 89 HDA_SYNC_R AV24 HDA_SYNC (IPD-boot) NC
5% 1/20W MF 201
SATA_RXN3 B32
PLACE_NEAR=U1100.AV24:5MM
NC
PCH_SPKR R32 SPKR SATA_RXP3 C32
11 (IPD-PLTRST#)
NC
SATA_TXN3 G33
NC
AZALIA
HDA_RST_L R1112 33 1 2 89 HDA_RST_R_L AU24 HDA_RST* SATA_TXP3 F33
89 52 OUT
5% 1/20W MF 201 NC
PLACE_NEAR=U1100.AU24:7MM
SATA_RXN4/PERN1 A26 SSD_D2R_N<0>
89 52 HDA_SDIN0 AT26 HDA_SDI0 (IPD)
IN 33 88
IN B26 SSD_D2R_P<0>
AV22 SATA_RXP4/PERP1 IN 33 88
82 TP_HDA_SDIN1 HDA_SDI1 (IPD) SSD
SATA_TXN4/PETN1 L28 SSD_R2D_N<0> =PP1V5_S0_PCH_SATA
82 TP_HDA_SDIN2 AT22 HDA_SDI2 (IPD)
OUT 33 88 80
SATA_TXP4/PETP1 K28 SSD_R2D_P<0>

82 TP_HDA_SDIN3 AW23 HDA_SDI3 (IPD)
OUT 33 88
SATA_RXN5/PERN2 C27 SSD_D2R_N<1> 33 88

IN
89 52 HDA_SDOUT R1113 33 1 2 89 19 HDA_SDOUT_R AU22 HDA_SDO (IPD-boot) SATA_RXP5/PERP2 B27 SSD_D2R_P<1> 33 88
R1130 1
OUT IN
5% 1/20W MF 201
G28 7.5K
PLACE_NEAR=U1100.AU22:6MM SATA_TXN5/PETN2 SSD_R2D_N<1> OUT 33 88 1%
(IPD-DOCKEN#?)
AV26 DOCKEN*/GPIO33 1/20W
=PP3V3_G3_PCH 12 80 58 41 11 DP_TBT_SEL SATA_TXP5/PETP2 F28 SSD_R2D_P<1> 33 88 MF
OUT OUT
AN22 HDA_DOCK_RST*/GPIO13 201
90 35 11 IN ENET_MEDIA_SENSE 2
PLACE_NEAR=U1100.D33:2.54MM
SATA_RCOMP D33 88 PCH_SATA_RCOMP
R1102 1
1
R1103 88 18 IN XDP_PCH_TCK Y40 JTAG_TCK (IPD)
1
20K 20K SATALED* J39 PCH_SATALED_L 11 33
R1100 1
R1101 5% 5% W40 JTAG_TMS
390K 1/20W 1/20W 88 18 IN XDP_PCH_TMS (IPU)
1M MF MF
SATA0GP/GPIO21 M37
JTAG
5%
5% 201 201 W39 JTAG_TDI DP_AUXIO_EN OUT 11 18 29 30
1/20W 1/20W 2 2 88 18 IN XDP_PCH_TDI (IPU)
MF MF SATA1GP/GPIO19 J40 SATARDRVR_EN OUT 11 18
201
2 2 201
PCH_SRTCRST_L 11 Y38 JTAG_TDO (IPU-PLTRST#)
88 18 OUT XDP_PCH_TDO
PCH_INTRUDER_L
SATA_IREF A33
11
PCH_INTVRMEN_L 11 AM34
NC TP25
RTC_RESET_L 11 19 45
AH24 TP22
C C1102 1 1
C1103
NC
NC
W37 TP20
TP9 K34
TP8 K33
NC
NC
C
1UF 1UF
10% 10%
10V 10V
X5R 2 2 X5R OMIT_TABLE
402 402
87 33 OUT PCIE_CLK100M_SSD_N AE10 CLKOUT_PCIE_N0
U1100 CLKOUT_PEG_A_N AA3 NC
87 33 OUT PCIE_CLK100M_SSD_P AE11 CLKOUT_PCIE_P0
LYNX CLKOUT_PEG_A_P AA2 NC
W34 PCIECLKRQ0*/GPIO73 FCBGA
33 11 IN SSD_CLKREQ_L DESKTOP
SYM 2 OF 11
87 35 OUT PCIE_CLK100M_ENET_N AC6 CLKOUT_PCIE_N1 CLKOUT_PEG_B_N AE6 NC
87 35 OUT PCIE_CLK100M_ENET_P AC7 CLKOUT_PCIE_P1 CLKOUT_PEG_B_P AE7 NC
35 18 11 ENET_CLKREQ_L P39 PCIECLKRQ1*/GPIO18
IN
87 32 OUT PCIE_CLK100M_AP_N AC11 CLKOUT_PCIE_N2 CLKOUT_DMI_N R2 DMI_CLK100M_CPU_N OUT 6 87
87 32 OUT PCIE_CLK100M_AP_P AC10 CLKOUT_PCIE_P2 CLKOUT_DMI_P T2 DMI_CLK100M_CPU_P OUT 6 87
AP_CLKREQ_L P37 PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_DP_N T3
32 18 11 IN CPU_CLK135M_DPLLSS_N OUT 6 87
W11 CLKOUT_PCIE_N3 CLKOUT_DP_P T5 CPU_CLK135M_DPLLSS_P OUT 6 87

87 26 OUT PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P W10 CLKOUT_PCIE_P3
CLKOUT_DPNS_N W2
87 26 OUT CPU_CLK135M_DPLLREF_N OUT 6 87
NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks. 11 PCH_CLKRQ3_L_GPIO25 AA39 PCIECLKRQ3*/GPIO25 CLKOUT_DPNS_P U2 CPU_CLK135M_DPLLREF_P OUT 6 87
CLOCKS
PEG-attached (CPU) PCIe devices must use one set, Unused clock terminations for FCIM Mode
while PCH-attached PCIe devices use the other set. 82 TP_PCIE_CLK100M_PE4N Y4 CLKOUT_PCIE_N4 CLKIN_DMI_N G22 PCIE_CLK100M_PCHN R1196 10K 1 2
5% 1/20W MF 201
If 2 or less devices are attached to PEG the 82 TP_PCIE_CLK100M_PE4P Y2 CLKOUT_PCIE_P4 CLKIN_DMI_P F22 PCIE_CLK100M_PCHP R1195 10K 1 2
5% 1/20W MF 201
CLKOUT_PEG outputs can be used for those devices. W35 PCIECLKRQ4*/GPIO26
28 11 IN TBT_CLKREQ_L
CLKIN_GND_N G16 PCH_CLKIN_GNDN R1171 10K 1 2
B 82 TP_PCIE_CLK100M_PE5N W7 CLKOUT_PCIE_N5 CLKIN_GND_P F16 PCH_CLKIN_GNDP R1170 10K 1 2

5%
5%
1/20W
1/20W
MF
MF
201
201
B
82 TP_PCIE_CLK100M_PE5P W6 CLKOUT_PCIE_P5
CLKIN_DOT96_N AP11 PCH_CLK96M_DOTN R1192 10K 1 2
5% 1/20W MF 201
11 PCH_CLKRQ5_L_GPIO44 AA36 PCIECLKRQ5*/GPIO44 CLKIN_DOT96_P AM11 PCH_CLK96M_DOTP R1191 10K 1 2
(IPU-RSMRST#) 5% 1/20W MF 201
86 72 OUT PEG_CLK100M_N AA7 CLKOUT_PCIE_N6 CLKIN_SATA_N H35 PCH_CLK100M_SATAN R1194 10K 1 2

5% 1/20W MF 201
86 72 OUT PEG_CLK100M_P AA6 CLKOUT_PCIE_P6 CLKIN_SATA_P H36 PCH_CLK100M_SATAP R1193 10K 1 2
5% 1/20W MF 201
72 11 PEG_CLKREQ_L W32 PCIECLKRQ6*/GPIO45

REFCLK14IN AR7
IN PCH_CLK14P3M_REFCLK R1197 10K 1 2
5% 1/20W MF 201
82 TP_PCIE_CLK100M_PE7N R6 CLKOUT_PCIE_N7 CLKIN_33MHZLOOPBACK AM22 PCH_CLK33M_PCIIN IN 19 89
82 TP_PCIE_CLK100M_PE7P R7 CLKOUT_PCIE_P7 R1172

340
AA40 PCIECLKRQ7*/GPIO46 XTAL25_IN N7 89 SYSCLK_CLK25M_SB_R 1 2 SYSCLK_CLK25M_SB IN 19 89
11 PCH_CLKRQ7_L_GPIO46
(IPU-RSMRST#) XTAL25_OUT N6 NC PLACE_NEAR=U1100.N7:5MM 1%
1/16W
1
=PP3V3_S5_PCH_VCCSUS_GPIO 12 13 14 15 17 80
R1173 MF-LF
402
(IPD-PWROK) CLKOUTFLEX0/GPIO64 AV8 TP_PCH_GPIO64_CLKOUTFLEX0 82 1K
=PP3V3_S0_PCH_VCC3_3_GPIO 12 13 14 15 17 80 1%
88 82 OUT ITPXDP_CLK100M_N U6 CLKOUT_ITPXDP_N (IPD-PWROK) CLKOUTFLEX1/GPIO65 AT9 TP_PCH_GPIO65_CLKOUTFLEX1 82 1/20W
MF
88 82 ITPXDP_CLK100M_P U7 CLKOUT_ITPXDP_P (IPD-PWROK) CLKOUTFLEX2/GPIO66 AV9 TP_PCH_GPIO66_CLKOUTFLEX2 82 201
R1177 4.7K 1 2 PCH_SPKR OUT 2
11
5% 1/20W MF 201 (IPD-PWROK) CLKOUTFLEX3/GPIO67 AU8 TP_PCH_GPIO67_CLKOUTFLEX3 82
R1176 10K 1 2 DP_TBT_SEL 11 41 58
5% 1/20W MF 201 =PP1V5_S0_PCH_CLK 19 80
R1178 10K 1 2 PCH_SATALED_L 11 33
5% 1/20W MF 201 ICLK_IREF N10
R1134 10K 1 2 DP_AUXIO_EN 11 18 29 30 89 19 OUT LPC_CLK33M_SMC_R AV5 CLKOUT_33MHZ0 (IPD-PWROK)
5% 1/20W MF 201
R1133 10K 1 2 SATARDRVR_EN 11 18 89 19 OUT LPC_CLK33M_LPCPLUS_R AV7 CLKOUT_33MHZ1 (IPD-PWROK) TP19 U11 NC
5% 1/20W MF 201
TP_PCI_CLK33M_OUT2 AU2 CLKOUT_33MHZ2 TP18 U10
R1143 10K 1 2 SSD_CLKREQ_L
82 (IPD-PWROK)
NC
5% 1/20W MF 201
11 33
82 TP_PCI_CLK33M_OUT3 AN9 CLKOUT_33MHZ3 (IPD-PWROK)
R1190 =PP1V5_S0_PCH_VCCVRM_BIAS 17
R1142 10K 1 2 ENET_CLKREQ_L 7.5K
DIFFCLK_BIASREF R11
11 18 35
5% 1/20W MF 201 89 19 OUT PCH_CLK33M_PCIOUT AU5 CLKOUT_33MHZ4 (IPD-PWROK) PCH_DIFFCLK_BIASREF 2 1
R1169 10K
A R1144 10K
1
1
2
2
5%
5%
1/20W
1/20W
MF
MF
201
201
AP_CLKREQ_L
PCH_CLKRQ3_L_GPIO25
11 18 32
11
PLACE_NEAR=U1100.R11:2.54MM 1%
1/20W
MF
R1145 10K 1 2 TBT_CLKREQ_L 11 28 201 PAGE TITLE
R1147 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH_CLKRQ5_L_GPIO44 11 PCH RTC/HDA/JTAG/SATA/CLK
R1114 10K 2 1 PEG_CLKREQ_L 11 72 DRAWING NUMBER SIZE
R1115 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH_CLKRQ7_L_GPIO46 11
REVISION
R
13.0.0
R1179 10K 1 2 ENET_MEDIA_SENSE 11 35 90 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
87 5 IN DMI_N2S_N<0> L24 DMI_RXN0 U1100 FDI_RXN0 N1 NC

DMI_N2S_N<1> G24 DMI_RXN1 LYNX FDI_RXN1 P2
87 5 IN NC
87 5 DMI_N2S_N<2> F26 DMI_RXN2 FCBGA
FDI_RXP0 N2
IN
K26 DESKTOP NC
87 5 DMI_N2S_N<3> DMI_RXN3
IN SYM 4 OF 11 FDI_RXP1 P3 NC
87 5 DMI_N2S_P<0> K24 DMI_RXP0
IN
87 5 DMI_N2S_P<1> H24 DMI_RXP1
IN
87 5 DMI_N2S_P<2> G26 DMI_RXP2
IN
DMI_N2S_P<3> L26 DMI_RXP3 TP16 R4
87 5 IN NC
TP5 K5
C20 P5
NC
DMI_S2N_N<0> DMI_TXN0 TP15
D
87 5
87 5
OUT
OUT DMI_S2N_N<1> D21
B22
DMI_TXN1 TP10 L5
NC
NC D
87 5 OUT DMI_S2N_N<2> DMI_TXN2
DMI
FDI
87 5 DMI_S2N_N<3> A24 DMI_TXN3
OUT
87 5 DMI_S2N_P<0> B20 DMI_TXP0 FDI_CSYNC L2 FDI_CSYNC 5 88

OUT OUT
87 5 DMI_S2N_P<1> B21 DMI_TXP1 FDI_INT L3 FDI_INT 5 88
OUT OUT
87 5 DMI_S2N_P<2> C22 DMI_TXP2
=PP1V5_S0_PCH_RCOMP OUT =PP1V5_S0_PCH_RCOMP
80 13 12
87 5 DMI_S2N_P<3> B24 DMI_TXP3
12 13 80
OUT
A19 DMI_IREF FDI_IREF N11

R1200 1 R1210 1
7.5K L22 TP12 7.5K =PP3V3_G3_PCH 11 80
1%
NC TP17 R12 NC 1%
1/20W K22 TP7 TP13 N12
1/20W
MF
NC NC MF
1
201
2
PLACE_NEAR=U1100.K2:12.7MM
201
2 R1215
PLACE_NEAR=U1100.B19:12.7MM B19 DMI_RCOMP 390K
87 PCH_DMI_RCOMP FDI_RCOMP K2 88 PCH_FDI_RCOMP 5%
1/20W
MF
2 201
PCH_SUSACK_L AJ37 SUSACK* (IPU)
DSWVRMEN AM41 PCH_DSWVRMEN
SYSTEM POWER
MANAGEMENT
44 19 PM_SYSRST_L N36 SYS_RESET*
IN
DPWROK AV38 PM_RSMRST_PCH_L IN 12 18 71
PM_PCH_SYS_PWROK W31 SYS_PWROK

WAKE* AK34
71 45 18 IN
1
PCIE_WAKE_L IN 12 32 36
1
R1286 PM_PCH_PWROK AT40 PWROK (IPD-DeepSx) R1209
GPIO32 N32
71 39 20 18 IN
0 PCH_GPIO32 BI 12 10K
5% AA32 APWROK 5%
1/20W PM_PCH_APWROK 1/20W
SUS_STAT*/GPIO61 AD37
71 IN
MF LPC_PWRDWN_L OUT 20 44 46 MF
0201
2 PM_MEM_PWRGD AE38 DRAMPWROK 2 201
SUSCLK/GPIO62 W36
21 6 OUT
(OD) PM_CLK32K_SUSCLK_R OUT 45 89
AM40 RSMRST* (IPU-RSMRST#)
71 18 12 IN PM_RSMRST_PCH_L AA35
SLP_S5*/GPIO63 PM_SLP_S5_L 12 32 44 70
C
OUT
C 80 17 15 14 13 12 11 =PP3V3_S5_PCH_VCCSUS_GPIO
PCH_SUSWARN_L AG41 SUSWARN*/SUSPWRNACK/GPIO30
SLP_S4* AT35 PM_SLP_S4_L OUT 12 44 70
PM_PWRBTN_L AK41
R1205 1 44 18 12 IN PWRBTN* (IPU)
SLP_S3* AK40 PM_SLP_S3_L 12 21 36 44 45 70 71
OUT
10K AM36
5% 12 IN PCH_GPIO31 ACPRESENT/GPIO31 AN37
1/20W (IPD-DeepSx) SLP_A* TP_PM_SLP_A_L
MF AJ40
201 12 IN PCH_GPIO72 GPIO72 AK38
2
SLP_SUS* PM_SLP_SUS_L OUT 12
PCH_RI_L AE36 RI*

PMSYNCH F40 PM_SYNC 6 86
OUT
AC35 TP21
NC SLP_LAN* AU36 TP_PCH_SLP_LAN_L
TP_PCH_SLP_WLAN_L AL39 SLP_WLAN*/GPIO29
OMIT_TABLE
NC
AC3 VGA_BLUE U1100
NC
AE2 VGA_GREEN LYNX
AC2 VGA_RED FCBGA
NC DESKTOP AM1
SYM 5 OF 11 DDPB_CTRLCLK NC
AL2 VGA_DDC_CLK DDPB_CTRLDATA AJ5
VGA DAC Disabled per SB NC (IPD-PLTRST#)
NC
AL3 VGA_DDC_DATA
NC DDPC_CTRLCLK AN3
DG v1.0 (Table 11-11). NC
AH3 DDPC_CTRLDATA AM2 NC
NC VGA_HSYNC (IPD-PLTRST#)
AH2 VGA_VSYNC DDPD_CTRLCLK AN4
NC NC
DDPD_CTRLDATA AN2
CRT
(IPD-PLTRST#)
NC
DISPLAY
AF5 DAC_IREF
AG4 VGA_IRTN DDPB_AUXN AK6 NC
DDPC_AUXN AG7 NC
B NC
AP2 EDP_BKLTCTL DDPD_AUXN AG11 NC B
EDP
AT2 EDP_BKLTEN DDPB_AUXP AK8 NC
NC DDPC_AUXP AG6 NC
AP1 EDP_VDDEN DDPD_AUXP AG10
NC NC
80 17 15 14 13 12 11 =PP3V3_S0_PCH_VCC3_3_GPIO
DDPB_HPD AJ2 NC
R1260 10K 1 2 PCI_INTA_L AU29 PIRQA*
5% 1/20W MF 201 DDPC_HPD AH5 NC
=PP3V3_S5_PCH_VCCSUS_GPIO R1261 10K 1 2 PCI_INTB_L AU27 PIRQB*
DDPD_HPD AJ4
11 12 13 14 15 17 80
R1262 10K 1 2
5% 1/20W MF 201
PCI_INTC_L AW28 PIRQC* NC
5% 1/20W MF 201
=PP3V3_S0_PCH_VCC3_3_GPIO 11 12 13 14 15 17 80 R1263 10K 1 2 PCI_INTD_L AV27 PIRQD*
5% 1/20W MF 201 AR30
PCI
PIRQE*/GPIO2 SDCONN_OC_L IN 12 37
20 12 ENET_LOW_PWR_PCH AH26 GPIO50 PIRQF*/GPIO3 AV29 AUD_IP_PERIPHERAL_DET 12 58

R1226 10K 2 1 PCH_GPIO31 OUT IN
12 AV28
5% 1/20W MF 201 20 12 OUT AUD_IPHS_SWITCH_EN_PCH AJ26 GPIO52 PIRQG*/GPIO4 TBT_PWR_REQ_L IN 12 26
R1240 10K 2 1 PCH_GPIO72 12 32 12 BT_PWR_RST_L AW33 GPIO54 PIRQH*/GPIO5 AT27 AUD_I2C_INT_L 12 56

OUT IN
5% 1/20W MF 201
R1291 10K 1 2 PCH_GPIO32 12
AU31 GPIO51 AA31
5% 1/20W MF 201 TP_PCH_STRP_BBS1 (IPU)PME* TP_PCI_PME_L
R1216 10K 1 2 ENET_LOW_PWR_PCH 12 20 TP_PCH_STRP_ESI_L AV31 GPIO53
5% 1/20W MF 201
R1217 100K 1 2 AUD_IPHS_SWITCH_EN_PCH 12 20 45 OUT PCH_STRP_TOPBLK_SWP_L R30 GPIO55 PLTRST* AA37 PLT_RESET_L OUT 20
5% 1/20W MF 201 (IPU-PWROK&PCIRST#)
R1218 10K 1 2 BT_PWR_RST_L 12 32
5% 1/20W MF 201
R1230 10K 1 2 SDCONN_OC_L 12 37
5% 1/20W MF 201
NOSTUFF Redundant to pull-up on audio page

R1214 100K 1 2 AUD_IP_PERIPHERAL_DET 12 58
5% 1/20W MF 201
R1231 10K 1 2 TBT_PWR_REQ_L 12 26
5% 1/20W MF 201
NOSTUFF Redundant to pull-up on audio page

R1233 10K
A R1225 1K
1
1
2
2
5% 1/20W MF
AUD_I2C_INT_L
201
12 56
12 32 36
5% 1/20W MF 201
PAGE TITLE
PCIE_WAKE_L
MAKE_BASE=TRUE
=TBT_WAKE_L 26 PCH DMI/FDI/PM/GFX/PCI
DRAWING NUMBER SIZE

R1227 3.0K 1 2 PM_PWRBTN_L 12 18 44 REVISION
5% 1/20W MF 201 R
13.0.0
R1224 100K 2 1 PM_SLP_S3_L
12 21 36 44 45 70 71
5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE
R1221 100K 2 1 PM_SLP_S4_L 12 44 70 PROPRIETARY PROPERTY OF APPLE INC.
5% 1/20W MF 201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
R1222 100K 2 1 PM_SLP_S5_L 12 32 44 70
R1223 100K 2 1
5% 1/20W MF 201
PM_SLP_SUS_L
12 OF 123
12 II NOT TO REPRODUCE OR COPY IT
5% 1/20W MF 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE USB Port Assignments:
U1100 USB2N0 AV10 USB_EXTA_0_N BI 42 90

Ext A (LS/FS/HS)
LYNX USB2P0 AU10 USB_EXTA_0_P BI 42 90
FCBGA
DESKTOP USB2N1 AV11 USB_EXTC_1_N BI 43 90
Ext C (LS/FS/HS)
SYM 9 OF 11 USB2P1 AW11 USB_EXTC_1_P BI 43 90
L14 PERN1_USB3RN3 USB2N2 AN14

NC NC
K14 PERP1_USB3RP3 USB2P2 AP14
NC NC
B12 PETN1_USB3TN3 USB2N3 AJ16
NC NC
B11 PETP1_USB3TP3 USB2P3 AK16
NC NC
D NC
F14 PERN2_USB3RN4
USB2N4 AU15
USB2P4 AV15
NC
NC
D
G14 PERP2_USB3RP4
NC USB2N5 AU12 NC
D11 PETN2_USB3TN4 USB2P5 AT12
NC NC
C11 PETP2_USB3TP4
NC USB2N6 AV14 NC
USB2P6 AW14 NC
87 32 PCIE_AP_D2R_N F11 PERN3
IN
H11 PERP3 USB2N7 AU17 NC
87 32 PCIE_AP_D2R_P
USB2P7 AT17
IN
AirPort NC
87 32 PCIE_AP_R2D_C_N B9 PETN3
OUT
A9 PETP3 USB2N8 AW16 USB_EXTB_8_N BI 42 90
87 32 OUT PCIE_AP_R2D_C_P Ext B (LS/FS/HS)
USB2P8 AV16 USB_EXTB_8_P BI 42 90
J11 PERN4 USB2N9 AN16 USB_EXTD_9_N BI 43 90

PCIE_ENET_D2R_N Ext D (LS/FS/HS)
USB2P9 AP16
87 35 IN
L11 PERP4 USB_EXTD_9_P BI 43 90
87 35 IN PCIE_ENET_D2R_P
ENET
B8 PETN4 USB2N10 AJ18 USB_CAMERA_N BI 38 90
87 35 PCIE_ENET_R2D_C_N CAMERA
OUT
C8 PETP4 USB2P10 AK18 USB_CAMERA_P BI 38 90
87 35 OUT PCIE_ENET_R2D_C_P
USB2N11 AP18 USB_BT_N BI 32 90
BT
G9 PERN5 USB2P11 AN18 USB_BT_P BI 32 90
87 26 IN PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<0> F9 PERP5 USB2N12 AW18
87 26 IN NC
B7 PETN5 USB2P12 AV18 NC
87 26 OUT PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_P<0> A7 PETP5 USB2N13 AP20
87 26 OUT NC
USB2P13 AN20 NC
(IPD)
F7 PERN6 USB3 Port Assignments:
87 26 IN PCIE_TBT_D2R_N<1> F20 USB3_EXTA_RX_F_N
PCI-E
H7 PERP6 USB3RN1 IN 42 90
PCIE_TBT_D2R_P<1>
USB
87 26
C
IN G20
C 87 26 OUT PCIE_TBT_R2D_C_N<1> E1 PETN6
USB3RP1
USB3TN1 B18
USB3_EXTA_RX_F_P
USB3_EXTA_TX_N
IN
OUT
42 90
42 90
Ext A (SS)
87 26 PCIE_TBT_R2D_C_P<1> D2 PETP6 USB3TP1 C18 USB3_EXTA_TX_P 42 90

OUT OUT
TBT
USB3RN2 G18 USB3_EXTB_RX_F_N 42 90
IN
87 26 PCIE_TBT_D2R_N<2> K6 PERN7 USB3RP2 H18 USB3_EXTB_RX_F_P 42 90
IN IN
K8 PERP7 B15 Ext B (SS)
87 26 IN PCIE_TBT_D2R_P<2> USB3TN2 USB3_EXTB_TX_N OUT 42 90
USB3TP2 B16 USB3_EXTB_TX_P

87 26 PCIE_TBT_R2D_C_N<2> G3 PETN7 OUT 42 90
OUT
87 26 PCIE_TBT_R2D_C_P<2> G5 PETP7 USB3RN5 K20 USB3_EXTC_RX_F_N 43 90
OUT IN
USB3RP5 L20 USB3_EXTC_RX_F_P 43 90
IN
D15 Ext C (SS)
J2 PERN8 USB3TN5 USB3_EXTC_TX_N OUT 43 90
87 26 IN PCIE_TBT_D2R_N<3> C15
J3 PERP8 USB3TP5 USB3_EXTC_TX_P OUT 43 90
87 26 IN PCIE_TBT_D2R_P<3> 90 PCH_USB_RBIAS
USB3RN6 L18 USB3_EXTD_RX_F_N PLACE_NEAR=U1100.AV20:11.4MM
87 26 PCIE_TBT_R2D_C_N<3> H2 PETN8 IN 43 90
OUT
USB3RP6 K18 USB3_EXTD_RX_F_P 1
87 26 OUT PCIE_TBT_R2D_C_P<3> H1 PETP8 IN 43 90
Ext D (SS) R1370
USB3TN6 B14 USB3_EXTD_TX_N 43 90 22.6
OUT
A14 1%
USB3TP6 USB3_EXTD_TX_P OUT 43 90 1/20W
MF
2 201
USBRBIAS* AV20
USBRBIAS AU20
TP24 AK14 NC
TP23 AJ14 NC
80 12 =PP1V5_S0_PCH_RCOMP AE40
OC0*/GPIO59 USB_EXTA_OC_L IN 13 18 42
OC1*/GPIO40 AF37 USB_EXTC_OC_L 13 18 43

IN
B13 PCIE_IREF OC2*/GPIO41 AD39 PCH_GPIO41 13 18
1 OUT
R1300
B 7.5K
1%
NC
L16 TP11
OC3*/GPIO42
OC4*/GPIO43
AD40
AF39
PCH_GPIO42
USB_EXTB_OC_L
OUT
IN
13 18
13 18 42
B
1/20W K16 TP6 AC41
OC5*/GPIO9 USB_EXTD_OC_L
MF
201
NC AF40
IN 13 18 43
2
PLACE_NEAR=U1100.C13:12.7MM OC6*/GPIO10 PCH_GPIO10 OUT 13 18
87 PCH_PCIE_RCOMP C13 PCIE_RCOMP OC7*/GPIO14 AG40 SDCONN_STATE_CHANGE 13 18 37

IN
OMIT_TABLE
89 46 44 BI LPC_AD<0> R1340 33 1 2
5% 1/20W MF 201
89 LPC_AD_R<0> AN24 LAD0 (IPU) U1100 SMBALERT*/GPIO11 AG31 PCH_SMBALERT_L 13
89 46 44 BI LPC_AD<1> R1341 33 1 2
5% 1/20W MF 201
89 LPC_AD_R<1> AP26 LAD1 (IPU) LYNX SMBCLK AG36 SMBUS_PCH_CLK 47 91
LPC_AD<2> R1342 33 LPC_AD_R<2> AJ24 FCBGA OUT
89 46 44 1 2 89 LAD2 (IPU)
BI
5% 1/20W MF 201 DESKTOP SMBDATA AG32 SMBUS_PCH_DATA BI 47 91
89 46 44 BI LPC_AD<3> R1343 33 1 2 89 LPC_AD_R<3> AN26 LAD3 (IPU)
5% 1/20W MF 201 SYM 3 OF 11
89 46 44 OUT LPC_FRAME_L R1344 33 1 2 89 LPC_FRAME_R_L AP24 LFRAME* SML0ALERT*/GPIO60 AG35 PCH_SML0ALERT_L 13
SMBUS
5% 1/20W MF 201
TP_LPC_DREQ0_L AK22 LDRQ0* (IPU) SML0CLK AE32 SML_PCH_0_CLK
LPC
82 OUT 47 91
20 13 OUT TBT_PWR_EN_PCH AK26 LDRQ1*/GPIO23 SML0DATA AE35 SML_PCH_0_DATA BI 47 91

(IPU-LDRQ1#?)
46 44 13 LPC_SERIRQ G39 SERIRQ

BI
SML1ALERT*/PCHHOT*/GPIO74 AJ39 PCH_SML1ALERT_L 13
SML1CLK/GPIO58 AK36 SML_PCH_1_CLK IN 47 91

=PP3V3_S4_PCH 80
SML1DATA/GPIO75 AK33 SML_PCH_1_DATA BI 47 91
=PP3V3_S0_PCH_VCC3_3_GPIO 11 12 14 15 17 80
89 46 SPI_CLK_R U39 SPI_CLK

OUT
C-LINK
SPI
R1350 10K 1 2 LPC_SERIRQ 13 44 46
R38 SPI_CS0* (IPU/IPD) CL_CLK U36 TP_CLINK_CLK
5% 1/20W MF 201 89 46 OUT SPI_CS0_R_L (IPU)
R1351 10K 1 2 TBT_PWR_EN_PCH 13 20
R35 SPI_CS1* (IPU/IPD) CL_DATA U35 TP_CLINK_DATA
5% 1/20W MF 201 NC (IPU)
R1360 10K 1 2 USB_EXTA_OC_L 13 18 42
R40 SPI_CS2* CL_RST* U34 TP_CLINK_RESET_L
R1361 10K 5% 1/20W MF 201 NC (IPU)
A R1362 10K
1
1
2
2
5% 1/20W MF 201
USB_EXTC_OC_L
PCH_GPIO41
13 18 43
13 18 89 46 BI SPI_MOSI_R P40 SPI_MOSI (IPD)

TP1 A2 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
R1368 10K 1 2
5% 1/20W MF 201
PCH_GPIO42 NC PAGE TITLE
13 18
SPI_MISO R36 SPI_MISO TP2 A3
R1320 10K 1 2
5% 1/20W MF 201
USB_EXTB_OC_L 13 18 42
89 46 BI (IPU)
TP4 B2
NC PCH PCI-E/USB
R1321 10K 1 2
5% 1/20W MF 201
USB_EXTD_OC_L U40 SPI_IO2 NC DRAWING NUMBER SIZE
13 18 43
NC (IPU)
TP3 B1
R1367 10K 2 1
5% 1/20W MF 201
PCH_GPIO10 13 18
U37 SPI_IO3 TD_IREF C3
NC
PCH_TD_IREF Apple Inc. 051-9889 D
R1369 10K 1 2
5% 1/20W MF 201
SDCONN_STATE_CHANGE 13 18 37
NC (IPU)
REVISION
5% 1/20W MF 201 PLACE_NEAR=U1100.C3:11.4MM R
1
13.0.0
R1380 NOTICE OF PROPRIETARY PROPERTY: BRANCH
8.2K
1% THE INFORMATION CONTAINED HEREIN IS THE
1/20W PROPRIETARY PROPERTY OF APPLE INC.
R1353 10K 1 2 PCH_SMBALERT_L 13 MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 201
R1354 10K 1 2 PCH_SML0ALERT_L 13
2 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 13 OF 123
5% 1/20W MF 201 II NOT TO REPRODUCE OR COPY IT
R1355 10K 1 2 PCH_SML1ALERT_L 13
5% 1/20W MF 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D OMIT_TABLE D
TBT_CIO_PLUG_EVENT_ISOL G38 BMBUSY*/GPIO0
20 IN
U1100 =PP1V05_S0_PCH_V_PROC_IO
14 FW_PME_L AT31 TACH1/GPIO1 LYNX 15 17 80
FCBGA
DPMUX_UC_IRQ AM28 TACH2/GPIO6 DESKTOP PWM0 AL31 NOSTUFF
14
NC
AM31
91 44 14 IN SMC_RUNTIME_SCI_L AV34 TACH3/GPIO7 SYM 6 OF 11 PWM1 NC
1
R1457
PWM2 AP31
NC 1K
AC40 GPIO8 5%
HDD_PWR_EN (IPU-RSMRST#) PWM3 AV30 1/16W
69 18 OUT NC MF-LF
WOL_EN AL40 LAN_PHY_PWR_CTRL/GPIO12 SST AJ31 2 402
36 14 OUT NC
14 MEM_VDD_SEL_1V5_L AC32 GPIO15 TP14 N30 PCH_A20GATE 14
M39 SATA4GP/GPIO16 NOSTUFF

18 14 PCH_GPIO16 (IPD)
IN
(IPU-Boot/SATA4GP?) PECI G40 PCH_PECI R1470 43 1 2 CPU_PECI BI 6 44 45 86
AP28 TACH0/GPIO17 5% 1/20W
CPU/MISC
46 14 BI LPCPLUS_GPIO MF 201
L38 SCLOCK/GPIO22 RCIN* K36 PCH_RCIN_L 14

20 14 OUT JTAG_TBT_TMS_PCH
26 14 TBT_GO2SX_BIDIR AE34 GPIO24 PROCPWRGD D40 86 PCH_PROCPWRGD R1440 0 1 2 CPU_PWRGD 6 18 86

BI OUT
5% 1/20W
AU34 GPIO27 MF 0201
91 44 14 SMC_WAKE_SCI_L (IPU-DeepSx)
THRMTRIP* C40
IN 86 PM_THRMTRIP_L_R R1456 390 1 2 PM_THRMTRIP_L IN 45 86
V41 GPIO28 5% 1/20W
21 OUT ISOLATE_CPU_MEM_L MF 201
N34 GPIO34 PLTRST_PROC* F41 CPU_RESET_L OUT 6 18 86

28 OUT TBT_SW_RESET_L
18 3 GPU_GOOD M40 GPIO35/NMI* VSS AV33

OUT
GPIO
18 14 PCH_GPIO36 H40 SATA2GP/GPIO36
OUT
(IPD-PLTRST#)
80 28 =PP3V3_S0_PCH_GPIO 20 18 14 JTAG_ISP_TCK N41 SATA3GP/GPIO37

AT20
C
OUT
C 20 14 IN JTAG_ISP_TDO
(IPD-PLTRST#)
H41 SLOAD/GPIO38
VSS
VSS AT21
VSS AT23
20 14 JTAG_ISP_TDI R31 SDATAOUT0/GPIO39
OUT AT24
VSS
14 FW_PWR_EN_PCH L40 SDATAOUT1/GPIO48 VSS AT28
VSS AT29
18 14 PCH_GPIO49 N40 SATA5GP/GPIO49
IN AT33
1 (IPU-Boot/SATA5GP?) VSS
R1426 1 SPIROM_USE_MLB AC36 GPIO57 VSS AT36
R1427 89 46 BI
10K 10K 33.2 VSS AT38
5%
5% PCH_CAM_EXT_BOOT_R_L 1 2 R1461 14 PCH_CAM_EXT_BOOT_L AT30 TACH4/GPIO68
1/20W
1/20W
39 OUT 1% 1/20W MF 201 VSS AT41
MF 33.2
MF
201
2 201 39 PCH_CAM_RESET_R 1 2 R1462 14 PCH_CAM_RESET AV35 TACH5/GPIO69 VSS AT7
2 OUT 1% 1/20W MF 201
PLACE_NEAR=U1100.AT30:10MM VSS AT8
PLACE_NEAR=U1100.AV35:10MM PCH_BLC_MCU_RESET_R AK28 TACH6/GPIO70
(IPU-Boot?) VSS AU1
PCH_BLC_EXT_BOOT_R AT34 TACH7/GPIO71 VSS AU3
(IPU-Boot?) AU39
VSS
VSS AV1
AT14 VSS
VSS AV12
AT15 VSS
VSS AV17
AT16 VSS
VSS AV2
AT18 VSS
VSS AV21
B B
14 PCH_CAM_EXT_BOOT_L
14 PCH_CAM_RESET
=PP3V3_S0_PCH_VCC3_3_GPIO 11 12 13 15 17 80
R1422 1 1
R1423
R1485 10K 1 2 FW_PME_L 14 1K 1K
5% 1/20W MF 201
R1411 20K 2 1 DPMUX_UC_IRQ 14
5%
1/20W
5%
1/20W
5% 1/20W MF 201
R1496 10K 1 2 SMC_RUNTIME_SCI_L 14 44 91
MF
201
MF
201
5% 1/20W MF 201 2 2
R1494 10K 1 2 WOL_EN 14 36
5% 1/20W MF 201
R1489 10K 1 2 MEM_VDD_SEL_1V5_L 14
5% 1/20W MF 201
R1495 10K 1 2 PCH_GPIO16 14 18
5% 1/20W MF 201
R1490 100K 1 2 LPCPLUS_GPIO 14 46
5% 1/20W MF 201
R1412 10K 2 1 JTAG_TBT_TMS_PCH 14 20
5% 1/20W MF 201
R1492 10K 1 2 TBT_GO2SX_BIDIR 14 26
5% 1/20W MF 201
R1491 10K
A R1498 10K
1
2
2
1
5%
5%
1/20W
1/20W
MF
MF
201
201
SMC_WAKE_SCI_L
PCH_GPIO36
14 44 91
14 18 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
R1413 10K 2 1 JTAG_ISP_TCK 14 18 20
PAGE TITLE
R1486 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
JTAG_ISP_TDO 14 20 PCH GPIO/MISC/NCTF
R1499 10K 1 2 JTAG_ISP_TDI 14 20 DRAWING NUMBER SIZE
R1484 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
FW_PWR_EN_PCH 14
R1497 10K 1 2 PCH_GPIO49 14 18 REVISION
5% 1/20W MF 201 R
13.0.0
R1450 10K 1 2 PCH_A20GATE 14 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
R1455 10K 1 2 PCH_RCIN_L 14 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 14 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U1100
LYNX
FCBGA
DESKTOP
80 17 =PP1V05_S0_PCH_VCC
V20 SYM 7 OF 11 CKPLUS_WAIVE=PWRTERM2GND
VCC: 1312mA Max, 130mA Idle VCC VCCADAC1_5 AF2
V22 VCC VGA DAC Disabled per LPT
VSS AV40
CRT
V23 VCC DG v1.0 (Table 12-18).
V25 VCC VCCADACBG3_3 AE1 CKPLUS_WAIVE=PWRTERM2GND
W17 VCC
W19 =PP1V5_S0_PCH_VCCVRM_FDI 17
VCC VCCVRM: 158mA Max, 43mA Idle
VCCVRM B39
D
W23 VCC
D
FDI
W25 =PP1V05_S0_PCH_VCCIO 15 17 80
VCC VCCIO: 3491mA Max, 199mA Idle
AA19 VCCIO AC12
VCC
AA20 VCCIO AF19 =PP1V05_S0_PCH_VCCIO_USB2 15 17 80
VCC
17 PP1V05_S0_PCH_VCC_CLK_F AB1 VCC
HVCMOS
AB16 VCC VCC3_3 AG1 =PP3V3_S0_PCH_VCC3_3_HVCMOS 17 80
AB17 VCC3_3: 133mA Max, 3mA Idle
VCC
AB19 VCC
AB20 VCC
AD16 VCC DCPSUS1 AE30 NC
=PP3V3_S5_PCH_VCCSUS_GPIO 11 12 13 14 15 17 80
VCCSUS3_3: 261mA Max, 6mA Idle
R1550 VCCSUS3_3 AN33
PLACE_NEAR=R1550.1:2.54mm PLACE_NEAR=U1100.AU40:2.54MM
5.11 AU40 DCPSUSBYP VCCSUS3_3 P20 =PP3V3_S5_PCH_VCCSUS_USB3 80
PPVOUT_S5_PCH_DCPSUSBYP 1 2 PPVOUT_S5_PCH_DCPSUSBYP_R
CORE
MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm
USB3
MIN_NECK_WIDTH=0.2 mm 1% MIN_NECK_WIDTH=0.2 mm Powered in DeepSx AU41 DCPSUSBYP
1VOLTAGE=1.05V
1/20W VOLTAGE=1.05V DCPSUS3 P19 NC
C1550 MF-LF
201 C1 VCCVRM
1UF
10% C2 VCCVRM =PP1V05_S0_PCH_VCCIO 15 17 80
6.3V
2 VCCIO: 3491mA Max, 199mA Idle
CERM
402
K1 VCCVRM VCCIO P25
17 15 =PP1V5_S0_PCH_VCCVRM_CLK T14 VCCVRM =PP1V5_S0_PCH_VCCVRM_USB3 17
VCCVRM: 158mA Max, 43mA Idle VCCVRM: 158mA Max, 43mA Idle
VCCVRM A39
VCCVRM A4
=PP1V5_S0_PCH_VCCVRM_PCIE 17
PCIE/DMI
VCCVRM: 158mA Max, 43mA Idle
VCCVRM B4
80 17 15 =PP1V05_S0_PCH_VCCASW AF25 VCCASW VCCIO P23

VCCASW: 670mA Max, 34mA Idle AA25 VCCASW
AA26 =PP1V5_S0_PCH_VCCVRM_SATA 17
VCCASW VCCVRM: 158mA Max, 43mA Idle
C VCCVRM A40
C
SATA
AB22 VCCASW
AB23 VCCASW
AB25 VCCIO P26
VCCASW
AB26 VCCASW
AD17 VCCASW VCCIO P28
VCCMPHY
AD19 VCCASW VCCIO T19
AD20 VCCASW VCCIO T20
AD22 VCCASW VCCIO AF20 =PP1V05_S0_PCH_VCCIO_USB2 15 17 80
AD23 VCCASW VCCIO AF22
AD25 VCCASW VCCIO AF23
OMIT_TABLE
U1100
LYNX
FCBGA
DESKTOP VCCSUS3_3 AH18 =PP3V3_S5_PCH_VCCSUS_USB 15 17 80
80 17 15 =PP3V3_S5_PCH_VCCSUS_USB VCCSUS3_3: 261mA Max, 6mA Idle
VCCSUS3_3: 261mA Max, 6mA Idle AH22 VCCSUS3_3 SYM 8 OF 11 VCCSUS3_3 AH20
AJ20 VCCSUS3_3 VCCDSW3_3 AV39 =PP3V3_S5_PCH_VCCDSW 17 80
AK20 VCCSUS3_3 VCCDSW3_3: 15mA Max, 1mA Idle
VCCDSW3_3 AW38
80 17 15 14 13 12 11 =PP3V3_S5_PCH_VCCSUS_GPIO AM33 VCCSUS3_3 VCCDSW3_3 AW39
GPIO/LPC
AV41 VSS BYPASS=U1100.AH28:6.35MM
DCPSST AH28 PPVOUT_S0_PCH_DCPSST
MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
80 17 =PP1V05_S0_PCH_VCCUSBPLL AP22 VCCUSBPLL VCC3_3 AF26 =PP3V3_S0_PCH_VCC_FUSE 17 80

1
C1580
VCC3_3 U30 =PP3V3_S0_PCH_VCC3_3_GPIO 11 12 13 14 15 17 80
0.1UF
20%
VCC3_3 AW21 =PP3V3_S0_PCH_VCC3_3_USB 10V
B M14 VCCIO
VCC3_3 W30 =PP3V3_S0_PCH_VCC3_3_GPIO
17 80
11 12 13 14 15 17 80
2 CERM
402 B
VCCIO P14
USB
80 17 =PP1V05_S0_PCH_VCCIO_FDI =PP1V05_S0_PCH_VCCIO 15 17 80
P16 VCCIO VCCIO: 3491mA Max, 199mA Idle
80 17 15 =PP1V05_S0_PCH_VCCIO
VCCIO: 3491mA Max, 199mA Idle P17 VCCIO
HDA
P22 VCCIO
VCCSUSHDA AW26 =PP3V3_S5_PCH_VCCSUS_HDA 17 80
VCCSUSHDA: 10mA Max, 1mA Idle
AJ22 DCPSUS2
NC
VCCSUS3_3 AP35 =PP3V3_S5_PCH_VCCSUS_RTC 17 80
RTC
A38 VCCVRM =PP3V3_G3_PCH_RTC 80
17 15 =PP1V5_S0_PCH_VCCVRM_CLK
VCCVRM: 158mA Max, 43mA Idle VCCRTC AP33
6uA Max (3.0V, room temperature)
BYPASS=U1100.AW35:6.35MM
DCPRTC AW35 PPVOUT_S0_PCH_DCPRTC C1533 1
C1532 1 1
C1531
0.1UF 0.1UF 1UF
80 17 =PP1V05_S0_PCH_VCCCLK_SSC T16 VCCCLK VOLTAGE=1.05V 20% 20% 10%
10V 10V 6.3V
VCCCLK: 306mA Max, 89mA Idle CERM 2 CERM 2 2 CERM
402 402 402
=PP3V3_S0_PCH_VCCCLK3_3 AM9 VCCCLK3_3 CPU 1
C1590
CLK/MISC
80 17
VCCCLK3_3: 55mA Max, 11mA Idle AK11 BYPASS=U1100.AP33:6.35MM
VCCCLK3_3 V_PROC_IO C39 =PP1V05_S0_PCH_V_PROC_IO 14 17 80
0.1UF
20%
BYPASS=U1100.AP33:6.35MM
AG12 V_PROC_IO: 4mA Max, 2mA Idle 10V BYPASS=U1100.AP33:6.35MM
VCCCLK3_3 2 CERM
AM7 VCCCLK3_3 402
AP5 VCCCLK3_3
SPI
AP7 VCCCLK3_3
AW3 VCCSPI R41 =PP3V3_S5_PCH_VCC_SPI 17 80
VCCCLK3_3 VCCSPI: 22mA Max, 1mA Idle
AW4 VCCCLK3_3
AW9 VCCCLK3_3
AR4 VCCCLK3_3 VCC V17 =PP1V05_S0_PCH_VCCIO 15 17 80
A AT5
AV3
VCCCLK3_3
VCCCLK3_3
VCC V19
PAGE TITLE
AV4 VCCCLK3_3 VCCASW W26 =PP1V05_S0_PCH_VCCASW
VCCASW: 670mA Max, 34mA Idle
15 17 80
PCH Power
V16 DRAWING NUMBER SIZE
VCCCLK VCCASW AA23 =PP1V05_S0_PCH_VCCASW
80 17 =PP1V05_S0_PCH_VCCCLK_CLK100 U12 VCCCLK
VCCASW: 670mA Max, 34mA Idle
15 17 80

VCCCLK: 306mA Max, 89mA Idle V14 REVISION
VCCCLK R
THERMAL
=PP1V05_S0_PCH_VCCCLK_CLK135 W14 13.0.0

80 17 VCCCLK
VCCCLK: 306mA Max, 89mA Idle W16 VCCVRM B37 =PP1V5_S0_PCH_VCCVRM_THRM 17 NOTICE OF PROPRIETARY PROPERTY: BRANCH
VCCCLK VCCVRM: 158mA Max, 43mA Idle
AA16 THE INFORMATION CONTAINED HEREIN IS THE
80 17 =PP1V05_S0_PCH_VCCCLK_SSC100 VCCCLK PROPRIETARY PROPERTY OF APPLE INC.
VCCCLK: 306mA Max, 89mA Idle AB2 VCC3_3 B6 =PP3V3_S0_PCH_VCC3_3_THRM 17 80 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VCCCLK VCC3_3: 133mA Max, 3mA Idle I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 15 OF 123
Current data from LPT EDS (doc #486708, Rev 1.0).
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT_TABLE
OMIT_TABLE
A12 VSS U1100 VSS F18
T23 VSS U1100 VSS AE12
A16 VSS LYNX VSS F24
A21 VSS FCBGA VSS F35
T25 VSS LYNX VSS AE31
DESKTOP T26 VSS FCBGA VSS AE4
A35 VSS VSS F37 DESKTOP
SYM 10 OF 11 T28 VSS VSS AE41
B25 VSS VSS F38 SYM 11 OF 11
U1 AE8
B3 VSS VSS VSS G2 VSS VSS
AF14
B30 VSS VSS H14
U31 VSS VSS VSS
U32 VSS VSS AF16
B33 VSS VSS H16
U4 VSS VSS AF17
B38 VSS VSS H20
U8 VSS VSS AF28
B40 VSS VSS H22
V26 VSS VSS AF3
B41 VSS VSS H26
V28 VSS VSS AG2
C25 VSS VSS H28
V38 VSS VSS AG30
C37 VSS VSS H33
V40 VSS VSS AG34
C41 VSS VSS H34
W12 VSS VSS AG38
C6 VSS VSS H38
W20 VSS VSS AG8
D1 VSS VSS H4
AH14
C D12
D13
VSS
VSS
VSS
VSS
H6
H8
W22
W28
VSS
VSS
VSS
VSS AH16 C
W3 VSS VSS AJ1
D14 VSS VSS H9
W5 VSS VSS AJ28
D16 VSS VSS J31
W8 VSS VSS AK24
D18 VSS VSS J37
Y1 VSS VSS AK37
D19 VSS VSS J5
Y41 VSS VSS AK9
D20 VSS VSS K31
AA10 VSS VSS AL11
D22 VSS VSS K4
AA11 VSS VSS AL37
D24 VSS VSS K9
AA12 VSS VSS AL5
D25 VSS VSS L37
AA14 VSS VSS AM14
D26 VSS VSS L41
AA17 VSS VSS AM16
D27 VSS VSS M16
AA22 VSS VSS AM18
D28 VSS VSS M18
AA28 VSS VSS AM20
D31 VSS VSS M20
AA30 VSS VSS AM24
D32 VSS VSS M22
AA34 VSS VSS AM26
D34 VSS VSS M24
AA5 VSS VSS AM35
D37 VSS VSS M26
AA8 VSS VSS AM38
D4 VSS VSS M28
AB14 VSS VSS AM4
D41 VSS VSS N31
AB28 VSS VSS AM6
D6 VSS VSS N35
AB4 VSS VSS AM8
D7 VSS VSS N38
AC30 VSS VSS AN28
D8 VSS VSS N4
AC31 VSS VSS AP4
D9 VSS VSS N8
AC34 VSS VSS AP9
E12 VSS VSS R1
AC38 VSS VSS AR11
E3 VSS VSS R10
AC5 VSS VSS AR35
E31 VSS VSS R34
AC8 VSS VSS AR37
B E35
E38
VSS
VSS
VSS
VSS
R8
T17
AD14
AD26
VSS VSS AT1
AT10
B
E4 T22 VSS VSS
VSS VSS AD28 AT11
E5 AW2 VSS VSS
VSS VSS
E7 VSS VSS AW30
VSS AW40
VSS AW7
PAGE TITLE
PCH Grounds
DRAWING NUMBER SIZE

REVISION
R
13.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCCLK3_3 BYPASS 55mA Max, 11mA Idle PCH VCCASW BYPASS
PCH VCCDSW3_3 BYPASS (PCH 3.3V CLK PWR) INTEL:4X 1UF(402) (PCH 1.05V ME CORE PWR) INTEL:1X10UF(805), 1X1UF(402)
(PCH 3.3V DSW PWR) INTEL:1X 0.1UF(402) 80 15 =PP3V3_S0_PCH_VCCCLK3_3 80 15 =PP1V05_S0_PCH_VCCASW
80 15 =PP3V3_S5_PCH_VCCDSW 670mA Max, 34mA Idle
15mA Max, 1mA Idle
C1700 1
C1720 1
C1721 1
C1722 1
C1723 1
C1750 1 1
C1751 1
C1752
0.1UF 1UF 1UF 1UF 1UF 10UF 1UF 1UF
20% 10% 10% 10% 10% 20% 10% 10%
10V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 X5R 2 2 CERM 2 CERM
402 402 402 402 402 603 402 402
BYPASS=U1100.AP5:6.35MM place_near=U1100.AD17:2.54MM
BYPASS=U1100.AV4:6.35MM place_near=U1100.AD17:2.54MM
BYPASS=U1100.AR4:6.35MM place_near=U1100.AD19:2.54MM
D PCH VCCSPI BYPASS PCH VCC3_3 BYPASS

BYPASS=U1100.AT5:6.35MM
PCH VCC BYPASS D

(PCH 3.3V SPI PWR) INTEL:1X 1UF(402) (PCH 3.3V HVCMOS PWR) INTEL:1X 0.1UF(402) (PCH 1.05V CORE PWR)
THESE 4X1UF ARE EXTRA BYPASS
80 15 =PP3V3_S5_PCH_VCC_SPI 80 15 =PP3V3_S0_PCH_VCC3_3_HVCMOS 80 15 =PP1V05_S0_PCH_VCC
22mA Max, 1mA Idle 133mA Max, 3mA Idle 1312mA Max, 130mA Idle
C1702 1
C1726 1
1UF 0.1UF 1
C1761 1
C1756 1
C1757 1
C1758
10% 20%
6.3V
2
10V
2 1UF 1UF 1UF 1UF
CERM CERM 10% 10% 10% 10%
402 402 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM
BYPASS=U1100.R41:6.35MM BYPASS=U1100.AG1:6.35MM 402 402 402 402
BYPASS=U1100.P14:6.35MM
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS BYPASS=U1100.V22:6.35MM
INTEL:1X 0.1UF(402) BYPASS=U1100.V25:6.35MM
(PCH 3.3V SUSPEND PWR) (PCH 3.3V GPIO/LPC PWR) INTEL:1X 0.1UF(402) BYPASS=U1100.AA19:6.35MM
80 15 14 13 12 11 =PP3V3_S5_PCH_VCCSUS_GPIO 80 15 14 13 12 11 =PP3V3_S0_PCH_VCC3_3_GPIO PCH VCCIO BYPASS

261mA Max, 6mA Idle 133mA Max, 3mA Idle (PCH 1.05V PCIe/DMI/SATA/USB3 PWR) INTEL:2X10UF(805), 3X1UF(402)
C1704 1
C1728 1
80 15 =PP1V05_S0_PCH_VCCIO
0.1UF 0.1UF 3491mA Max, 114mA Idle
20% 20%
10V 10V
CERM 2 CERM 2
402
BYPASS=U1100.AN33:6.35MM BYPASS=U1100.W30:6.35MM
402
C1760 1 C1755 1 1
C1762 1
C1763 1
C1764
10UF 10UF 1UF 1UF 1UF
20% 20% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 X5R 2 2 CERM 2 CERM 2 CERM
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS 603 603 402 402 402
(PCH 3.3V SUSPEND USB PWR) INTEL:1X 0.1UF(402) (PCH 3.3V USB2 PWR) INTEL:1X 1UF(402)
80 15 =PP3V3_S5_PCH_VCCSUS_USB 80 15 =PP3V3_S0_PCH_VCC3_3_USB BYPASS=U1100.P28:12.7MM
261mA Max, 6mA Idle 133mA Max, 3mA Idle BYPASS=U1100.P17:6.35MM
BYPASS=U1100.P26:6.35MM PCH VCCCLK BYPASS
C1706 1
C1730 1
PCH VCCUSBPLL BYPASS
0.1UF 1UF (PCH 1.05V SSC100 PWR) INTEL:2X 1UF(402)
(PCH 1.05V USB2 PLL PWR) INTEL:1X 1UF(402)
20%
10V
10%
6.3V 80 15 =PP1V05_S0_PCH_VCCCLK_SSC100
CERM 2 CERM 2 80 15 =PP1V05_S0_PCH_VCCUSBPLL
306mA Max, 89mA Idle
C
402
BYPASS=U1100.AK20:6.35MM
402
C1770 1
C1776 1
C1777 1
C
1UF
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS 10% 1UF 1UF
6.3V 10% 10%
CERM 2 6.3V 6.3V
(PCH 3.3V DSW RTC PWR) INTEL:1X 1UF(402) (PCH 3.3V THERMAL PWR) INTEL:1X 0.1UF(402) 402 CERM 2 CERM 2
=PP3V3_S5_PCH_VCCSUS_RTC =PP3V3_S0_PCH_VCC3_3_THRM 402 402
80 15 80 15 BYPASS=U1100.AP22:6.35MM
133mA Max, 3mA Idle BYPASS=U1100.AA16:6.35MM

BYPASS=U1100.W16:6.35MM
C1708 1
C1732 1
PCH VCCIO BYPASS
1UF 0.1UF INTEL:1X 1UF(402)
10% 20%
(PCH 1.05V FDI PWR)
6.3V 10V =PP1V05_S0_PCH_VCCIO_FDI
CERM 2 CERM 2 80 15 PCH VCCCLK BYPASS
402 402 INTEL:2X 1UF(402)
3491mA Max, 114mA Idle (PCH 1.05V DIFFCLK PWR)
BYPASS=U1100.AP35:6.35MM BYPASS=U1100.B6:6.35MM
C1772 1
80 15 =PP1V05_S0_PCH_VCCCLK_CLK100
1UF
10%
PCH VCC BYPASS 306mA Max, 89mA Idle
6.3V
CERM 2 C1778 1
C1783 1
(PCH 3.3V FUSE PWR) INTEL:1X 1UF(402) 402 1UF 1UF
80 15 =PP3V3_S0_PCH_VCC_FUSE BYPASS=U1100.M14:6.35MM 10%
6.3V
10%
6.3V
CERM 2 CERM 2
133mA Max, 3mA Idle 402 402
C1734 1
PCH VCCIO BYPASS BYPASS=U1100.U12:6.35MM
BYPASS=U1100.AB2:6.35MM
1UF (PCH 1.05V USB2 PWR) INTEL:1X 1UF(402)
10%
6.3V =PP1V05_S0_PCH_VCCIO_USB2
CERM 2 80 15 PCH VCCCLK BYPASS
402 INTEL:1X 1UF(402)
3491mA Max, 114mA Idle (PCH 1.05V DIFFCLK135 PWR)
BYPASS=U1100.AF26:6.35MM
C1774 1
80 15 =PP1V05_S0_PCH_VCCCLK_CLK135
1UF
10%
6.3V
CERM 2 C1780 1
402 1UF
10%
BYPASS=U1100.AF19:6.35MM 6.3V
CERM 2
402
PCH VCCSUSHDA BYPASS PCH VCCVRM BYPASS PCH V_PROC_IO BYPASS BYPASS=U1100.W14:6.35MM
INTEL:1X 0.1UF(402)
B 80 15
(PCH 3.3V HDA PWR)
=PP3V3_S5_PCH_VCCSUS_HDA
INTEL:1X 0.1UF(402)
80
(PCH 1.5V VCCVRM PWR)
=PP1V5_S0_PCH_VCCVRM 80 15 14
(PCH 1.05V CPU I/F PWR)
=PP1V05_S0_PCH_V_PROC_IO
INTEL:1X1UF(603), 2X0.1UF(402)
PCH VCCCLK BYPASS
B
10mA Max, 1mA Idle 4mA Max, 2mA Idle (PCH 1.05V SSC PWR) INTEL:1X 1UF(402)
C1710 1
11 =PP1V5_S0_PCH_VCCVRM_BIAS 80 15 =PP1V05_S0_PCH_VCCCLK_SSC
0.1UF 15 =PP1V5_S0_PCH_VCCVRM_FDI C1785 1 1
C1786 1
C1787
20% 306mA Max, 89mA Idle
10V
2 15 =PP1V5_S0_PCH_VCCVRM_USB3 1UF 0.1UF 0.1UF C1782 1
CERM 10% 20% 20%
402
15 =PP1V5_S0_PCH_VCCVRM_PCIE 6.3V
2 2
10V
2
10V 1UF
CERM CERM CERM 10%
BYPASS=U1100.AW26:6.35MM 402 402 402 6.3V
15 =PP1V5_S0_PCH_VCCVRM_SATA CERM 2
=PP1V5_S0_PCH_VCCVRM_CLK 402
15 BYPASS=U1100.C39:12.7MM
BYPASS=U1100.C39:6.35MM BYPASS=U1100.V16:6.35MM
15 =PP1V5_S0_PCH_VCCVRM_THRM BYPASS=U1100.C39:6.35MM
C1740 1 PCH CLK VCC BYPASS INTEL:1X10UF(603), 1X1UF(402)

0.1UF (PCH 1.05V CLK PLL PWR. NOSTUFF 10UF IF IDG NO USED)
20%
16V
CERM 2 L1790 PP1V05_S0_PCH_VCC_CLK_F 15
603
=PP1V05_S0_PCH_VCC_CLK 1
0 2
MIN_LINE_WIDTH=0.2 MM
BYPASS=U1100.T14:12.7MM 80 MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
5% 1/10W MF-LF 603
C1790 1 1
C1791
NOSTUFF 10UF
20%
1UF
10%
6.3V 10V
X5R 2 2 X5R
603 402
BYPASS=U1100.AB1:12.7mm
BYPASS=U1100.AB1:6.35mm
PAGE TITLE
PCH DECOUPLING
DRAWING NUMBER SIZE

REVISION
R
13.0.0
Current data from LPT EDS (doc #486708, Rev 1.0).
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Extra BPM Testpoints 61 8 6 PPVCCIO_S0_CPU CPU Micro2-XDP 80 18 =PP1V05_S0_XDP
CRITICAL NOTE: This is not the standard XDP pinout. XDP

88 6 IN XDP_BPM_L<2> 1
TP XDP_CONN Use with 921-0133 Adapter Flex to 88 18 6 XDP_CPU_TDO R1820 51 2 1
TP1802 =PP1V05_S0_XDP
PLACE_NEAR=J1800.51:5MM 5% 1/20W MF 201
TP-P6 80 18 J1800 support chipset debug.
TP XDP
TP-P6
TP1803 DF40RC-60DP-0.4V
XDP_CPU_TCK R1823 51 2 1
M-ST-SM1 88 18 6
TP R1830 1 5% 1/20W MF 201
TP1804 150 62 61
TP-P6 XDP
88 6 IN XDP_BPM_L<5> 1 5%
TP
TP-P6
TP1805 1/16W 18 6 XDP_CPU_TRST_L R1824 51 2 1
MF-LF 5% 1/20W MF 201
TP 402
TP-P6
TP1806 2 2 1
TDI and TMS are terminated in CPU.
XDP_BPM_L<7> XDP_CPU_PREQ_L OBSFN_A0 4 3
OBSFN_C0 CPU_CFG<17>
D
88 6 IN 1 6 BI IN 6 88
TP TP1807
D TP-P6 6 IN XDP_CPU_PRDY_L OBSFN_A1 6
8
5
7
OBSFN_C1 CPU_CFG<16> IN 6 88
88 6 IN CPU_CFG<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<8> IN 6 88
CPU_CFG<1> 12 11 CPU_CFG<9>
88 6 IN OBSDATA_A1 OBSDATA_C1 IN 6 88
14 13
88 6 IN CPU_CFG<2> OBSDATA_A2 16 15 OBSDATA_C2 CPU_CFG<10> IN 6 88
88 6 IN OBSDATA_A3 OBSDATA_C3 IN 6 88
20 19
86 6 IN XDP_BPM_L<0> OBSFN_B0 22 21
OBSFN_D0 CPU_CFG<19> IN 6
86 6 XDP_BPM_L<1> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<18> 6

IN IN
26 25
88 6 IN CPU_CFG<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<12> IN 6 82 88
88 6 IN CPU_CFG<5> OBSDATA_B1 30 29
OBSDATA_D1 CPU_CFG<13> IN 6 82 88
32 31
88 6 IN OBSDATA_B2 OBSDATA_D2 IN 6 82 88
XDP
88 6 IN CPU_CFG<7> OBSDATA_B3 36 35 OBSDATA_D3 CPU_CFG<15> IN 6 82 88
86 14 6 IN CPU_PWRGD R1800 1K 1 2
38 37
PLACE_NEAR=U0500.AB35:16.5mm 5% 1/20W MF 201
XDP 86 XDP_CPU_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 NC
44 18 12 OUT PM_PWRBTN_L R1802 0 1 2 XDP_CPU_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 NC NC per Intel DPDG.
5% 1/20W MF 0201
VCC_OBS_AB 44 43 VCC_OBS_CD XDP
WF: SB DPDG says HOOK1 is BP_PWRGD_RST#
XDP 8 OUT CPU_PWR_DEBUG HOOK2 46 45
RESET#/HOOK6 86 XDP_CPURST_L R1805 1K 1 2 CPU_RESET_L IN 6 14 86
71 45 12 OUT PM_PCH_SYS_PWROK R1804 220 1 2 XDP_VR_READY HOOK3 48 47

DBR#/HOOK7 XDP_DBRESET_L OUT 6 18 19
5% 1/20W MF 201
5% 1/20W MF 201
50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
47 18 BI =SMBUS_XDP_SDA SDA 52 51
TDO XDP_CPU_TDO IN 6 18 88
47 18 IN =SMBUS_XDP_SCL SCL 54 53
TRSTn XDP_CPU_TRST_L OUT 6 18 CPU-PCH JTAG Chain Support
56 55 XDP_CPU_TDI
TCK1 NC TDI OUT 6 88
To link CPU and PCH JTAG pull ICT_JTAG_EN to 5V (must be in S0)
C 88 18 6 OUT XDP_CPU_TCK TCK0 58
60
57
59
TMS
XDP_PRESENT#
XDP_CPU_TMS OUT 6 18 88
TP1845 TP
TP-P6
1 C
XDP SIGNALS XDP 1
XDP XDP XDP XDP Q1840 ICT_JTAG_EN
Q1846
OMIT
5
PCH SIGNALS (All 18 R’s) R1831 C1804 1
C1800 1 1
C1801 1
C1806 DMN5L06VK-7 DMN5L06VK-7
G
1K 64 63 SOT-563 SOT-563
0.1UF 0.1UF 0.1UF 0.1UF
42 13 IN USB_EXTA_OC_L R1890 SHORT 1 2 XDP_DA0_USB_EXTA_OC_L 18
5%
1/16W
20%
10V
20%
10V
20%
10V
20%
10V
R1893 NONE NONE NONE 402 MF-LF 2 2 2 2
D
43 13 IN USB_EXTC_OC_L SHORT 1 2 XDP_DA1_USB_EXTC_OC_L 18 402 2
CERM
402
CERM
402 998-2516 CERM
402
CERM
402 88 18 6 XDP_CPU_TMS XDP_CPU_PCH_TMS XDP_PCH_TMS 11 18 88
R1894 NONE NONE NONE 402 PLACE_NEAR=J1800.57:5.08mm PLACE_NEAR=J1850.57:6mm
3
4
4
13 IN PCH_GPIO41 SHORT 1 2 XDP_DA2_PCH_GPIO41 18
13 IN PCH_GPIO42 R1895 SHORT 1 2

NONE NONE NONE 402
XDP_DA3_PCH_GPIO42 18 TP1840 TP 1
USB_EXTB_OC_L R1880 NONE NONE NONE 402

XDP_DB0_USB_EXTB_OC_L
Q1840 TP-P6 Q1846
SHORT 1 2
2
42 13 IN 18
DMN5L06VK-7 DMN5L06VK-7
R1881 NONE NONE NONE 402
G
43 13 IN USB_EXTD_OC_L SHORT 1 2 XDP_DB1_USB_EXTD_OC_L 18 XDP_CPU_PRESENT_L SOT-563 SOT-563
13 IN PCH_GPIO10 R1896 SHORT 1 2

NONE NONE NONE 402
XDP_DB2_PCH_GPIO10 18
D
37 13 OUT SDCONN_STATE_CHANGE SHORT 1 2 XDP_DB3_SDCONN_STATE_CHANGE_L 18 88 18 6 XDP_CPU_TCK XDP_CPU_PCH_TCK XDP_PCH_TCK 11 18 88
R1872 NONE NONE NONE 402 PLACE_NEAR=J1800.58:5.08mm PLACE_NEAR=J1850.58:5.08mm
6
1
1
30 29 11 IN DP_AUXIO_EN SHORT 1 2 XDP_DC0_DP_AUXCH_ISOL_L 18
11 IN SATARDRVR_EN R1873 SHORT 1 2

NONE NONE NONE 402
XDP_DC1_SATARDRVR_EN 18 TP1841 TP 1
R1874 NONE NONE NONE 402 Q1842 TP-P6 Q1848

PCH_GPIO36 SHORT 1 2 XDP_DC2_PCH_GPIO36
1
14 IN 18 DMN32D2LFB4 DMN32D2LFB4
G
DFN1006H4-3 DFN1006H4-3
20 14 IN JTAG_ISP_TCK SHORT 1 2 XDP_DC3_JTAG_ISP_TCK 18 SYM_VER_3 SYM_VER_3
14 OUT PCH_GPIO16 R1878 SHORT 1 2
NONE NONE NONE 402
XDP_DD0_PCH_GPIO16 18
D
PCH_GPIO49 SHORT 1 2 XDP_DD1_PCH_GPIO49 XDP_CPU_TDO XDP_CPU_TDO_PCH_TDI XDP_PCH_TDI
14 OUT
18
PCH Micro2-XDP =PP3V3_S5_XDP
88 18 6
PLACE_NEAR=J1800.51:5.08mm PLACE_NEAR=J1850.55:5.08mm
11 18 88
3
18 80
2
35 11 OUT ENET_CLKREQ_L SHORT 1 2 XDP_DD2_ENET_CLKREQ_L 18
32 11 OUT AP_CLKREQ_L R1883 SHORT 1 2

NONE NONE NONE 402
XDP_DD3_AP_CLKREQ_L 18
R1886 NONE NONE NONE 402 CRITICAL
69 14 OUT HDD_PWR_EN SHORT 1 2 XDP_FC0_HDD_PWR_EN 18
14 3 GPU_GOOD R1887 SHORT 1 2

NONE NONE NONE 402
XDP_FC1_GPU_GOOD 18
XDP_CONN R1842 1 1
R1841 1
R1840 R1845 1
OUT NONE NONE NONE 402
J1850 1M 1M 1M 1K
5% 5% 5% 5%
DF40RC-60DP-0.4V NOTE: This is not the standard XDP pinout. 1/20W 1/20W 1/20W 1/20W
M-ST-SM1 MF MF MF MF
Use with 921-0133 Adapter Flex to 201
2 2
201
2
201 201
2
62 61 support chipset debug.
B 2 1
NOSTUFF
B
OBSFN_A0 4 3
OBSFN_C0 XDP_FC0_HDD_PWR_EN R1892
NC 18
0
OBSFN_A1 6 5
OBSFN_C1 XDP_FC1_GPU_GOOD =PP3V3_S5_XDP 1 2 PP3V3_S5_XDP_R
NC 18 80 18
8 7 5% VOLTAGE=3.3V
1/16W MIN_LINE_WIDTH=0.2MM
18 XDP_DA0_USB_EXTA_OC_L OBSDATA_A0 10 9
OBSDATA_C0 XDP_DC0_DP_AUXCH_ISOL_L 18 MF-LF MIN_NECK_WIDTH=0.15MM
402 MAX_NECK_LENGTH=3MM
18 XDP_DA1_USB_EXTC_OC_L OBSDATA_A1 12 11
OBSDATA_C1 XDP_DC1_SATARDRVR_EN 18
PCH/XDP Signal Isolation Notes: 14 13
’Output’ non-XDP signals require pulls. 18 XDP_DA2_PCH_GPIO41 OBSDATA_A2 16 15

OBSDATA_C2 XDP_DC2_PCH_GPIO36 18
XDP XDP XDP
’Output’ PCH/XDP signals require pulls. XDP_DA3_PCH_GPIO42 OBSDATA_A3 18 17
OBSDATA_C3 XDP_DC3_JTAG_ISP_TCK 1 1 1
18 18
R1860 R1861 R1862
20 19 210 210 210
22 21 1% 1% 1%
R187x and R189x should be placed where OBSFN_B0 NC NC OBSFN_D0 1/20W 1/20W 1/20W
24 23
MF MF MF
signal path needs to split between route OBSFN_B1 NC NC OBSFN_D1 2 201 2 201 2 201
from PCH to J1850 and path to non-XDP 26 25 88 18 11 XDP_PCH_TDO U1100.W40:21mm
J1850.51:2.54mm U1100.W39:21mm
signal destination (to minimize stub). 18 XDP_DB0_USB_EXTB_OC_L OBSDATA_B0 28 27 OBSDATA_D0 XDP_DD0_PCH_GPIO16 18 88 18 11 XDP_PCH_TDI
XDP_DB1_USB_EXTD_OC_L 30 29 XDP_DD1_PCH_GPIO49 XDP_PCH_TMS
18 OBSDATA_B1 OBSDATA_D1 18 88 18 11
32 31 88 18 11 XDP_PCH_TCK
18 XDP_DB2_PCH_GPIO10 OBSDATA_B2 34 33
OBSDATA_D2 XDP_DD2_ENET_CLKREQ_L 18
XDP_DB3_SDCONN_STATE_CHANGE_L 36 35 XDP_DD3_AP_CLKREQ_L
18 OBSDATA_B3 OBSDATA_D3 18 XDP XDP
38 37
XDP XDP
XDP 1 J1850.51:5mm
1 U1100.W40:20MM 1
PLACE_NEAR=J1850.40:2.54mm R1867 1 U1100.W39:21MM R1869 R1866
71 12 IN PM_RSMRST_PCH_L R1884 1K 1 2 XDP_PCH_S5_PWRGD PWRGD/HOOK0 40 39
NC ITPCLK/HOOK4 R1868
5% 1/20W MF 201
42 41 XDP 100 100 100 51
XDP_PCH_PWRBTN_L HOOK1 NC ITPCLK#/HOOK5 5% 5% 5%
XDP 44 43
R1870 1K 1 2 PM_PCH_PWROK IN 12 20 39 71 1/20W
5%
1/20W 1/20W 1/20W
VCC_OBS_AB VCC_OBS_CD MF MF MF
44 18 12 OUT PM_PWRBTN_L R1885 0 1 2 5% 1/20W MF 201
2 201
MF
2 201 2 201
HOOK2 46 45 RESET#/HOOK6 XDP_PM_PCH_PWROK 2 201
PLACE_NEAR=U5000.J3:2.54mm 5% 1/20W MF 0201
NC
HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L
NC OUT 6 18 19
50 49
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 47 18
47 18
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52
54
51
53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
IN 11 18 88
SYNC_MASTER=MASTER SYNC_DATE=04/21/2013 A
IN PAGE TITLE
TCK1 56 55 TDI XDP_PCH_TDI
88 18 11 XDP_PCH_TCK TCK0
NC
58 57
TMS XDP_PCH_TMS
OUT 11 18 88
11 18 88
CPU & PCH XDP
OUT OUT
60 59
DRAWING NUMBER SIZE
XDP_PRESENT#
XDP XDP Apple Inc. 051-9889 D
REVISION
C1880 1 1
C1881 R
0.1UF
64 63
0.1UF 13.0.0
20%
10V
20%
10V NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 2
CERM
402 998-2516 CERM
402 THE INFORMATION CONTAINED HEREIN IS THE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH Reset Button

System 25MHz Clock Generator 80 =PP3V3_S0_PCH
1
R1995
VDD must be powered if any VDDIO is. 4.7K
5%
ENET > S0 > TBT, so ENET is used here. XDP 1/16W
MF-LF
GreenClk 25MHz Power =PP3V3_ENET_SYSCLK
80
R1996 2
402
0
18 6 IN XDP_DBRESET_L 1 2 PM_SYSRST_L OUT 12 44
D Ethernet XTAL Power

SB XTAL Power
80
80 11
=PPVDDIO_ENET_CLK
=PP1V5_S0_PCH_CLK
5%
1/16W
MF-LF 1
OMIT
R1997
D
402
TBT XTAL Power 80 =PPVDDIO_TBT_CLK 0
5%
1/16W
MF-LF
402
2
C1924 1
C1922 1
C1920 1 1
C1902 SILK_PART=SYS RESET
VDD 2
VDDIO_A 6
VDDIO_B 3
VDDIO_C 7
0.1UF 0.1UF 0.1UF 1UF
20% 20% 20% 10%
10V 10V 10V 6.3V
CERM 2 CERM 2 CERM 2 2 CERM
402 402 402 402
U1900
C1905 SLG3NB146V
12PF R1905 TDFN
0 CRITICAL
1 2 89 SYSCLK_CLK25M_X2 1 2 89 SYSCLK_CLK25M_X2_R 10 XOUT
5%
5% NOSTUFF 1 XIN 25MHZ_A 5 SYSCLK_CLK25M_SB OUT 11 89
1/16W
50V MF-LF 1
R1906 25MHZ_B 4 SYSCLK_CLK25M_ENET_R
1
19 89
C0G-CERM CRITICAL 402
0402 NC 1M 25MHZ_C 8 SYSCLK_CLK25M_TBT
Y1905
2 4
OUT 26 89
NC 5%
1/16W
25.000MHZ-20PPM-12PF-85C
C1906 MF-LF
3
9 GND
3.2X2.5MM-SM 402
12PF 2 THRM
PAD
1 2 89 SYSCLK_CLK25M_X1
11
5% NOTE: 30 PPM crystal required
50V
C0G-CERM
0402
RTC Power Sources

C D1900
C
BAT54DW-X-G
SOT-363
PP3V3_G3_RTC 80
MIN_LINE_WIDTH=0.6MM
80 =PP3V3_G3H_RTC_D 1 6 MIN_NECK_WIDTH=0.2MM
Coin-Cell Holder R1902 VOLTAGE=3.3V
1K
PPVBATT_G3_RTC 2 1 PPVBATT_G3_RTC_R 4 3
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1/16W VOLTAGE=3.3V
MF-LF
NC
5 NC NC 2 NC
402
1
J1900
BB10201-C1403-7H
2 SM
511S0054 TP1900 TP1901

1.97X2.02MM-NSP 1.97X2.02MM-NSP
SMT-PAD SMT-PAD
1 1
OMIT OMIT
Place TP1901-TP1903 on bottom side
TP1902 TP1903
1.4-SQ-NSP 1.4-SQ-NSP
SM-PAD SM-PAD
45 11 RTC_RESET_L 1 1
OMIT OMIT
B PCH ME Disable Strap B

PCH RTC Crystal PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
PLACE_NEAR=Y1910.4:2MM
SMC controls strap enable to allow in-field control of strap setting.
C1910
R1910 12PF
0 1 2
89 11 IN PCH_CLK32K_RTCX2 1 2 89 PCH_CLK32K_RTCX2_R
5%
1/16W 5%
R19111 =PP3V3_S5_PCH
50V
MF-LF CRITICAL C0G-CERM 80 20
4
402
10M Y1910 0402
5% 32.768K-12.5PF
1/16W SM-HF 2
MF-LF C1911
1
402
2 12PF
1 2 SPI_DESCRIPTOR_OVERRIDE_L S SOT23-3-HF
89 11 OUT PCH_CLK32K_RTCX1 44 IN 1 NTR1P02L
G
5%
Q1920
50V
C0G-CERM
0402
D
PLACE_NEAR=Y1910.1:2MM 3
PLACE_NEAR=R1113.2:15MM
R1921
Clock series termination SPI_DESCRIPTOR_OVERRIDE_R 330 1
5%
2 HDA_SDOUT_R
1/16W MF-LF 402
OUT 11 89
R1955
33
89 11 IN LPC_CLK33M_SMC_R PLACE_NEAR=U1100:10MM 1 2 LPC_CLK33M_SMC OUT 44 89
A 5%
1/16W
MF-LF
402 R1956 SYNC_MASTER=J17 SYNC_DATE=04/21/2013 A
33 PAGE TITLE
LPC_CLK33M_LPCPLUS_R PLACE_NEAR=U1100:10MM 1 2 LPC_CLK33M_LPCPLUS
89 11 IN
5%
OUT 46 89
Chipset Support
1/16W DRAWING NUMBER SIZE
MF-LF
R1959 402 051-9889 D
89 11 PCH_CLK33M_PCIOUT PLACE_NEAR=U1100:13MM 1
33
2 PCH_CLK33M_PCIIN 11 89
Apple Inc. REVISION
IN OUT
5%
1/16W
R
13.0.0
R1958 MF-LF NOTICE OF PROPRIETARY PROPERTY: BRANCH
33 402
89 19 SYSCLK_CLK25M_ENET_R 1 2 SYSCLK_CLK25M_ENET OUT 35 89 THE INFORMATION CONTAINED HEREIN IS THE
PLACE_NEAR=U1900.4:10MM
5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W
MF-LF
402
19 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections

R2081
33
12 IN PLT_RESET_L 1 2 DEBUG_RESET_L OUT 46
MAKE_BASE=TRUE
5%
1/16W
Unbuffered MF-LF
402
R2055
33
D
1
5%
2 SMC_LRESET_L
MAKE_BASE=TRUE
OUT 44 91
D
1/16W
MF-LF
402
R2094
33
1 2 PCA9557D_RESET_L OUT 21 22
5%
1/16W
MF-LF
402
R2095
33
1 2 SSD_RESET_L OUT 33
5%
1/16W
MF-LF
Buffered 402
80 =PP3V3_S0_RSTBUF
CRITICAL
MC74VHC1G08 EXT_GPU:YES
5 SOT23-5-HF
1 R2090
4
33
PLT_RST_BUF_L 1 2 GPU_RESET_L
2
U2080 OUT 72 78
5%
1/16W
1
3 R2080 MF-LF
402
C2080 1 100K
0.1UF 5%
1/16W
R2091
20% MF-LF 33
C
10V
CERM
402
2 2 402
1
5%
1/16W
2 TBT_PLT_RST_L
MAKE_BASE=TRUE
=TBT_RESET_L OUT 28
C
MF-LF
402
R2088
33
1 2 AP_RESET_L OUT 32
5%
1/16W
MF-LF
402
R2092
33
GPIO Glitch Prevention 1
5%
1/16W
2 ENET_SD_RESET_L OUT 37
MF-LF
402
80 20 19 =PP3V3_S5_PCH
R2093
33
C2040 1 1 2 BT_RESET_MASK_L OUT 32
0.1UF 5%
10% 1/16W
6.3V MF-LF
CERM-X5R 2
402
0201
CRITICAL
5 TC7SZ08FEAPE
12 AUD_IPHS_SWITCH_EN_PCH 2 SOT665
IN A
4 AUD_IPHS_SWITCH_EN
U2040Y OUT 56
JTAG GPIO Isolation due to glitch in and out of sleep
71 39 20 18 12 PM_PCH_PWROK 1
B
NOTE: TCK from PCH is Push-Pull CMOS
3
NOTE: TMS/TDI from PCH is Open Drain
=PP3V3_TBT_PCH_GPIO 80
NOTE: TDO from CR is Push-Pull CMOS
B CRITICAL
Q2060 1
R2063
B
DMN5L06VK-7 10K
2
5%
1/20W
G
SOT-563
MF
80 20 19 =PP3V3_S5_PCH 2 201
S
14 IN JTAG_TBT_TMS_PCH JTAG_TBT_TMS OUT 26 95
1
CRITICAL 8 1
C2050
0.1UF CRITICAL
VCC 20%
U2050
SOT833
2
10V
CERM Q2060
1
R2061
402
08 DMN5L06VK-7 10K
5
5%
74LVC2G08GT/S505
ENET_LOW_PWR_PCH 1 7 ENET_LOW_PWR
A1 Y1 1/20W
G
12 IN OUT 35 37 SOT-563
MF
PM_PCH_PWROK 2
71 39 20 18 12 IN
5
B1 3
2 201
TBT_PWR_EN_PCH TBT_PWR_EN
13 IN A2 Y2 OUT 20 26
S
6 14 IN JTAG_ISP_TDI JTAG_TBT_TDI OUT 26 95
LPC_PWRDWN_L
B2
3
46 44 12 IN
4
GND
4 CRITICAL 1
Q2062 R2062
DMN32D2LFB4 10K
1
DFN1006H4-3 5%
1/20W
G
SYM_VER_3 MF
2 201
S
80 20 19 =PP3V3_S5_PCH 14 OUT JTAG_ISP_TDO JTAG_TBT_TDO IN 26 95
2
CRITICAL 8 1
C2013
0.1UF
A U2000
VCC
2
10%
16V
X5R-CERM SYNC_MASTER=MASTER SYNC_DATE=04/21/2013 A
SOT833 0201 PAGE TITLE
TBT_PWR_EN goes high for JTAG Programming
08
Project Chipset Support
74LVC2G08GT/S505
TBT_PWR_EN 1 7 JTAG_TBT_TCK
R2060 26 20 IN A1 Y1 OUT 26
JTAG_ISP_TCK 2 R2074 DRAWING NUMBER SIZE

10K
18 14 IN B1 1K
2 1 TBT_CIO_PLUG_EVENT 20 26
26 20 IN TBT_CIO_PLUG_EVENT 5
A2 Y2
3 TBT_CIO_PLUG_EVENT_BUF 2 1 TBT_CIO_PLUG_EVENT_ISOL OUT 14
5% 1/20W MF 201 6 R2074 for current 5% REVISION
B2 1/20W
GND limit if PCH glitches MF

201
R
13.0.0
4 NOTICE OF PROPRIETARY PROPERTY: BRANCH
20 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
D WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
MEMVTT_EN = PLT_RESET_L * PM_SLP_S3_L

MEM S0 "PGOOD" FOR CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
PM_MEM_PWRGD MUST ASSERT MIN 100 NS AFTER MEM_VDDQ RAMPS 80%
80 =PP5V_S4_MEMRESET THIS IS GUARANTEED BY THE 2 V/MS RAMP RATE OF THE FET
80 =PP3V3_S4_PM
R21181 R21151 CRITICAL

10K 100K
5% 5%
1/16W
MF-LF
1/16W
MF-LF
5 U2120
402 2 402 2 74LVC1G07
SC70
81 IN =PM_PGOOD_MEM_S0 2 4 PM_MEM_PWRGD OUT 6 12
22 MEMRESET_ISOL_LS5V_L
NC
=PPVDDQ_S3_MEMRESET 80
CRITICAL C2121 1 1 3
Q2115 D 3 0.01UF NC
20%
SSM6N15AFE 16V
X7R-CERM 2
SOT563
R21161 0402
1K
5%
1 C2116
1/16W 0.1UF
5 G S 4 MF-LF 10%
CRITICAL 402 2 2 16V
X7R-CERM
C Q2116
0402
C
ISOLATE_MEM_5V
1
VESM
G
CRITICAL =MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L
D
6 IN OUT 23 24 85
MAKE_BASE=TRUE
Q2115 D 6
3
2
SSM6N15AFE SSM3K15AMFVAPE
SOT563
2 G S 1
14 IN ISOLATE_CPU_MEM_L
MEMVTT Clamp
Ensures CKE signals are held low in S3
80 =PPDDRVTT_S0_CLAMP
R21501
10 75mA max load @ 0.75V
5%
80 21 =PP3V3_S4_MEMRESET 1/10W 60mW max power
MF-LF
603 2
1 C2110 VTTCLAMP_L
0.01UF MIN_NECK_WIDTH=0.25mm
20% CRITICAL MIN_LINE_WIDTH=0.25mm
2 16V
X7R-CERM 80 21 =PP3V3_S4_MEMRESET
B 0402
R21511 SSM6N15AFE
Q2150 D 6
B
SOT563
6 74LVC1G08
100K
SOT891 5%
71 70 45 44 36 12 IN PM_SLP_S3_L 2 1/16W
MF-LF
U2110 4 MEMVTT_EN OUT 21 70 402 2 2 G S 1
22 20 IN PCA9557D_RESET_L 1 08
NC VTTCLAMP_EN
5 3
NOSTUFF CRITICAL
NOSTUFF
R2112 NC Q2150 D 3
C2151 1
0 SSM6N15AFE
71 44 3 IN ALL_SYS_PWRGD 2 1 SOT563 0.001UF
20%
5% 50V
1/16W CERM 2
MF-LF 0402
402 5 G S 4
70 21 IN MEMVTT_EN
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN

S0 0 1 1 1 1 CPU_MEM_RESET_L 1
1 0 1 1 1 1 1
to 2 0 0 1 1 1 0
A S3
3
4
0
0
0
0
0
1
X
X
1
1
0
0
PAGE TITLE
to 5
6
0
0
1
1
1
1
0 (*)
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 CPU_MEM_RESET_L 1
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
13.0.0
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
21 OF 123
must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. II NOT TO REPRODUCE OR COPY IT
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes CPU-Based Margining VRef Dividers =PPDDR_S3_MEMVREF 80
CPU_MEM_VREFDQ_A_ISOL
Power aliases required by this page:
FETs for CPU isolation during S3 DDRVREF_DAC CRITICAL Always used, regardless
- =PP3V3_S3_VREFMRGN 1
R2225 EN RC’s to avoid drain glitches DDRVREF_DAC of margining option. R2221
- =PPDDR_S3_MEMVREF CRITICAL
100K Q2225 1K
Q2220 VREFMRGN_DQ_A_EN_RC
2
1 2 1%
MEMRESET_ISOL_LS5V_L DMN5L06VK-7
2
Signal aliases required by this page: PLACE_NEAR=C2220.1:2mm
G
21 IN 1/16W
DMN5L06VK-7 DDRVREF_DAC 5% DDRVREF_DAC SOT-563
G
MF-LF
- =I2C_VREFDACS_SCL SOT-563 1/16W
1
C2225 1 R2223 2
402
- =I2C_VREFDACS_SDA R2201 MF-LF

402 2
PLACE_NEAR=R2223.2:1.5MM
0.1UF
D
100K 1 2 PPVREF_S3_MEM_VREFDQ_A 23
D
- =I2C_PCA9557D_SCL CPU_DIMMA_VREFDQ 20%
6
7 IN 5%
1
10V 5% PLACE_NEAR=R2221.2:1mm MIN_NECK_WIDTH=0.2 mm
6
1/20W 2
1
CERM
- =I2C_PCA9557D_SDA MF 402
1/20W
1
201
2
Q2225 pin 6: MF
R2222
201
BOM options provided by this page: 1K
D - DDRVREF_DAC - Stuffs DAC margining circuit.

PLACE_NEAR=Q2220.6:5mm
1
PLACE_NEAR=Q2220.6:2mm
C2220
1%
1/16W
MF-LF
D
CRITICAL 0.022UF 402
2
Q2260 CPU_MEM_VREFDQ_B_ISOL 10%
6.3V
2
2
DMN5L06VK-7 DDRVREF_DAC CRITICAL X5R-CERM
R2220
G
SOT-563 0201
24.9 1
R2245 DDRVREF_DAC R2241
MEM_VREFDQ_A_RC 1 2
100K Q2265 1K
D
CPU_DIMMB_VREFDQ VREFMRGN_DQ_B_EN_RC
2
7 1 2 1% 1%
IN DMN5L06VK-7 1/20W
PLACE_NEAR=C2240.1:2mm
6
1/16W
G
1
DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF-LF
1/16W 201
1
C2245 1 R2243 2
402
NOTE: CPU DAC output step sizes: R2202 MF-LF

402 2
0.1UF
D
100K 1 2 PPVREF_S3_MEM_VREFDQ_B 24
20%
DDR3 (1.5V) 7.70mV per step MIN_LINE_WIDTH=0.3 mm
6
5%
1
10V 5%
1/20W CERM 2 PLACE_NEAR=R2241.2:1mm MIN_NECK_WIDTH=0.2 mm
DDR3L (1.35V) 6.99mV per step CRITICAL MF 402
1/20W
1
201 Q2265 pin 6: MF
R2242
Q2220 2 201
1K
5
DMN5L06VK-7 PLACE_NEAR=Q2260.6:5mm
PLACE_NEAR=Q2260.6:4MM
G
1%
SOT-563 1/16W
1
C2240 MF-LF
402
0.022UF 2
D
7 IN CPU_DIMM_VREFCA CPU_MEM_VREFCA_A_ISOL 10%
6.3V
3
2
4
X5R-CERM
DDRVREF_DAC CRITICAL 0201 R2240
NOTE: CPU has single output for 1
R2265 DDRVREF_DAC 24.9 R2261
VREFCA. Split into two MEM_VREFDQ_B_RC 1 2
100K
VREFMRGN_CA_A_EN_RC
Q2225 1K
signals for independent DAC
5
1 2 1% 1%
DMN5L06VK-7 PLACE_NEAR=C2260.1:2mm 1/20W 1/16W
G
margining support. When CRITICAL DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF-LF
1/16W 201
DAC margining VREFCA ensure Q2260 1
C2265 1 R2263 2
402
R2207 MF-LF
2
5
402
DMN5L06VK-7 0.1UF
D
ISOLATE_CPU_MEM_L is low 100K 1 2 PPVREF_S3_MEM_VREFCA_A
G
23
SOT-563 20%
3
5%
4
10V
to remove short due to CPU. 1/20W CERM 2 5% PLACE_NEAR=R2261.2:1mm MIN_NECK_WIDTH=0.2 mm
MF 1/20W
402 1
201 MF
R2262
D
2 201
1K
3
4
PLACE_NEAR=Q2220.3:2mm 1%
1/16W
1
C2260 MF-LF
C DAC-Based Margining CPU_MEM_VREFCA_B_ISOL

2
0.022UF
10%
6.3V
402
2
C
X5R-CERM
DDRVREF_DAC CRITICAL 0201 R2260
DAC sets voltage level, PCA9557 & FETs enable outputs 1
OMIT R2285 DDRVREF_DAC 24.9 R2281
and disables margining after platform reset. MEM_VREFCA_A_RC 1 2
=PP3V3_S3_VREFMRGN R2218 100K

VREFMRGN_CA_B_EN_RC
Q2265 1K
5
80 22 1 2 1% 1%
SHORT DMN5L06VK-7 PLACE_NEAR=C2280.1:2mm 1/20W 1/16W
G
1 2 PP3V3_S3_VREFMRGN DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF-LF
1/16W 201
1
C2285 1 R2283 2
402
NONE
NONE
VOLTAGE=3.3V
R2208 MF-LF
402 2
PLACE_NEAR=R2283.2:1.5MM
0.1UF
D
NONE DDRVREF_DAC DDRVREF_DAC 100K 20%
1 2 PPVREF_S3_MEM_VREFCA_B 24
402 MIN_LINE_WIDTH=0.3 mm
3
5%
4
C2200 1 1
C2201 1/20W
10V
CERM 2 5%
1/20W
PLACE_NEAR=R2281.2:1mm MIN_NECK_WIDTH=0.2 mm
MF
2.2UF 0.1UF 402 1
20% 10%
201
2
MF
201 R2282
6.3V 6.3V
CERM 2 2 CERM-X5R CRITICAL 1K
402-LF 0201 PLACE_NEAR=Q2260.3:2mm 1%
DDRVREF_DAC (All 4 R’s) 1/16W
8 1
C2280 MF-LF
VDD DDRVREF_DAC 0.022UF 402
2
47 IN =I2C_VREFDACS_SCL 6 SCL
U2200 VOUTA 1 VREFMRGN_DQ_A R2226 332 1 2 VREFMRGN_DQ_A_RDIV R22x6 pin 2: 10%
6.3V
MSOP 1% 1/16W MF-LF 402 2 X5R-CERM
R2280
DAC5574
PLACE_NEAR=Q2225.1:5.5mm
47 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_DQ_B R2246 332 1 2 VREFMRGN_DQ_B_RDIV 0201
1% 1/16W MF-LF 402 PLACE_NEAR=Q2265.4:5.5mm 24.9
MEM_VREFCA_B_RC 1 2
9 A0 VOUTC 4 VREFMRGN_CA_AB R2266 332 1 2 VREFMRGN_CA_A_RDIV PLACE_NEAR=Q2225.1:5.5mm
1% 1/16W MF-LF 402 1%
Addr=0x98(WR)/0x99(RD) PLACE_NEAR=Q2265.4:5.5mm 1/20W
10 A1 VOUTD 5 VREFMRGN_MEMVREG_FBVREF R2286 332 1 2 VREFMRGN_CA_B_RDIV MF
1% 1/16W MF-LF 402 201
GND
3
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!
=PP3V3_S3_VREFMRGN 22 80
CRITICAL
DDRVREF_DAC
B DDRVREF_DAC
CRITICAL C2205
0.1UF
1
DDRVREF_DAC
B
DDRVREF_DAC
16
C2202 1 10%
6.3V B1 U2204 DDRVREF_DAC
2
0.1UF VCC CERM-X5R C2
10% 0201
V+
MAX4253
UCSP
R2214
6.3V
CERM-X5R 2 U2201 C1 VREFMRGN_MEMVREG_BUF 1
33.2K
2 DDRREG_FB OUT 63
0201 PCA9557
QFN C4 1%
C3
(OD) P0 6
NC V- 1/16W
MF-LF
3
A0 P1 7 VREFMRGN_DQ_A_EN B4 402
Addr=0x30(WR)/0x31(RD) 4
A1 P2 9 VREFMRGN_DQ_B_EN
5
A2 P3 10 VREFMRGN_CA_A_EN
P4 11 VREFMRGN_CA_B_EN
P5 12 VREFMRGN_MEMVREG_EN CRITICAL
47 IN =I2C_PCA9557D_SCL 1
SCL P6 13 VREFMRGN_FRAMEBUF_EN DDRVREF_DAC DDRVREF_DAC
=I2C_PCA9557D_SDA 2
SDA P7 14
R2213
1
47 BI NC
100K
THRM RESET* 15 5%
A2
B1 U2204
1/20W MAX4253
PAD GND MF V+ UCSP
201
17
RST* on ’platform reset’ so that system 2 A1 66 VREFMRGN_FRAMEBUF_BUF

watchdog will disable margining. A3 A4 DDRVREF_DAC
V- 1
NOTE: Margining will be disabled across all B4 R2217
1M
soft-resets and sleep/wake cycles. Pins B1 & B4: 5%
1/16W
CKPLUS_WAIVE=unconnected_pins MF-LF
21 20 IN PCA9557D_RESET_L 2
402
DDRVREF_DAC
R2215 1
MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG 100K
5%
1/20W
A DAC Channel: A B C C D
MF
201
2
PCA9557D Pin: 1 2 3 4 5 PAGE TITLE
DDR3 (1.5V) DDR3L (1.35V) DDR3 (1.5V) DDR3L (1.35V)

DDR3 VREF MARGINING
DRAWING NUMBER SIZE
Nominal value 0.750V (DAC: 0x3A = 0.747mV) 0.675V (DAC: 0x34 = 0.670mV) 1.500V (DAC: 0x74 = 1.495V) 1.343V (DAC: 0x68 = 1.341V) NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider REVISION
Margined target: 0.300V - 1.200V (+/- 450mV) 0.275V - 1.075V (+/- 400mV) 1.200V - 1.800V (+/- 300mV) 0.950V - 1.750V (+/- 400mV) R
13.0.0
DAC range: 0.000V - 1.508V (0x00 - 0x75) 0.000V - 1.354V (0x00 - 0x69) 0.000V - 3.004V (0x00 - 0xE9) 0.000V - 2.707V (0x00 - 0xD2) NOTICE OF PROPRIETARY PROPERTY: BRANCH
Margined range: 0.299V - 1.206V (+/- 453mV) 0.269V - 1.083V (+/- 406mV) 1.199V - 1.801V (+/- 301mV) 0.932V - 1.760V (+/- 414mV) PROPRIETARY PROPERTY OF APPLE INC.
VRef current: +901uA - -911uA (- = sourced) +811uA - -816uA (- = sourced) +36uA - -36uA (- = sourced) +28uA - -29uA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 22 OF 123
DAC step size: 7.68mV / step @ output 7.67mV / step @ output 2.575mV / step @ output 3.923mV / step @ output
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVREF_S3_MEM_VREFDQ_A 1 2
22 VREFDQ VSS_0
VOLTAGE=0.75V 3 4
VSS_1
CRITICAL
DQ4 =MEM_A_DQ<4> BI 25
25 BI =MEM_A_DQ<0> 5
DQ0 J2300 DQ5
6 =MEM_A_DQ<5> BI 25
=MEM_A_DQ<1> 7 F-RT-SM 8
25 BI DQ1 VSS_2
2-2013310-1
9 10 =MEM_A_DQS_N<0> BI
VSS_3 DQS0* 25
1 C2330 1 C2331 11
DM0 DQS0
12 =MEM_A_DQS_P<0> BI 25
2.2UF 0.1UF 13
VSS_4 VSS_5
14
20% 20%
2 6.3V
CERM 2 10V
CERM 25 BI =MEM_A_DQ<2> 15
DQ2 DQ6
16 =MEM_A_DQ<6> BI 25
402-LF 402 =MEM_A_DQ<3> 17 18 =MEM_A_DQ<7>
25 BI DQ3 DQ7 BI 25
19 20
VSS_6 VSS_7
=MEM_A_DQ<8> 21 22 =MEM_A_DQ<12>
25 BI DQ8 DQ12 BI 25
=MEM_A_DQ<9> 23 24 =MEM_A_DQ<13>
D 25 BI =MEM_A_DQS_N<1>
25
27
VSS_8
DQS1*
VSS_9
DM1
26
28 D
=MEM_A_DQS_P<1> 29 30 MEM_RESET_L
25 BI DQS1 RESET* IN 21 24 85
31 32
VSS_10 VSS_11
=MEM_A_DQ<10> 33 34 =MEM_A_DQ<14>
25 BI DQ10 DQ14 BI 25
=MEM_A_DQ<11> 35 36 =MEM_A_DQ<15>
25 BI DQ11 DQ15 BI 25
37 38
VSS_12 VSS_13
=MEM_A_DQ<16> 39 40 =MEM_A_DQ<20>
25 BI DQ16 DQ20 BI 25
=MEM_A_DQ<17> 41 42 =MEM_A_DQ<21>
25 BI DQ17 DQ21 BI 25
43 44
VSS_14 VSS_15
=MEM_A_DQS_N<2> 45 46
25 BI DQS2* DM2
=MEM_A_DQS_P<2> 47 48
25 BI DQS2 VSS_16
49 50 =MEM_A_DQ<22>
VSS_17 DQ22 BI 25
=MEM_A_DQ<18> 51 52 =MEM_A_DQ<23>
25 BI DQ18 DQ23 BI 25
=MEM_A_DQ<19> 53 54
25 BI DQ19 VSS_18
55 56 =MEM_A_DQ<28>
VSS_19 DQ28 BI 25
=MEM_A_DQ<24> 57 58 =MEM_A_DQ<29>
25 BI DQ24 DQ29 BI 25
=MEM_A_DQ<25> 59 60
25 BI DQ25 VSS_20
61 62 =MEM_A_DQS_N<3> BI
VSS_21 DQS3* 25
63 64 =MEM_A_DQS_P<3> BI
DM3 DQS3 25
65 66
VSS_22 VSS_23
=MEM_A_DQ<26> 67 68 =MEM_A_DQ<30>
25 BI DQ26 DQ30 BI 25
=MEM_A_DQ<27> 69 70 =MEM_A_DQ<31>
25 BI DQ27 DQ31 BI 25
71 72
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) VSS_24
KEY
VSS_25
MEM_A_CKE<0> 73 74 MEM_A_CKE<1>
85 7 IN CKE0 CKE1 IN 7 85
=PPVDDQ_S3_MEM_A 75 76 =PPVDDQ_S3_MEM_A
80 23 VDD_0 VDD_1 23 80
77 78
C 1 C2310 1 C2311 1 C2312 1 C2313 1 C2314 1 C2315 1 C2316 1 C2317 1 C2302
85 7 IN MEM_A_BA<2>
NC
79
NC_0
BA2
A15
A14
80
MEM_A_A<15>
MEM_A_A<14>
IN
IN
7 85
7 85
C
81 82
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VDD_2 VDD_3 1 C2300 1 C2301 1 C2318 1 C2319 1 C2320 1 C2321 1 C2322
20% 20% 20% 20% 20% 20% 20% 20% 20% MEM_A_A<12> 83 84 MEM_A_A<11> 1 C2323 1 C2324
2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V
85 7 IN A12/BC* A11 IN 7 85
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402 MEM_A_A<9> 85
A9 A7
86 MEM_A_A<7> 20% 20% 20% 20% 20% 20% 20% 0.1UF 0.1UF
2 6.3V 2 6.3V 2 10V 2 10V 2 10V 2 10V 2 10V
85 7 IN IN 7 85
20% 20%
87 88 X5R X5R CERM CERM CERM CERM CERM 2 10V 2 10V
VDD_4 VDD_5 603 603 402 402 402 402 402 CERM CERM
MEM_A_A<8> 89 90 MEM_A_A<6> 402 402
85 7 IN A8 A6 IN 7 85
MEM_A_A<5> 91 92 MEM_A_A<4>
85 7 IN A5 A4 IN 7 85
93 94
VDD_6 VDD_7
MEM_A_A<3> 95 96 MEM_A_A<2>
85 7 IN A3 A2 IN 7 85
MEM_A_A<1> 97 98 MEM_A_A<0>
85 7 IN A1 A0 IN 7 85
99 100
VDD_8 VDD_9
MEM_A_CLK_P<0> 101 102 MEM_A_CLK_P<1>
85 7 IN CK0 CK1 IN 7 85
MEM_A_CLK_N<0> 103 104 MEM_A_CLK_N<1>

85 7 IN CK0* CK1* IN 7 85
105 106
VDD_10 VDD_11
MEM_A_A<10> 107 108 MEM_A_BA<1>
85 7 IN A10_AP BA1 IN 7 85
MEM_A_BA<0> 109 110 MEM_A_RAS_L

85 7 IN BA0 RAS* IN 7 85
111 112
VDD_12 VDD_13
MEM_A_WE_L 113 114 MEM_A_CS_L<0>
85 7 IN WE* S0* IN 7 85
MEM_A_CAS_L 115 116 MEM_A_ODT<0>

85 7 IN CAS* ODT0 IN 7 85
117 118
VDD_14 VDD_15
MEM_A_A<13> 119 120 MEM_A_ODT<1>
85 7 IN A13 ODT1 IN 7 85
MEM_A_CS_L<1> 121 122

85 7 IN S1* NC_1 NC
123 124
VDD_16 VDD_17
125 126 PPVREF_S3_MEM_VREFCA_A
NC TEST VREFCA 22
127 128 VOLTAGE=0.75V
VSS_26 VSS_27
=MEM_A_DQ<32> 129 130 =MEM_A_DQ<36>
B
25
25
BI
BI =MEM_A_DQ<33> 131
133
DQ32
DQ33
DQ36
DQ37
132
134
=MEM_A_DQ<37>
BI
BI
25
25
1 C2335
2.2UF
1 C2336
0.1UF
B
VSS_28 VSS_29 20% 20%
=MEM_A_DQS_N<4> 135 136 2 6.3V 2 10V
25 BI DQS4* DM4 CERM CERM
=MEM_A_DQS_P<4> 137 138 402-LF 402
25 BI DQS4 VSS_30
139 140 =MEM_A_DQ<38>
VSS_31 DQ38 BI 25
MEM_A_SA<1> =MEM_A_DQ<34> 141 142 =MEM_A_DQ<39>

23 25 BI DQ34 DQ39 BI 25
=MEM_A_DQ<35> 143 144

MEM_A_SA<0> 25 BI DQ35 VSS_32
23 145 146 =MEM_A_DQ<44>
VSS_33 DQ44 BI 25
=PPSPD_S0_MEM_A =MEM_A_DQ<40> 147 148 =MEM_A_DQ<45>

80 23 25 BI DQ40 DQ45 BI 25
=MEM_A_DQ<41> 149 150

1 1 25 BI DQ41 VSS_34
1 C2340 R2340 R2341 151
VSS_35 DQS5*
152 =MEM_A_DQS_N<5>BI 25
2.2UF 10K 10K 153 154
20% 5% 5% DM5 DQS5 =MEM_A_DQS_P<5>BI 25
1/16W 1/16W
2 6.3V
CERM MF-LF MF-LF 155
VSS_36 VSS_37
156
402-LF 2 402 2 402 =MEM_A_DQ<42> 157 158 =MEM_A_DQ<46>
25 BI DQ42 DQ46 BI 25
=MEM_A_DQ<43> 159 160 =MEM_A_DQ<47>

25 BI DQ43 DQ47 BI 25
=PPDDRVTT_S0_MEM_A
161 162 23 80
80 23 =PPDDRVTT_S0_MEM_A VSS_38 VSS_39

=MEM_A_DQ<48> 163 164 =MEM_A_DQ<52>
25 BI DQ48 DQ52 BI 25
=MEM_A_DQ<49> 165 166 =MEM_A_DQ<53>

25 BI DQ49 DQ53 BI 25
167 168
VSS_40 VSS_41
25 BI =MEM_A_DQS_N<6> 169
DQS6* DM6
170 1 C2350 1 C2351 1 C2352 1 C2353
25 BI =MEM_A_DQS_P<6> 171
DQS6 VSS_42
172 1UF 1UF 1UF 1UF
10% 10% 10% 10%
173 174 =MEM_A_DQ<54> 10V
2 X6S-CERM 10V
2 X6S-CERM 10V
2 X6S-CERM 10V
2 X6S-CERM
VSS_43 DQ54 BI 25
=MEM_A_DQ<50> 175 176 =MEM_A_DQ<55> 0402 0402 0402 0402

25 BI DQ50 DQ55 BI 25
=MEM_A_DQ<51> 177 178

25 BI DQ51 VSS_44
179 180 =MEM_A_DQ<60>
VSS_45 DQ60 BI 25
=MEM_A_DQ<56> 181 182 =MEM_A_DQ<61>

A 25
25
BI
BI =MEM_A_DQ<57> 183
DQ56
DQ57
DQ61
VSS_46
184
BI 25
SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
185 186 =MEM_A_DQS_N<7>BI PAGE TITLE
VSS_47 DQS7* 25
187
189
DM7 DQS7
188
190
=MEM_A_DQS_P<7>BI 25 DDR3 SO-DIMM Connector A
VSS_48 VSS_49 DRAWING NUMBER SIZE
25 BI =MEM_A_DQ<58> 191
DQ58 DQ62
192 =MEM_A_DQ<62> BI 25
=MEM_A_DQ<59> 193 194 =MEM_A_DQ<63> REVISION
25 BI DQ59 DQ63 BI 25
195
VSS_50 VSS_51
196 R
13.0.0
MEM_A_SA<0> 197 198 MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
23 SA0 EVENT* OUT 24 44 45
=PPSPD_S0_MEM_A 199 200 =I2C_SODIMMA_SDA THE INFORMATION CONTAINED HEREIN IS THE

80 23 VDDSPD SDA BI 47
MEM_A_SA<1> 201 202 =I2C_SODIMMA_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
23 SA1 SCL IN 47
203
VTT_0 VTT_1
204 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
23 OF 123
205 206 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG_PIN MTG_PIN
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVREF_S3_MEM_VREFDQ_B 1 2
22 VREFDQ VSS_0
VOLTAGE=0.75V
3 CRITICAL 4
VSS_1 DQ4 =MEM_B_DQ<4> BI 25
25 BI =MEM_B_DQ<0> 5
DQ0 J2500 DQ5
6 =MEM_B_DQ<5> BI 25
=MEM_B_DQ<1> 7 F-RT-SM 8
1 C2530 1 C2531 25 BI DQ1 VSS_2
2-2013289-1
9 10 =MEM_B_DQS_N<0> BI
2.2UF 0.1UF VSS_3 DQS0* 25
20% 20% 11 12 =MEM_B_DQS_P<0> BI
6.3V
2 CERM 10V
2 CERM DM0 DQS0 25
13 14
402-LF 402 VSS_4 VSS_5
=MEM_B_DQ<2> 15 16 =MEM_B_DQ<6>
25 BI DQ2 DQ6 BI 25
=MEM_B_DQ<3> 17 18 =MEM_B_DQ<7>
25 BI DQ3 DQ7 BI 25
19 20
VSS_6 VSS_7
=MEM_B_DQ<8> 21 22 =MEM_B_DQ<12>
=MEM_B_DQ<9> 23 24 =MEM_B_DQ<13>
D 25 BI =MEM_B_DQS_N<1>
25
27
VSS_8
DQS1*
VSS_9
DM1
26
28 D
=MEM_B_DQS_P<1> 29 30 MEM_RESET_L
25 BI DQS1 RESET* IN 21 23 85
31 32
VSS_10 VSS_11
=MEM_B_DQ<10> 33 34 =MEM_B_DQ<14>
25 BI DQ10 DQ14 BI 25
=MEM_B_DQ<11> 35 36 =MEM_B_DQ<15>
25 BI DQ11 DQ15 BI 25
37 38
VSS_12 VSS_13
=MEM_B_DQ<16> 39 40 =MEM_B_DQ<20>
25 BI DQ16 DQ20 BI 25
=MEM_B_DQ<17> 41 42 =MEM_B_DQ<21>
25 BI DQ17 DQ21 BI 25
43 44
VSS_14 VSS_15
=MEM_B_DQS_N<2> 45 46
25 BI DQS2* DM2
=MEM_B_DQS_P<2> 47 48
25 BI DQS2 VSS_16
49 50 =MEM_B_DQ<22>
VSS_17 DQ22 BI 25
=MEM_B_DQ<18> 51 52 =MEM_B_DQ<23>
25 BI DQ18 DQ23 BI 25
=MEM_B_DQ<19> 53 54
25 BI DQ19 VSS_18
55 56 =MEM_B_DQ<28>
VSS_19 DQ28 BI 25
=MEM_B_DQ<24> 57 58 =MEM_B_DQ<29>
25 BI DQ24 DQ29 BI 25
=MEM_B_DQ<25> 59 60
25 BI DQ25 VSS_20
61 62 =MEM_B_DQS_N<3> BI
VSS_21 DQS3* 25
63 64 =MEM_B_DQS_P<3> BI
DM3 DQS3 25
65 66
VSS_22 VSS_23
=MEM_B_DQ<26> 67 68 =MEM_B_DQ<30>
25 BI DQ26 DQ30 BI 25
=MEM_B_DQ<27> 69 70 =MEM_B_DQ<31>
25 BI DQ27 DQ31 BI 25
71 72
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) VSS_24
KEY
VSS_25
MEM_B_CKE<0> 73 74 MEM_B_CKE<1>
85 7 IN CKE0 CKE1 IN 7 85
=PPVDDQ_S3_MEM_B 75 76 =PPVDDQ_S3_MEM_B
80 24 VDD_0 VDD_1 24 80
77 78
C 1 C2510 1 C2511 1 C2512 1 C2513 1 C2514 1 C2515 1 C2516 1 C2517 1 C2502
85 7 IN MEM_B_BA<2>
NC
79
NC_0
BA2
A15
A14
80
MEM_B_A<15>
MEM_B_A<14>
IN
IN
7 85
7 85
C
81 82 1 C2500 1 C2501 1 C2518 1 C2519 1 C2520 1 C2521 1 C2522
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VDD_2 VDD_3 1 C2523 1 C2524
20% 20% 20% 20% 20% 20% 20% 20% 20% MEM_B_A<12> 83 84 MEM_B_A<11> 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
85 7 IN
85
A12/BC* A11
86
IN 7 85
20% 20% 20% 20% 20% 20% 20% 0.1UF 0.1UF
402 402 402 402 402 402 402 402 402 MEM_B_A<9> A9 A7 MEM_B_A<7> 2 6.3V
X5R 2 6.3V
X5R 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
20% 20%
2 10V 2 10V
85 7 IN IN 7 85
87 88 603 603 402 402 402 402 402 CERM CERM
VDD_4 VDD_5 402 402
MEM_B_A<8> 89 90 MEM_B_A<6>
85 7 IN A8 A6 IN 7 85
MEM_B_A<5> 91 92 MEM_B_A<4>
85 7 IN A5 A4 IN 7 85
93 94
VDD_6 VDD_7
MEM_B_A<3> 95 96 MEM_B_A<2>
85 7 IN A3 A2 IN 7 85
MEM_B_A<1> 97 98 MEM_B_A<0>
85 7 IN A1 A0 IN 7 85
99 100
VDD_8 VDD_9
MEM_B_CLK_P<0> 101 102 MEM_B_CLK_P<1>
85 7 IN CK0 CK1 IN 7 85
MEM_B_CLK_N<0> 103 104 MEM_B_CLK_N<1>

85 7 IN CK0* CK1* IN 7 85
105 106
VDD_10 VDD_11
MEM_B_A<10> 107 108 MEM_B_BA<1>
85 7 IN A10_AP BA1 IN 7 85
MEM_B_BA<0> 109 110 MEM_B_RAS_L

85 7 IN BA0 RAS* IN 7 85
111 112
VDD_12 VDD_13
MEM_B_WE_L 113 114 MEM_B_CS_L<0>
85 7 IN WE* S0* IN 7 85
MEM_B_CAS_L 115 116 MEM_B_ODT<0>

85 7 IN CAS* ODT0 IN 7 85
117 118
VDD_14 VDD_15
MEM_B_A<13> 119 120 MEM_B_ODT<1>
=PPSPD_S0_MEM_B 85 7 IN A13 ODT1 IN 7 85
80 24 121 122
85 7 IN MEM_B_CS_L<1> S1* NC_1 NC
123 124
VDD_16 VDD_17
125 126 PPVREF_S3_MEM_VREFCA_B
NC TEST VREFCA 22
127 128 VOLTAGE=0.75V
VSS_26 VSS_27
1 =MEM_B_DQ<32> 129 130 =MEM_B_DQ<36>
R2541
B 10K
5%
25
25
BI
BI =MEM_B_DQ<33> 131
133
DQ32
DQ33
DQ36
DQ37
132
134
=MEM_B_DQ<37>
BI
BI
25
25
1 C2535 C2536
2.2UF
1
0.1UF
20%
B
1/16W VSS_28 VSS_29
MF-LF 135 136
20% 2 10V
2 402 25 BI =MEM_B_DQS_N<4> DQS4* DM4 2 6.3V
CERM
CERM
402
=MEM_B_DQS_P<4> 137 138 402-LF
25 BI DQS4 VSS_30
139 140 =MEM_B_DQ<38>
VSS_31 DQ38 BI 25
MEM_B_SA<1> =MEM_B_DQ<34> 141 142 =MEM_B_DQ<39>

24 25 BI DQ34 DQ39 BI 25
=MEM_B_DQ<35> 143 144

MEM_B_SA<0> 25 BI DQ35 VSS_32
24 145 146 =MEM_B_DQ<44>
VSS_33 DQ44 BI 25
=MEM_B_DQ<40> 147 148 =MEM_B_DQ<45>

25 BI DQ40 DQ45 BI 25
=MEM_B_DQ<41> 149 150

1 25 BI DQ41 VSS_34
R2540 151
VSS_35 DQS5*
152 =MEM_B_DQS_N<5>BI 25
10K 153 154
5% DM5 DQS5 =MEM_B_DQS_P<5>BI 25
1/16W 155 156
MF-LF VSS_36 VSS_37
2 402 =MEM_B_DQ<42> 157 158 =MEM_B_DQ<46>
25 BI DQ42 DQ46 BI 25
=PPDDRVTT_S0_MEM_B =MEM_B_DQ<43> 159 160 =MEM_B_DQ<47> =PPDDRVTT_S0_MEM_B

80 24 25 BI DQ43 DQ47 BI 25 24 80
161 162
VSS_38 VSS_39
=MEM_B_DQ<48> 163 164 =MEM_B_DQ<52>
25 BI DQ48 DQ52 BI 25
25 BI =MEM_B_DQ<49> 165
DQ49 DQ53
166 =MEM_B_DQ<53> BI 25
1 C2550 1 C2551 1 C2552 1 C2553
167
VSS_40 VSS_41
168 1UF 1UF 1UF 1UF
10% 10% 10% 10%
=MEM_B_DQS_N<6> 169 170 2 10V 2 10V 2 10V 2 10V
25 BI DQS6* DM6 X6S-CERM X6S-CERM X6S-CERM X6S-CERM
=MEM_B_DQS_P<6> 171 172 0402 0402 0402 0402
25 BI DQS6 VSS_42
173 174 =MEM_B_DQ<54>
VSS_43 DQ54 BI 25
=MEM_B_DQ<50> 175 176 =MEM_B_DQ<55>

=PPSPD_S0_MEM_B 25 BI DQ50 DQ55 BI 25
80 24
=MEM_B_DQ<51> 177 178
25 BI DQ51 VSS_44
179 180 =MEM_B_DQ<60>
1 C2540 =MEM_B_DQ<56> 181
VSS_45 DQ60
182 =MEM_B_DQ<61>
BI 25
A 2.2UF
20%
2 6.3V
25
25
BI
BI =MEM_B_DQ<57> 183
DQ56
DQ57
DQ61
VSS_46
184
BI 25
CERM 185 186 =MEM_B_DQS_N<7>BI PAGE TITLE
402-LF VSS_47 DQS7* 25
187
189
DM7 DQS7
188
190
=MEM_B_DQS_P<7>BI 25 DDR3 SO-DIMM CONNECTOR B
VSS_48 VSS_49 DRAWING NUMBER SIZE
25 BI =MEM_B_DQ<58> 191
DQ58 DQ62
192 =MEM_B_DQ<62> BI 25
=MEM_B_DQ<59> 193 194 =MEM_B_DQ<63> REVISION
25 BI DQ59 DQ63 BI 25
195
VSS_50 VSS_51
196 R
13.0.0
MEM_B_SA<0> 197 198 MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
24 SA0 EVENT* OUT 23 44 45
=PPSPD_S0_MEM_B 199 200 =I2C_SODIMMB_SDA THE INFORMATION CONTAINED HEREIN IS THE

80 24 VDDSPD SDA BI 47
MEM_B_SA<1> 201 202 =I2C_SODIMMB_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
24 SA1 SCL IN 47
203
VTT_0 VTT_1
25 OF 123
205 206 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG_PIN MTG_PIN
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THERE ARE NO PIN SWAPS
85 7 MEM_A_DQS_N<0> =MEM_A_DQS_N<0> 23 85 7 MEM_B_DQS_N<0> =MEM_B_DQS_N<0> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
85 7 MEM_A_DQS_P<0> =MEM_A_DQS_P<0> 23 85 7 MEM_B_DQS_P<0> =MEM_B_DQS_P<0> 24
85 7 MEM_A_DQ<7> =MEM_A_DQ<7> 23 85 7 MEM_B_DQ<7> =MEM_B_DQ<7> 24

D 85 7
85 7
MEM_A_DQ<2>
MEM_A_DQ<1>
MAKE_BASE=TRUE
=MEM_A_DQ<2>
=MEM_A_DQ<1>
23
23
85 7
85 7
MEM_B_DQ<2>
MEM_B_DQ<1>
MAKE_BASE=TRUE
=MEM_B_DQ<2>
=MEM_B_DQ<1>
24
24
D




C 85 7 MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<16> 23 85 7 MEM_B_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<16> 24 C



B B



A 85 7 MEM_A_DQS_N<7>
MAKE_BASE=TRUE
=MEM_A_DQS_N<7> 23 85 7 MEM_B_DQS_N<7>
MAKE_BASE=TRUE
=MEM_B_DQS_N<7> 24 SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
PAGE TITLE
DDR3 ALIASES AND BITSWAPS
85 7 MEM_A_DQ<63> =MEM_A_DQ<63> 23 85 7 MEM_B_DQ<63> =MEM_B_DQ<63> 24 DRAWING NUMBER SIZE
85 7 MEM_A_DQ<62>
MAKE_BASE=TRUE
=MEM_A_DQ<62> 23 85 7 MEM_B_DQ<62>
MAKE_BASE=TRUE
=MEM_B_DQ<62> 24
85 7 MEM_A_DQ<61> =MEM_A_DQ<61> 23 85 7 MEM_B_DQ<61> =MEM_B_DQ<61> 24 REVISION
85 7 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<60> 23 85 7 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<60> 24
R
13.0.0
85 7 MEM_A_DQ<59> =MEM_A_DQ<59> 23 85 7 MEM_B_DQ<59> =MEM_B_DQ<59> 24 NOTICE OF PROPRIETARY PROPERTY: BRANCH
85 7 MEM_A_DQ<58> =MEM_A_DQ<58> 23 85 7 MEM_B_DQ<58> =MEM_B_DQ<58> 24 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE INC.
85 7 MEM_A_DQ<57> =MEM_A_DQ<57> 23 85 7 MEM_B_DQ<57> =MEM_B_DQ<57> 24 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
85 7 MEM_A_DQ<56>
MAKE_BASE=TRUE
=MEM_A_DQ<56> 23 85 7 MEM_B_DQ<56>
MAKE_BASE=TRUE
=MEM_B_DQ<56> 24
27 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
87 13 IN PCIE_TBT_R2D_C_P<0> C2800 1 2
AB9 OMIT_TABLE AD5
C2840 1 2 PCIE_TBT_D2R_P<0> OUT 13 87
10% 16V X5R-CERM 0201 87 PCIE_TBT_R2D_P<0> PERP_0 PETP_0 87 PCIE_TBT_D2R_C_P<0> 10% 16V X5R-CERM 0201
0.1UF 0.1UF
87 PCIE_TBT_R2D_N<0> AA10
PERN_0 U2800 PETN_0 AD7 87 PCIE_TBT_D2R_C_N<0>
87 13 IN PCIE_TBT_R2D_C_N<0> C2801 1 2
CACTUSRIDGE4C C2841 1 2
PCIE_TBT_D2R_N<0> OUT 13 87
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF FCBGA 0.1UF
(SYM 1 OF 2)
87 13 IN PCIE_TBT_R2D_C_P<1> C2802 1 2 C2842 1 2 PCIE_TBT_D2R_P<1> OUT 13 87
PCIE GEN2
PCIE_TBT_R2D_P<1> AA12 AD9 PCIE_TBT_D2R_C_P<1>
10% 16V X5R-CERM 0201 87 PERP_1 PETP_1 87 10% 16V X5R-CERM 0201
0.1UF AB13 AD11
0.1UF
87 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 87 PCIE_TBT_D2R_C_N<1>
C2803 C2843
RECEIVE
TRANSMIT
87 13 IN PCIE_TBT_R2D_C_N<1> 1 2 1 2
PCIE_TBT_D2R_N<1> OUT 13 87
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF 0.1UF
PCIE_TBT_R2D_C_P<2> C2804 C2844 PCIE_TBT_D2R_P<2>

D
1 2 1 2
87 13 IN OUT 13 87
PCIE_TBT_R2D_P<2> AB15 AD13 PCIE_TBT_D2R_C_P<2>
PERP_2 PETP_2
D 10% 16V X5R-CERM 0201 87 87 10% 16V X5R-CERM 0201
0.1UF AA16 AD15
0.1UF
87 PCIE_TBT_R2D_N<2> PERN_2 PETN_2 87 PCIE_TBT_D2R_C_N<2>
87 13 IN PCIE_TBT_R2D_C_N<2> C2805 1 2 C2845 1 2 PCIE_TBT_D2R_N<2> OUT 13 87
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF 0.1UF
80 70 30 29 28 27 26 =PP3V3_S4_TBT
87 13 IN PCIE_TBT_R2D_C_P<3> C2806 1 2
AA18 AD17
C2846 1 2 PCIE_TBT_D2R_P<3> OUT 13 87
10% 16V X5R-CERM 0201 87 PCIE_TBT_R2D_P<3> PERP_3 PETP_3 87 PCIE_TBT_D2R_C_P<3> 10% 16V X5R-CERM 0201
R2810 1 0.1UF
87 PCIE_TBT_R2D_N<3> AB19
PERN_3 PETN_3 AD19 87 PCIE_TBT_D2R_C_N<3>
0.1UF
47K 87 13 IN PCIE_TBT_R2D_C_N<3> C2807 1 2 C2847 1 2 PCIE_TBT_D2R_N<3> OUT 13 87
5% 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
1/16W 0.1UF 0.1UF
MF-LF R6 U20
402
2
28 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE
TBT_PWR_ON_POC_RST_L J2
28 IN PWR_ON_POC_RSTN W20
RBIAS TBT_RBIAS 1
R2855
NO STUFF NOTE: The following pins require testpoints:
1K
=PP3V3_TBTLC_RTR 26 27 28 80 C2810 1 TP_TBT_MONDC0 AD23
MONDC0 U4 1% 0 - GPIO_13 8 - GPIO_15
0.1UF AC24 NC NC 1/20W
OMIT TP_TBT_MONDC1 MONDC1 MF 1 - GPIO_1 9 - GPIO_11
10%
16V 201
1 2
X7R-CERM 2 R2815 DEBUG: For monitoring current/voltage 2 - GPIO_2 10 - GPIO_14
C2890 1
R2892 1
1
R2893
0402 NOSTUFF TBT_MONOBSP W18
MONOBS_P 3 - GPIO_3 11 - GPIO_0
R2890 1
1
R2891 1UF 3.3K 3.3K
NONE
NONE TBT_MONOBSN W16
MONOBS_N 4 - GPIO_5 12 - GPIO_12
3.3K 3.3K 10%
6.3V 5% 5% NONE Not used in host mode.
PCIE RESET
5% 5% 2 1/16W 1/16W 402 2 DEBUG: For monitoring clock 5 - PCIE_RST_1_N 13 - GPIO_10
MISC
CERM N6 TP_TBT_PCIE_RESET0_L
1/16W 1/16W 402 CRITICAL MF-LF MF-LF Y7 PCIE_RST_0_N 82
MF-LF MF-LF 402 402 82 TP_TBT_THERM_DP THERMDA T1 6 - PCIE_RST_2_N 14 - PB_LSTX
402
2 2
402 8 OMIT_TABLE 2 2
Use AA8 GND ball for THERM_DN PCIE_RST_1_N TP_TBT_PCIE_RESET1_L 82
Y5 7 - PCIE_RST_3_N 15 - PB_LSRX
VCC R4 PCIE_RST_2_N TP_TBT_PCIE_RESET2_L 82
95 TBT_SPI_MOSI EE_DI U2
PCIE_RST_3_N TP_TBT_PCIE_RESET3_L
EEPROM
82
5 2 TBT_SPI_MISO P5
(TBT_SPI_MOSI) D U2890 Q (TBT_SPI_MISO) 95 EE_DO
TBT_SPI_CS_L AD3
M95256-RMC6XG 95 EE_CS_N W6
(TBT_SPI_CLK) 6 C MLP
W4 PCIE_CLKREQ_OD_N =TBT_CLKREQ_L OUT 28
95 TBT_SPI_CLK EE_CLK =PP3V3_TBTLC_RTR 26 27 28 80
(TBT_SPI_CS_L) 1 S* K5 TBT_EN_LC_PWR
EN_LC_PWR
JTAG/TEST PORT
V1 OUT 28
95 20 IN JTAG_TBT_TDI TDI 1
R2898
TBTROM_WP_L 3 W* AB3
95 20 IN JTAG_TBT_TMS TMS 10K
REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P 11 87 5%
C
IN
C TBTROM_HOLD_L 7 JTAG_TBT_TCK AA6
HOLD* 20 IN TCK AD21 1/16W
R2 REFCLK_100_IN_N PCIE_CLK100M_TBT_N IN 11 87 MF-LF
VSS THM 95 20 OUT JTAG_TBT_TDO TDO 2
402
R2895
PAD N4
TBT_TEST_EN TEST_EN 806
CLOCKS
4 9 AA24 SYSCLK_CLK25M_TBT_R SYSCLK_CLK25M_TBT
AB5 XTAL_25_IN 89 1 2
IN 19 89
TBT_TEST_PWR_GOOD TEST_PWR_GOOD AB23
XTAL_25_OUT TP_TBT_XTAL25OUT 1%
1/16W Divides 3.3V to 1.8V
MF-LF
1 1
R2825 R2829 95 26 DP_TBTSNK0_ML_P<3> E14
DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT
402
0 0 D13 Y3
5% 5% 95 26 DP_TBTSNK0_ML_N<3> DPSNK0_3_N TMU_CLK_IN TBT_TMU_CLK_IN 80 28 27 26 =PP3V3_TBTLC_RTR
1/16W 1/16W
MF-LF MF-LF E16 NO STUFF
402 2 2 402 95 26 DP_TBTSNK0_ML_P<2> DPSNK0_2_P
TBT_SPI_CLK_RES R28011 2
95 26 DP_TBTSNK0_ML_N<2> D15
DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3> 41
1
R2897 R2899
1 1
R2896 1
R2880
DISPLAYPORT
0
SINK PORT 0
5% 1/20W
B15
100K 10K 1K 10K
MF 0201 E18 DPSRC_3_N TP_DP_TBTSRC_ML_CN<3> 41 5% 5% 5% 5%
95 26 DP_TBTSNK0_ML_P<1> DPSNK0_1_P 1/16W 1/16W 1/16W 1/16W
D17 A12 MF-LF MF-LF MF-LF MF-LF
DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2> 2 402 402 2
2 402
95 26 41 402
2
B13 TP_DP_TBTSRC_ML_CN<2>
E20 DPSRC_2_N 41
DP_TBTSNK0_ML_P<0> DPSNK0_0_P TBT_DDC_XBAR_EN_L
SOURCE PORT 0
95 26 31 26
DP_TBTSNK0_ML_N<0> D19 A10 TP_DP_TBTSRC_ML_CP<1> TBT_GO2SX_BIDIR

95 26 DPSNK0_0_N DPSRC_1_P 41 26 14
B11 TP_DP_TBTSRC_ML_CN<1>
A6 DPSRC_1_N 41 R2881 FOR CYA,
95 26 DP_TBTSNK0_AUXCH_P DPSNK0_AUX_P 1
B5 A8 allows separation R2881
95 26 DP_TBTSNK0_AUXCH_N DPSNK0_AUX_N DPSRC_0_P TP_DP_TBTSRC_ML_CP<0> 41
SNK0 AC Coupling B9 TP_DP_TBTSRC_ML_CN<0>
of GPIO_2/GPIO_9 0
U6 DPSRC_0_N 41 5%
78 OUT DP_TBTSNK0_HPD DPSNK0_HPD if necessary. 1/16W
95 77 IN DP_TBTSNK0_ML_C_P<0> C2820 1 2 DP_TBTSNK0_ML_P<0> 26 95 C2 MF-LF
10% 16V DPSRC_AUX_P TP_DP_TBTSRC_AUXCH_CP 41 STUFF ONE OF R2881/2. 2
402
0.1UF X5R-CERM 0201 E6 D3
R2830 1 95 26 DP_TBTSNK1_ML_P<3> DPSNK1_3_P DPSRC_AUX_N TP_DP_TBTSRC_AUXCH_CN 41
95 77 IN DP_TBTSNK0_ML_C_N<0> C2821 1 2 DP_TBTSNK0_ML_N<0> 26 95 D5 26 TBT_GPIO_9
10% 16V 100K 95 26 DP_TBTSNK1_ML_N<3> DPSNK1_3_N V3
0.1UF X5R-CERM 0201 5% DPSRC_HPD_OD DP_TBTSRC_HPD IN 41 26 TBT_GPIO_14
1/16W E8
MF-LF 95 26 DP_TBTSNK1_ML_P<2> DPSNK1_2_P NO STUFF
95 77 IN DP_TBTSNK0_ML_C_P<1> C2822 1 2 DP_TBTSNK0_ML_P<1> 26 95 402 D7
10% 16V
2
95 26 DP_TBTSNK1_ML_N<2> DPSNK1_2_N Y1
1
R2832 R2883 1
1
R2882
TBT_GO2SX_BIDIR
SINK PORT 1
0.1UF X5R-CERM 0201 GPIO_2/GO2SX BI 14 26
100K 10K 10K
95 77 IN DP_TBTSNK0_ML_C_N<1> C2823 1 2 DP_TBTSNK0_ML_N<1> 26 95 95 26 DP_TBTSNK1_ML_P<1> E10
DPSNK1_1_P (FORCE_PWR) GPIO_3 W2 TBT_PWR_EN IN 20 5% 5% 5%
10% 16V D9 J4 1/16W 1/16W 1/16W
0.1UF DP_TBTSNK1_ML_N<1> DPSNK1_1_N GPIO_4/WAKE_N_OD =TBT_WAKE_L
B 95 77 IN DP_TBTSNK0_ML_C_P<2> C2824 1
X5R-CERM 0201
2 DP_TBTSNK0_ML_P<2> 26 95
95 26
95 26 DP_TBTSNK1_ML_P<0> E12
DPSNK1_0_P
GPIO_5/CIO_PLUG_EVENT AA2
AB1
TBT_CIO_PLUG_EVENT
OUT
OUT
12
20
2
MF-LF
402
MF-LF
402
2 2
MF-LF
402
B
10% 16V D11 GPIO_6/CIO_SDA_OD I2C_TBTRTR_SDA 26 95
0.1UF X5R-CERM 0201 95 26 DP_TBTSNK1_ML_N<0> DPSNK1_0_N AC2
GPIO_7/CIO_SCL_OD I2C_TBTRTR_SCL 26 95
95 77 IN DP_TBTSNK0_ML_C_N<2> C2825 1 2 DP_TBTSNK0_ML_N<2> 26 95
A4 P3
10% 16V 95 26 DP_TBTSNK1_AUXCH_P DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* (TBT_EN_CIO_PWR_L) TBT_PWR_REQ_L OUT 12
0.1UF X5R-CERM 0201 B3 M5
95 26 DP_TBTSNK1_AUXCH_N DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* TBT_GPIO_9 26 TBT_EN_CIO_PWR_L OUT 28
MAKE_BASE=TRUE 80 70 30 29 28 27 26 =PP3V3_S4_TBT
95 77 IN DP_TBTSNK0_ML_C_P<3> C2826 1 2
DP_TBTSNK0_ML_P<3> 26 95 T5 GPIO_14 T3 TBT_GPIO_14 26
10% 16V 78 OUT DP_TBTSNK1_HPD DPSNK1_HPD V5
0.1UF X5R-CERM 0201 GPIO_15 TBT_DDC_XBAR_EN_L OUT 26 31
=PP3V3_TBTLC_RTR 26 27 28 80
R2831 1 R2885 1
1
0.1UF
10% 16V
TBT_A_R2D_C_P<0> G24
PA_CIO0_TX_P/DP_SRC_0_P PB_CIO2_TX_P/DP_SRC_0_P R24 TBT_B_R2D_C_P<0> 1 1 R2886
X5R-CERM 0201
100K
95 29 OUT OUT 30 95 R2889 R2894 10K 10K
TBT_A_R2D_C_N<0> E24 N24 TBT_B_R2D_C_N<0> 3.3K 3.3K
5% 95 29 OUT PA_CIO0_TX_N/DP_SRC_0_N PB_CIO2_TX_N/DP_SRC_0_N OUT 30 95 5% 5%
1/16W 5% 5% 1/16W 1/16W
95 77 DP_TBTSNK0_AUXCH_C_P C2828 1 2 DP_TBTSNK0_AUXCH_P 26 95 MF-LF 1/16W 1/16W MF-LF MF-LF
PORT0
PORT2
BI TBT_A_D2R_P<0> G22 R22 TBT_B_D2R_P<0>
10% 16V 402
2
95 29 IN PA_CIO0_RX_P PB_CIO2_RX_P IN 30 95 MF-LF MF-LF 402
2 2
402
0.1UF X5R-CERM 0201 E22 N22 402 402
95 29 IN TBT_A_D2R_N<0> PA_CIO0_RX_N PB_CIO2_RX_N TBT_B_D2R_N<0> IN 30 95
2 2
95 77 BI DP_TBTSNK0_AUXCH_C_N C2829 1 2 DP_TBTSNK0_AUXCH_N 26 95 I2C_TBTRTR_SDA 29 26 TBT_A_DP_PWRDN
10% 16V K1 P1 95 26
0.1UF X5R-CERM 0201 29 OUT TBT_A_CONFIG1_BUF PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO TBT_B_CONFIG1_BUF OUT 30 30 26 TBT_B_DP_PWRDN
TBT_A_CONFIG2_RC G4 H5 TBT_B_CONFIG2_RC I2C_TBTRTR_SCL TBT_A_HV_EN
29 IN PA_CONFIG2/CIO_0_LSOE PB_CONFIG2/CIO_2_LSOE IN 30 95 26 29 26
SNK1 AC Coupling 30 26 TBT_B_HV_EN

TBT_A_R2D_C_P<1> L24 W24 TBT_B_R2D_C_P<1>
95 29 OUT PA_CIO1_TX_P/DP_SRC_2_P PB_CIO3_TX_P/DP_SRC_2_P OUT 30 95
95 77 IN DP_TBTSNK1_ML_C_P<0> C2830 1 2 DP_TBTSNK1_ML_P<0> 26 95
J24 U24
10% 16V 95 29 OUT TBT_A_R2D_C_N<1> PA_CIO1_TX_N/DP_SRC_2_N PB_CIO3_TX_N/DP_SRC_2_N TBT_B_R2D_C_N<1> OUT 30 95 R2888 1 1
R2887
0.1UF X5R-CERM 0201
10K 10K
PORT1
PORT3
95 77 IN DP_TBTSNK1_ML_C_N<0> C2831 1 2 DP_TBTSNK1_ML_N<0> 26 95 95 29 IN TBT_A_D2R_P<1> L22
PA_CIO1_RX_P PB_CIO3_RX_P W22 TBT_B_D2R_P<1> IN 30 95 5% 5%
10% 16V J22 U22 1/16W 1/16W
0.1UF X5R-CERM 0201 95 29 IN TBT_A_D2R_N<1> PA_CIO1_RX_N PB_CIO3_RX_N TBT_B_D2R_N<1> IN 30 95 MF-LF MF-LF
402 402
2 2
95 77 IN DP_TBTSNK1_ML_C_P<1> C2832 1 2 DP_TBTSNK1_ML_P<1> 26 95 29 OUT TBT_A_LSTX N2
PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO L6 TBT_B_LSTX OUT 30
10% 16V J6 G6
0.1UF X5R-CERM 0201 29 IN TBT_A_LSRX PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE TBT_B_LSRX IN 30

10% 16V A16 A20
PORTS
0.1UF X5R-CERM 0201 95 29 OUT DP_TBTPA_ML_C_P<1> PA_DPSRC_1_P PB_DPSRC_1_P DP_TBTPB_ML_C_P<1> OUT 30 95
A DP_TBTPA_ML_C_N<1> B17 B21 DP_TBTPB_ML_C_N<1>

PA_DPSRC_1_N PB_DPSRC_1_N
95 77 IN DP_TBTSNK1_ML_C_P<2> C2834
0.1UF
1 2
10% 16V
X5R-CERM 0201
DP_TBTSNK1_ML_P<2> 26 95
95 29
95 29
OUT
OUT DP_TBTPA_ML_C_P<3> A18

PA_DPSRC_3_P PB_DPSRC_3_P A22 DP_TBTPB_ML_C_P<3>
OUT
OUT
30 95
30 95
SYNC_MASTER=J16_MLB_IG
PAGE TITLE
SYNC_DATE=05/01/2013 A
95 77 IN DP_TBTSNK1_ML_C_N<2> C2835
0.1UF
1 2
10% 16V
X5R-CERM 0201
DP_TBTSNK1_ML_N<2> 26 95 95 29 OUT DP_TBTPA_ML_C_N<3> B19
PA_DPSRC_3_N PB_DPSRC_3_N B23 DP_TBTPB_ML_C_N<3> OUT 30 95
Thunderbolt Host (1 of 2)
F3 D1 DRAWING NUMBER SIZE
DP_TBTPA_AUXCH_C_P PA_AUX_P PB_AUX_P DP_TBTPB_AUXCH_C_P
95 77 IN DP_TBTSNK1_ML_C_P<3> C2836 1 2
10% 16V
DP_TBTSNK1_ML_P<3> 26 95
95 29
95 29
BI
DP_TBTPA_AUXCH_C_N F1
PA_AUX_N PB_AUX_N E2 DP_TBTPB_AUXCH_C_N
BI 30 95
30 95 Apple Inc. 051-9889 D

0.1UF BI BI
X5R-CERM 0201 REVISION
R
95 77 IN DP_TBTSNK1_ML_C_N<3> C2837 1 2 DP_TBTSNK1_ML_N<3> 26 95 29 IN DP_TBTPA_HPD H1
PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 30 13.0.0
10% 16V
0.1UF X5R-CERM 0201
TBT_A_HV_EN G2 M1 TBT_B_HV_EN
29 26 OUT GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 OUT 26 30
M3 L2 THE INFORMATION CONTAINED HEREIN IS THE
29 OUT TBT_A_CIO_SEL GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 TBT_B_CIO_SEL OUT 30 PROPRIETARY PROPERTY OF APPLE INC.
95 77 BI DP_TBTSNK1_AUXCH_C_P C2838 1 2 DP_TBTSNK1_AUXCH_P 26 95 H3 L4 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10% 16V 29 26 OUT TBT_A_DP_PWRDN GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 TBT_B_DP_PWRDN OUT 26 30
0.1UF X5R-CERM 0201 28 OF 123
95 77 BI DP_TBTSNK1_AUXCH_C_N C2839 1 2 DP_TBTSNK1_AUXCH_N 26 95
10% 16V For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
0.1UF X5R-CERM 0201 IV ALL RIGHTS RESERVED 26 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_TBTCIO_RTR 80
CRITICAL
D 80 =PP1V05_TBTLC_RTR
J10 OMIT_TABLE K11
???? mW (Single-Port)
2700 mW (Dual-Port)
D
??? mW (Single Port) VCC1P0_ON VCC1P0
J12 U2800 K15 EDP: 3000 mA
250 mW (Dual Port) VCC1P0_ON VCC1P0
EDP: 1000 mA C2900 1 1
C2910 1
C2911 1
C2912 1
C2913 J14
VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10
C2940 1
C2941 1
C2942 1
C2943 1
C2944 1
C2945 1 1
C2905
10UF 1.0UF 1.0UF 1.0UF 1.0UF J16 FCBGA L14 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
20% 20% 20% 20% 20% VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V J8 M11 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM-X5R 2 2 X5R 2 X5R 2 X5R 2 X5R VCC1P0_ON VCC1P0 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 2 CERM-X5R
0402-1 0201-1 0201-1 0201-1 0201-1 K17 M15 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
VCC1P0_ON VCC1P0
T15 N10
VCC1P0_ON VCC1P0
U14 N14
VCC1P0_ON VCC1P0
V7 P11
VCC1P0_ON VCC1P0
C2901 1 1 C2914 1 C2915 1 C2916 1 C2917 W8
VCC1P0_ON VCC1P0 P15
10UF 1.0UF 1.0UF 1.0UF 1.0UF VCC1P0 R10

20% 20% 20% 20% 20% G10
VCC1P0_PE
VCC
6.3V 6.3V 6.3V 6.3V 6.3V R14
CERM-X5R 2 2 X5R 2 X5R 2 X5R 2 X5R G12 VCC1P0
0402-1 0201-1 0201-1 0201-1 0201-1 VCC1P0_PE T11
G14 VCC1P0
VCC1P0_PE U10
G16 VCC1P0
VCC1P0_PE V11
G18 VCC1P0
VCC1P0_PE W10
=PP3V3_TBTLC_RTR 26 28 80
H19 VCC1P0
VCC1P0_PE ??? mW (Single-Port)
K19
VCC1P0_PE M7 250 mW (Dual-Port)
M19 VCC3P3
VCC1P0_PE P7 EDP: 240 mA
P19 VCC3P3
VCC1P0_PE
T19 VCC3P3 T7
C2970 1
C2971 1
C2972 1
C2973 1
C2974 1 1
C2960
VCC1P0_PE 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
V15 L18 20% 20% 20% 20% 20% 20%
VCC1P0_PE VCC3P3_CIO 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
V19 N18 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 2 CERM-X5R
VCC1P0_PE VCC3P3_CIO 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
W12 R18
VCC1P0_PE VCC3P3_CIO
W14
VCC1P0_PE H11
VCC3P3_DP
C G8
H9
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_DP
VCC3P3_DP
H13
H15 C
H17
VCC3P3_DP
AD1 H7
VSS VCC3P3_DPAUX
K13
VSS
K9
VSS
L12 =PP3V3_S4_TBT
VSS 26 28 29 30 70 80
L16 K7
VSS VCC3P3_POC EDP: 10 mA
L8
VSS
M13
VSS VSSPE C22
C2990 1
M17
VSS VSSPE C24 1.0UF
20%
M9 C4 6.3V
VSS VSSPE X5R 2
N12 C6 0201-1
VSS VSSPE
N16 C8
VSS VSSPE
N8 D21
VSS VSSPE
P13 D23
VSS VSSPE
P17 E4
VSS VSSPE
P9 F11
VSS VSSPE
R12 F13
VSS VSSPE
R16 F15
VSS VSSPE
R8 F17
VSS VSSPE
T13 F19
VSS VSSPE
T17 F21
VSS VSSPE
T9 F23
VSS VSSPE
U12 F5
VSS VSSPE
GND
U16 F7
VSS VSSPE
B U8
V9
VSS
VSS
VSSPE
VSSPE
F9
G20
B
H21
VSSPE
A2 H23
VSSPE VSSPE
A24 J18
VSSPE VSSPE
AA14 J20
VSSPE VSSPE
AA20 K21
VSSPE VSSPE
AA22 K23
VSSPE VSSPE
AA8 L20
VSSPE VSSPE
AB11 M21
VSSPE VSSPE
AB17 M23
VSSPE VSSPE
AB7 N20
VSSPE VSSPE
AC10 P21
VSSPE VSSPE
AC12 P23
VSSPE VSSPE
AC14 R20
VSSPE VSSPE
AC16 T21
VSSPE VSSPE
AC18 T23
VSSPE VSSPE
AC20 U18
VSSPE VSSPE
AC22 V13
VSSPE VSSPE
AC4 V17
VSSPE VSSPE
AC6 V21
VSSPE VSSPE
AC8 V23
VSSPE VSSPE
B1 Y11
VSSPE VSSPE
B7 Y13
VSSPE VSSPE
C10 Y15
VSSPE VSSPE
C12 Y17
VSSPE VSSPE
A C14
C16
VSSPE
VSSPE
VSSPE
VSSPE
Y19
Y21 SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A

PAGE TITLE
C18
C20
VSSPE
VSSPE
VSSPE
VSSPE
Y23
Y9 Thunderbolt Host (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
13.0.0
29 OF 123
EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PPVIN_SW_TBTBST (8-13V Boost Input)
- =PP15V_TBT_REG (15V Boost Output)
- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)
- =PP3V3_TBT_FET (3.3V FET Output)
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)
- =PP1V05_TBT_FET (1.05V FET Output)
Signal aliases required by this page:
D - =TBT_CLKREQ_L
- =TBT_RESET_L
D
BOM options provided by this page:
TBTBST:Y - Stuffs 15V boost circuitry.
Supervisor & CLKREQ# Isolation

=PP3V3_TBTLC_RTR 26 27 28 80
C C
80 =PP3V3_S0_TBTPWRCTL
C3000 1
CRITICAL 1
R3007
1
0.1UF
Q3040 1
R3040 10%
25V
VDD 100K
5%
SSM3K15AMFVAPE 10K X5R 2
U3000 1/16W
G 1
5% 402 MF-LF
VESM 1/16W
SLG4AP016V 2
402
MF-LF
2
402 TDFN PP1V05_TBTLC 80 92
+ SENSE
2
D
26 IN TBT_EN_LC_PWR - 0.7V
3
DLY
RESET* 4 TBT_PCIE_RESET_L OUT 26
20 IN =TBT_RESET_L 3 MR*
DLY = 60 ms +/- 20%
Platform(PCIe) Reset
TBT_EN_LC_ISOL 6 EN
=TBT_CLKREQ_L IN 26
11 OUT TBT_CLKREQ_L 8 OUT
(OD) IN 7 TBT_CLKREQ_ISOL_L
Pull-up provided by SB page. MAKE_BASE=TRUE
THRM
GND PAD
5
TBT "POC" Power-up Reset

Intel investigating whether RC is sufficient.
B 3.3V TBT "LC" Switch 80 70 30 29 27 26 =PP3V3_S4_TBT

B
U3010 SMC_DELAYED_PWRGD IN 44 45 71
=PP3V3_S0_P3V3TBTFET TPS22924 =PP3V3_TBTLC_FET CRITICAL
1
80 80
CSP
A2 A1 Max Current = 2A (85C) Pull-up: R2810
VDD =PP3V3_S0_PCH_GPIO
B2 VIN VOUT B1
14 80
R3011 2 SENSE U3030 RESET* 6 TBT_PWR_ON_POC_RST_L

36.5K2
CRITICAL U3010 TPS3808
OUT 26
1 TBT_EN_LC_RC3V3 C2 ON (IPU)
TBTPOCRST_CT QFN 4 TBTPOCRST_MR_L 1
GND Part TPS22924C 3 CT MR* R3030
C3010 1 1% THRM
1UF
1/16W GND PAD Q3025 100K
C1
5
MF-LF 1 Type Load Switch
10% 402 C3011 1 C3031 C3030 1 SSM6N37FEAPE 5%
G
6.3V 1/16W
7
CERM 2 1UF 0.0047UF 0.1UF SOT563 MF-LF
402 10% R(on) 18.5 mOhm Typ 10% 10% TPS3808G25 2
402
6.3V
CERM 2 @ 2.5V 25.8 mOhm Max 2
25V 25V
2 Vt = 2.33V +/- 2%
S
CERM X5R TBT_SW_RESET_L
402 IN 14
0402 402
Delay = 27.3ms
4
C3025 1
330PF
10%
50V
X7R-CERM 2
0402
1.05V TBT "LC" Switch 80 28 =PP1V05_S0_P1V05TBTFET 1.05V TBT "CIO" Switch

=PP3V3_TBTLC_RTR
U3015 80 28 27 26
U3020
=PP1V05_S0_P1V05TBTFET TPS22924 =PP1V05_TBTLC_FET 80 TPS22920 =PP1V05_TBTCIO_FET
80 28 CSP 80
A2 A1 Max Current = 2A (85C) R3020 1 A2
CSP
A1 Max Current = 4A (85C)
B2 VIN VOUT B1 100K
B2 B1
5% VIN VOUT
R3016 U3015
0
CRITICAL 1/16W
MF-LF C2 C1 U3020
A C3015 1
1
5%
2 TBT_EN_LC_RC1V05 C2 ON
GND Part TPS22924C
402
2
TBT_EN_CIO_PWR D2 ON
CRITICAL
Part TPS22920 SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
1UF
1/16W NOSTUFF PAGE TITLE
C1
GND
10%
6.3V
MF-LF
402 C3016
1UF
1 Type Load Switch
C3020
Type Load Switch
Thunderbolt Power Support
D1
CERM 2 1
402 10% R(on) 20.3 mOhm Typ Q3025 D 6
R(on) 8 mOhm Typ DRAWING NUMBER SIZE
6.3V 1UF
CERM
402
2
@ 1.0V 28.6 mOhm Max SSM6N37FEAPE
SOT563
10%
6.3V
2
@ 1.05V 11.5 mOhm Max
CERM
402 REVISION
R
13.0.0
2 G S 1
26 IN TBT_EN_CIO_PWR_L PROPRIETARY PROPERTY OF APPLE INC.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/HV Power MUX 80 70 30 29 28 27 26 =PP3V3_S4_TBT
V3P3 must be S4 to support

C3220 1
C3221 1 1
R3229 1
TABLE_ALT_HEAD
wake from Thunderbolt devices. PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: R3227
PART NUMBER 0.1UF 0.1UF 10K 100K
=PP3V3_S4_TBTAPWRSW 10% 10%
80 TABLE_ALT_ITEM
6.3V 6.3V 5% 5%
Nominal Min Max 311S0596 311S0593 ALL TI Alternate CERM-X5R 2 CERM-X5R 2 1/20W 1/20W
15
0201 0201 MF MF
3
IV3P3 1100mA 1030mA 1200mA TABLE_ALT_ITEM
2
201 201
2
CRITICAL CRITICAL 128S0398 128S0220 ALL 3.3V INPUT CAP
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) VDD
C3287 1
C3280 1 1
C3281 TBT_A_BIAS 29
100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) CRITICAL VOLTAGE=3.3V
20% 20% 20% U3220
6.3V 2
6.3V
X5R-CERM-1 2 2
10V
CERM CBTL05023 1
C3225
D
POLY-TANT
603 402 HVQFN 0.1UF
D
CASE-B2-SM
19 V3P3OUT 18
NC 26 IN TBT_A_CIO_SEL 1
BIASIN BIASOUT 24 10%
6.3V
V3P3 2 CERM-X5R
20
=PPHV_SW_TBTAPWRSW 12 PPHV_SW_TBTAPWR DP_AUXIO_EN 2 0201
80 30 18 11 IN AUXIO_EN
OUT MIN_LINE_WIDTH=0.38 MM
18.9V Max 6 14 MIN_NECK_WIDTH=0.20 MM C3230 1 2
7
VHV VOLTAGE=15V 95 26 BI DP_TBTPA_AUXCH_C_N 10% 6.3V 95 DP_TBTPA_AUXCH_N AUX-
7 0.1UF CERM-X5R
0201
1
1
C3211 95 26 BI DP_TBTPA_AUXCH_C_P
C3231
95 DP_TBTPA_AUXCH_P 8 AUX+ AUXIO- 23 DP_A_AUXCH_DDC_N 29 95
C3215 1
C3210 CRITICAL 0.1UF
1 2
22 DP_A_AUXCH_DDC_P
4.7UF 0.1UF 10% 6.3V AUXIO+ 29 95
10% 10%
U3210 10%
50V
0.1UF CERM-X5R
0201 95 31 BI DP_TBTPA_DDC_DATA 4 DDC_DAT
25V 50V CD3210A0RGP 2 X7R TBT: RX_1 Bias Sink
X5R-CERM 2 2 X7R 603-1 95 31 IN DP_TBTPA_DDC_CLK 5 DDC_CLK
QFN
0603 603-1
16 RSVD RSVD 15 26 OUT TBT_A_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_A_CONFIG1_RC 29 95
C3232 1 2
70 IN =TBTAPWRSW_EN 5 EN ISET_V3P3 8 TBTAPWRSW_ISET_V3P3 95 26 IN DP_TBTPA_ML_C_P<1> 20% 6.3V 95 DP_TBTPA_ML_P<1> 11

DP+
0.22UF X5R 0201
95 26 IN DP_TBTPA_ML_C_N<1> 95 DP_TBTPA_ML_N<1> 10
DP- DPMLO+ 19 DP_A_LSX_ML_P<1> 29 95
26 IN TBT_A_HV_EN 11 HV_EN ISET_S0 10 TBTAPWRSW_ISET_S0 C3233 1 2
20% 6.3V DPMLO- 20 DP_A_LSX_ML_N<1> 29 95

0.22UF X5R 0201 26 IN TBT_A_LSTX 14
LSTX
70 30 IN =TBT_S0_EN 17 S0 ISET_S3 9 TBTAPWRSW_ISET_S3 TBT: LSX_A_R2P/P2R (P/N)
80 70 30 29 28 27 26 =PP3V3_S4_TBT TBT_A_LSRX_UNBUF 13
LSRX
TBTHV:P15V TBTHV:P15V
GND THRM
PAD R3210 1
1
R3211
1
R3212 CRITICAL 26 IN TBT_A_DP_PWRDN 6 DP_PD
12V: See
1
3
4
13
21
below
22.6K
1%
22.6K
1%
36.5K
1%
U3260 26 OUT DP_TBTPA_HPD 12
HPDOUT HPD 17 TBT_A_HPD 29
1/16W 1/16W 1/16W 5 74AUP1T97GM
MF-LF MF-LF MF-LF SOT886
402 402 402 GND THMPAD
2 2 2 26 OUT TBT_A_LSRX 4 1 R3226 1
1
R3228
TBTAPWRSW_ISET_S3_R
21
25
6 1M 100K
TBTAPWRSW_ISET_S0_R 3 5% 5%
1 C3260 2 1/20W 1/20W
TBTHV:P15V TBTHV:P15V MF MF
1 1
0.1UF 201 201
R3213 R3214 10%
16V
2 2
22.6K 22.6K Two Rs in series required by CD3210 2 X5R-CERM
1% 1% for single-fault protection(S0,S3 only) 0201
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
C Thunderbolt Connector A C
For 12V systems: L3200
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION FERR-120-OHM-3A C3205
1 2 PP3V3RHV_SW_TBTAPWR
0.01UF
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3210,R3213 TBTHV:P12V MIN_LINE_WIDTH=0.38 MM TBTACONN_1_C 1 2
0603 MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.38 MM GND_VOID=TRUE
VOLTAGE=15V MIN_NECK_WIDTH=0.20 MM 10%
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3211,R3214 TBTHV:P12V C3200 1
R3201 VOLTAGE=18.9V 25V (Both C’s)
(0-18.9V)
0.01UF 12 X5R-CERM
0201
C3270 1 2
10%
50V
TBTACONN_20_RC 1 2 DP Dir TBT Dir 20% 6.3V TBT_A_R2D_C_P<0> IN 26 95
Nominal Min Max 2 MIN_LINE_WIDTH=0.38 MM 0.22UF X5R 0201
X7R-CERM
MIN_NECK_WIDTH=0.20 MM 5% 95 TBT_A_R2D_P<0> TBT_A_R2D_C_N<0> IN 26 95
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) 0402
VOLTAGE=18.9V 1/20W C3271 1 2
1
C3201 MF
201
95 TBT_A_R2D_N<0>
0.22UF
20% 6.3V
X5R 0201
0.01UF
10%
GND_VOID=TRUE 50V TBT: TX_0
2 X7R-CERM CRITICAL GND_VOID=TRUE GND_VOID=TRUE
(Both C’s) 0402 1 1
TBT Dir DP Dir R3270 R3271
C3274 1 2
95 26 OUT TBT_A_D2R_N<0> 20% 4V 95 TBT_A_D2R_C_P<0> 470K 470K

0.47UF
46
45
44
43
42
41
CERM-X5R-1 201 5% 5%
95 26 OUT TBT_A_D2R_P<0> 95 TBT_A_D2R_C_N<0> 1/20W 1/20W
C3275 1 2
MF MF
20% 4V GND_VOID=TRUE GND_VOID=TRUE 201 201
0.47UF CERM-X5R-1 201 SHLD 2 2
R3294 1
1
R3295
NOTE: Polarity Swapped for layout! 1K 1K J3200 C3206
5%
1/20W
5%
1/20W
DUAL-MDP-K70 0.01UF
MF MF 2 HPD F-ANG-TH GND0 1
201 201 TBTACONN_7_C 1 2
2 2 4 CONFIG1 ML_LANE0P 3 MIN_LINE_WIDTH=0.38 MM
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE MIN_NECK_WIDTH=0.20 MM
6 CONFIG2 ML_LANE0N 5 VOLTAGE=18.9V
10%
R3278 470K 1 2 (0-18.9V) 25V
5% 1/20W 8 GND2 GND1 7 X5R-CERM
C3278 1 2
MF 201
10 9
0201
95 26 IN DP_TBTPA_ML_C_P<3> 20% 6.3V 95 DP_TBTPA_ML_P<3> ML_LANE3P ML_LANE1P DP_A_LSX_ML_P<1> 29 95
0.22UF
B 95 26 IN DP_TBTPA_ML_C_N<3>
C3279 1
X5R
2
20%
0201
6.3V
95 DP_TBTPA_ML_N<3>
TBT: Terminated
12
14
ML_LANE3N
GND4
ML_LANE1N
GND3
11
13
DP_A_LSX_ML_N<1> 29 95
B
0.22UF X5R 0201 R3279 470K 1 2
16 15 TBT: LSX_R2P/P2R (P/N)
5% 1/20W AUX_CHP ML_LANE2P
MF 201
29 TBT_A_BIAS 18 AUX_CHN ML_LANE2N 17
20 DP_PWR 19
PORT A RETURN NOTE: Polarity Swapped for layout!
R3298 1
1
R3299 SHLD GND_VOID=TRUE
2.2K 2.2K CRITICAL (Both C’s)
5% 5%
C3272
65
52
51
50
49
48
47
1 2
GND_VOID=TRUE 1/20W 1/20W GND_VOID=TRUE
MF MF 20% 6.3V TBT_A_R2D_C_N<1> IN 26 95
(Both C’s) 201 201 (Both D’s) 0.22UF X5R 0201
GND_VOID=TRUE
2 2
GND_VOID=TRUE
D3298 95 TBT_A_R2D_P<1> TBT_A_R2D_C_P<1> IN 26 95
C3276 1 2 A K C3273 1 2
95 26 OUT TBT_A_D2R_N<1> 20% 4V 95 TBT_A_D2R_C_P<1> BAR90-02LRH TSLP-2-7 95 TBT_A_D2R1_AUXDDC_P 95 TBT_A_R2D_N<1> 20% 6.3V
0.47UF CERM-X5R-1 201 0.22UF X5R 0201
95 26 OUT TBT_A_D2R_P<1> 95 TBT_A_D2R_C_N<1> D3299 95 TBT_A_D2R1_AUXDDC_N
C3277 1 2 A K
TBT: TX_1
20% 4V BAR90-02LRH TSLP-2-7 GND_VOID=TRUE GND_VOID=TRUE
0.47UF CERM-X5R-1 201
1 1
CRITICAL J16:514-0824 / J17:514-0831 R3272 R3273
NOTE: Polarity Swapped for layout! 470K 470K
L3298 5% 5%
650NH-5%-0.430MA-0.52OHM 1/20W 1/20W
MF MF
GND_VOID=TRUE 201 201
95 29 DP_A_AUXCH_DDC_P 2 1 2 2
95 29 DP_A_AUXCH_DDC_N 0603
NO_XNET_CONNECTION=TRUE
CRITICAL 470k R’s for ESD protection

C3298 1 1
C3299 L3299
30PF 30PF on AC-coupled signals.
5% 5% 650NH-5%-0.430MA-0.52OHM
50V 50V
C0G-NP0 2 2 C0G-NP0 2 1
0402 0402
GND_VOID=TRUE
0603
A 29 TBT_A_HPD
95 29 TBT_A_CONFIG1_RC DP Source must pull PAGE TITLE
26 OUT TBT_A_CONFIG2_RC
C3202
0.01UF
10%
1
down HPD input with Thunderbolt Connector A
25V greater than or equal DRAWING NUMBER SIZE
1 1 1
X5R-CERM
0201
2
to 100K (DPv1.1a).
R3252 R3251 C3294 1 1
C3295 R3241 REVISION
1M 1M 100K
5%
1/20W
5%
1/20W
330PF
10%
330PF
10%
5%
1/20W
Sink HPD range:
R
13.0.0
MF MF
16V
X7R-CERM 2 2
16V
X7R-CERM MF High: 2.0 - 5.0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
201 201 0201 0201 201
2 2 2
Low: 0 - 0.8V THE INFORMATION CONTAINED HEREIN IS THE
32 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/HV Power MUX 80 70 30 29 28 27 26 =PP3V3_S4_TBT
V3P3 must be S4 to support

wake from Thunderbolt devices. C3320 1
C3321 1 1
R3327 R3329 1
0.1UF 0.1UF 10K 100K
=PP3V3_S4_TBTBPWRSW 10% 10%
80 6.3V 6.3V 5% 5%
Nominal Min Max CERM-X5R 2 CERM-X5R 2 1/20W 1/20W
15
0201 0201 MF MF
3
IV3P3 1100mA 1030mA 1200mA 2
201 201
2
CRITICAL CRITICAL
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) VDD
C3387 1
C3380 1 1
C3381 TBT_B_BIAS 30
100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) CRITICAL VOLTAGE=3.3V
20% 20% 20% U3320
6.3V 2
6.3V
X5R-CERM-1 2 2
10V
CERM CBTL05023 1
C3325
D
POLY-TANT
603 402 HVQFN 0.1UF
D
CASE-B2-SM
19 V3P3OUT 18
NC 26 IN TBT_B_CIO_SEL 1
BIASIN BIASOUT 24 10%
6.3V
V3P3 2 CERM-X5R
20
=PPHV_SW_TBTBPWRSW 12 PPHV_SW_TBTBPWR DP_AUXIO_EN 2 0201
80 29 18 11 IN AUXIO_EN
OUT MIN_LINE_WIDTH=0.38 MM
18.9V Max 6 14 MIN_NECK_WIDTH=0.20 MM C3330 1 2
7
VHV VOLTAGE=15V 95 26 BI DP_TBTPB_AUXCH_C_N 10% 6.3V 95 DP_TBTPB_AUXCH_N AUX-
7 0.1UF CERM-X5R
0201
1
C3311 95 26 BI DP_TBTPB_AUXCH_C_P
C3331
95 DP_TBTPB_AUXCH_P 8 AUX+ AUXIO- 23 DP_B_AUXCH_DDC_N 30 95
C3315 1 1
C3310 CRITICAL 0.1UF
1 2
22 DP_B_AUXCH_DDC_P
4.7UF 0.1UF 10% 6.3V AUXIO+ 30 95
10% 10%
U3310 10%
50V
0.1UF CERM-X5R
0201 95 31 BI DP_TBTPB_DDC_DATA 4 DDC_DAT
25V 50V CD3210A0RGP 2 X7R TBT: RX_1 Bias Sink
X5R-CERM 2 2 X7R 603-1 95 31 IN DP_TBTPB_DDC_CLK 5 DDC_CLK
QFN
0603 603-1
16 RSVD RSVD 15 26 OUT TBT_B_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_B_CONFIG1_RC 30 95
C3332 1 2
70 IN =TBTBPWRSW_EN 5 EN ISET_V3P3 8 TBTBPWRSW_ISET_V3P3 95 26 IN DP_TBTPB_ML_C_P<1> 20% 6.3V 95 DP_TBTPB_ML_P<1> 11

DP+
0.22UF X5R 0201
95 26 IN DP_TBTPB_ML_C_N<1> 95 DP_TBTPB_ML_N<1> 10
DP- DPMLO+ 19 DP_B_LSX_ML_P<1> 30 95
26 IN TBT_B_HV_EN 11 HV_EN ISET_S0 10 TBTBPWRSW_ISET_S0 C3333 1 2
20% 6.3V DPMLO- 20 DP_B_LSX_ML_N<1> 30 95

0.22UF X5R 0201 26 IN TBT_B_LSTX 14
LSTX
70 29 IN =TBT_S0_EN 17 S0 ISET_S3 9 TBTBPWRSW_ISET_S3 TBT: LSX_B_R2P/P2R (P/N)
80 70 30 29 28 27 26 =PP3V3_S4_TBT TBT_B_LSRX_UNBUF 13
LSRX
TBTHV:P15V TBTHV:P15V
GND THRM
PAD R3310 1
1
R3311
1
R3312 CRITICAL 26 IN TBT_B_DP_PWRDN 6 DP_PD
12V: See
1
3
4
13
21
below
22.6K
1%
22.6K
1%
36.5K
1%
U3360 26 OUT DP_TBTPB_HPD 12
HPDOUT HPD 17 TBT_B_HPD 30
1/16W 1/16W 1/16W 5 74AUP1T97GM
MF-LF MF-LF MF-LF SOT886
402 402 402 GND THMPAD
2 2 2 26 OUT TBT_B_LSRX 4 1 R3326 1
1
R3328
TBTBPWRSW_ISET_S3_R
21
25
6 1M 100K
TBTBPWRSW_ISET_S0_R 3 5% 5%
1 C3360 2 1/20W 1/20W
TBTHV:P15V TBTHV:P15V MF MF
1 1
0.1UF 201 201
R3313 R3314 10%
16V
2 2
22.6K 22.6K Two Rs in series required by CD3210 2 X5R-CERM
1% 1% for single-fault protection(S0,S3 only) 0201
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
C Thunderbolt Connector B C
For 12V systems: L3300
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION FERR-120-OHM-3A C3305
1 2 PP3V3RHV_SW_TBTBPWR
0.01UF
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3310,R3313 TBTHV:P12V MIN_LINE_WIDTH=0.38 MM TBTBCONN_1_C 1 2
0603 MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.38 MM GND_VOID=TRUE
VOLTAGE=15V MIN_NECK_WIDTH=0.20 MM 10%
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3311,R3314 TBTHV:P12V C3300 1
R3301 VOLTAGE=18.9V 25V (Both C’s)
(0-18.9V)
0.01UF 12 X5R-CERM
0201
C3370 1 2
10%
50V
TBTBCONN_20_RC 1 2 DP Dir TBT Dir 20% 6.3V TBT_B_R2D_C_P<0> IN 26 95
Nominal Min Max 2 MIN_LINE_WIDTH=0.38 MM 0.22UF X5R 0201
X7R-CERM
MIN_NECK_WIDTH=0.20 MM 5% 95 TBT_B_R2D_P<0> TBT_B_R2D_C_N<0> IN 26 95
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) 0402
VOLTAGE=18.9V 1/20W C3371 1 2
1
C3301 MF
201
95 TBT_B_R2D_N<0>
0.22UF
20% 6.3V
X5R 0201
0.01UF
10%
GND_VOID=TRUE 50V TBT: TX_0
2 X7R-CERM CRITICAL GND_VOID=TRUE GND_VOID=TRUE
(Both C’s) 0402 1 1
TBT Dir DP Dir R3370 R3371
C3374 1 2
95 26 OUT TBT_B_D2R_N<0> 20% 4V 95 TBT_B_D2R_C_P<0> 470K 470K

0.47UF
58
57
56
55
54
53
CERM-X5R-1 201 5% 5%
95 26 OUT TBT_B_D2R_P<0> 95 TBT_B_D2R_C_N<0> 1/20W 1/20W
C3375 1 2
MF MF
20% 4V GND_VOID=TRUE GND_VOID=TRUE 201 201
0.47UF CERM-X5R-1 201 SHLD 2 2
R3394 1
1
R3395
NOTE: Polarity Swapped for Layout! 1K 1K J3200 C3306
5%
1/20W
5%
1/20W
DUAL-MDP-K70 0.01UF
MF MF 22 HPD F-ANG-TH GND0 21
201 201 TBTBCONN_7_C 1 2
2 2 24 CONFIG1 ML_LANE0P 23 MIN_LINE_WIDTH=0.38 MM
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE MIN_NECK_WIDTH=0.20 MM
26 CONFIG2 ML_LANE0N 25 VOLTAGE=18.9V
10%
R3378 470K 1 2 (0-18.9V) 25V
5% 1/20W 28 GND2 GND1 27 X5R-CERM
C3378 1 2
MF 201
30 29
0201
95 26 IN DP_TBTPB_ML_C_P<3> 20% 6.3V 95 DP_TBTPB_ML_P<3> ML_LANE3P ML_LANE1P DP_B_LSX_ML_P<1> 30 95
0.22UF
B 95 26 IN DP_TBTPB_ML_C_N<3>
C3379 1
X5R
2
20%
0201
6.3V
95 DP_TBTPB_ML_N<3>
TBT: Terminated
32
34
ML_LANE3N
GND4
ML_LANE1N
GND3
31
33
DP_B_LSX_ML_N<1> 30 95
B
0.22UF X5R 0201 R3379 470K 1 2
36 35 TBT: LSX_R2P/P2R (P/N)
5% 1/20W AUX_CHP ML_LANE2P
MF 201
30 TBT_B_BIAS 38 AUX_CHN ML_LANE2N 37
40 DP_PWR 39
PORT B RETURN NOTE: Polarity Swapped for Layout!
R3398 1
1
R3399 SHLD GND_VOID=TRUE
2.2K 2.2K CRITICAL (Both C’s)
5% 5%
C3372
65
64
63
62
61
60
59
1 2
GND_VOID=TRUE 1/20W 1/20W GND_VOID=TRUE
MF MF 20% 6.3V TBT_B_R2D_C_N<1> IN 26 95
(Both C’s) 201 201 (Both D’s) 0.22UF X5R 0201
GND_VOID=TRUE
2 2
GND_VOID=TRUE
D3398 95 TBT_B_R2D_P<1> TBT_B_R2D_C_P<1> IN 26 95
C3376 1 2 A K C3373 1 2
95 26 OUT TBT_B_D2R_N<1> 20% 4V 95 TBT_B_D2R_C_P<1> BAR90-02LRH TSLP-2-7 95 TBT_B_D2R1_AUXDDC_P 95 TBT_B_R2D_N<1> 20% 6.3V
0.47UF CERM-X5R-1 201 0.22UF X5R 0201
95 26 OUT TBT_B_D2R_P<1> 95 TBT_B_D2R_C_N<1> D3399 95 TBT_B_D2R1_AUXDDC_N
C3377 1 2 A K
TBT: TX_1
20% 4V BAR90-02LRH TSLP-2-7 GND_VOID=TRUE GND_VOID=TRUE
0.47UF CERM-X5R-1 201
1 1
CRITICAL J16:514-0824 / J17:514-0831 R3372 R3373
NOTE: Polarity Swapped for Layout! 470K 470K
L3398 5% 5%
650NH-5%-0.430MA-0.52OHM 1/20W 1/20W
MF MF
GND_VOID=TRUE 201 201
95 30 DP_B_AUXCH_DDC_P 2 1 2 2
95 30 DP_B_AUXCH_DDC_N 0603
CRITICAL 470k R’s for ESD protection

C3398 1 1
C3399 L3399
30PF 30PF on AC-coupled signals.
5% 5% 650NH-5%-0.430MA-0.52OHM
50V 50V
C0G-NP0 2 2 C0G-NP0 2 1
0402 0402
GND_VOID=TRUE
0603
A 30 TBT_B_HPD
95 30 TBT_B_CONFIG1_RC DP Source must pull PAGE TITLE
26 OUT TBT_B_CONFIG2_RC
C3302
0.01UF
10%
1
down HPD input with Thunderbolt Connector B
25V greater than or equal DRAWING NUMBER SIZE
1 1 1
X5R-CERM
0201
2
to 100K (DPv1.1a).
R3352 R3351 C3394 1 1
C3395 R3341 REVISION
1M 1M 100K
5%
1/20W
5%
1/20W
330PF
10%
330PF
10%
5%
1/20W
Sink HPD range:
R
13.0.0
MF MF
16V
X7R-CERM 2 2
16V
X7R-CERM MF High: 2.0 - 5.0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
201 201 0201 0201 201
2 2 2
Low: 0 - 0.8V THE INFORMATION CONTAINED HEREIN IS THE
33 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Dual-Port Host DDC Crossbar

C 80 47 40 =PP3V3_S0_DP
C
VCC 13
1 C3400
0.1UF
U3400 2
20%
10V
CERM
16
TS3DS10224 402
ENA QFN
95 29 OUT
DP_TBTPA_DDC_CLK 1 INA+ OUTA1+ 20
CRITICAL
95 29 BI
DP_TBTPA_DDC_DATA 2 INA- OUTA1- 19
OUTA0+ 18 DP_TBTSNK0_DDC_CLK IN 77
OUTA0- 17 DP_TBTSNK0_DDC_DATA BI 77
14 SAI SAO 15
10 ENB
95 30 DP_TBTPB_DDC_CLK 3 INB+ OUTB1+ 6

OUT
95 30 BI
DP_TBTPB_DDC_DATA 4 INB- OUTB1- 7
OUTB0+ 8 DP_TBTSNK1_DDC_CLK IN 77
OUTB0- 9 DP_TBTSNK1_DDC_DATA BI 77
26 IN TBT_DDC_XBAR_EN_L 12 SBI SBO 11
THRM
PAD
GND
B B
21
PAGE TITLE
TBT DDC Crossbar

DRAWING NUMBER SIZE

REVISION
R
13.0.0
34 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP & BT Load Switch
TPS22924B
SWITCH
CHANNEL
N-TYPE
18.4 MOHM @3.3V

AIRPORT
RDS(ON)
LOADING
2 A (EDP)
BLUETOOTH
CRITICAL
U3510 L3502
D TPS22924
CSP
FERR-220-OHM-2.5A
PP3V3_S4_AP_FLT
D
80 45 32 =PP3V3_S4_AP A2 A1 45 PP3V3_S4_AP_FET 1 2 32
B2 VIN VOUT B1 MIN_LINE_WIDTH=0.6 mm 0603 MIN_LINE_WIDTH=0.6 mm 514S0335

MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm CRITICAL
VOLTAGE=3.3V VOLTAGE=3.3V
CRITICAL
AP_PWR_EN C2 ON
1 C3502 1 C3503 1 C3504 J3500
45 32 IN
GND
0.1UF 0.1UF 10UF SSD-K99
10% 10% 20%
2 16V
X7R-CERM 2 16V
X7R-CERM 2 6.3V
X5R
F-RT-SM1
C1
0402 0402 603
1
PLACE_NEAR=J3500.4:7mm
45 44 BI AP_EVENT_L 2
0.1UF 3
87 13 IN PCIE_AP_R2D_C_N C3505 1 2
0201 10%
CERM-X5R
6.3V 87 PCIE_AP_R2D_N 4
C3506 1 0.1UF 87 PCIE_AP_R2D_P 5

87 13 IN PCIE_AP_R2D_C_P 2
6
0201 10%
CERM-X5R
6.3V
87 11 IN PCIE_CLK100M_AP_N 7
87 11 IN PCIE_CLK100M_AP_P 8
9
87 13 OUT PCIE_AP_D2R_P 10
87 13 OUT PCIE_AP_D2R_N 11
12
80 32 =PP3V3_G3H_BT 32 AP_WAKE_L 13
CRITICAL 32 AP_RESET_CONN_L 14
32 AP_CLKREQ_Q_L
15
BT_RESET_MASK_L U3540 CRITICAL

L3501
FERR-220-OHM-2.5A
90 32 USB_BT_MUX_N
16
20
TPS22924B 90 32 USB_BT_MUX_P
17
CSP PP3V3_G3H_BT_FLT
BT_RESET_MASK_L GATES BT_PWR_RST_L A2 A1 PP3V3_G3H_BT_FET 1 2 18
C until after S0 GPIO is guranteed stable B2 VIN VOUT B1 VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM
0603 VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM 19
C
C2 ON 20
45 44 SMC_G3_WAKESRC_EN GND C3507 1 C3508 1
21
CRITICAL 0.1UF 10UF
10% 20%
C1
Q3540 16V
X7R-CERM 2
6.3V 2
X5R
DMC2400UV 0402 603
SOT563
R35421
P-CHN 10K
5%
3 D S 4 1/16W
MF-LF
402 2
BT_PWR_RST_L BT_PWR_EN
12 IN
6
D
Q3540
N-CHN
BT_PWR_RST 2 G DMC2400UV Supervisor & CLKREQ# Isolation

SOT563
S Delay = 130 ms +/- 20%
1
R3543 1 C3541
10K 0.01UF
5% 1 PP3V3_S4_AP_FLT 32 =PP3V3_S4_AP 32 45 80
1/16W 20%
MF-LF 2 16V
2 402 CERM CRITICAL
B B
1
1 1
402 R3530 R3531 VDD
100K 232K 1 C3530
1%
1/16W
1%
1/16W U3530 0.1uF
20%
MF-LF
2 402
MF-LF
2 402
SLG4AP041V 2 10V
CERM
TDFN 402
P3V3AP_VMON 2 SENSE
+
VREF -
Wake from BT in G3H circuit
DLY
=PP3V3_G3H_BT 32 AP_RESET_CONN_L 4 RESET*
80 32 MR* 3 AP_RESET_L IN 20
45 44 OUT SMC_PME_S4_WAKE_L
EN 6 AP_PWR_EN 32 45
OUT 8 AP_CLKREQ_L OUT 11 18

AP_CLKREQ_Q_L 7 IN
CRITICAL
Q3501
1 C3500 32
THRM
(OD)
0.1UF PAD GND

SSM3K15AMFVAPE 1
3 D 10%
10V R3532
5
2 X5R-CERM
5
VESM
0201 100K
VDD 1%
1/16W
U3501 MF-LF
2 402
USB3740
2 S G 1 90 13 BI USB_BT_N 6 DP_2 DFN
90 13 USB_BT_P 7 DM_2 CRITICAL

BI USB_BT_MUX_N 32
DP 10 90
PP3V3_S4_AP_FLT 32
USB_BT_WAKEN 2 DP_1
DM 9 USB_BT_MUX_P 32 90
1 DM_1
NC 1
Q3570 CRITICAL R3570
3 OE* 10K
A SSM3K15AMFVAPE 5%
A
G 1
1/16W
70 44 12 IN PM_SLP_S5_L 4 S VESM MF-LF SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013
GND 2 402 PAGE TITLE
AIRPORT/BT
8
R3501 1
D
S
SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO 36 12 PCIE_WAKE_L AP_WAKE_L 32
15K 3 DRAWING NUMBER SIZE
2
1%
1/20W Apple Inc. 051-9889 D
MF REVISION
201 2 R
13.0.0
35 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
HDD SIGNAL CONNECTOR
SATA Activity LED
J3720
SILK_PART=HDD
CRITICAL 80 33 =PP3V3_S0_LED_SATA
PSA127-0747-A01-1H C3721 1 2 0.01UF
M-ST-SM DEVELOPMENT
8 10% 25V
402
X7R
SATA_HDD_R2D_C_P IN 11 88 R37991
GND_VOID=TRUE
330
1 SATA_HDD_R2D_C_N IN 11 88 5%
1/10W
2 SATA_HDD_R2D_P 1 2 MF-LF
GND_VOID=TRUE 88 603 2 SATALED_R_L
10% 25V X7R
GND_VOID=TRUE
3 88 SATA_HDD_R2D_N 402 0.01UF
4 C3722 GND_VOID=TRUE
5 SATA_HDD_D2R_C_N A DEVELOPMENT
GND_VOID=TRUE
6
88
SATA_HDD_D2R_C_P DS3799
GND_VOID=TRUE 88
C3723 1 2 0.01UF GREEN-3.6MCD
7 2.0X1.25MM-SM
10% 25V X7R K
402 SATA_HDD_D2R_N OUT 11 88 SILK_PART=SATA ACTIVE
GND_VOID=TRUE
9
SATA_HDD_D2R_P OUT 11 88 11 PCH_SATALED_L
1 2
518S0893 10% 25V X7R
402 0.01UF
C3724 GND_VOID=TRUE
C C
GS3 SSD
DC R =0.01-ohm
SSD:Y
PLACE_NEAR=J3700.1:10MM
CRITICAL
J3700 80 33
=PP3V3_S0_LED_SATA
SSD:Y
L3700 SILK_PART=SSD
FERR-26-OHM-6A R37121 1
R3713
80
=PP3V3_S0_SSD 2 1 33 PP3V3_S0_SSD_FLT CRITICAL
SSD-J90
100K
5% 5%
100K
0603 MIN_LINE_WIDTH=0.6mm 1/16W 1/16W
SSD:Y SSD:Y MIN_NECK_WIDTH=0.4mm F-RT-SM MF-LF MF-LF
VOLTAGE=3.3V 402 2 2 402
1 C3701 C3700 1 1 53
0.1UF 0.1UF 2 52 SMC_OOB2_R2D_L IN 45 91
20% 20%
2 10V
CERM
10V
CERM 2
3 51 SMC_OOB2_D2R_L OUT 45 91
402 402 4
5 50 SATA=H,PCIE=L
NC SATA_PCIE_SEL
6 49
NC DEVSLP
7 48
SSD_RESET_L PP3V3_AUX NC
47
NC PFW_L
20
8 SSD:Y
IN
NC
9 SSD_EN 1 2 PP3V3_S0_SSD_FLT 33
MFG_RSVD 10 46 5% 1/16W
402
MF-LF
45
PCIE TX3 NC
11
12 44
NC PCIE RX3 R3717 0
B NC
13 43
NC B
14 42
SSD:Y PCIE TX2 NC NC PCIE RX2
C3711 1 2 0.1UF NC
15 41
NC
16 40
88 11 IN
SSD_R2D_P<1> 10% 16V X5R-CERM 0201
GND_VOID=TRUE
SSD_R2D_N<1> PLACE_NEAR=J3700.18:5MM
PCIE TX1 11
88 IN
SSD:Y GND_VOID=TRUE
17 39 GND_VOID=TRUE
SSD_D2R_P<1>
(POLARITY REVERSED) 10% 16V
1 2 0.1UF
X5R-CERM 0201
88
88
SSD_R2D_C_P<1>
SSD_R2D_C_N<1>
18
19
38
37 SSD_D2R_N<1>
OUT 11 88
11 88
PCIE RX1
OUT
C3710 GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
20 36 GND_VOID=TRUE
GND_VOID=TRUE
Polarity Reversed
88 SSD_R2D_C_N<0> 21 35 SSD_D2R_P<0>
SSD:Y
88 SSD_R2D_C_P<0> 22 34 SSD_D2R_N<0>
OUT
OUT
11 88
11 88
PCIE RX0
C3713 1 2 0.1UF
GND_VOID=TRUE
23 33 GND_VOID=TRUE
Polarity Reversed
24
SSD_R2D_N<0> 10% 16V X5R-CERM 0201
PCIE TX0 11
88
IN GND_VOID=TRUE
25 32 PCIEx2 SSD requires AC coupling caps on TX side
88 11 IN SSD_R2D_P<0> SSD:Y
26 31 PCIE_CLK100M_SSD_N IN 11 87
1 2 0.1UF 27 30 PCIE_CLK100M_SSD_P IN 11 87
10% 16V X5R-CERM 0201 28 29

C3712 GND_VOID=TRUE
54 64
55 65
11 OUT SSD_CLKREQ_L 56 66
57 67
58 68
59
A 60
61 SYNC_MASTER=MASTER SYNC_DATE=05/01/2013 A
62 PAGE TITLE
63 SATA/SSD Connectors
DRAWING NUMBER SIZE

REVISION
POR:514S0457 (tall) R
13.0.0
37 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
HDD POWER/OOB CONNECTOR
HDD Out-of-Band Temperature Sensing

Notes:
Drive active: Valid signal protocol
Drive asleep: HDD drives HDD_OOB_TEMP low
Drive disconnected: Pulled high
80 50 49 48 34 =PP3V3_S0_SENSE
=PP1V5_S0_SENSE =PP3V3_S0_SENSE From drive:
1 SSD:N 80 80 50 49 48 34
R3815 Low: 0.0V to 0.3V
0 1 1 1 C3807 High: 1.2V to 2.0V
5%
R3802 R3800
1/16W 100K 49.9K 0.1UF
MF-LF 5% 1% 10%
2 402 1/16W 1/16W 2 16V

X7R-CERM
MF-LF MF-LF 0402
2 402 Trip is 1.0V
J3830 80 34 =PP5V_S0_SATA 1
R3814
2 402
HDD_OOB_1V00_REF
=PP3V3_S0_SENSE
C 78047-0483
M-ST-SM safety isolation
10K
5%
1/16W
1
R3801 1 C3806 1
34 48 49 50 80
C
1 R3808 MF-LF
2 402
100K 0.1UF R3805
SMC_OOB1_R2D_R_L 523 1%
10% 1K
2 91 1 2 1/16W 2 16V
X7R-CERM CRITICAL 5%
MF-LF 1/16W
3 91 HDD_OOB1_D2R_L 1% 1/16W SMC_OOB1_R2D_L IN 44 91
2 402
0402
5 U3800 MF-LF
MF-LF 402
4 3 2 402
LMV331
VCC+ SC70-5
CRITICAL
L3830 R3803
4 SMC_OOB1_D2R_L OUT 44 91
518S0864 C3830 1
1 2 HDD_OOB1_D2R_F_L Node is at 1.5V 1
3.3K
2 HDD_OOB1_D2R_R_L 1 GND
10UF 91 91
20%
6.3V 2
0402 FERR-220-OHM 5% 2
1/16W
X5R MF-LF
603 402
SSD:Y
CRITICAL
Q3801
NTR1P02L
SOT23-3-HF
80 50 49 48 34 =PP3V3_S0_SENSE 2 S D 3 P3V3_S0_OOB
MIN_LINE_WIDTH=0.3mm
MIN_NECK_WIDTH=0.15mm
VOLTAGE=3.3V
G
1SSD:Y D 6
R3816 1
SSD:Y
CRITICAL
10K
5% Q3800
1/16W
MF-LF
SSM6N15AFE
2 402
2 G S 1 SOT563
SATA_PWR_L
B D 3 SSD:Y
CRITICAL
B
Q3800
SSM6N15AFE
SOT563
5 G S 4
80 34 =PP5V_S0_SATA
PAGE TITLE
HDD Connector
DRAWING NUMBER SIZE

REVISION
R
13.0.0
38 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_ENET_PHY 36
396mA (1000base-T, Caesar II)

80 36 35 =PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV) VDD for Card Reader I/O
36 =PP3V3R1V8_CR_VDDIO
CRITICAL ENET_SR_LX 36
Internal 1.2V Switching Regulator pins.
L3900 =ENET_SR_VFB CRITICAL
FERR-600-OHM-300MA-0.85OHM 36
L3920
ENET_XTALVDDH
D
1
0402
2
VOLTAGE=3.3V C3900 1
VOLTAGE=3.3V
PP1V2_ENET_PHY_AVDDL
FERR-600-OHM-300MA-0.85OHM
1 2
D
0.1UF MIN_NECK_WIDTH=0.2 mm 0402
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3921 1 1 C3920
CRITICAL 0.1UF 4.7UF
10% 20%
L3905 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-300MA-0.85OHM 0201 402 L3925
1 2 PP3V3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
0402
VOLTAGE=3.3V C3905 1 PP1V2_ENET_PHY_PCIEPLL 1 2
MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3926 1 1 C3925
CRITICAL 0.1UF 4.7UF
10% 20%
L3910 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-300MA-0.85OHM 0201 402 L3930
1 2 PP3V3_ENET_PHY_AVDDH FERR-600-OHM-300MA-0.85OHM
0402 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V R39101
1 C3910 1 C3911 PP1V2_ENET_PHY_GPHYPLL
1 2
0.1UF 0.1UF MIN_NECK_WIDTH=0.15 mm 0402
4.7K 10% 10% VOLTAGE=1.2V
5% 2 16V 2 16V
1/16W
MF-LF
X5R-CERM
0201 X5R-CERM
0201
C3931 1 1 C3930
402 2 0.1UF 4.7UF
10% 20%
16V 2 6.3V
X5R-CERM 2 X5R-CERM1
0201 402
R39401 1
R3941 C3915 1 1 C3916
4.7K 4.7K 4.7UF 0.1UF
20% 10%
C3936 1 C3935
42
48
BIASVDDH 37
XTALVDDH 17
20
56
62
SR_VDD 14
SR_VDDP 15
SR_LX 16
SR_VFB 13
39
45
51
29
32
GPHY_PLLVDDL 36
35
61
6.3V 1
5% 5% 2 16V
7
1/16W 1/16W X5R-CERM1 2 X5R-CERM 0.1UF 10UF
C =PP3V3_S0_ENET MF-LF
402 2
MF-LF
2 402
402 0201
AVDDH AVDDL VDDC
10% 20%
C
PCIE_PLLVDDL
80 VDDO 16V 2 6.3V
X5R-CERM 2 X5R LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
0201 603 the card reader on-chip I/O.
1
C3950 R3942 Connect only to U3900 pin 20.
1K
0.1UF 5% Current
1 2 1/16WLimiting OMIT_TABLE
87 13 OUT PCIE_ENET_D2R_N MF-LF
2 402 Resistor U3900
10%
16V
X5R-CERM
C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD-ENET) BCM57766C0KMLG TRD0_P 40 ENETCONN_MDI_P<0> BI 36 90
0201 0.1UF QFN-8X8 ENETCONN_MDI_N<0>
1 2 TRD0_N 41 BI 36 90
87 13 OUT PCIE_ENET_D2R_P
87 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENETCONN_MDI_P<1> BI 36 90
10% 87 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENETCONN_MDI_N<1> 36 90
16V BI
C3955 X5R-CERM
0201 TRD2_P 46 ENETCONN_MDI_P<2> BI 36 90
87 PCIE_ENET_R2D_P 33 PCIE_RXD_P PP3V3R1V8_ENET_LR_OUT
0.1UF TRD2_N 47 ENETCONN_MDI_N<2> BI 36 90
36
1 2 87 PCIE_ENET_R2D_N 34 PCIE_RXD_N MIN_LINE_WIDTH=0.3 mm

87 13 IN PCIE_ENET_R2D_C_P TRD3_P 50 ENETCONN_MDI_P<3> BI 36 90
VOLTAGE=3.3V
10% 87 11 IN PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENETCONN_MDI_N<3> BI 36 90
16V
X5R-CERM
C3956 87 11 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
0201 0.1UF
GPIO_0/CR_ACT_LED* 5
(IPD)
87 13 IN PCIE_ENET_R2D_C_N 1 2 37 IN ENET_RESET_L 11 PERST* (IPD)
NC
GPIO_1/LR_OUT 8
10%
16V 18 11 OUT ENET_CLKREQ_L 12 CLKREQ* (OD) GPIO_2/MEDIA_SENSE 9 ENET_MEDIA_SENSE OUT 11 90
X5R-CERM NOTE: "IPx" == Programmable pull-up/down
36 =ENET_WAKE_L 0201 3 WAKE* (OD)
OUT ENET_SD_DETECT_L
(See note)
(IPx-ENET) SD_DETECT o1 IN 37 90
37 20 IN ENET_LOW_PWR 4 LOW_PWR (IPD)

SD_DETECT can only be used active low due to errata.
(IPU-ENET) CR_CMD 26 90 ENET_SD_CMD R3961 33 1 2 SDCONN_CMD IN 37 90
WAKE# 5% 1/20W MF 201
CR_CLK 21 90 ENET_SD_CLK R3979 33 1 2 SDCONN_CLK OUT 37 90
Must isolate from PCIe WAKE# if PHY SMB_ENET_SCL 6 SMB_CLK 5% 1/20W MF 201
is powered-down in S3/S5. Standard SMB_ENET_SDA 10 SMB_DATA (IPD-ENETM) CR_DATA0 25 90 ENET_CR_DATA<0> R3971 33 1 2 SDCONN_DATA<0> BI 37 90
N-channel FET isolation suggested. CR_DATA1 24 90 ENET_CR_DATA<1> R3972 33 1 2 5% 1/20W MF 201

SDCONN_DATA<1> BI 37 90
ENET_SCLK 66 SCLK_SPD1000LED* R3973 5% 1/20W MF 201
B If PHY is always powered then alias
90 35
90 35
BI
IN ENET_MISO 64 SI/EEDATA
CR_DATA2 23
22
90 ENET_CR_DATA<2>
ENET_CR_DATA<3> R3974
33
33
1 2
5% 1/20W MF 201
SDCONN_DATA<2>
SDCONN_DATA<3>
BI 37 90
B
(IPU)
=ENET_WAKE_L to PCIE_WAKE_L. CR_DATA3 90 1 2 BI 37 90
ENET_MOSI 65 SO_LINKLED* R3975 5% 1/20W MF 201
(IPU-ENET)
90 35 BI
CR_DATA4 52 90 ENET_CR_DATA<4> 33 1 2 SDCONN_DATA<4> BI 37 90
90 35 BI ENET_CS_L 63 CS*/EECLK R3976 33 5% 1/20W MF 201
CR_DATA5 53 90 ENET_CR_DATA<5> 1 2 SDCONN_DATA<5> BI 37 90
NC
2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 90 ENET_CR_DATA<6> R3977 33 1 2 5% 1/20W MF 201
36 OUT ENET_TRAFFICLED_L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 90 ENET_CR_DATA<7> R3978 33 1 2 5% 1/20W MF 201

No MS (Memory Stick) Insert feature needed. 5% 1/20W MF 201
(IPU-ENET)
MS_INS* 59 Control signal to light LED or control SD bus power.
89 19 IN SYSCLK_CLK25M_ENET 18 XTALI NC
19 XTALO
(IPU-ENET)
CR_LED*/CR_BUS_PWR 60 ENET_CR_PWREN OUT 37
NC (IPU-ENET)
CR_WP* 57 SDCONN_WP IN 37
90 ENET_RDAC 38 RDAC (NO IPU OR IPD-ENET) SR_DISABLE 68 ENET_SR_DISABLE R3981 1K 1 2 402

THRM_PAD 5% 1/16W MF-LF
(See note)
PHY Non-Volatile Memory 1
69
R3965 ENET 1.2V SR IS ENABLED IF FLOATING. ENET supports both active-levels for WP.
1.24K
ROM contains MAC address, PCIe config 1% ENET_CR Signals
1/16W
info as well as code for Bonjour proxy. MF-LF
Avoids need for EFI to program at startup. 2 402 BCM requests SD CR[0:7], CMD, CLK termination. PLACEMENT_NOTE=PLACE R3961 NEAR U3900
(Required ROM size 1 Mbit)

ENET_SR_DISABLE PLACEMENT_NOTE=PLACE R3979 NEAR U3900
80 36 35 =PP3V3_ENET_PHY If ENET switching regulator is PLACEMENT_NOTE=PLACE R3971 NEAR U3900
used, this pin should have PLACEMENT_NOTE=PLACE R3972 NEAR U3900
a 1K pull-down to GND
C3990 PLACEMENT_NOTE=PLACE R3973 NEAR U3900
6
1
VCC 0.1UF PLACEMENT_NOTE=PLACE R3974 NEAR U3900
10% PLACEMENT_NOTE=PLACE R3975 NEAR U3900
U3990 2 16V
X5R-CERM
0201 PLACEMENT_NOTE=PLACE R3976 NEAR U3900
AT45DB011D
SOIC-8S1 PLACEMENT_NOTE=PLACE R3977 NEAR U3900
90 35 IN ENET_SCLK 2 SCK OMIT_TABLE SI 1 ENET_MOSI IN 35 90 PLACEMENT_NOTE=PLACE R3978 NEAR U3900
A 90 35 ENET_CS_L 4 CS*
IN PAGE TITLE
5 WP*
SO 8 ENET_MISO
NOSTUFF
OUT 35 90
ETHERNET PHY (CAESAR IV)
1 DRAWING NUMBER SIZE
3 RESET* R3990 1R3997 051-9889 D
GND 4.7K
5%
4.7K
5%
Apple Inc. REVISION
7
NOTE: Pull-down on SO plus internal pull-ups on 1/16W 1/16W R

MF-LF MF-LF 13.0.0
other 3 SPI pins configures ENET for the 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Atmel AT45DB011D (1Mbit) ROM. If a different THE INFORMATION CONTAINED HEREIN IS THE
ROM is used then the straps must change. PROPRIETARY PROPERTY OF APPLE INC.
NOTE: ENETM requires SI pull-down instead of SO. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
39 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V ENET FET

CAESAR IV 1.2V INT.VR CMPTS ENET Enable Generation CRITICAL
Q4020
CAESAR IV ACTIVITY LED
"ENET" = "S0" || ("S4" && "WOL_EN")
NTR4101P
CRITICAL SOT-23-HF
L4010 80 36 35 =PP3V3_ENET_PHY
80 36 35 =PP3V3_ENET_PHY 4.7UH-0.8A 80 =PP3V3_S4_FET_ENET 2 S D 3 PP3V3_ENET_FET 80
35 ENET_SR_LX 1 2 PP1V2_ENET_INTREG 36
D 1 C4010 1 C4011
VOLTAGE=1.2V
PCAA031B-SM
MIN_NECK_WIDTH=0.2MM R40201
1 C4020
0.033UF
G
DEVELOPMENT
1
R4050
D
Power decoupling
4.7UF 0.1UF SWITCH_NODE=TRUE C4012 1 C4013 1 VOLTAGE=1.2V 10K 10%
16V 1 330
20% 10% DIDT=TRUE 10UF 0.1UF 5% 2 X5R 5%
2 6.3V
X5R-CERM1 2 16V
X7R-CERM
20%
6.3V
10%
16V
Feedback loop 1/16W
MF-LF R4021
402 C4021 1/16W
MF-LF
402 0402 X5R 2 X7R-CERM 2 402 2 0.01UF
603 0402
100K 2 402
PM_EN_ENET_L 1 2 P3V3ENET_SS 2 1
ENET_ACT
CRITICAL 3
5%
1/16W 10% A
50V DEVELOPMENT
Q4021 D
MF-LF
402 X7R-CERM
2N7002DW-X-G 0402 LED4050
SOT-363 GREEN-3.6MCD
2.0X1.25MM-SM
14 WOL_EN 5 G S CRITICAL 6 K
IN SILKSCREEN:ENET ACT
Q4021 D
4 2N7002DW-X-G
SOT-363
71 70 45 44 21 12 IN PM_SLP_S3_L 2 G S
36 PP1V2_ENET_INTREG =PP1V2_ENET_PHY 35
1
ENET_TRAFFICLED_L
MAKE_BASE=TRUE 35
=ENET_SR_VFB 35
CAESAR IV WAKE# ISOLATION

C =PP3V3_ENET_PHY 35 36 80 C
1
Q4070 R4070
SSM3K15AMFVAPE 10K
5%
G 1
VESM 1/16W
MF-LF
2 402
D
32 12 PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L 35

MAKE_BASE=TRUE
3
PP3V3R1V8_ENET_LR_OUT =PP3V3R1V8_CR_VDDIO 35
35
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.15 mm 1 C4030 1 C4031 1 C4032
4.7UF 0.1UF 0.1UF
514-0822 20% 10% 10%
157S0058 CRITICAL 6.3V
2 X5R-CERM12
16V 16V
CRITICAL X5R-CERM 2 X5R-CERM
T4000 J4000 402 0201 0201
90 35 ENETCONN_MDI_P<1> 1 SM 12 ENETCONN_MDI_T_P<1> BI 36 90
K70-K72
BI F-ANG-TH
ENET_MDI
ENETCONN_MDI_N<1> 2 11 ENETCONN_MDI_T_N<1> BI
90 35 BI 36 90
90 36 BI ENETCONN_MDI_T_N<3> 8 ENET_MDI_TRAN3-
90 36 BI ENETCONN_MDI_T_P<3> 7 ENET_MDI_TRAN3+
3 90 10 ENETCONN_MCT1
TX
LFE8904CF 90 36 BI ENETCONN_MDI_T_P<2> 4 ENET_MDI_TRAN2+
4 9 ENETCONN_MCT3
90
ENETCONN_MDI_T_P<1> 3 ENET_MDI_TRAN1+
B ENETCONN_MDI_P<3> 5 8 ENETCONN_MDI_T_P<3> BI
90 36
90 36
BI
BI ENETCONN_MDI_T_N<0> 2 ENET_MDI_TRAN0- B
90 35 BI 36 90
90 36 BI ENETCONN_MDI_T_P<0> 1 ENET_MDI_TRAN0+
ENETCONN_MDI_N<3> 6 7 ENETCONN_MDI_T_N<3> BI
90 35 BI 36 90 9
RX 10
11
CRITICAL 12 SHIELD
PINS
T4010
SM
13
90 35 ENETCONN_MDI_N<2> 1 12 ENETCONN_MDI_T_N<2> BI 36 90 14
BI
90 35 ENETCONN_MDI_P<2> 2 11 ENETCONN_MDI_T_P<2> BI 36 90
BI
TX
LFE8904CF
90 35 ENETCONN_MDI_N<0> 5 8 ENETCONN_MDI_T_N<0> BI 36 90
BI
90 35 ENETCONN_MDI_P<0> 6 7 ENETCONN_MDI_T_P<0> BI 36 90
BI
RX
ENETCONN_TCT
R4000
1
R4001
1 1
R4002 1
R4003
A 1 C4001
0.1UF
1 C4002
0.1UF
1 C4003
0.1UF
1 C4004
0.1UF
75
5% 5%
75 75
5% 5%
75 SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
20% 20% 20% 20% 1/16W 1/16W 1/16W 1/16W PAGE TITLE
10V 10V 10V 10V
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402 Ethernet Support & Connector
DRAWING NUMBER SIZE
90 ENETCONN_MCT_BS Apple Inc. 051-9889 D
MIN_LINE_WIDTH=0.4 MM REVISION
NOSTUFF
R
13.0.0
1 C4000 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1000PF THE INFORMATION CONTAINED HEREIN IS THE
10% PROPRIETARY PROPERTY OF APPLE INC.
2KV THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 CERM
40 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SD CARD 3.3V OVERCURRENT PROTECTION CHIP
D 353S2548 D
U4100 =PP3V3_S0_SW_SD_PWR 37
TPS2553
=PP3V3_S0_SDCARD 6 IN SON
80 OUT 1 PP3V3_S0_SW_SD_PWR
CRITICAL MAKE_BASE=TRUE
ILIM 2 SDCONN_ILIM MIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V
35 IN ENET_CR_PWREN 4 EN FAULT* 3 SDCONN_OC_L 12
THRML
GND
C4100 1 C4101 1
PAD R4118
1 1 C4102 1 C4103 1
R4100
13K 47K
7
22UF 0.1UF 10UF 0.1UF
20% 10% 1% 20% 10% 5%
6.3V 16V 1/16W 2 6.3V
X5R 2 16V
X7R-CERM
1/16W
X5R-CERM1 2 X7R-CERM 2 MF-LF
603 0402
MF-LF
0603 0402 2 402 2 402
SDCONN_ILIM_R
R4119
1
13K
1%
1/16W
MF-LF
2 402
J16:516-0249 / J17:512-0038
SD CARD CONNECTOR
=PP3V3_S0_SW_SD_PWR
37
J4100
SD-CARD-D7
F-ANG-TH
CRITICAL
C 90 35
90 35
BI SDCONN_DATA<3>
SDCONN_CMD
1
2
CD/DAT3
CMD
C
OUT
L4102 3 VSS
47NH-1.3OHM 4 VDD
CRITICAL1 2 5
90 35 IN SDCONN_CLK 90 SDCONN_CLK_R CLK
0402 6 VSS
90 35 SDCONN_DATA<0> 7 DAT0
BI
BI
BI
90 35 BI SDCONN_DATA<4> 10 DAT4
BI
37 SDCONN_DETECT_L
14 CRD_DETECT_SWITCH
35 SDCONN_WP 15 WRITE_PROTECT_SWITCH
OUT
SD switch is normally connected (i.e. gnd)
16 SHLD_PIN
17 SHLD_PIN
18 SHLD_PIN
NOSTUFF NOSTUFF 19 SHLD_PIN
1 C4171 1 C4170 20 SHLD_PIN
22PF 15PF 21
5% 5% SHLD_PIN
SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION. 2 50V
CERM
0402
2 50V
CERM
402
22 SHLD_PIN
80 =PP3V3_S4_SDCARD 23 SHLD_PIN
24 SHLD_PIN
25 SHLD_PIN
B C4110
1UF
1
26
27
SHLD_PIN
SHLD_PIN
B
10%
10V
X5R 2
402-1
10
CRITICAL
VDD
U4111
SLG4AP026V
TDFN
2
R4114
35 20 IN ENET_LOW_PWR LOW_PWR
RST RST_OUT* 4 0
SLG_ENET_RESET_R_L 1 2 ENET_RESET_L OUT 35
3 RST_IN* LOGIC
20 IN ENET_SD_RESET_L 5%
1/16W
MF-LF
DET_CH_EN* 6 402
NOSTUFF
37 SDCONN_DETECT_L 7 DET_IN
DLY (OD) 9 SDCONN_STATE_CHANGE OUT
XOR
-> TO PCH GPIO

R4110 1
FROM SD CONN -> (IPU) 13 18
10K DET_CHNGD*
5% (OD) 8 ENET_SD_DETECT_L
XOR
1/16W 1 OUT 35 90 -> TO ENET CHIP

MF-LF
SD_DETECT_LVL DET_OUT
402 2
DET_LVL
THRM
R41151 GND PAD
10K
5
11
5%
1/16W
MF-LF
402 2
When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms
regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#
DLY block is 20ms nominal
PAGE TITLE
SD READER CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
13.0.0
41 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Camera/ALS/DMIC connector J4200
USB CAMERA CONTROLLER APN:518S0879
20455-A20E-32
F-RT-SM
21
22 25
90 38 SMIA_DATA_N 1
90 38 SMIA_DATA_P 2
3
90 38 SMIA_CLK_N 4
D 90 38 SMIA_CLK_P 5
6
D
90 38 I2C_CAMSENSOR_SDA 7
90 38 I2C_CAMSENSOR_SCL 8
9
=PP3V3_S4_CAMERA PP1V8_S4_CAMERA
80 39 38 38 39
38 PP5V_S4_CAMERA_F 10
1 1 SMB_ALS_F_SDA 11
C4222 C4224 38
1 1.0UF 0.1UF SMB_ALS_F_SCL 12

C4213 20% 10%
38
0.1UF 6.3V 6.3V 13

10% 2 X5R 2 CERM-X5R
PP1V8_S4_CAMERA_F 14
2 6.3V
CERM-X5R
0201-1 0201 38
0201 38 PP3V3_S4_ALS_F 15
52 GND_AUDIO_DMIC
16
52 AUD_DMIC_SDA1 1 2 AUD_DMIC_SDA1_CONN 17
L4220 PP1V2_S4_CAMERA 38 L4200 R4260 0 18
FERR-600-OHM-300MA-0.85OHM MIN_NECK_WIDTH=0.15 MM 39 FERR-1000-OHM 52 AUD_DMIC_CLK 1 2 AUD_DMIC_CLK_CONN 19
1 2 PP3V3_S4_CAMFILT VOLTAGE=3.3V 1 C4228 80 58 55 54 52 =PP3V3_S0_AUDIO 1 2 PP3V3_DMIC_CONN R4264 0 20
0402 0.1UF 0402 MIN_NECK_WIDTH=0.15MM
1 C4216 1 C4218 1 C4220 10% MIN_LINE_WIDTH=0.4MM
1.0UF 0.1UF 0.1UF 2 6.3V
CERM-X5R VOLTAGE=3.3V 1 C4265
23 26
20% 10% 10% 0201 24
1UF
2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 10%
0201-1 0201 0201 16V
2 X5R
38 CAM_AGND 402
MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.2V R4220 VOLTAGE=1.2V L4210
39 38 PP1V2_S4_CAMERA
10 1 2 L4202
PP1V2_S4_CAMFILT 1 2 PP1V2_S4_F_R
FERR-1000-OHM
5% MF 0402
1 C4214 1 C4215 1 C4217 1/20W 201 FERR-1000-OHM R4218 1R4219
1
80 =PP5V_S4_CAMERA 1 2 PP5V_S4_CAMERA_F 38
R4267
C
0.1UF
10%
6.3V
2 CERM-X5R
0.1UF
10%
6.3V
2 CERM-X5R
0.1UF
10%
6.3V
2 CERM-X5R 1 C4221 1 C4223
1K
1%
1/20W
MF
1K
1%
1/20W
MF
0402
MIN_NECK_WIDTH=0.15 MM
1 C4262
1UF 47 =SMB_ALS_SDA 1
0 2 SMB_ALS_F_SDA 38
C
0201 0201 0201 1.0UF 0.1UF VOLTAGE=5V 10% 5%
20% 10% 2 201 2 201 16V
2 X5R 1/20W 1 C4267
NC 2 6.3V
X5R 2 6.3V
CERM-X5R 402
MF
150PF
0201-1 0201 0201
L4204 5%
DVDD3 16
DVDD4 34
DVDD6 43
MAVDD33 32
USB_VDDA0 23
OVDD2 40
USB_VDDL0 19
VDDA_PLL 26
NC 45
50V
GPIO3, EXT/IN FIRMWARE BOOT SEL
OVDD1 7
CAM_PLLGND 38 FERR-1000-OHM 2 CERM
402
’1’= EXT FW 1 2 NOSTUFF
39 38 PP1V8_S4_CAMERA PP1V8_S4_CAMERA_F 38
’0’= INT FW 0402 1 C4264
90 38 SMIA_DATA_P GPIO3 CAN BE CONFIGED AS MIN_NECK_WIDTH=0.15 MM 1UF
SMIA_DATA_N
MIN_LINE_WIDTH=0.6 MM 10% R4268
90 38
GENERAL GPIO AFTER POWER ON CRITICAL VOLTAGE=1.8V 0
2 16V
X5R =SMB_ALS_SCL 1 2 SMB_ALS_F_SCL
SMIA_CLK_P 47 38
90 38
SMIA_CLK_N
U4200 L4206
402
5%
90 38
VC0359 FERR-1000-OHM
1/20W
MF
1 C4268
0201 150PF
FQFN =PP3V3_S4_ALS 1 2 PP3V3_S4_ALS_F
5%
48 GPIO0 CS_PWDB 37 TP_CS_PWD_L 80 38 50V
2 CERM
NC 0402
TP_CAM_GPIO1 47 GPIO1 CS_CLK 38 TP_ISM_CLK 1 C4266 402
MIN_NECK_WIDTH=0.15 MM NOSTUFF
39 CAM_EXT_BOOT 46 GPIO3 CS_RSTB 36 TP_ISM_RST_L MIN_LINE_WIDTH=0.6 MM 1UF
VOLTAGE=3.3V 10%
12 GPIO9 CS_SCK 41 I2C_CAMSENSOR_SCL 38 90 2 16V
NC 42
X5R
402
Use 100 ohms and 150pF for 10MHz filter
28 MRXDATAINP CS_SDA I2C_CAMSENSOR_SDA 38 90
27 MRXDATAINN 337S4151 CLKIN 9 CAM_XTAL_IN 38

30 MRXCLKINP CLKOUT 10 CAM_XTAL_OUT 38
29 MRXCLKINN TEST 11 CAM_TEST
90 13 USB_CAMERA_P 20 USB_PADP USB_VRES 24 CAM_USB_VRES 80 39 38 =PP3V3_S4_CAMERA

90 13 USB_CAMERA_N 21 USB_PADM PLACE_NEAR=U4200:5mm
1 C4219
MIPI_RESISTOR 33 MIPI_RESISTOR R4213
1
1 C4226 R4216
1
0.1UF
LED_FIXED 17 NC 8.2K 0.1UF 47 R4207 2 2 R4206 1
R4208 10%
8
6.3V
B 90 38 CAM_SF_CLK
CAM_SF_CS_L
6 SF_CLK
3 SF_CS* RST* 1 CAM_PROC_RESET_L 39
1%
1/20W
MF
2 201
10%
6.3V
2 CERM-X5R
1%
1/20W
MF
2 201
10K
1%
1/20W
10K
1%
1/20W 5%
4.7K
1/20W
VCC 2 CERM-X5R
0201 B
90 38
5 SF_DIN
0201 MF MF MF U4202
90 38 CAM_SF_DIN UART1_RX 14 CAM_RX
PLACE_NEAR=U4200:5mm
201 201
2 201 1MBIT-104MHZ
USB_VSSA0
USB_VSDL0
4 SF_DOUT 1 1 PLACE_NEAR=U4200:5mm
CAM_SF_DOUT UART1_TX 13 CAM_TX PLACE_NEAR=U4200:5mm
VSSA_PLL
1
R4204 90 38
CAM_SF_WP_L 2 SF_WP*
1
R4210 CAM_SF_CLK
R4203
1 2
33
CAM_SF_CLK_R 6 SCLK
USON
SI/SIO0 5 CAM_SF_DOUT_R 2
33 R4205
1 CAM_SF_DOUT
24K 90 38
10K 90 38 90 90 38 90
DVSS4
DVSS6
MAVSS
OVSS1
OVSS2
DVSS3
1% MF MF 1%
THRM
1% 1% MX25L1006EZUI-10G
=PP3V3_S4_CAMERA
PAD
1/20W 38 39 80 1/20W 201 201 1/20W

MF 1/20W
MF CRITICAL R4209
2 201 2 201 90 38 CAM_SF_CS_L 1 CS*
OMIT_TABLE
PLACE_NEAR=U4200:5mm 33
CAM_SF_WP_L 3 WP* SO/SIO1 2 CAM_SF_DIN_R 1 2 CAM_SF_DIN
35
44
31
22
8
39
18
25
15
49
90 38 90 38 90
CAM_SF_HOLD_L 7 HOLD* 1%
2 1/20W
R4211 GND
THRM
PAD
MF
201
10K PLACE_NEAR=U4202:5mm
9
201 335S0852
MF
CAM_AGND 38
XW4202
SHORT-0201
1 1/20W
1%
1 2 38 CAM_AGND CAM_PLLGND 38
2
XW4203
SHORT-0201
UART1_TX is strap for selection
of pos/neg edge sampling of SERIAL FLASH
SPI clock during power-on.
STITCH THERMAL PAD TO INNER GROUND 1
’1’ = POSITIVE EDGE
’0’ = NEGATIVE EDGE
CRYSTAL
C4227
R4215 18PF
47 1 2
38 CAM_XTAL_OUT 1 2 CAM_XTAL_OUT_R
1%
1/20W 5%
A MF 25V
R4214
2 201 NP0-C0G-CERM
0201 SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
3
PAGE TITLE
2 4
1M
1%
1/20W
MF
CRITICAL
Y4200
3.2X2.5MM-SM
Camera Controller
1
201 1 12.000MHZ-30PPM-10PF-85C
DRAWING NUMBER SIZE
C4225 Apple Inc. 051-9889 D

18PF REVISION
38 CAM_XTAL_IN 1 2 R
13.0.0
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
25V THE INFORMATION CONTAINED HEREIN IS THE
NP0-C0G-CERM PROPRIETARY PROPERTY OF APPLE INC.
0201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
42 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D Camera Processor Reset Camera Processor ExtBoot Cntl D

80 39 38 =PP3V3_S4_CAMERA 80 39 38 =PP3V3_S4_CAMERA
1 C4300 1
0.1UF R4302
10% 10K
2 6.3V
CERM-X5R
1
R4300 5%
0201 1/20W
51K MF
5% 2 201
1/20W
MF CAM_EXT_BOOT 38
2 201 CRITICAL CRITICAL
CRITICAL
CAM_PROC_RESET_L 74LVC2G08GM/S505 Q4302
38
8 74LVC2G08GM/S505 CRITICAL 71 8 SOT902 SSM3K15AMFVAPE D 3
71 39 20 18 12 PM_PCH_PWROK 3
A
SOT902 Q4300 20
12 PM_PCH_PWROK 7
A VESM
SSM3K15AMFVAPE D 3 18
2
U4300Y 5 VESM
39
6
U4300Y 1
14 PCH_CAM_RESET_R B 08 14 PCH_CAM_EXT_BOOT_R_L B 08
1 C4301
4 4
2.2UF CAM_EXT_BOOT_L
1 G S 2
20%
1 G S 2 2 10V
X5R-CERM
CAM_PROC_RESET 402
80 39 38 =PP3V3_S4_CAMERA
C PP1V2_S4_CAMERA 1
C
39 38 R4306
10K
5%
1/20W
1 MF 3
R4304 2 201
1K
5% CAM_P1V2_RST_HOLDOFF_L 5
Q4310
1/20W MMDT3904-X-G
MF SOT-363-LF
6
2 201
CAM_P1V2_RST_HOLDOFF 2 Q4310 4
MMDT3904-X-G
SOT-363-LF
1
B B
PP1V8_S4_CAMERA Vreg PP1V2_S4_CAMERA Vreg

80 39 38 =PP3V3_S4_CAMERA 80 39 38 =PP3V3_S4_CAMERA
1 C4310 1 C4320
1UF 1UF
10% 39 38 PP1V8_S4_CAMERA 10%
2 16V
X5R 2 16V
X5R
402 402
1 1
R4310 R4320
4.7K CRITICAL 4.7K
1
5% 5% CRITICAL
1/20W VIN 1/20W VIN
MF MF
2 201 2 201
P1V8_S4_EN 3 EN U4310 VO 6 PP1V8_S4_CAMERA 38 39 P1V2_S4_EN 3 EN U4320 VO 6 PP1V2_S4_CAMERA 38 39
ISL9021AIRUCZ-T 2 MIN_NECK_WIDTH=0.15 MM ISL9021AIRUWZ-T 2 MIN_NECK_WIDTH=0.15 MM

1 NC MIN_LINE_WIDTH=0.6 MM 1 NC MIN_LINE_WIDTH=0.6 MM
C4312 DFN NC VOLTAGE=1.8V C4322 DFN NC VOLTAGE=1.2V
1UF NC 5 NC 1UF NC 5 NC
A 10%
10V
2 X5R-CERM
0402 GND
1 C4314
4.7UF
10%
10V
2 X5R-CERM
0402 GND
1 C4324
4.7UF SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
20% 20% PAGE TITLE
6.3V 6.3V
Camera Controller Support
4
2 X5R-CERM1 2 X5R-CERM1
402 402
DRAWING NUMBER SIZE

REVISION
R
13.0.0
43 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Internal DP Connector
Backlight Control
518S0829 Delay applies only on a L->H transition on VIDEO_ON. This guarantees video is valid before the backlight is enabled.
On a H->L transition, output follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video
CRITICAL
J4400
C 20525-130E-01
F-RT-SM
C
L4400 31 80 47 31 =PP3V3_S0_DP
F4400 FERR-220-OHM
3AMP-32V-467
=PP12V_S0_LCD
80
1 2 PP12V_LCD_F 1 2 PP12V_LCD 1 1 C4450
VOLTAGE=12V
MIN_LINE_WIDTH=0.4 mm 0805 VOLTAGE=12V
2 0.1UF
603-HF MIN_NECK_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm 1 C4420 1 C4401 3
10%
6.3V
1 C4451
10UF 0.001UF 2 CERM-X5R 10UF
10% 20% 4 0201 20%
16V 50V 6.3V
2 X5R-CERM 2 CERM 5 2 CERM-X5R
0805 0402 5 U4450 0402-1 5 U4450
6 74AUP2G14GM
SOT886
D4450
SOD-523
74AUP2G14GM
SOT886
7
40 VIDEO_ON 1 6 A K VIDEO_ON_L_DLY 3 4 BKLT_EN 68
8 OUT
To BLC
9
R4451
1
BAT54XV2T1
10 100K 2 2
5%
11 1/20W
MF
R4450
12 30.1K2
2 201 1
91 47 SMB_DP_TCON_SDA 13
BI 1%
Display TCon Master 14 1/20W
91 47 OUT SMB_DP_TCON_SCL MF
SMB_DP_TCON_SLA_SDA 15 201
47 BI
Display TCon Slave 16
47 IN SMB_DP_TCON_SLA_SCL
95 52 DP_INT_SPDIF_AUDIO 17
OUT
41 DP_INTPNL_HPD 18 VIDEO_ON_L OUT 3
OUT To Diag LED
19
95 41 DP_INTPNL_AUX_N 20
BI
95 41 DP_INTPNL_AUX_P 21
BI
22
B 95 41 IN DP_INTPNL_ML_P<0> 23
24
B
95 41 IN DP_INTPNL_ML_N<0>
25
95 41 DP_INTPNL_ML_P<1> 26
IN
95 41 DP_INTPNL_ML_N<1> 27
IN
28
40 VIDEO_ON 29
68 BKLT_VSYNC 30
OUT
33
34
35
36
37
38
39
40
41
32
PAGE TITLE
Internal DP Support
DRAWING NUMBER SIZE

REVISION
R
13.0.0
44 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TP to DP aliases
26 IN
TP_DP_TBTSRC_ML_CP<0> DP_TBTSRC_ML_P<0> 41 95
MAKE_BASE=TRUE
26 IN
TP_DP_TBTSRC_ML_CN<0> DP_TBTSRC_ML_N<0> 41 95
MAKE_BASE=TRUE
TP_DP_TBTSRC_ML_CP<1> DP_TBTSRC_ML_P<1>
D
26
26
IN
TP_DP_TBTSRC_ML_CN<1> DP_TBTSRC_ML_N<1>
MAKE_BASE=TRUE
41 95
41 95
D
IN
MAKE_BASE=TRUE
26 BI
TP_DP_TBTSRC_AUXCH_CP DP_TBTSRC_AUXCH_P 41 95
MAKE_BASE=TRUE
26 BI
TP_DP_TBTSRC_AUXCH_CN DP_TBTSRC_AUXCH_N 41 95
MAKE_BASE=TRUE
=PP3V3_S0_INTDPMUX 41 80
NC aliases
DP_INT_EG_HPD
TP_DP_TBTSRC_ML_CP<2> NC_DP_TBTSRC_ML_P<2>
78 41
1 C4568 1 C4569
26 IN
NO_TEST=TRUE MAKE_BASE=TRUE
0.1UF 0.1UF
10% 10%
26 IN TP_DP_TBTSRC_ML_CN<2> NC_DP_TBTSRC_ML_N<2> 1
R4500 6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
100K 0201 0201
5%
29
20
16
12
1/20W
TP_DP_TBTSRC_ML_CP<3> NC_DP_TBTSRC_ML_P<3>
9
3
26 IN MF
2 201
26 IN
TP_DP_TBTSRC_ML_CN<3> NC_DP_TBTSRC_ML_N<3> 95 77 IN DP_INT_EG_ML_P<0> 31 D0+A VDD
30
95 77 IN DP_INT_EG_ML_N<0> D0-A U4500
DP_INT_EG_ML_P<2> NC_DP_INT_EG_ML_P<2> DP_INT_EG_ML_P<1> 27 PI3VEDP212 C4500 1 2
77 IN 95 77 IN D1+A
NO_TEST=TRUE MAKE_BASE=TRUE TQFN 0.15UF 0201 10% DP_INTPNL_ML_P<0> OUT 40 95
DP_INT_EG_ML_N<1> 26 D1-A CRITICAL D0+ 1 95 DP_INTPNL_ML_C_P<0> X5R 6.3V
77 IN DP_INT_EG_ML_N<2> NC_DP_INT_EG_ML_N<2> C4508
95 77 IN
C4501 1 DP_INTPNL_ML_N<0> OUT 40 95
NO_TEST=TRUE MAKE_BASE=TRUE 95 77 BI DP_INT_EG_AUX_P 1 2 0201
19 D0- 2 95 DP_INTPNL_ML_C_N<0> 2
0.1UF CERM-X5R
10% 6.3V
95 DP_INT_EG_AUX_C_P AUX+A 0.15UF 0201 10%
X5R 6.3V
95 DP_INT_EG_AUX_C_N 18 AUX-A
77 IN
DP_INT_EG_ML_P<3> NC_DP_INT_EG_ML_P<3> 95 77 BI DP_INT_EG_AUX_N C4509 1 2 0201 C4502 1 2
CERM-X5R
0.15UF 0201 10% DP_INTPNL_ML_P<1> 40 95
C
17 OUT
D1+ 4
C
0.1UF
OUT DP_INT_EG_HPD DP_INTPNL_ML_C_P<1>
10% 6.3V X5R 6.3V
DP_INT_EG_ML_N<3> NC_DP_INT_EG_ML_N<3> 78 41 HPD_A 95
77 IN C4503 1 DP_INTPNL_ML_N<1> OUT 40 95
NO_TEST=TRUE MAKE_BASE=TRUE D1- 5 95 DP_INTPNL_ML_C_N<1> 2
25 0.15UF 0201 10%
95 41 DP_TBTSRC_ML_C_P<0> D0+B X5R 6.3V
95 41 DP_TBTSRC_ML_C_N<0> 24 D0-B
23 AUX+ 6 DP_INTPNL_AUX_P BI 40 95
95 41 DP_TBTSRC_ML_C_P<1> D1+B
22 AUX- 7 DP_INTPNL_AUX_N BI 40 95
95 41 DP_TBTSRC_ML_C_N<1> D1-B
95 41 BI DP_TBTSRC_AUXCH_P C4510 1 2 0201
15
0.1UF
CERM-X5R
10% 6.3V
95 DP_TBTSRC_AUX_C_P
14
AUX+B 1
R4502 R4503 1
C4511 1 2 0201
95 DP_TBTSRC_AUX_C_N AUX-B HPD 8 DP_INTPNL_HPD IN 40 100K 100K
95 41 BI DP_TBTSRC_AUXCH_N CERM-X5R
5% 5%
0.1UF 13 1/20W 1/20W
OUT DP_TBTSRC_HPD
10% 6.3V
26 HPD_B MF MF
PD is on the CR page 2 201 2 201
58 11 DP_TBT_SEL 10 SEL =PP3V3_S0_INTDPMUX 41 80

IN
32 AUX_SEL
11 HPD_SEL
THMPAD GND
33
28
21
B B
95 41 IN DP_TBTSRC_ML_P<0> C4512 1 2 DP_TBTSRC_ML_C_P<0> 41 95

20% 6.3V
0.22UF X5R 0201
95 41 IN DP_TBTSRC_ML_N<0> C4513 1 2 DP_TBTSRC_ML_C_N<0> 41 95

20% 6.3V
0.22UF X5R 0201
95 41 IN DP_TBTSRC_ML_P<1> C4514 1 2 DP_TBTSRC_ML_C_P<1> 41 95

20% 6.3V
0.22UF X5R 0201
95 41 IN DP_TBTSRC_ML_N<1> C4515 1 2 DP_TBTSRC_ML_C_N<1> 41 95

20% 6.3V
0.22UF X5R 0201
1 1 1 1
R4512 R4513 R4514 R4515
2.7K 2.7K 2.7K 2.7K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
2 201 2 201 2 201 2 201
PAGE TITLE
Internal DP MUXing
DRAWING NUMBER SIZE

REVISION
R
13.0.0
45 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L4601
FERR-120-OHM-3A
PP5V_S4_EXTA_ILIM 1 2 PP5V_S4_EXTA_F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
L4602
120-OHM-90MA 1 1
C4605 1 1 C4607
DLP0NS
SYM_VER-1
CRITICAL CRITICAL EXT PORT A
0.01UF CRITICAL TSSLP-2-1 TSSLP-2-1
20% 0.1UF 4 3 CRITICAL 2
ESD0P2RF-02LS ESD0P2RF-02LS
16V
X7R-CERM 2
20%
10V
2
D4601 D4606 D4602 D4603 CRITICAL
0402 2 CERM
ESD0P2RF-02LS ESD0P2RF-02LS J4600
D
402
1 2 TSSLP-2-1 TSSLP-2-1 2 2
USB-NO1-K70
F-ANG-TH
D
CRITICAL 1 1
1
VBUS
90 USB2_EXTA_N 2
D-
90 USB2_EXTA_P 3
D+
4
GND
90 USB3_EXTA_RX_N 5
CRITICAL STDA_SSRX-
80 =PP3V3_G3H_SMC_USBMUX L4603 90 USB3_EXTA_RX_P 6
STDA_SSRX+
80OHM-25%-100MA 7
GND_DRAIN
0504
90 USB3_EXTA_TX_F_N 8
STDA_SSTX-
L2 USB3_EXTA_TX_F_P 9
C4606 1 1
R4605 90
STDA_SSTX+
0.1UF 100K 90 13 OUT USB3_EXTA_RX_F_N 4 3
20% 5% CRITICAL
10V 1/16W CRITICAL 2 10
CERM 2
402
2
MF-LF
402 1
2
D4604 D4605 11
USB3_EXTA_RX_F_P 2 ESD0P2RF-02LS ESD0P2RF-02LS
9
90 13 OUT
TSSLP-2-1 12
L1 TSSLP-2-1
VCC 13
CKPLUS_WAIVE=ndifpr_badterm GND_VOID=TRUE
5 M+ 1
45 44 IN SMC_DEBUGPRT_TX_L CRITICAL Y+ 1 90 USB2_EXTA_MUXED_N 1 14
4 M- Y- 2 15
45 44 OUT SMC_DEBUGPRT_RX_L
U4610 USB2_EXTA_MUXED_P
16 SHIELD
CKPLUS_WAIVE=ndifpr_badterm PI3USB102EZLE CKPLUS_WAIVE=pdifpr_badterm
90 13 USB_EXTA_0_N 7 D+ TQFN 17
BI
6 D- CRITICAL 18
90 13 BI USB_EXTA_0_P
80 43 =PP5V_S4_USB CKPLUS_WAIVE=pdifpr_badterm L4604 19
8 OE* SEL 10 SMC_DEBUGPRT_EN_L 44
80OHM-25%-100MA 20
CRITICAL IN 0504
21
C4601 1 1
C4602 GND
L2 22
0.1UF 330UF-25MOHM
C4608
3
20% SIGNAL_MODEL=PI3USB102_TQFN_PI3USB102ZLE_MOJO 0.1UF
C
20%
C 10V
CERM 2
402
2 6.3V
TANT
CASE-D2E
90 13 IN USB3_EXTA_TX_N 1
10% CERM-X5R
2 90 USB3_EXTA_TX_C_N
6.3V 0201
4 3
C4609 0.1UF
1
514-0817
CRITICAL 90 13 USB3_EXTA_TX_P 1 2 90 USB3_EXTA_TX_C_P 2
IN
10% CERM-X5R 6.3V 0201 L1
U4600
TPS2561DR GND_VOID=TRUE
SON
2 IN_0 OUT1 9
3 IN_1 OUT2 8
10 FAULT1* ILIM 7
18 13 OUT USB_EXTB_OC_L USB_ILIM1
6 FAULT2*
18 13 OUT USB_EXTA_OC_L
70 43 PM_EN_USB_PWR 4 EN1 R46021

5 EN2 11.5K
THRM 1%
GND PAD 1/16W
MF-LF L4611
402 2 FERR-120-OHM-3A
1
11
USB_ILIM1_R PP5V_S4_EXTB_ILIM 1 2 PP5V_S4_EXTB_F

VOLTAGE=5V VOLTAGE=5V 1 1 EXT PORT B
MIN_LINE_WIDTH=0.6MM 0603 MIN_LINE_WIDTH=0.6MM CRITICAL CRITICAL
1 MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
TSSLP-2-1 TSSLP-2-1
R4603 CRITICAL
ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
11.5K L4612 D4612 D4613
1%
1/16W
C4615 1 1 C4617 120-OHM-90MA
DLP0NS 2 5 3 4 2 2 J4610
0.01UF 0.1UF
MF-LF SYM_VER-1
USB-NO2-K70
NC
IO
NC
IO
402 2 20% 20%
16V 10V USB_EXTB_8_P 4 3 6 VBUS
X7R-CERM 2 2 CERM 90 13 BI F-ANG-TH
0402 402
90 13 USB_EXTB_8_N 1 GND 1
BI
1 2 VBUS
90 USB2_EXTB_N 2
D-
USB2_EXTB_P 3
D4611 90
4
D+
RCLAMP0582N GND
B SLP1210N6
CRITICAL
90
90
USB3_EXTB_RX_N
USB3_EXTB_RX_P
5
6
STDA_SSRX- B
STDA_SSRX+
7
GND_DRAIN
90 USB3_EXTB_TX_F_N 8
STDA_SSTX-
90 USB3_EXTB_TX_F_P 9
STDA_SSTX+
CRITICAL CRITICAL
CRITICAL 2 10
L4613
2
D4614 D4615 11
80OHM-25%-100MA ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 12
0504 TSSLP-2-1
13
L2 1 1 14
USB3_EXTB_RX_F_N 4 3 15
90 13 BI
16 SHIELD
17
USB3_EXTB_RX_F_P 1 2
90 13 BI 18
L1 19
GND_VOID=TRUE 20
21
22
CRITICAL
L4614
80OHM-25%-100MA 514-0825
0504
L2
C4618 0.1UF
90 13 USB3_EXTB_TX_N 1 2 90 USB3_EXTB_TX_C_N 4 3
IN
A
10% CERM-X5R 6.3V 0201
90 13 USB3_EXTB_TX_P
C4619
1
0.1UF
2 90 USB3_EXTB_TX_C_P 1 2
PAGE TITLE
IN
10% CERM-X5R 6.3V 0201 L1
GND_VOID=TRUE
EXTERNAL USB PORTS A & B
DRAWING NUMBER SIZE

REVISION
R
13.0.0
46 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L4701
FERR-120-OHM-3A
PP5V_S4_EXTC_ILIM 1 2 PP5V_S4_EXTC_F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
CRITICAL 1 1 EXT PORT C

C4705 1 1 C4707 L4702
CRITICAL
TSSLP-2-1
CRITICAL
TSSLP-2-1
0.01UF 120-OHM-90MA 2 5 3 4
ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
20% 0.1UF DLP0NS
D4702 D4703
NC
IO
NC
IO
16V 20%
X7R-CERM 2
J4700
SYM_VER-1
10V 6 VBUS
0402 2 CERM 4 3 2 2
USB_EXTC_1_P
D
402 90 13 BI
1 GND USB-NO3-K70
F-ANG-TH D
90 13 USB_EXTC_1_N 1 2
BI 1
VBUS
D4701 90 USB2_EXTC_N 2
D-
RCLAMP0582N 90 USB2_EXTC_P 3
SLP1210N6 D+
CRITICAL 4
GND
90 USB3_EXTC_RX_N 5
CRITICAL STDA_SSRX-
L4703 90 USB3_EXTC_RX_P 6
STDA_SSRX+
80OHM-25%-100MA 7
GND_DRAIN
0504
90 USB3_EXTC_TX_F_N 8
STDA_SSTX-
L2 90 USB3_EXTC_TX_F_P 9
STDA_SSTX+
90 13 USB3_EXTC_RX_F_N 4 3
OUT CRITICAL
CRITICAL 2 10
=PP5V_S4_USB 1
2
D4704 D4705 11
80 42
90 13 OUT USB3_EXTC_RX_F_P 2 ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 12
L1 TSSLP-2-1
13
CRITICAL GND_VOID=TRUE 1
1 14
C4701 1 1
C4702 15
0.1UF 330UF-25MOHM CRITICAL
20% 20% 16 SHIELD
10V
CERM 2 2 6.3V
TANT
L4704 17
402 CASE-D2E 80OHM-25%-100MA
CRITICAL 0504 18
U4700 L2
19
TPS2561DR C47081 0.1UF 20
SON 90 13 IN USB3_EXTC_TX_N 2 90 USB3_EXTC_TX_C_N 4 3 21
2 IN_0 OUT1 9 10% CERM-X5R 6.3V 0201
22
3 IN_1 OUT2 8 C47091 0.1UF
USB3_EXTC_TX_P 2 90 USB3_EXTC_TX_C_P 1 2
C 18 13 OUT USB_EXTD_OC_L
10 FAULT1* ILIM 7
6 FAULT2*
USB_ILIM2
90 13 IN
10% CERM-X5R 6.3V 0201 L1
J16:514-0826
C
18 13 OUT USB_EXTC_OC_L GND_VOID=TRUE
J17:514-0841
70 42 PM_EN_USB_PWR 4 EN1 R47021
5 EN2 11.5K
THRM 1%
PAD 1/16W
GND MF-LF
402 2
1
11
USB_ILIM2_R
R47031
11.5K
1%
1/16W
MF-LF
402 2
L4711
FERR-120-OHM-3A
PP5V_S4_EXTD_ILIM
1 2 PP5V_S4_EXTD_F
1
CRITICAL
1
CRITICAL EXT PORT D
VOLTAGE=5V
0603
VOLTAGE=5V TSSLP-2-1 TSSLP-2-1
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
CRITICAL D4712 D4713 J4710
L4712 2 2
C4715 1 120-OHM-90MA
DLP0NS 2 5 3 4 USB-NO4-K70
1 C4717 SYM_VER-1 F-ANG-TH
0.01UF
NC
IO
NC
IO
20% 0.1UF 90 13 BI USB_EXTD_9_P 4 3 6 VBUS
16V 20% 1
X7R-CERM 2 10V VBUS
0402 2 CERM 2
1 GND 90 USB2_EXTD_N
402 D-
90 13 BI USB_EXTD_9_N 1 2 90 USB2_EXTD_P 3
D+
4
GND
D4711 90 USB3_EXTD_RX_N 5
STDA_SSRX-
RCLAMP0582N USB3_EXTD_RX_P 6
B B
90
SLP1210N6 STDA_SSRX+
CRITICAL 7
GND_DRAIN
90 USB3_EXTD_TX_F_N 8
STDA_SSTX-
90 USB3_EXTD_TX_F_P 9
STDA_SSTX+
CRITICAL CRITICAL CRITICAL

2 10
L4713 2
D4714 D4715 11
80OHM-25%-100MA ESD0P2RF-02LS ESD0P2RF-02LS
0504 TSSLP-2-1 12
TSSLP-2-1
13
L2 1 1
14
90 13 USB3_EXTD_RX_F_N 4 3 15
OUT
16 SHIELD
1
17
90 13 USB3_EXTD_RX_F_P 2
OUT 18
L1
19
GND_VOID=TRUE
20
21
CRITICAL 22
L4714
80OHM-25%-100MA
0504
J16:514-0827
L2 J17:514-0842
C47181 0.1UF
2 90 USB3_EXTD_TX_C_N 4
90 13 USB3_EXTD_TX_N 3
IN
10% CERM-X5R 6.3V 0201
C4719 0.1UF
90 13 USB3_EXTD_TX_P 1 2 90 USB3_EXTD_TX_C_P 1 2
IN
10% CERM-X5R 6.3V 0201 L1
A GND_VOID=TRUE
PAGE TITLE
EXTERNAL USB PORTS C & D

DRAWING NUMBER SIZE

REVISION
R
13.0.0
47 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
L5001
pins designed as outputs can be left floating,
80 51 45 =PP3V3_G3H_SMC 30-OHM-1.7A
those designated as inputs require pull-ups. 1 2 PP3V3_G3H_SMC_VDDA
0402 MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V
1 C5001
C5002 1 1 C5003 1 C5004 1 C5005 1 C5006 0.1UF
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1 10%
R5002
20%
10V
X5R-CERM 2
10%
2 6.3V
CERM-X5R
10%
2 6.3V
CERM-X5R
10%
2 6.3V
CERM-X5R
10%
2 6.3V
CERM-X5R 1M U5000 6.3V
2 CERM-X5R
0201
0603-1 0201 0201 0201 0201 5%
1/20W
LM4FSXAH5BB
MF
201 BGA
2 (2 OF 2)
46 45 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 45 46
IN
SWDIO/TMS A10 SMC_TMS 45
D
1 C5007
0.1UF
10%
1 C5008
0.1UF
10%
1 C5009
0.1UF
10%
45 32 BI AP_EVENT_L (OD) B11
N13
PK4/RTCCLK SWO/TDO A11
B10
SMC_TDO 45
46
46 D
6.3V 6.3V 6.3V
SMC_WAKE_L WAKE* OMIT_TABLE TDI SMC_TDI 45 46
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R M12
0201 0201 0201
NC_SMC_HIB_L HIB*
NO_TEST=TRUE A2
NC NC
89 45 SMC_CLK32K M10 XOSC0
IN
NC_SMC_XOSC1 N10 XOSC1
U5000 NO_TEST=TRUE
VDDA D3
PP3V3_G3H_AVREF_SMC
LM4FSXAH5BB 91 45 SMC_EXTAL G12 OSC0
45
BGA 91 45 SMC_XTAL G13 OSC1 VREFA+ D2

89 46 13 BI LPC_AD<0> arch B13 LPC0AD0 (1 OF 2) AIN00 E2 proj analog SMC_ADC0 IN 45 PLACE_NEAR=U5000.D1:4mm
VREFA- D1 PLACE_NEAR=U5000.D2:4mm
89 46 13 LPC_AD<1> arch A13 LPC0AD1 AIN01 E1 proj analog SMC_ADC1 45 XW5000
BI IN K12 1 1
C12 F2 VBAT SM C5020 C5021
89 46 13 BI LPC_AD<2> arch LPC0AD2 OMIT_TABLE AIN02 proj analog SMC_ADC2 IN 45
C3 2 1 1.0UF 0.01UF
89 46 13 LPC_AD<3> arch D11 LPC0AD3 AIN03 F1 proj analog SMC_ADC3 45
20% 10%
BI IN D7 GNDA E3 PLACE_NEAR=U5000.A1:4MM 6.3V 2 2 10V
LPC_CLK33M_SMC H12 B3 SMC_ADC4 X5R X5R-CERM
89 19 IN arch LPC0CLK AIN04 proj analog IN 45 E6 0201-1 0201
LPC_FRAME_L arch D12 LPC0FRAME* AIN05 A3 proj analog SMC_ADC5
89 46 13 IN
SMC_LRESET_L arch C13 LPC0RESET* AIN06 B4 proj analog SMC_ADC6
IN 45
1 C5010 1 C5011 1 C5012 E8 A1
91 20 IN IN 45
1UF 1UF 1UF E9 C7
LPC_SERIRQ arch od H13 LPC0SERIRQ AIN07 A4 proj analog SMC_ADC7 10% 10% 10%
46 13 BI IN 45 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
F10 VDD D9
46 45 PM_CLKRUN_L arch od G11 LPC0CLKRUN* AIN08 B5 proj analog SMC_ADC8 45
OUT IN 402 402 402 J7 E5
46 20 12 LPC_PWRDWN_L arch F13 LPC0PD* AIN09 A5 proj analog SMC_ADC9 45
GND_SMC_AVSS 45 48 49 91
IN IN J9 F9
91 14 SMC_RUNTIME_SCI_L arch F12 LPC0SCI* AIN10 B6 proj analog SMC_ADC10 45
OUT IN J10 H5
91 14 SMC_WAKE_SCI_L arch B12 PK5 AIN11 A6 proj analog SMC_ADC11 45
OUT IN H9
AIN12 C1 proj analog SMC_ADC12 GND
IN 45
PP1V2_G3H_SMC_VDDC J1 J5
91 47 SMBUS_SMC_0_S0_SCL arch od E10 I2C0SCL AIN13 C2 proj analog SMC_ADC13 45 MIN_LINE_WIDTH=0.25 MM
BI IN
MIN_NECK_WIDTH=0.1 MM
J6 J8
91 47 SMBUS_SMC_0_S0_SDA arch od D13 I2C0SDA AIN14 B1 proj analog SMC_ADC14 45 VOLTAGE=1.2V
BI IN 1 C5013 1 C5014 1 C5015 1 C5016 1 C5017 K13 VDDC J11
91 47 BI SMBUS_SMC_1_S0_SCL arch od M4 I2C1SCL AIN15 B2 proj analog SMC_ADC15 IN 45
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D6 K11
91 47 SMBUS_SMC_1_S0_SDA arch od N2 I2C1SDA AIN16 G2 proj analog SMC_ADC16 45
10% 10% 10% 10% 10%
BI IN 6.3V 6.3V 6.3V 6.3V 6.3V
N8 G1 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
91 47 SMBUS_SMC_2_S4_SCL arch od I2C2SCL AIN17 proj analog SMC_ADC17 45
C
BI IN 0201 0201 0201 0201 0201
C 91 47
91 47
BI SMBUS_SMC_2_S4_SDA
SMBUS_SMC_3_SCL
arch
arch
od
od
M8
L8
I2C2SDA
I2C3SCL
AIN18
AIN19
H1
H2
proj
proj
analog
analog
SMC_ADC18
SMC_ADC19
IN 45
45
BI IN
91 47 BI SMBUS_SMC_3_SDA arch od K8 I2C3SDA AIN20 B7 proj analog SMC_ADC20 IN 45
91 45 BI SMBUS_SMC_4_ASF_SCL arch od N7 I2C4SCL AIN21 A7 proj analog SMC_ADC21 IN 45
91 45 BI SMBUS_SMC_4_ASF_SDA arch od M7 I2C4SDA AIN22 B8 proj analog SMC_ADC22 IN 45
91 45 SMBUS_SMC_5_G3H_SCL arch od N4 I2C5SCL AIN23 A8 proj analog SMC_ADC23 45

BI IN
91 45 SMBUS_SMC_5_G3H_SDA arch od N3 I2C5SDA
BI
C0- K2 arch analog CPU_PROCHOT_L 6 45 61 86
IN
91 51 SMC_FAN_0_CTL arch H11 PM6/FAN0PWM0 C0+ K1 arch analog SMC_VCCIO_CPU_DIV2 45
OUT IN
91 51 IN SMC_FAN_0_TACH arch L13 PM7/FAN0TACH0 C1- L2 arch analog SMC_S5_PWRGD_VIN IN 45
51 OUT SMC_FAN_1_CTL arch C11 PK6/FAN0PWM1 PC5/C1+ L1 arch SPI_DESCRIPTOR_OVERRIDE_L OUT 19
51 SMC_FAN_1_TACH arch A12 PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 arch SMC_CPU_CATERR_L 45 86

IN IN
45 SMC_TOPBLK_SWP_L arch G3 PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 arch analog CPU_THRMTRIP_3V3 45
OUT IN
45 SMC_PN3 proj D10 PN3/FAN0TACH2
IN
SSI0CLK/PA2 M2 arch SMC_PM_G2_EN 45 60
OUT
45 SMC_PN4 proj L11 PN4/FAN0PWM3 SSI0FSS/PA3 M3 arch PM_DSW_PWRGD 45 71
OUT OUT
45 SMC_PN5 proj N12 PN5/FAN0TACH3 SSI0RX/PA4 L4 arch SMC_DELAYED_PWRGD 28 45 71
OUT OUT
45 32 SMC_G3_WAKESRC_EN arch N11 PN6/FAN0PWM4 SSI0TX/PA5 N1 arch SMC_PROCHOT 45
OUT OUT
45 SMC_PN7 proj M11 PN7/FAN0TACH4
IN
45 IN SMC_PH2 proj J4 PH2/FAN0PWM5 U1RX/B0 F11 arch SMC_DEBUGPRT_RX_L IN 42 45
45 SMC_PH3 proj J2 PH3/FAN0TACH5 U1TX/PB1 E11 arch SMC_DEBUGPRT_TX_L 42 45

OUT OUT
T0CCP0/PB6 F4 arch pwm SMC_SYS_LED 45
OUT
86 45 14 6 IN CPU_PECI arch analog C4 PECI0RX T0CCP1/PB7 F3 arch SMC_GFX_THROTTLE_L OUT 78
91 45 OUT SMC_PECI_L arch C6 PECI0TX

SSI1RX/PF0 M9 arch SPI_SMC_MISO IN 46 89
45 IN SMC_PP0 proj int M13 PP0/IRQ116 SSI1TX/PF1 N9 arch SPI_SMC_MOSI OUT 46 89
B 45
45 32
IN
IN
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
proj
proj
int
int
L12
M5
PP1/IRQ117
PP2/IRQ118
SSI1CLK/PF2
SSI1FSS/PF3
L10
K10
arch
arch
SPI_SMC_CLK
SPI_SMC_CS_L
OUT
OUT
46 89
46 89
B
45 SMC_PME_S4_DARK_L proj int J12 PP3/IRQ119 PF4 L9 arch S5_PWRGD 71
IN IN
45 OUT SMC_PP4 proj int J13 PP4/IRQ120 PF5 K9 arch SMC_PM_PCH_SYS_PWROK IN 45
45 SMC_PP5 proj int L5 PP5/IRQ121

IN
45 IN SMC_PP6 proj int D8 PP6/IRQ122 WT0CCP0/PG4 K7 arch SMC_DEBUGPRT_EN_L OUT 42
45 IN SMC_PP7 proj int K6 PP7/IRQ123 WT0CCP1/PG5 L7 arch SMC_GFX_OVERTEMP IN 45 78
45 OUT ENET_ASF_GPIO arch od D4 PQ0/IRQ124 WT2CCP0/PH0 K3 arch ALL_SYS_PWRGD IN 3 21 71
45 IN SMS_INT_L arch int E4 PQ1/IRQ125 WT2CCP1/PH1 K4 arch SMC_THRMTRIP OUT 45
45 SMC_BC_ACOK arch int F5 PQ2/IRQ126

IN
45 G3_POWERON_L arch int N5 PQ3/IRQ127 WT3CCP0/PH4 J3 arch od PM_PWRBTN_L 12 18
IN OUT
71 70 45 36 21 12 PM_SLP_S3_L arch int N6 PQ4/IRQ128 WT3CCP1/PH5 H4 arch PM_SYSRST_L 12 19
IN OUT
70 12 PM_SLP_S4_L arch int K5 PQ5/IRQ129 WT4CCP0/PH6 H3 arch od MEM_EVENT_L 23 24 45
IN OUT
70 32 12 PM_SLP_S5_L arch int M6 PQ6/IRQ130 WT4CCP1/PH7 G4 proj SMC_PH7 45
IN OUT
45 SMC_ONOFF_L arch int L6 PQ7/IRQ131
IN
T1CCP0/PJ0 C9 arch SMC_OOB1_D2R_L IN 34 91
46 45 SMC_RX_L arch L3 U0RX T1CCP1/PJ1 B9 arch SMC_OOB1_R2D_L 34 91

IN OUT
46 45 SMC_TX_L arch M1 U0TX T2CCP0/PJ2 A9 proj SMC_PJ2 45
OUT IN
T2CCP1/PJ3 C8 proj SMC_PJ3 OUT 45
45 BI SMC_PL7 arch E13 USB0DM

45 BI SMC_PL6 arch E12 USB0DP WT5CCP1/PM3 H10 arch SMC_BATLOW_L OUT 45
PAGE TITLE
SMC
DRAWING NUMBER SIZE

REVISION
R
13.0.0
50 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADC Channel Aliases Unused ADC Channels
SMC Supervisor and AVREF Supply 44 SMC_ADC0 VSNS_P12VG3H
MAKE_BASE=TRUE
48 91 44 SMC_PH3 NC_SMC_PH3
MAKE_BASE=TRUE NO_TEST=TRUE
SMC 32KHz Clock
44 SMC_ADC1 ISNS_P12VG3H 48 91 44 SMC_ADC16 NC_SMC_ADC16 R5160
80 51 45 44 =PP3V3_G3H_SMC MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
22
R5102 44 SMC_ADC2 VSNS_P12VS0_GPUCORE 48 91 44 SMC_ADC18 NC_SMC_ADC18 89 12 IN PM_CLK32K_SUSCLK_R 2 1 SMC_CLK32K OUT 44 89
47 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
PLACE_NEAR=U1100.W36:10MM 5%
51 45 44 =PP3V3_G3H_SMC 1 2 PP3V42_G3H_SMC_SPVSR SMC_ADC3 ISNS_P12VS0_GPUCORE SMC_ADC19 NC_SMC_ADC19 1/16W
80 44 48 91 44
MIN_LINE_WIDTH=0.4MM MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MF-LF
5% MIN_NECK_WIDTH=0.1MM 402
1/16W
MF-LF
1 C5102 VOLTAGE=3.42V 44 SMC_ADC4 VSNS_P1V5S0 49 91
44 SMC_ADC22 NC_SMC_ADC22
4.7UF MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
402
20%
6.3V 44 SMC_ADC5 ISNS_P1V5S0 49 91
44 SMC_ADC23 NC_SMC_ADC23
SMC Crystal
2 X5R-CERM1 MAKE_BASE=TRUE NOTE: SMC team wants 12MHz for this Xtal
1
402 R5105 SMC_ADC6 VSNS_VDDQS3_DDR SMC_EXTAL
100K
44 49 91
Unused Project-specific 44 91
D 80 =PPVIN_G3H_SMCVREF
5%
1/16W
MF-LF
44 SMC_ADC7
MAKE_BASE=TRUE
ISNS_VDDQS3_DDR
MAKE_BASE=TRUE
49 91 44 SMC_S5_PWRGD_VIN NC_SMC_S5_PWRGD_VIN
D
2 402 NOSTUFF 1
44 SMC_ADC8 VSNS_P12VS0_FBVDDQ 48 91
44 SMC_PL7 NC_SMC_PL7 R5166
MAKE_BASE=TRUE
3
MAKE_BASE=TRUE NO_TEST=TRUE 1M
C5100 1 V+ VIN 44 SMC_ADC9 ISNS_P12VS0_FBVDDQ 48 91
44 SMC_PN3 NC_SMC_PN3 5%
MAKE_BASE=TRUE 1/16W
0.47UF
10%
U5100 44 SMC_ADC10 VSNS_CPUVCC 48 91 SMC_PN4
MAKE_BASE=TRUE
NC_SMC_PN4
NO_TEST=TRUE MF-LF
402 2
6.3V
CERM-X5R 2
VREF-3.3V-VDET-3.0V R5103 MAKE_BASE=TRUE 44
MAKE_BASE=TRUE NO_TEST=TRUE CRITICAL
DFN 5% 1/20W SMC_ADC11 ISNS_CPUVCC
402 0
NC
6 MR1* (ipu)
SN0903049 RESET* 5 SMC_RESET_R_L 2 1 SMC_RESET_L OUT 44 46
44
MAKE_BASE=TRUE
48 91
44 SMC_PP4 NC_SMC_S4_WAKESRC_EN
MAKE_BASE=TRUE NO_TEST=TRUE Y5165 R5165
7 MR2* (ipu) MF 201 SMC_ADC12 VSNS_GPUCORE_ALT 12.000MHZ-50PPM-8PF-100OHM 0
NC 44
MAKE_BASE=TRUE
48 91
44 SMC_PN7 NC_SMC_PN7 1 2 91 SMC_XTAL_R 2 1 SMC_XTAL 44 91
SMC_MANUAL_RST_L 4 DELAY CRITICAL REFOUT 8 PP3V3_G3H_AVREF_SMC 44 SMC_ADC13 ISNS_GPUCORE_ALT 5%
44
MAKE_BASE=TRUE
48 91
44 SMC_PP5 NC_SMC_PP5 5X3.2X1.2-SM 1/16W
GND
THRM
PAD MIN_NECK_WIDTH=0.1MM
SMC_ADC14 VSNS_HDDS0
MAKE_BASE=TRUE NO_TEST=TRUE C5165 1 1 C5166 MF-LF
402
VOLTAGE=3.3V NOSTUFF 44 48 91
44 SMC_PP6 NC_SMC_PP6 12PF 12PF
MAKE_BASE=TRUE 5% 5%
C5101 2 C5103 MAKE_BASE=TRUE NO_TEST=TRUE
9
1 1
C5105 1 1 C5106 44 SMC_ADC15 ISNS_HDDS0 48 91 SMC_PP7 NC_SMC_PP7
50V
C0G-CERM 2 2 50V
C0G-CERM
0.01UF 1UF 0.01UF 1000PF MAKE_BASE=TRUE
44
MAKE_BASE=TRUE NO_TEST=TRUE 0402 0402
10% 20% 10% 5%
16V 10V 16V 2 25V 44 SMC_ADC17 VSNS_P1V05S0_PCH 48 91 SMC_DP_HPD_L NC_SMC_DP_HPD_L
X7R-CERM 2 X5R-CERM 2 2 X7R-CERM CERM MAKE_BASE=TRUE
44
0402 0402 MAKE_BASE=TRUE NO_TEST=TRUE
0603-1 0402 SMC_ADC20 ISNS_SSDS0
44
MAKE_BASE=TRUE
49 91
44 SMC_PME_S4_DARK_L NC_SMC_PME_S4_DARK_L
44 SMC_ADC21 VSNS_P3V3S5 49 91
44 SMC_PH7 TP_SMC_PH7
MAKE_BASE=TRUE TP for access if ZPB re-intstated MAKE_BASE=TRUE NO_TEST=TRUE
MIN_LINE_WIDTH=0.4MM 91 44 SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL
Note: IPU are pulled to VIN rail MIN_NECK_WIDTH=0.1MM MAKE_BASE=TRUE NO_TEST=TRUE
VOLTAGE=0V
SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA
SMC control for AirPort power
Project-specific Aliases 91 44
SMC_PN5 ACDC_BURST_EN_L 91 44 SMBUS_SMC_5_G3H_SCL NC_SMBUS_SMC_5_G3H_SCL

SMC Controlled RTC Reset To absorb current from discharging RTC Reset CAP
44
MAKE_BASE=TRUE
45
MAKE_BASE=TRUE NO_TEST=TRUE 80 32 =PP3V3_S4_AP
SMC_PJ3 SMC_OOB2_R2D_L SMBUS_SMC_5_G3H_SDA NC_SMBUS_SMC_5_G3H_SDA
R5194 91 44
330
44
MAKE_BASE=TRUE
33 91
MAKE_BASE=TRUE NO_TEST=TRUE R51421
Power Button CRITICAL RTC_RESET_L_R 1 2 RTC_RESET_L OUT 11 19
44 SMC_PJ2 SMC_OOB2_D2R_L 33 91
44 SMC_BATLOW_L NC_SMC_BATLOW_L 100K
Q5199 5% MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 5%
1/20W
C
SSM3K15AMFVAPE 1/16W
C D 3 SMC_PP0 SMC_ACDC_ID MF
80 51 45 44 =PP3V3_G3H_SMC MF-LF 44
MAKE_BASE=TRUE
60
201 2
VESM 402
SILK_PART=PwrBtn SMC_PH2 SMC_ASSERT_RTCRST 45 IN SMC_WIFI_PWR_EN AP_PWR_EN OUT 32
44 45
1 MAKE_BASE=TRUE MAKE_BASE=TRUE
R5120 SMC_PL6 SMC_WIFI_PWR_EN
DEVELOPMENT 10K 44
MAKE_BASE=TRUE
45
5%
J5120 1/20W
MF
1 G S 2
NTC020AA1JB260T 2 201 45 SMC_ASSERT_RTCRST
NOSTUFF 80 45 =PP1V05_S0_SMC
1 SM 2 SMC_ONOFF_L OUT 44 R51991 1 C5199
MAKE_BASE=TRUE
10K 1.0UF R51231
5% 20% 51
PWR_BTN OUT 60 1/16W
MF-LF 2 6.3V
X5R-CERM
5%
1/20W Platform Thermal Control
402 2 0402 MF
3 4
201 2
PM_THRMTRIP_L 14 86
Arch Pull Up/Down
BI
80 45 =PP3V3_S0_SMC
D 6
CRITICAL 44 24 23 MEM_EVENT_L R5170 10K 1 2 5% 1/20W
MF 201
PECI Support Q5123 46 44 PM_CLKRUN_L R5171 10K 1 2 5% 1/20W
MF 201
Level-shifter that allows SMC to drive PECI SSM6N15AFE
SOT563
Place this circuit near the Tee point to minimize reflections D 3 80 51 45 44 =PP3V3_G3H_SMC
2 G S 1 CRITICAL
=PP1V05_S0_SMC
Comparator Reference 80 45
78 44 IN SMC_GFX_OVERTEMP Q5123 44 ENET_ASF_GPIO R5175 10K 1 2 5% 1/20W
MF 201
CRITICAL SSM6N15AFE 44 G3_POWERON_L R5176 10K 1 2 5% 1/20W
80 45 =PP1V05_S0_SMC 91 44 IN SMC_PECI_L Q5135 R51241 SOT563 MF 201
SSM3K15AMFVAPE D 3 10K 5 G S 4 R5178
5% 44 SMC_BC_ACOK 100K 1 2 5% 1/20W
R51301 R51351 VESM 1/20W
MF 80 45 =PP3V3_S0_SMC 44 SMC_SYS_LED NOSTUFF R5179 100K 1
MF
2 5%
201
1/20W
10K 0 201 2 R5180 MF 201
1% 5% 44 SMS_INT_L 10K 1 2 5% 1/20W
MF 201
1/16W
MF-LF
1/16W
MF-LF R5125 R51281 44 32 SMC_PME_S4_WAKE_L R5181 10K 1 2 5% 1/20W
MF 201
402 2 402 2
1 G S 2 R5138 1K 3.3K
PLACE_NEAR=U5000.K1:5MM 43 SMC_ROMBOOT 2 1
B PLACE_NEAR=U5000.K1:5MM
SMC_VCCIO_CPU_DIV2
PLACE_NEAR=U5000.K1:3MM
OUT 44
OMIT
91 SMC_PECI_L_R 86 CPU_PECI_R 2
5%
1 CPU_PECI BI 6 14 44 86
46 IN
Note: For SMC recovery mode

5%
1/20W
5%
1/20W
MF
201 2 3 CRITICAL
32 PP3V3_S4_AP_FET B
1/16W MF
R51311 R51361 1
R5137 MF-LF 201 Q5127 44 32 AP_EVENT_L R5185 10K 1 2 5% 1/20W
10K
1 C5131 NOSTUFF 330
402 44 IN SMC_THRMTRIP 5
MMDT3904-X-G MF 201
1% 10%
0.1UF NONE 5% SOT-363-LF 44 32 SMC_G3_WAKESRC_EN R5118 100K 1 2 5% 1/20W
1/16W
MF-LF
16V
2 X7R-CERM
NONE
NONE
1/16W
MF-LF
R51261 4
MF 201
402 2 0402 402 2 2 402 10K R5186
5% 71 44 28 SMC_DELAYED_PWRGD 100K 1 2 5% 1/16W
MF-LF 402
1/20W
MF 71 44 PM_DSW_PWRGD R5184 100K 1 2 5% 1/16W
MF-LF 402
201 2
60 44 SMC_PM_G2_EN R5187 100K 1 2 5% 1/20W
MF 201
CPU_THRMTRIP_3V3 OUT 44
=PP3V3_S4_SMC Note:
80
Open-drain stage on S4 to account

Serial/JTAG Interface Pull-ups
R51411 case when SMC is initializing in S5, R5127 6 CRITICAL
80 45 =PP3V3_S5_SMC 10K
CPU_THRMTRIP_L 2
3.3K
1 CPU_TT_OC_L 2
Q5127 80 51 45 44 =PP3V3_G3H_SMC
5% and chip is not yet configured. 6 IN MMDT3904-X-G
1/20W
MF and ACDC_BURST_EN_L could be floating. 5% SOT-363-LF 46 44 SMC_TX_L R5190 10K 1 2 5% 1/20W
R51401 201 2 1/20W
MF 1 46 44 SMC_RX_L R5191 100K 1
MF
2 5%
201
1/20W
10K BURSTMODE_EN_L OUT 60 65 201 MF 201
5% SMC_TCK R5195 10K 1 2 5%
1/20W
MF
AC/DC Burst Mode Enable See (RADAR://PROBLEM/11724870)
This circuit will not work
46 44
R5196 MF
1/20W
201
D 6 Changing second stage to FET will not fix 46 44 SMC_TDI 10K 1 2 5% 1/20W
201 2 S0 collapses before signal reaches 3.3 MF 201
CRITICAL Soltution will require latching of TT 46 44 SMC_TDO R5197 10K 1 2 5% 1/20W
MF 201
Q5140 46 44 SMC_TMS R5198 10K 1 2 5% 1/20W
SSM6N15AFE MF 201
SOT563
2 G S 1 SMC_DEBUGPRT_TX_L R5192 20K 1 2 5% 1/20W
ACDC_BURST
PROCHOT Support R5148
44 42
SMC_DEBUGPRT_RX_L R5193 20K 1

MF
2 5%
201
1/20W
Level-shifter that allows SMC to drive PROCHOT 0 44 42
MF 201
71 18 12 IN PM_PCH_SYS_PWROK 2 1 SMC_PM_PCH_SYS_PWROK OUT 44
CRITICAL 5%
Q5140 D 3 1/20W
A SSM6N15AFE
SOT563
80 45 =PP3V3_S5_SMC
1 C5140
CRITICAL
Q5125
CPU_PROCHOT_L BI 6 44 61 86 MF
201
SYNC_MASTER=J16_TONY SYNC_DATE=06/11/2013 A
PAGE TITLE
0.1UF SSM3K15AMFVAPE D 3
10%
6.3V
2 CERM-X5R
VESM
86 6 CPU_CATERR_L
R5149
2
0
1 SMC_CPU_CATERR_L 44 86
SMC Support
5 G S 4 IN OUT DRAWING NUMBER SIZE
0201
45 ACDC_BURST_EN_L
5%
1/20W
MF
5 201 REVISION
1 G S 2
2
A
R
13.0.0
U5140Y 4 PM_SLP_S3_BUF_L 44 IN SMC_PROCHOT R5154 NOTICE OF PROPRIETARY PROPERTY: BRANCH
PM_SLP_S3_L 1 1K THE INFORMATION CONTAINED HEREIN IS THE
71 70 44 36 21 12 IN B 44 IN SMC_TOPBLK_SWP_L 1 2 PCH_STRP_TOPBLK_SWP_L OUT 12
3 5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TC7SZ08FEAPE
SOT665
1/20W
MF
51 OF 123
201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPI BootROM LPC+SPI Connector D

D MATT CONNECTOR
LPCPLUS
80 =PP3V3_S5_ROM CRITICAL
J5200
DF40C-30DP-0.4V
M-ST-SM
1 CRITICAL
8
1
R5212 R5211 C5210 1 80 =PP3V3_G3H_LPCPLUS 31 32
100K 3.3K 1UF VDD 80 =PP5V_S0_LPCPLUS
5% 5% 10%
1/16W 1/16W 6.3V
2 1 2 SPI_ALT_MISO IN 46 89
MF-LF
402
2
MF-LF
402
2
CERM
402 U5210 89 19 LPC_CLK33M_LPCPLUS 3 4 LPC_FRAME_L 13 44 89
64MBIT IN IN
SOIC 89 44 13 BI LPC_AD<0> 5 6 SPIROM_USE_MLB OUT 14 46 89
89 46 IN SPI_MLB_CLK 6 SCK SI 5 SPI_MLB_MOSI IN 46 89
7 8
SST25VF064C 89 44 13 LPC_AD<2> 9 10 PM_CLKRUN_L 44 45
BI OUT
89 46 IN SPI_MLB_CS_L 1 CE* 89 44 13 BI LPC_AD<1> 11 12 SPI_ALT_CLK IN 46 89
SO 2 SPI_MLB_MISO OUT 46 89
SPI_WP_L 3 WP* OMIT_TABLE 89 44 13 BI LPC_AD<3> 13 14 SPI_ALT_CS_L IN 46 89
89 46 14 IN SPIROM_USE_MLB 7 HOLD* 89 46 IN SPI_ALT_MOSI 15 16 LPC_SERIRQ BI 13 44
VSS 14 OUT LPCPLUS_GPIO 17 18 LPC_PWRDWN_L IN 12 20 44
20 IN DEBUG_RESET_L 19 20 SMC_TDI OUT 44 45
4
45 44 OUT SMC_TDO 21 22 SMC_TCK OUT 44 45
TP_SMC_TRST_L 23 24 SMC_RESET_L OUT 44 45
TP_SMC_MD1 25 26 SMC_ROMBOOT OUT 45
45 44 IN SMC_TX_L 27 28 SMC_RX_L OUT 44 45

29 30 SMC_TMS OUT 44 45
33 34
C C
516s1039
SPI Series Termination

SPI_ALT_MISO 46 89
SPI_ALT_MOSI 46 89
SPI_ALT_CLK 46 89
SPI_ALT_CS_L 46 89
1 1 1 1
R5223 R5224 R5225 R5226 PLACE_NEAR=J5200.11:5mm
24 43 43 43 PLACE_NEAR=J5200.12:10mm
5% 5% 5% 5% PLACE_NEAR=J5200.14:5mm
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402
R5220 R5227
PLACE_NEAR=U1100.AJ7:11MM 15 43
SPI_CS0_R_L 1 2 SPI_CS0_L 1 2 SPI_MLB_CS_L
B B
89 13 89 46 89
IN OUT
5% PLACE_NEAR=R5226.2:5mm 5%
R5221 1/16W
MF-LF R5228 1/16W
MF-LF
PLACE_NEAR=U1100.AJ11:12.5MM 15 402 43 402
89 13 IN SPI_CLK_R 1 2 89 SPI_CLK 1 2 SPI_MLB_CLK OUT 46 89
5% 5%
R5222 1/16W
MF-LF R5229 1/16W
MF-LF
15 402 43 402
89 13 IN SPI_MOSI_R 1 2 89 SPI_MOSI 1 2 SPI_MLB_MOSI OUT 46 89
5% PLACE_NEAR=R5224.2:5mm 5%
PLACE_NEAR=U1100.AH1:18.5MM
1/16W
1/16W
MF-LF R5230 MF-LF
402 24 402
89 13 OUT SPI_MISO 1 2 SPI_MLB_MISO IN 46 89
5% PLACE_NEAR=U5210.2:5MM
1/16W
MF-LF
402
SMC SPI Support
R5250
24
89 44 OUT SPI_SMC_MISO 2 1
5% PLACE_NEAR=U5210.2:5MM
1/16W
MF-LF
402 R5251
43
89 44 IN SPI_SMC_MOSI 2 1
PLACE_NEAR=U5000.N9:8.5MM 5%
1/16W
MF-LF
R5252
A 89 44 IN SPI_SMC_CLK 2
15
1
402
PLACE_NEAR=U5000.L10:15MM 5% PAGE TITLE
1/16W
MF-LF
402 R5253 SPI and Debug Connector
15 DRAWING NUMBER SIZE
SPI_SMC_CS_L 2 1
89 44 IN
PLACE_NEAR=U5000.K10:12.7MM 5% Apple Inc. 051-9889 D
1/16W REVISION
MF-LF
402
R
13.0.0
52 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Line Legend
80 47 =PP3V3_S0_SMBUS 80 =PP3V3_S0_SMBUS_SMC_0 Master
80 47 =PP3V3_S0_SMBUS
Slave
R53601 1
R5361 R53001 1
R5301 R5364 1 1
R5365
Mux
2.2K 2.2K 2.2K 2.2K
5% 5% 5% 5% 8.2K 8.2K
1/16W 1/16W 1/16W 1/16W 5% 5%
U1100 MF-LF MF-LF J2300 U5000 MF-LF MF-LF U8700 1/16W 1/16W
402 2 2 402 402 2 2 402 U1100 MF-LF MF-LF
PCH (SMBus) Memory Channel A SMC (SMBus 0) GPU Die Temp 402
2 2 402
DIMM 0:
0xA0 Write 0x9E Write
13 SMBUS_PCH_CLK =I2C_SODIMMA_SCL 23 0xA1 Read SMB_0_S0_CLK GPU_SMB_CLK_R 78 0x9F Read
SML_PCH_0_CLK
D
91 MAKE_BASE=TRUE MAKE_BASE=TRUE 96 13
D
91 MAKE_BASE=TRUE
13 SMBUS_PCH_DATA =I2C_SODIMMA_SDA 23 SMB_0_S0_DATA GPU_SMB_DAT_R 78
91 MAKE_BASE=TRUE MAKE_BASE=TRUE 96 13 SML_PCH_0_DATA
91 MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA 44 91
SMBUS_SMC_0_S0_SCL 44 91
Unused PCH SM Link
J2500 U5600
Memory Channel B Temp Sensors "T1"
DIMM 2: U5600
0xA4 Write EMC1414 (Prod):
=I2C_SODIMMB_SCL 24 0xA5 Read =SMB_SNS1_SCL 50 0x98 Write
0x99 Read
=I2C_SODIMMB_SDA 24 =SMB_SNS1_SDA 50
U2200 U1100
VRef DAC PCH (SML 1)
0x98 Write 0x88 Write
0x99 Read 0x89 Read
=I2C_VREFDACS_SCL 22 SML_PCH_1_CLK 13
91
=I2C_VREFDACS_SDA 22 SML_PCH_1_DATA 13
91
U2201 U5690
Vref Control LCD Temp IRemote (Dev)
0x30 Write U5690
0x31 Read TMP006 (Prod):
=I2C_PCA9557D_SCL 22 =SMB_SNS3_SCL 50 0x8A Write
0x8B Read
80 40 31 =PP3V3_S0_DP These are needed in addition to TCON PU
=I2C_PCA9557D_SDA 22 =SMB_SNS3_SDA 50
C R5390 1 1
R5391
C
2.2K 2.2K
5% 5%
1/16W 1/16W
U8100 J4400 MF-LF MF-LF U8100
402 2
Backlight Control Display TCon 2 402 BLC Control from TCon
0x58 Write
0x59 Read 80 =PP3V3_S0_SMBUS_SMC_1
=I2C_BKLT_SCL 68 40 SMB_DP_TCON_SCL =SMB_DP_BLC_SCL 68 0x58 Write
91 MAKE_BASE=TRUE 0x59 Read
=I2C_BKLT_SDA 68 R53101 1
R5311 40
91
SMB_DP_TCON_SDA
MAKE_BASE=TRUE
=SMB_DP_BLC_SDA 68
4.7K 4.7K
5% 5%
1/16W 1/16W
U5000 MF-LF MF-LF U5650
402 2
SMC (SMBus 1) 2 402 Temp Sensors "T2"
J6500 For J16:
U5650
CHS SMB_1_S0_CLK =SMB_SNS2_SCL 50
TMP423B (Dev):
0x9A Write
0x76 Write MAKE_BASE=TRUE 0x9B Read
0x77 Read
=I2C_CHS_SCL 56 SMB_1_S0_DATA =SMB_SNS2_SDA 50
MAKE_BASE=TRUE For J17:
U5650
=I2C_CHS_SDA 56 SMBUS_SMC_1_S0_SDA 44 91 EMC1428-7:
0x92 Write
SMBUS_SMC_1_S0_SCL 0x93 Read
44 91
J4400
U6551
Display TCon
TMP421:
Mikey SMB_DP_TCON_SLA_SCL 40
0x9E Write
0x9F Read
0x72 Write
0x73 Read
=I2C_MIKEY_SCL 56 SMB_DP_TCON_SLA_SDA 40 Panel/Vendor ID:
0x1A Write
0x1B Read
=I2C_MIKEY_SDA 56
B B
J1800,J1850
XDP 80 =PP3V3_S4_SMBUS_SMC_2
0x94 Write
0x95 Read
=SMBUS_XDP_SCL 18 R53201 1
R5321
4.7K 4.7K
=SMBUS_XDP_SDA 18 5% 5%
1/16W 1/16W
U5000 MF-LF MF-LF J4200
402
SMC (SMBus 2) 2 2 402 ALS
0x52 Write
0x53 Read
SMB_2_S4_CLK 91 44 SMBUS_SMC_2_S4_SCL =SMB_ALS_SCL 38
MAKE_BASE=TRUE
SMB_2_S4_DATA 91 44 SMBUS_SMC_2_S4_SDA =SMB_ALS_SDA 38
MAKE_BASE=TRUE
80 =PP3V3_S0_SMBUS_SMC_3
R53301 1
R5331
4.7K 4.7K
5% 5%
1/16W 1/16W
U5000 MF-LF MF-LF
A SMC (SMBus 3) 402 2 2 402

SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013 A
PAGE TITLE
SMB_3_CLK
MAKE_BASE=TRUE
SMBUS_SMC_3_SCL 44 91
SMBus Connections
SMB_3_DATA SMBUS_SMC_3_SDA 44 91 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
REVISION
SMC multi-master experiment R
13.0.0
53 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
12V G3H (VD2R:ADC0/ID2R:ADC1) AC/DC lowside sense (System total) CPU Core (VC0C:ADC10/IC0C:ADC11)
Voltage sense and IMON amp (VC0C, IC0C)
CRITICAL
R5400 R5461
0.002 4.53K
1%
PP12V_G3H_SNS OUT 80 NOTE:VSNS on S5 to avoid burning G3H Power 80 61 10 8 6 =PPCPUVCC_S0_CPU 1 2 VSNS_CPUVCC OUT 45 91
1W U5000.B6:10mm
TFT R5401 1%
1/16W
80 =PP12V_G3H_SNS_R 1
0612
2 80 =PP12V_S5_SNS 1
18.2K
2 VSNS_P12VG3H 45 91
MF-LF
402
1 C5461
OUT 0.22UF
3 4 1% 20%
1/16W 2 6.3V
X5R
MF-LF
1 U5000.E2:10mm 0201
R5402
D
402
U5000.E2:10mm 1 C5402
D 80 =PP3V3_S5_SENSE
1%
6.04K
1/16W
0.22UF
20%
91
1 C5400 MF-LF 2
6.3V
X5R =PP5V_S0_ISENSE
0.22UF 2 402 0201 80 48
20%
3
6.3V
2 X5R GND_SMC_AVSS 44 45 48 49
91
1 C5460
V+ 0201 0.01UF
20%
U5000.E1:10mm
U5400 R5405 C7050.1:10mm
2 16V
X7R-CERM
INA214 4.53K VMax = 0.9V R5462 0402
U5000.A6:10mm
91 SNS_P12VG3H_N 5 IN- SC70 OUT 6 91 ISNS_P12VG3H_R 1 2 ISNS_P12VG3H OUT 45 91
REG_CPUVCC_IMON 1
10K
2 REG_CPUVCC_IMON_R 1 5
CRITICAL 1%
93 61 IN R5465
1
1/16W 1%
4 5.1K
SNS_P12VG3H_P 4 IN+ REF 1 1 2 ISNS_CPUVCC
91 R5406 MF-LF
402
U5000.E1:10mm 1/16W
MF-LF
CRITICAL OUT 45 91
20K 1 C5405 402

ISNS_CPUVCC_FB_R 3
5%
1/16W
U5000.A6:10mm
5%
353S2208 GND 1/20W 0.22UF 2 U5460 MF-LF 1 C5465
MF 20% 402
2 6.3V 1 OPA348 0.22UF
2
Gain: 100 V/V 2 201 X5R R5463 20%

0201 SC70-5 6.3V
Range: 0-16.5A 10K 2 X5R
1% 0201
GND_SMC_AVSS 44 45 48 49 1/16W
R5464
91 MF-LF
2 402 2.0K GND_SMC_AVSS 44 45 48 49
1 2 91 ISNS_CPUVCC_FB 91
GPU Core (VG1C:ADC2/IG1C:ADC3) GPU highside sense for GPU Core Regulator
1%
1/16W
MF-LF
402
CRITICAL
R5410
0.003 PP12V_S0_SNS_GPUCORE OUT 80
1%
1W
TFT R5411 GPU Core - Alt (VG0C:ADC12/IG0C:ADC13) PP1V05_S0_PCH (VN1R:ADC17)
0612 18.2K Alternate low side V-sense and IMON amp
80 =PP12V_S0_SNS_GPUCORE_R 1 2 1 2 VSNS_P12VS0_GPUCORE OUT 45 91 I/V-sense for PP1V05_S0_PCH
3 4 1%
1/16W R5441 Since PP1V05 Vreg feedback is coming
MF-LF
1 U5000.F2:10.1mm 4.53K
402
R5412 80 =PPGPUCORE_S0_SNS 1 2 VSNS_GPUCORE_ALT OUT 45 91 from near GPU, place this sensor near PCH.
1 C5412
C 49 48 34
80 50
=PP3V3_S0_SENSE
1 C5410
6.04K
1%
1/16W
MF-LF
0.22UF
20%
2 6.3V
1%
1/20W
MF
201
1
U5000.C1:10mm
C5441 R5476
C
402
X5R 0.22UF 4.53K
0.22UF 2 0201
80 48 =PP5V_S0_ISENSE 20%
80 =PP1V05_S0_SNS 1 2 VSNS_P1V05S0_PCH 45 91
20% 6.3V OUT
2
3
6.3V GND_SMC_AVSS X5R

2 44 45 48 49 1%
V+
X5R
0201
91 1 C5440 0201 1/20W
MF
U5000.G1:10mm
0.01UF GND_SMC_AVSS 44 45 48 49 91 201
U5410 R5415 PLACE_NEAR=U7800.18:7.5MM 2
20%
16V
1 C5476
INA210 4.53K X7R-CERM 0.22UF
91 SNS_P12VS0_GPUCORE_N 5 IN- SC70 91 6 ISNS_P12VS0_GPUCORE_R 1
OUT 2 ISNS_P12VS0_GPUCORE OUT 45 VMax = 0.9V (=50A) R5442 0402 20%
6.3V
91 10K U5000.A6:10mm 2 X5R
1% 67 IN GFXIMVP6_IMON 1 2 GFXIMVP6_IMON_R 1 5
R5445 0201
4 IN+
CRITICAL 1/16W
91 SNS_P12VS0_GPUCORE_P REF 1 MF-LF U5000.F1:10mm 1%
4 5.1K
402 1/20W CRITICAL 1 2 ISNS_GPUCORE_ALT OUT 45 91 GND_SMC_AVSS 44 45 48 49 91
1 C5415 MF
201 5% U5000.C2:10mm
353S2073 GND 0.22UF ISNS_GPUCORE_R 3 1/20W
20%
6.3V 2 U5440 MF 1 C5445
2
Gain: 200 V/V 2 X5R 1 OPA348

201
0.22UF
Range: 0-5.5A 0201 R5443 SC70-5 20%
6.3V
10K 2 X5R
GND_SMC_AVSS 44 45 48 49 1% 0201
91 1/20W
MF
R5444
2 201 9.31K GND_SMC_AVSS 44 45 48 49 91
1 2 ISNS_GPUCORE_FB
1%
1/20W
MF
201
HDD S0 (VH05:ADC14/IH05:ADC15)
I/V-sense for HDD (Development, but need R5420) GPU FB (VG0F:ADC8/IG0F:ADC9)
B GPU highside sense for GPU Frame Buffer 1.5V VDDQ Regulator
CRITICAL
B
CRITICAL
R5420 R5450 PP12V_S0_SNS_FBVDDQ 80
0.005 OUT
0.010 PPHDD_S0_SNS 80 1%
1% OUT 1W
1/4W
HDD_IVSNS:Y MF R5451
MF R5421 0612-2 18.2K
0805-2 4.02K VSNS_HDDS0 80 =PP12V_S0_SNS_FBVDDQ_R 1 2 1 2 VSNS_P12VS0_FBVDDQ OUT 45 91
80 =PPHDD_S0_SNS_R 1 2 1 2 OUT 45 91
3 4 1%
3 4 1% 1/16W
1/16W OMIT_TABLE MF-LF U5000.B5:10mm
HDD_IVSNS:Y U5000.B1:10mm 1
MF-LF
1
402
R5452 1 C5452
402
R5422 1 C5422 49 48 34 =PP3V3_S0_SENSE 6.04K
6.04K 80 50 1% 0.22UF
1% 0.22UF 1/16W 20%
1/16W
2
20%
6.3V
1 C5450 MF-LF 2 X5R
6.3V
MF-LF X5R 0.22UF 2 402 0201
402
2 0201 20%
3
HDD_IVSNS:Y 2
6.3V GND_SMC_AVSS 44 45 48 49
GND_SMC_AVSS X5R 91
44 45 48 49 V+ 0201
U5420 91
U5450
INA216A4YFFX HDD_IVSNS:Y
R5425
R5455
WCSP-4 INA210 4.53K
A1 B2 4.53K 91 SNS_P12VS0_FBVDDQ_N 5 IN- SC70 OUT 6 91 ISNS_P12VS0_FBVDDQ_R 1 2 ISNS_P12VS0_FBVDDQ OUT 45 91
91 SNS_HDD_P IN+ CRITICAL OUT 91 ISNS_HDDS0_R 1 2 ISNS_HDDS0 OUT 45 91
1%
A2 HDD_IVSNS:Y 1%
OMIT_TABLE 4 IN+
CRITICAL 1/16W
91 SNS_HDD_N IN- DZ5420 K 1/16W 91 SNS_P12VS0_FBVDDQ_P REF 1 MF-LF U5000.F1:10mm
MF-LF U5000.B2:10mm 402
CDZ3.0B 402
1 C5425
1 C5455
GND SM 0.22UF 353S2073 GND 0.22UF
20%
353S3597 B1 A
2 6.3V
2
20% Gain: 200 V/V

6.3V X5R
Gain: 200 V/V 2 X5R 0201
0201 Range: 0-3.3A
Range: 0-1.65A
GND_SMC_AVSS 44 45 48 49 91
91
A SYNC_MASTER=J16_TONY SYNC_DATE=06/11/2013 A
PAGE TITLE
I and V Sense
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM
132S0304 2 CAP,0.22UF,201 C5422,C5425 HDD_IVSNS:Y DRAWING NUMBER SIZE

TABLE_5_ITEM

117S0002 2 RES,0 OHM,201 C5422,C5425 HDD_IVSNS:N REVISION
R
13.0.0
54 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP1V5_S0 (VC0M:ADC4/IC0M:ADC5)
lowside sense for VCCVRM,PCH,CPU mem, audio
CRITICAL
R5530
0.0005 PP1V5_S0_SNS 80
1% OUT
1W
MF R5531
0612 4.53K
80 =PP1V5_S0_SNS_R 1 2 1 2 VSNS_P1V5S0 OUT 45 91
3 4 1%
1/20W
U5000.B3:12.7mm
D
MF
D
201
=PP3V3_S0_SENSE
1 C5531
49 48 34
80 50 0.22UF
20%
1 C5530 2 X5R
6.3V
0.22UF 0201
20%
3
2 6.3V
X5R
GND_SMC_AVSS 44 45 48 49 91
V+ 0201
CRITICAL
U5530 R5535
INA211 4.53K
91 SNS_P1V5S0_N 5 IN- SC70 OUT 6 91 ISNS_P1V5S0_R 1 2 ISNS_P1V5S0 OUT 45 91
1%
1/20W
91 SNS_P1V5S0_P 4 IN+ REF 1 MF U5000.A3:10mm
201
1 C5535
353S2216 GND 0.22UF
20%
6.3V
2
Gain: 500 V/V 2 X5R
0201
Range: 0-13.2A
GND_SMC_AVSS 44 45 48 49 91
VDDQ S3 (VM0R:ADC6/IM0R:ADC7)
VDDQ lowside sense for SO-DIMM modules
C CRITICAL
R5540 C
0.0005 PPVDDQ_S3_SNS_DDR 80
1% OUT
1W
MF R5541
0612 4.53K
80 =PPVDDQ_S3_SNS_DDR_R 1 2 1 2 VSNS_VDDQS3_DDR OUT 45 91
3 4 1%
1/20W
MF U5000.B4:10mm
201
=PP3V3_S0_SENSE
1 C5541
49 48 34
80 50 0.22UF
20%
1 C5540 6.3V
2 X5R
0.22UF 0201
20%
3
6.3V GND_SMC_AVSS
2 X5R 44 45 48 49
91
V+ 0201
CRITICAL
U5540 R5545
INA211 4.53K
91 SNS_VDDQS3_DDR_N 5 IN- SC70 OUT 6 91 ISNS_VDDQS3_DDR_R 1 2 ISNS_VDDQS3_DDR OUT 45 91
1%
1/20W
SNS_VDDQS3_DDR_P 4 IN+ REF 1 1
91 R5546 MF
201
U5000.A4:10mm
20K 1 C5545
5% 0.22UF
353S2216 GND 1/20W 20%
MF 6.3V
2
Gain: 500 V/V 2 201 2 X5R
0201
Range: 0-13.2A
91
SSD S0 (IH1R:ADC20/VR3R:ADC21) I-sense for SSD / V-sense for PP3V3_S5)

B SSD:Y B
CRITICAL
R5520
0.002 PPSSD_S0_SNS 80
1% OUT
1W R5526
TFT 4.53K
0612 80 =PP3V3_S5_SNS 1 2 VSNS_P3V3S5 OUT 45 91
80 =PPSSD_S0_SNS_R 2 1
1%
4 3 U5000.A7:10mm 1/20W OMIT_TABLE
MF U5000.A7:10mm
201
1 C5526
0.22UF
20%
6.3V
2 X5R
0201
SSD:Y
GND_SMC_AVSS 44 45 48 49 91
U5520 SSD:Y
INA216A4YFFX R5525
WCSP-4
A1 B2 4.53K
91 SNS_SSD_P IN+ CRITICAL OUT 91 ISNS_SSDS0_R 1 2 ISNS_SSDS0 OUT 45 91
1%
91 SNS_SSD_N A2 IN- 1/20W OMIT_TABLE
MF U5000.B7:12.7mm
201
GND
1 C5525
353S3597 0.22UF
B1 20%
6.3V
Gain: 200 V/V 2 X5R
Range: 0-8.25A 0201
91
A TABLE_5_HEAD
PAGE TITLE
132S0304 2 CAP,0.22UF,201 C5525,C5526 SSD:Y

TABLE_5_ITEM
I and V Sense(Continued)
DRAWING NUMBER SIZE
051-9889 D
TABLE_5_ITEM
117S0002 2 RES,0 OHM,201 C5525,C5526 SSD:N

Apple Inc. REVISION
R
13.0.0
55 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Temperature Sensor T1
GPU Proximity AC/DC Diode on supply
L5614
FERR-220-OHM
SNS_T1_1_P 1 2 SNS_T1_3_P
D 3
50 91
0402
L5614.2:2MM
50 91
D
Q5610.3:2MM 80 50 49 48 34 =PP3V3_S0_SENSE
CRITICAL 91 60 IN SNS_ACDC_P
1 C5610 1 C5614
1 Q5610 2.2PF 91 60 IN SNS_ACDC_N 0.0022UF
BC846BLP +/-0.1PF L5615 10% 1 C5600 1
R5600
DFN1006H4-3 2 25V
NP0 FERR-220-OHM 2 50V
CERM 1UF
2 201 402 10%
10K
5%
SNS_T1_1_N 50 91
1 2 SNS_T1_3_N 50 91 2 10V
X5R 1/16W
402-1 MF-LF
PLACEMENT_NOTE=Place Q5610 near GPU 0402
2 402
CRITICAL 1
VDD
CPU Proximity U5600

EMC1414-1-AIZL
SNS_T1_2_P MSOP
50 91
GPU Prox (TG0p) SNS_T1_1_P 2 DP1 THERM*/ADDR 7
91 50
NC
3 Q5612.3:2MM 91 50 SNS_T1_1_N 3 DN1 ALERT* 8 SNS1_ALERT_L
CRITICAL 1 C5612 4 DP2/DN3 9 =SMB_SNS1_SDA
1 Q5612 2.2PF CPU Prox (TC0p) 91 50 SNS_T1_2_P SMDATA BI 47
BC846BLP +/-0.1PF MAKE_BASE=TRUE
DFN1006H4-3 25V
2 NP0 91 50 SNS_T1_2_N 5 DN2/DP3 SMCLK 10 =SMB_SNS1_SCL 47
IN
2 201 MAKE_BASE=TRUE GND
SNS_T1_2_N 50 91
AC/DC (Tp2h) 91 50 SNS_T1_3_P NOSTUFF NOSTUFF 6
PLACEMENT_NOTE=Place Q5612 between CPU socket and CPU Power supply components U5600.4:2MM U5600.5:2MM I2C Address (EMC1414-1):
91 50 SNS_T1_3_N
C5604 1 1 C5605 0x98 (Write)
47PF 47PF 0x99 (Read)
5% 5%
50V 2 50V
CERM 2 CERM
402 402
Note:
C TABLE_ALT_HEAD
Filter Caps: Stuff if needed for PSU sensor SI
Internal sensor of the EMC 1414
will be used as the ambient sensor.
C
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: Place U5600 at the coolest location
PART NUMBER
TABLE_ALT_ITEM
on the MLB.
372S0186 372S0185 ALL Alternate Temp Diode
Temperature Sensor T2 Temperature Sensor T3: LCD Remote Sensor(Dev Only)

80 50 49 48 34 =PP3V3_S0_SENSE
TEMPSNSDEV
SO-DIMM Proximity 1 C5690
0.01UF
SNS_T2_1_P 50 91 10%
16V
2 X7R-CERM TEMPSNSDEV
NO_XNET_CONNECTION=TRUE 0402 1
3 Q5660.3:2MM R5690
B 1
CRITICAL
Q5660
1 C5660 10K B
A3
5%
2.2PF 1/16W
BC846BLP +/-0.1PF
25V
MF-LF
DFN1006H4-3 2 NP0 V+ 2 402
SNS_T2_1_P
2 201 SO-DIMM Proximity (TM0p) 91 50
U5690
SNS_T2_1_N 50 91 TMP0006AIYZER
OMIT WCSP
NO_XNET_CONNECTION=TRUE 47 =SMB_SNS3_SDA C3 ADR0 C1
PLACEMENT_NOTE=Place Q5660 near SO-DIMM connectors U5650.4:2MM BI SDA CRITICAL
XW5651 B3 ADR1 B1
SM 47 IN =SMB_SNS3_SCL SCL
50 49 48 34 =PP3V3_S0_SENSE DRDY* C2 TMP006_DRDY
91 50 SNS_T2_1_N 1 2 80
BLC Proximity TEMPSNSDEV

I2C Address (TMP006):
MLB Proximity 2 (Tm2p) 91 50 SNS_T2_2_P 1 C5650 DGND AGND
SNS_T2_3_P 50 91
0x8A (Write)
A1
A2
1UF
OMIT 10% 0x8B (Read)
10V
3 NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE 2 X5R
Q5664.3:2MM U5650.4:2MM 402-1
CRITICAL 1 C5664 XW5652 NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!
1 Q5664 2.2PF SM
BC846BLP +/-0.1PF
25V 91 50 SNS_T2_2_N 1 2
8
DFN1006H4-3 2 NP0
2 201 V+ This PD part is a rubber bumper to protect TMP006
SNS_T2_3_N SNS_T2_3_P Added to board BOM (DEV only) to clean up PD BOM
50 91 BLC Proximity (Tb0p) 91 50
U5650
TMP423
TABLE_5_HEAD
OMIT 1 DXP1 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

PLACEMENT_NOTE=Place Q5554 near BLC controller NO_XNET_CONNECTION=TRUE SOT23-8 SCL 7 =SMB_SNS2_SCL IN 47
U5650.4:2MM 2 DXP2 6
TABLE_5_ITEM
CRITICAL SDA =SMB_SNS2_SDA BI 47 875-6433 1 BUMPER,U5690,D7 BUMPER_U5690 TEMPSNSDEV

XW5653 3 DXP3
SM
91 50 SNS_T2_3_N 1 2 SNS_T2_DXN 4 DXN I2C Address (TMP432B):
GND 0x9A (Write)
5 0x9B (Read)
A MLB Proximity SYNC_MASTER=J16_FIYIN SYNC_DATE=06/11/2013 A

PAGE TITLE
SNS_T2_2_P 50 91
Temperature Sensors
3 NO_XNET_CONNECTION=TRUE DRAWING NUMBER SIZE
Q5665.3:2MM
CRITICAL 1 C5662 Apple Inc. 051-9889 D
1 Q5665 0.0022UF REVISION
BC846BLP
DFN1006H4-3
10%
50V
2 CERM
R
13.0.0
2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SNS_T2_2_N 50 91 THE INFORMATION CONTAINED HEREIN IS THE
PLACEMENT_NOTE=PLACE Q565 SOUTH OF SO-DIMM CONNECTORS NEAR DDR VR I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
56 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C SMC Fan 0 (System) C
Note:
The circuit for the PWM input to L6000
the fan acts as a non-inverting 220-OHM-1.4A
level-shifter to protect the SMC. 80 =PP12V_S0_FAN 1 2
It is assumed there is a pull-up to 0603
VOLTAGE=12V
5V/12V inside the fan, otherwise
1 C6000 1 C6001 CRITICAL MIN_NECK_WIDTH=0.25MM
4.7UF 0.01UF
when the SMC PWM goes low and Q6010 10% 20%
16V 16V
turns on, there would be 5V/12V 2 X7R-CERM 2 X7R-CERM
1206 0402
present on the SMC pin! Then by
definition, the drain of Q6010 is
at common and the SMC sinks current
when Q6010 is on.
80 51 45 44 =PP3V3_G3H_SMC SEE RADAR:12960082 J16/J17 CONNECT GATE OF FAN PWM FET TO PP3V42_G3H
This resembles an open-drain if
80 51 =PP3V3_S0_FAN 518S0730
there is a pull-up, going to a Hi-Z CRITICAL
FET input. 1
R6010 Q6010 J6000
Otherwise, this is simply a pass-FET. 10K SSM3K15AMFVAPE 53780-8604
1
5% M-RT-SM
See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors). 1/16W VESM
G
MF-LF L6010 5
2 402 CRITICAL FERR-220-OHM MIN_LINE_WIDTH=0.5MM
SMC_FAN_0_CTL
D
91 44 IN FAN_0_PWM_FET 1 2 FAN_0_PWM_FILT 1
3
2
0402 FAN_0_TACH_FILT 2 Tach
1 C6010 CRITICAL
B 5%
100PF
50V PP12V_S0_FAN_0_FILT
3
4
GND
12V DC
B
2 CERM
0402
6
80 51 45 44 =PP3V3_G3H_SMC 80 51 =PP3V3_S0_FAN
1
K R6026
47K
D6020 5%
BAS316DG 1/16W
MF-LF
SOD323-SM
A
2 402 L6021
R6020 FERR-220-OHM
SMC_FAN_0_TACH 1
47K 2 FAN_0_TACH_FET 1 2
91 44 OUT
5% 0402
1 C6020 1/16W
MF-LF
1 C6021 CRITICAL
1000PF 402 100PF
PLACE_NEAR=U5000.L13:5MM
10% 5%
2 16V
X7R-CERM 2 50V
CERM
0201 0402
Add C6020 1000pF Cap, Change R6020 to 47K -- Radar 11661918 D8 Proto1 Fan Tach instability.
A SMC Fan 1 (Unused) SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A

PAGE TITLE
System Fan
DRAWING NUMBER SIZE
44 IN SMC_FAN_1_CTL NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE NO_TEST=TRUE Apple Inc. 051-9889 D
REVISION
44 SMC_FAN_1_TACH NC_SMC_FAN_1_TACH
R
13.0.0
OUT
MAKE_BASE=TRUE NO_TEST=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
60 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC PLACE C6100 AS CLOSE TO PIN 9 AS POSSIBLE
APPLE P/N 353S2592 PP5V_AUDIO_HPAMP 52 53
IN
VD MUST BE LESS THAN OR EQUAL TO VL_HD
80 =PP1V5_S0_AUD_DIG
=PP3V3_S0_AUDIO IN 38 52 54 55 58 80
C6101 1 1 C6100
4.7UF 0.47UF
20%
4V
10% PP4V5_AUDIO_ANALOG IN 52 56 58
X5R-1 2 2 10V
X5R CRITICAL
402 0402
C6105 1 1 C6104C6106 C6107
C6108 1
1UF 0.47UF
1 1
10UF 10% 10% 0.47UF 10UF
20% C6102 1 1
C6103 10V 10V 10% 20%
D 59 58 56 52 GND_AUDIO_CODEC
16V 2
POLY-TANT
CASE-B2-SM
0.47UF
10%
10V 2
10UF
20%
X5R
402-1
2 2 X5R
0402
10V 2
X5R
0402
2 10V
X5R-CERM
0402-1 D
24
46
25
2 16V
PP4V5_AUDIO_ANALOG X5R GND_AUDIO_CODEC
9
POLY-TANT
58 56 52 IN
C6109 1 1 C6110 0402 CASE-B2-SM
GND_AUDIO_CODEC
52 56 58 59
2.2UF 2.2UF VD VA_REF VA_HP VA 52 56 58 59

R6100
1
20%
6.3V
20%
6.3V
VBIAS_DAC 29 VBIAS_DAC
1
R6105
2.67K 2 2 0
1%
CERM CERM
HPOUT_L 38 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM TP_AUD_HP_L NC 5%
1/16W
402-LF 402-LF CS4206_FP 44 VHP_FILT+ CRITICAL 1/16W
40 TP_AUD_HP_R NC
MF-LF
2 402
CS4206_FN 41 VHP_FILT- U6101 HPOUT_R MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM MF-LF
2 402
CS4206B HPREF 39 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM CS4206_HPREF
QFN
DMICS 1 & 2 38 AUD_DMIC_SDA1
OUT 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 53 54 59
NC TP_DMIC_SDA2 12 GPIO1/DMIC_SDA2
/SPDIF_OUT2
LINEOUT_L1- 34 AUD_LO1_L_N OUT 53 54 59 HP AMP/LINE OUT RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT
HP AMP CNTRL 53 OUT AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 53 55 59 TWEETERS
15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 53 55 59
Q6170_P_S
MAC SPKR AMP CNTRL
D6100
SOD-523 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 54 59
DEVEL_AUDIO DEVEL_AUDIO
54 52 IN AUD_CODEC_MICBIAS A K CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 54 59 WOOFERS CRITICAL
CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_R_P OUT 55 59 Q6170
1
R6170
BAT54XV2T1 45 FLYP
DMC2400UV 0
R61061 LINEOUT_R2- 33 AUD_LO2_R_N 5%
C6111 C6112
4
OUT 55 59
1 1 43 FLYC 1/16W
SOT563
100K 2.2UF 2.2UF MF-LF
WIN SPKR AMP CNTRL 54 OUT AUD_GPIO_3 1% 20% 20%
42 FLYN 2 402
1/16W
59 58 IN AUD_SENSE_A MF-LF 6.3V
CERM 2 2 6.3V
CERM MICBIAS 16 AUD_CODEC_MICBIAS OUT 52 54
402 2 402-LF 402-LF Q6170_P_G
S
3 VL_HD
P-CHN
CS4206_FLYN
5
G
VCOM 28 CS4206_VCOM MIN_NECK_WIDTH=0.15MM
D
1 VL_IF
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
3
HDA_BIT_CLK 6 BITCLK
LINEIN_L+ 21 NO_TEST=TRUE AUD_LI_P_L NC NC
89 11 IN
LINEIN_C- 22 NO_TEST=TRUE AUD_LI_COM NC
C 89 11 IN HDA_SYNC LINEIN_R+ 23 NO_TEST=TRUE AUD_LI_P_R NC 6
NC DEVEL_AUDIO
CRITICAL
C
R6101 10 SYNC
Q6170
HDA_SDIN0 22 AUD_SDI_R AUD_MIC_INL_P
89 11 OUT 1 2 89 8 SDI MICIN_L+ 18 IN 56 59
D DMC2400UV
SOT563
5% 5 SDO MICIN_L- 17 AUD_MIC_INL_N
N-CHN
IN 56 59
1/16W
MF-LF
402 11 RESET*
MICIN_R+ 19 NO_TEST=TRUE AUD_MIC_INP_R NC G 2 Q6170_N_G
89 11 IN HDA_SDOUT MICIN_R- 20 NO_TEST=TRUE AUD_MIC_INN_R NC S
89 11 IN HDA_RST_L
DEVEL_AUDIO
95 40 DP_INT_SPDIF_AUDIO 47 SPDIF_IN MIN_LINE_WIDTH=0.20MM
IN
VREF+_ADC 27 MIN_NECK_WIDTH=0.15MM CS4206_VREF_ADC NC 1
R6171
89 AUD_SPDIF_CHIP 48 SPDIF_OUT 1
R6102 R6104 0
5%
22 CS4206_DMIC_SCL 22 1/16W
89 56 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4 1 2 AUD_DMIC_CLK OUT 38 MF-LF
5% R6103 1
5% 2 402
1/16W 100K 1/16W
MF-LF 1% MF-LF Q6170_N_S
402 1/16W DGND THRM_PAD AGND 402
MF-LF
402 2
49
26
DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA
XW6100 CRITICAL CRITICAL
38 OUT GND_AUDIO_DMIC
C6113 1 1
C6114 1 C6115 R61071 R61081 R61091 R61101 R61111
1UF 10UF 0.47UF
1
MIN_NECK_WIDTH=0.15MM SM
10% 20% 10%
100K 100K 100K 100K 100K Q6171_P_S
VOLTAGE=0V 10V 1% 1% 1% 1% 1%
20V 2 2 16V 2 X5R 1/16W 1/16W 1/16W 1/16W 1/16W
TANT POLY-TANT MF-LF MF-LF MF-LF MF-LF MF-LF
CASE-P3-HF CASE-B2-SM 0402
402 2 402 2 402 2 402 2 402 2 DEVEL_AUDIO DEVEL_AUDIO
CRITICAL
Q6171
1
R6172
DMC2400UV 0
5%
4
SOT563 1/16W
MF-LF
59 58 56 52 GND_AUDIO_CODEC 2 402
Q6171_P_G
S
B B
P-CHN
5
G
APPLE P/N 353S2456
D
4.5V POWER SUPPLY FOR CODEC
3
NC
NC DEVEL_AUDIO
6 CRITICAL
Q6171
DIFF FSINPUT= 2.45VRMS D
DMC2400UV
SOT563
MIN_NECK_WIDTH=0.20MM SE FSINPUT= 1.22VRMS
N-CHN
L6111 VOLTAGE=4.5V
DAC1 FSOUTPUT= 1.34VRMS
FERR-220-OHM G 2 Q6171_N_G
1 2 PP5V_AUDIO_HPAMP DAC2/3 FSOUTPUTDIFF= 2.67VRMS S
0402
OUT 52 53
DAC2/3 FSOUTPUTSE= 1.34VRMS DEVEL_AUDIO
1
1
R6173
MIN_LINE_WIDTH=0.40MM 0
MIN_NECK_WIDTH=0.20MM 5%
VOLTAGE=4.5V 1/16W
MF-LF
L6110 2 402
FERR-220-OHM VR6101
TPS71745 Q6171_N_S
80 59 =PP5V_S0_AUDIO 1 94 2 4V5_REG_IN 6 IN SON 1 PP4V5_AUDIO_ANALOG 52 56 58
IN OUT OUT
0402 MIN_LINE_WIDTH=0.40MM
CRITICAL MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V
R6120 4V5_REG_EN 4 EN NR/FB 3 4V5_NR
=PP3V3_S0_AUDIO
0
80 58 55 54 52 38 IN
1 2
GND NC 5 MIN_LINE_WIDTH=0.4MM
5%
1/16W
C6122 1
2
MF-LF 1UF C6123 1 1 C6124
A 402 10%
10V
X5R 2
402-1
XW6110 0.1UF
10%
16V
X7R-CERM 2
1UF
10%
2 10V
1
X5R PAGE TITLE

SM 0402 402-1
GND_AUDIO_CODEC 52 56 58 59
AUDIO: CODEC/REGULATORS
MIN_LINE_WIDTH=0.5MM DRAWING NUMBER SIZE
VOLTAGE=0V
XW6111 REVISION
GND_AUDIO_HPAMP
53 R
13.0.0
1
SM MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
61 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C6262
100PF
1 2
5%
50V
CERM
0402
R6262
19.6K2
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL 1
1%
1/20W
MF MAX97220_OUTR OUT 53 56 53 52 IN PP5V_AUDIO_HPAMP
201
D CRITICAL
C6261 R6261
D
33UF
AUD_LO1_R_N 1 2 AUD_LO1_R_C_N 1
26.1K2
MAX97220_INR_N C6250 1 1 C6251 C6252 1 1 C6253
59 55 52 IN 59
OUT 53 59
0.1UF 10UF 1UF 1UF
1% 10% 20% 10% 10%
1/20W 16V 10V 10V 10V
20% X7R-CERM 2 2 X5R-CERM X5R 2 2 X5R
6.3V MF
201 0402 0402-1 402-1 402-1
TANT
CASE-A
53 52 GND_AUDIO_HPAMP GND_AUDIO_HPAMP 52 53
CRITICAL
C6263 R6263
33UF
13
26.1K2
9
59 55 52 IN AUD_LO1_R_P 1 2 59 AUD_LO1_R_C_P 1 MAX97220_INR_P OUT 53 59
PVDD
SVDD
SVDD2
1%
20% 1/20W
MF
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
6.3V
TANT 201
CASE-A
NO_XNET_CONNECTION=TRUE 59 53 IN MAX97220_INR_N 14 INL- OUTL 12 MAX97220_OUTR OUT 53 56
NO_XNET_CONNECTION=TRUE 15 INL+ CRITICAL MIN_LINE_WIDTH=0.4MM
R62641 MAX97220_INR_P MIN_NECK_WIDTH=0.2MM
19.6K
1 C6264 59 53 IN
U6250 BIAS 11 MAX97220_BIAS
1% 100PF MAX97220AETE MIN_NECK_WIDTH=0.2MM
1/20W 5%
50V 59 53 IN MAX97220_INL_P 7 INR+ TQFN OUTR 10 MAX97220_OUTL OUT 53 56
MF 2 CERM MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
201 2 0402 59 53 IN MAX97220_INL_N 8 INR- MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
2
C1P MAX97220_C1P
AUD_HP_PORT_REF MAX97220_SHDN_L 16 SHDN* C1N 4
17 THM_PAD
56 53
1 C6255 1 C6256
PGND
SGND
PVSS
2.2UF 1UF
20% 10%
NO_XNET_CONNECTION=TRUE 2 25V 2 10V
R6274 1 NO_XNET_CONNECTION=TRUE X5R-CERM X5R R62531 R6254
1
NOSTUFF
1 C6274 0402-1 402-1 2.0K 2.0K NOSTUFF
5
19.6K 100PF 5% 5% CRITICAL CRITICAL
1% 1/16W 1/16W
1/20W
MF
5%
2 50V
MAX97220_C1N
C6257 1 1 C6258 MF-LF
402 2
MF-LF Q6250 Q6251
201 2
CERM
MIN_NECK_WIDTH=0.2MM 0.1UF 0.1UF 2 402 DMN2015UFDE DMN2015UFDE
0402 10% 10%
UDFN 1UDFN
C CRITICAL
C6273
16V
X7R-CERM 2
0402
2 16V
X7R-CERM
0402
1
D D
C
33UF R6273 NC MAX97220_OUTL_ZOBEL MAX97220_OUTR_ZOBEL NC
AUD_LO1_L_C_P 126.1K2
MAX97220_PVSS
59 54 52 IN AUD_LO1_L_P 1 2 59 MAX97220_INL_P OUT 53 59
1% MIN_NECK_WIDTH=0.2MM G 3 3 G
20%
6.3V
1/20W
MF 1 C6254 R62511 R6252
1
TANT 201
2.2UF 33 33 S S
CASE-A 20% 5% 5%
25V 1/16W 1/16W
2 X5R-CERM MF-LF MF-LF
CRITICAL 0402-1 402 2 2 402 7 4 4 7
C6271 R6271
33UF
59 54 52 IN AUD_LO1_L_N 1 2 59 AUD_LO1_L_C_N 126.1K2 MAX97220_INL_N OUT 53 59
1%
20% 1/20W 53 52 GND_AUDIO_HPAMP
6.3V MF
TANT 201
CASE-A
MAX97220_OUTL
OUT 53 56
R6272
19.6K2
1
1%
1/20W
MF PP5V_AUDIO_HPAMP
201 53 52 IN
NOSTUFF
C6272 R62571
100PF 100K
1 2 5%
1/20W
5% MF
50V 201 2
CERM MUTE_SWITCH
0402
NC
NOSTUFF NOSTUFF
B Q6252
SSM6N15AFE
D 6
Q6252
SSM6N15AFE
D 3
NOSTUFF
R6256 2 B
SOT563 SOT563
0
5%
1/16W
NOSTUFF MF-LF
R6255 2 G S 1 5 G S 4 402 1
0 MUTE_CONTROL
53 MAX97220_SHDN_L 1 2
5%
1/16W NOSTUFF NOSTUFF
MF-LF
402 R62581 R62591
100K 100K
5% 5%
1/20W 1/20W
MF MF
201 2 201 2
53 52 GND_AUDIO_HPAMP
L6250
FERR-220-OHM
52 IN AUD_GPIO_2 1 2 MAX97220_SHDN_L 53
0402
R62501
100K
5%
1/20W
A
MF
201 2
PAGE TITLE
AUDIO: HEADPHONE AMP
DRAWING NUMBER SIZE

REVISION
R
13.0.0
62 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT CH SPEAKER AMP
APPLE P/N 353S3163 SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
80 55 IN =PP12V_S0_AUDIO_SPKRAMP FC_HPF, TWEETERS = ~847 HZ (4700 PF)
CRITICAL
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)
C6300 1 1 C6301 C6302 1 1 C6303 C6304 1 1 C6305 C6306 1
10UF 10UF 0.1UF 1UF 0.1UF 1UF 470UF
10% 10% 10% 10% 10% 10% 20%
25V 2 25V
2 X5R 25V 2 25V
2 X5R 25V 2 25V
2 X5R 16V 2
X5R X5R X5R POLY
805 805 402 603-1 402 603-1 SM
D D
INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

L6303 C6308 OUTPUT POLARITY FLIP TO
FERR-1000-OHM 4700PF
AUD_LO1_L_N 1 2 59 AUD_LAMP_RINC_P 1 2 59 AUD_LAMP_RIN_P TP_AUD_LAMP_THERM NC MAKE LAYOUT MORE LOGICAL
34
35
36
37
59 53 52 IN
0402
5%
50V
NPO-C0G-CERM PVDD
C6313 NO_XNET_CONNECTION=TRUE
20 INR+ 0.22UF CRITICAL
0805 THERM 17 1 2
AUD_LAMP_BOOTRP
L6302 C6309 19 INR- CRITICAL MIN_LINE_WIDTH=0.20MM
AUD_LAMP_OUTPR
L6305
110-OHM-3A AUD_SPKR_LTWT_OUT_P
FERR-1000-OHM 4700PF WOOFERS & TWEETERS ON UNDER MAC OS U6300 BOOTR+ 30
MIN_NECK_WIDTH=0.15MM 20% MIN_LINE_WIDTH=0.6MM
54
DLY5ATN111SQ2 OUT 57 59
25V MIN_NECK_WIDTH=0.25MM SYM_VER-1
59 53 52 IN AUD_LO1_L_P 1 2 59 AUD_LAMP_RINC_N 1 2 59 AUD_LAMP_RIN_N 55 54 IN AUD_SPKRAMP_MAC_SHDN_L 22 SDNR* SSM3302 X5R
603 AUD_LAMP_OUTNR 4 3 CRITICAL
0402
5%
LFCSP
OUTR+
28 54
1 C6323
50V 29 1000PF
NPO-C0G-CERM 5%
0805 54 AUD_LAMP_MONO 16 MONO 54 AUD_LAMP_OUTPR 1 2 2 25V
CERM
L6300 C6310 26
C6314 0402
FERR-1000-OHM 1UF ONLY WOOFERS ON UNDER WINDOWS OUTR- 27 0.22UF AUD_LAMP_OUTNR 54 AUD_SPKR_LTWT_OUT_N 57 59
OUT
59 52 IN AUD_LO2_L_N 1 2 59 AUD_LAMP_LINC_P 1 2 59 AUD_LAMP_LIN_P 55 54 IN AUD_SPKRAMP_WIN_SHDN_L 9 SDNL* AUD_LAMP_BOOTRN 1 2 MIN_NECK_WIDTH=0.25MM
0402
10% BOOTR- 25 MIN_NECK_WIDTH=0.15MM 20%
25V 11 INL+ 25V
X5R X5R
0402 12 INL- EDGE 10 AUD_LAMP_EDGE 54
603
L6301 C6311 C6315 NO_XNET_CONNECTION=TRUE
FERR-1000-OHM 1UF BOOTL+ 1 0.22UF CRITICAL
1 2 AUD_LAMP_LINC_N 1 2 AUD_LAMP_LIN_N AUD_LAMP_GAIN 21 GAIN AUD_LAMP_BOOTLP 1 2
59 52 AUD_LO2_L_P 59 59 54
L6307
C
IN
C 0402
10%
25V OUTL+
2
3
25V
AUD_LAMP_OUTPL
110-OHM-3A
DLY5ATN111SQ2
SYM_VER-1
AUD_SPKR_LWFR_OUT_N
OUT 57 59
X5R X5R CRITICAL

0402 AUD_LAMP_AVDD 8 VREG/AVDD 603 4 3

54
1 C6324
VOLTAGE=5V 1000PF
OUTL- 5 5%
1 2 2 25V
CERM
0402
80 58 55 52 38 =PP3V3_S0_AUDIO 23 REGEN BOOTL- 6 C6316
0.22UF AUD_LAMP_OUTNL AUD_SPKR_LWFR_OUT_P OUT 57 59
1 2 MIN_LINE_WIDTH=0.6MM
AUD_LAMP_BOOTLN MIN_NECK_WIDTH=0.25MM
NC MIN_NECK_WIDTH=0.15MM
NC 13 20%
NC 25V
C6317 1 14 X5R
603 OUTPUT POLARITY FLIP TO
2.2UF AGND PGND
TEST 15
20%
10V THRM_PAD MAKE LAYOUT MORE LOGICAL CRITICAL CRITICAL
X5R-CERM 2
402
C6320
1 C6322 1
7
24
41
31
32
33
38
39
40
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
25V 25V
CERM 2 CERM 2
PINS 14 & 15 ARE TEST PINS AND 0402 0402
SHOULD BE TIED TO GND

CRITICAL CRITICAL
1
NO_XNET_CONNECTION=TRUE C6319 1 C6321 NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
2 25V
CERM 2 25V
CERM
0402 0402
B B
L6308
FERR-1000-OHM
52 IN AUD_CODEC_MICBIAS1 2 AUD_SPKRAMP_MAC_SHDN_L OUT 54 55
0402 GAIN R6306 R6307
+9 DB NOSTUFF 0 OHM
NOSTUFF
EDGE RATE +12 DB NOSTUFF 47 KOHM
R63011 1 C6312 CONTROL R6304 R6305 AUD_RAMP_MONO NET: +15 DB NOSTUFF NOSTUFF
100K
5% 100PF ON 0 OHM NOSTUFF HIGH = MONO OPERATION +18 DB 47 KOHM NOSTUFF
1/16W
MF-LF
5%
50V
2 CERM
OFF NOSTUFF 0 OHM LOW = STEREO OPERATION +24 DB 0 OHM NOSTUFF
402 2 0402
54 AUD_LAMP_AVDD
NOSTUFF
R6304
1
R6306
1
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
R6308 AUD_LAMP_EDGE 54 AUD_LAMP_MONO 54 AUD_LAMP_GAIN 54
0
52 IN AUD_GPIO_3 1 2 AUD_SPKRAMP_WIN_SHDN_L OUT 54 55
NOSTUFF
5%
1/16W
MF-LF R6305
1 1
R6303 R6307
1
402 0 0 47K
A R6309 1
1
NOSTUFF
C6318
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
100K 2 402 2 402 2 402 PAGE TITLE
100PF
5%
1/16W
MF-LF
5%
50V
2 CERM
AUDIO: LEFT SPKR AMP
402 2 0402 DRAWING NUMBER SIZE

REVISION
R
13.0.0
63 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT CH SPEAKER AMP
APPLE P/N 353S3163 SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
80 54 IN =PP12V_S0_AUDIO_SPKRAMP FC_HPF, TWEETERS = ~847 HZ (4700 PF)
CRITICAL
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)
C6400 1 1 C6401 C6402 1 1 C6403 C6404 1 1 C6405 C6406 1
10UF 10UF 0.1UF 1UF 0.1UF 1UF 470UF
10% 10% 10% 10% 10% 10% 20%
25V 2 25V
2 X5R 25V 2 25V
2 X5R 25V 2 25V
2 X5R 16V 2
X5R X5R X5R POLY
805 805 402 603-1 402 603-1 SM
D D

L6400 C6408 OUTPUT POLARITY FLIP TO
FERR-1000-OHM 1UF
AUD_LO2_R_N 1 2 59 AUD_RAMP_RINC_P 1 2 59 AUD_RAMP_RIN_P TP_AUD_RAMP_THERM NC MAKE LAYOUT MORE LOGICAL
34
35
36
37
59 52 IN
0402
10%
25V
X5R PVDD
C6413 NO_XNET_CONNECTION=TRUE
20 INR+ 0.22UF CRITICAL
0402 THERM 17 1 2
AUD_RAMP_BOOTRP
L6401 C6409 19 INR- CRITICAL MIN_LINE_WIDTH=0.20MM
AUD_RAMP_OUTPR
L6405
110-OHM-3A AUD_SPKR_RWFR_OUT_P
FERR-1000-OHM 1UF ONLY WOOFERS ON UNDER WINDOWS U6400 BOOTR+ 30
MIN_NECK_WIDTH=0.15MM 20% MIN_LINE_WIDTH=0.6MM
55
DLY5ATN111SQ2 OUT 57 59
25V MIN_NECK_WIDTH=0.25MM SYM_VER-1
59 52 IN AUD_LO2_R_P 1 2 59 AUD_RAMP_RINC_N 1 2 59 AUD_RAMP_RIN_N 54 IN AUD_SPKRAMP_WIN_SHDN_L 22 SDNR* SSM3302 X5R
603 AUD_RAMP_OUTNR 4 3 CRITICAL
0402
10%
LFCSP
OUTR+
28 55
1 C6423
25V 29 1000PF
X5R 5%
0402 55 AUD_RAMP_MONO 16 MONO 55 AUD_RAMP_OUTPR 1 2 2 25V
CERM
L6402 C6410 26
C6414 0402
FERR-1000-OHM 4700PF WOOFERS & TWEETERS ON UNDER MAC OS OUTR- 27 0.22UF AUD_RAMP_OUTNR 55 AUD_SPKR_RWFR_OUT_N 57 59
OUT
59 53 52 IN AUD_LO1_R_P 1 2 59 AUD_RAMP_LINC_P 1 2 59 AUD_RAMP_LIN_P 54 IN AUD_SPKRAMP_MAC_SHDN_L 9 SDNL* AUD_RAMP_BOOTRN 1 2 MIN_NECK_WIDTH=0.25MM
0402
5% BOOTR- 25 MIN_NECK_WIDTH=0.15MM 20%
50V 11 INL+ 25V
NPO-C0G-CERM X5R
0805 12 INL- EDGE 10 AUD_RAMP_EDGE 55
603
L6403 C6411 C6415
FERR-1000-OHM 4700PF BOOTL+ 1 0.22UF
CRITICAL
1 2 AUD_RAMP_LINC_N 1 2 AUD_RAMP_LIN_N AUD_RAMP_GAIN 21 GAIN AUD_RAMP_BOOTLP 1 2
59 53 52 AUD_LO1_R_N 59 59 55
L6407
C
IN
C 0402
5%
50V OUTL+
2
3
25V
AUD_RAMP_OUTPL
110-OHM-3A
DLY5ATN111SQ2
SYM_VER-1
AUD_SPKR_RTWT_OUT_P
OUT 57 59
NPO-C0G-CERM X5R CRITICAL

0805 AUD_RAMP_AVDD 8 VREG/AVDD 603 4 3
55
1 C6424
VOLTAGE=5V 1000PF
OUTL- 5 5%
1 2 2 25V
CERM
0402
80 58 54 52 38 =PP3V3_S0_AUDIO 23 REGEN BOOTL- 6 C6416
0.22UF AUD_RAMP_OUTNL AUD_SPKR_RTWT_OUT_N OUT 57 59
1 2 MIN_LINE_WIDTH=0.6MM
AUD_RAMP_BOOTLN MIN_NECK_WIDTH=0.25MM
NC MIN_NECK_WIDTH=0.15MM
NC 13 20%
NC 25V
C6417 1 14 X5R
603
2.2UF AGND PGND
TEST 15
20%
10V THRM_PAD CRITICAL CRITICAL
X5R-CERM 2
402
C6420
1 C6422 1
7
24
41
31
32
33
38
39
40
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
25V 25V
CERM 2 CERM 2
PINS 14 & 15 ARE TEST PINS AND 0402 0402
SHOULD BE TIED TO GND

CRITICAL CRITICAL
1
NO_XNET_CONNECTION=TRUE C6419 1 C6421 NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
2 25V
CERM 2 25V
CERM
0402 0402
B B
GAIN R6406 R6407

+9 DB NOSTUFF 0 OHM
EDGE RATE +12 DB NOSTUFF 47 KOHM
CONTROL R6404 R6405 AUD_RAMP_MONO NET: +15 DB NOSTUFF NOSTUFF
ON 0 OHM NOSTUFF HIGH = MONO OPERATION +18 DB 47 KOHM NOSTUFF
OFF NOSTUFF 0 OHM LOW = STEREO OPERATION +24 DB 0 OHM NOSTUFF
55 AUD_RAMP_AVDD
NOSTUFF
R6404
1
R6406
1
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
AUD_RAMP_EDGE 55 AUD_RAMP_MONO 55 AUD_RAMP_GAIN 55
NOSTUFF
R6405
1 1
R6403 R6407
1
0 0 47K
A 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A
2 402 2 402 2 402 PAGE TITLE
AUDIO: RIGHT SPKR AMP

DRAWING NUMBER SIZE

REVISION
R
13.0.0
64 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP4V5_AUDIO_ANALOG
MIKEY RECEIVER CKT

58 52 IN
80 =PP3V3_S0_AUDIO_DIG PORT B LEFT(HEADSET MIC)

I2C ADDRESSES
HP=80HZ, LP=10.63KHZ MIKEY READ 0111 0011 0X73
CRITICAL
C6555 C6560 WRITE: 0X72 READ: 0X73 APN 353S2640 MIKEY WRITE 0111 0010 0X72
R65621 4.7UF
1 1
0.1UF CHS READ 0111 0111 0X77
10K 20% 10%
5% 10V MIKEY 1A CHS WRITE 0111 0110 0X76
1/20W X5R-CERM 2 2 16V
X7R-CERM
MF 0402 0402 APN:353S2640
201 2
MIKEY ADDRESS: WRITE=72H, READ=73H
AUDIO JACK: HP CONNECTOR WITH MIKEY
PLACE XWS 6500 & 6501 AT J6500 PINS
14
15
CRITICAL
D AVDD
U6551
D
I2C PULLUPS ON SOUTHBRIDGE PAGE CD3285A0
MQFN-RSV
47 =I2C_MIKEY_SCL 3 SCL MICBIAS 10 HS_MIC_BIAS 56
IN
11 HS_SW_DET MIN_NECK_WIDTH=0.20MM
47 =I2C_MIKEY_SDA 2 SDA DETECT
BI
12 AUD_I2C_INT_L 4 INT* BYPASS 9 HS_RX_BP

OUT
1 NO_XNET_CONNECTION=TRUE
20 IN AUD_IPHS_SWITCH_EN ENABLE
R65541
HS_HDET 13 HDET 1K
NOSTUFF 5%
1/16W
16
R6561 CS MF-LF
402 2
47K 1 C6556
58 IN AUD_PORTD_DET_L 1 2
R65551 DGND AGND 0.01UF
5% 100K 10%
2 25V
5
6
7
8
12
1/16W 5%
MF-LF X7R
1/20W 402
402 MF
201 2
59 58 56 52 GND_AUDIO_CODEC
C6552 R6550
0.1UF 2.2K 2
1 2 1
59 52 OUT AUD_MIC_INL_P 59 AUD_HS_MIC_RC_P AUD_HS_MIC_P IN 56 59
5%
10% CRITICAL 1/16W CRITICAL
C
16V
X7R-CERM
0402
R6556
100K
5%
1
1 C6550
0.0082UF
MF-LF
402 1 C6558
27PF
C
1/20W 10% 5%
25V 50V
C6553 MF
201 2
2 X7R-CERM
0402 R6551
2 CERM
0402-1
0.1UF 0
1 2 AUD_HS_MIC_RC_N 1 2
59 52 OUT AUD_MIC_INL_N 59 AUD_HS_MIC_N IN 56 59
5%
10% 1/16W
16V MF-LF
X7R-CERM 402
0402
R/C6750 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)
NOSTUFF
R65531
1K
5%
1/16W
MF-LF
402 2
L6500
FERR-1000-OHM 59 58 56 52 GND_AUDIO_CODEC
58 AUD_TYPEDET_R 1 2
OUT
0402
L6501
FERR-1000-OHM
59 56 AUD_HS_MIC_N 1 2
OUT
0402
APN 516S0687
L6502
FERR-1000-OHM CRITICAL
B 59 56 OUT AUD_HS_MIC_P 1 2 NO_XNET_CONNECTION=TRUE B
0402
J6500 CRITICAL
CRITICAL 54722-0224 L6507
L6503 F-ST-SM FERR-120-OHM-2.0A
FERR-120-OHM-2.0A 1 2 1 2
AUD_J1_TYPEDET_R AUD_J1_HP_OUTL MAX97220_OUTL IN 53
HS_MIC_BIAS 1 2 3 4 MIN_LINE_WIDTH=0.25MM
56 59 AUD_J1_MIC_N AUD_J1_HP_PORT_REF MIN_NECK_WIDTH=0.20MM 0402
0402 MIN_LINE_WIDTH=0.25MM CRITICAL
MIN_NECK_WIDTH=0.20MM 59 AUD_J1_MIC_P 5 6 AUD_J1_HP_OUTR
7 8
L6508
FERR-120-OHM-2.0A
9 10
1 2 AUD_HP_PORT_REF 53
11 12 OUT
CRITICAL 0402
L6511 AUD_J1_MIC_BIAS 13 14
FERR-120-OHM-2.0A 15 16 CRITICAL
=PP3V3_S4_AUDIO_DIG 1 2 AUD_J1_PP3V3_S0 17 18 =I2C_CHS_SCL
L6509
80 IN 47 FERR-120-OHM-2.0A
0402 MIN_LINE_WIDTH=0.25MM 47 =I2C_CHS_SDA 19 20 AUD_SPDIF_OUT 52 89
IN IN 1 2 MAX97220_OUTR
MIN_NECK_WIDTH=0.20MM 21 22 IN 53
AUD_J1_TIPDET2_R AUD_J1_TIPDET1_R MIN_LINE_WIDTH=0.25MM
L6510
FERR-1000-OHM
L6505 1 2 AUD_TIPDET1_R OUT 58
FERR-1000-OHM 0402
1 2
58 OUT AUD_TIPDET2_R
0402
R6506
0
A 59 58 56 52 IN GND_AUDIO_CODEC 1
5%
1/16W
2
VOLTAGE=0V
AUD_J1_GND_ANALOG
NOSTUFF NOSTUFF NOSTUFF SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013 A

MF-LF
402
NOSTUFF NOSTUFF NOSTUFF DZ6503 DZ6504 DZ6505 PAGE TITLE
DZ6500 DZ6501 DZ6502 ESDALC5-1BM2 ESDALC5-1BM2 ESDALC5-1BM2 AUDIO: Jack, Mikey, CHS Switch
2
SOD882 SOD882 SOD882
ESDALC5-1BM2 ESDALC5-1BM2 ESDALC5-1BM2
2
DRAWING NUMBER SIZE

1
SOD882 SOD882 SOD882

POLARITY REVISION
1
INTENTIONALLY R
13.0.0
OPPOSIDE
1
1
2

65 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER CABLE CONNECTORS
APPLE P/N 518S0862
CRITICAL CRITICAL
J6603 J6602
504050-0691 504050-0691
M-RT-SM M-RT-SM
7 7
WOOFER (BL) WOOFER (BR)
59 54 IN AUD_SPKR_LWFR_OUT_P 1 59 55 IN AUD_SPKR_RWFR_OUT_P 1
AUD_SPKR_LWFR_OUT_N 2 AUD_SPKR_RWFR_OUT_N 2
D
59 54
59
IN
OUT AUD_SPKR_VENDOR_ID_L
3
59 55
59
IN
OUT AUD_SPKR_VENDOR_ID_R
3 D
4 4
59 54 IN AUD_SPKR_LTWT_OUT_P 5 59 55 IN AUD_SPKR_RTWT_OUT_P 5
59 54 IN AUD_SPKR_LTWT_OUT_N 6 59 55 IN AUD_SPKR_RTWT_OUT_N 6
TWEETER (FL) 8
TWEETER (FR) 8
C C
B B
PAGE TITLE
Audio: Spkr/Mic Conn.

DRAWING NUMBER SIZE

REVISION
R
13.0.0
66 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IPHS HS Detect Debounce CKT

80 55 54 52 38 =PP3V3_S0_AUDIO
R67441
100K
5%
1/20W
MF
201 2 R6745
0
D
AUD_IP_PERPH_DET_DB 1
5%
2 AUD_IP_PERIPHERAL_DET
OUT 12
D
1/16W
MF-LF
Q6741 D 3 402
SSM6N15AFE
SOT563
L6743 NC
FERR-1000-OHM
AUD_J1_DET_RC 1 2 AUD_IP_PERPH_DET_R 5 G S 4
58
0402
Q6741 D 6
SSM6N15AFE
AUDIO CONNECTOR DETECT STATES SOT563
NOSTUFF
1 C6741 NOTHING SPDIF HEADPHONE
0.1UF 2 G S 1
10%
16V
AUD_J1_TYPEDET_R 1 1 0
2 X7R-CERM
0402
AUD_J1_TIPDET_R 0 1 1
AUD_OUTJACK_INSERT_L 1 0 0
AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV
PORT D DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE)

59 58 52 OUT AUD_SENSE_A
C C
58 56 52 PP4V5_AUDIO_ANALOG
1
R6795 1
R6796
IN
1%
5.11K
1/16W
1%
20.0K
1/16W
Target Display Mode Detect
MF-LF MF-LF
2 402 2 402
R6742 1
47K AUD_SENSE_A
5%
1/20W
Q6740 AUD_PORTD_DET_L OUT 56 AUD_PORTB_DET_L NC
59 58 52 IN
MF NTZD3158P
SOT563
R6743 1
1
201 2
S
47K
AUD_TIPDET1_R 2
5%
1/20W
Q6796 D 3 Q6796 D 6
56 IN
G MF SSM6N15AFE SSM6N15AFE 1
R6731
201 2 SOT563 SOT563
R67411 D 39.2K
1%
47K
Q6740 1/16W
6
5% MF-LF
1/20W NTZD3158P 5 G S 4 2 G S 1 2 402
MF SOT563
4
201 2
S AUD_J1_DET_RC 58
AUD_OUTJACK_INSERT_L AUD_PORTA_DET_L NC
56 IN AUD_TIPDET2_R 5
G
D
APN:376S1032 TBT/DP Audio Enable
Q6797 D 3 Q6800 D 3
SSM6N15AFE Q6797 D 6 SSM6N15AFE
3
SOT563 SOT563
SSM6N15AFE
SOT563 L6732
FERR-1000-OHM
R6792 5 G S 4 DP_TBT_SEL 1 2 AUD_LI_TIPDET 5 G S 4
41 11 IN
47K 2 G S 1 0402
AUD_TIPDET_INV 1 2
5%
1/16W R67301
R67911 AUD_OUTJACK_INSERT 10K
B
MF-LF
B 100K
5%
402 1
C6791
0.1UF
5%
1/20W
MF
1/20W 20% 10V 201 2
MF 2 CERM 402
201 2
PLACE C6700 CLOSE TO Q6700 PIN 4

58 56 52 IN PP4V5_AUDIO_ANALOG
C6700 1
0.1UF
10%
16V
R67011 1
R6703
X7R-CERM 2 270K 100K
5%
0402
1/20W
MF
Q6700 5%
1/20W
201 2 DMC2400UV MF
4
59 58 56 52 GND_AUDIO_CODEC SOT563 2 201
AUD_TYPEDET_OD_INV
S
56 IN AUD_TYPEDET_R
P-CHN
5
6
D
A Q6700
A
3
N-CHN
AUD_TYPEDET_OD 2 G DMC2400UV SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013

SOT563 PAGE TITLE
S
AUDIO: Detects/Grounding
R67021 DRAWING NUMBER SIZE
100K 1 051-9889 D
5%
1/20W Apple Inc. REVISION
MF
201 2 R
13.0.0
59 58 56 52 GND_AUDIO_CODEC NOTICE OF PROPRIETARY PROPERTY: BRANCH
67 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD
CODEC OUTPUT SIGNAL PATHS SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM
FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX MAC SHDN WIN SHDN DET ASSIGNMENT AUDIO * 0.1 MM ? AUDIODIFF * Y 0.1 MM 0.1 MM 10 MM 0.1 MM 0.1 MM
HP/LINE OUT 0X03 (3) 0X03 (3) 0X0A (10,D) GPIO_2 GPIO_2 0X0A (DET D) TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM
SPKROUT * 0.2 MM ? SPKROUTDIFF * Y 0.6 MM 0.25 MM 10 MM 0.2 MM 0.2 MM

PRIMARY SPKRS (WFR) 0X04 (4) 0X04 (4) 0X0B (11) MICBIAS GPIO_3 N/A
SECONDARY SPKRS (TWT) 0X03 (3) 0X03 (3) 0X0A (10,V24) MICBIAS N/A N/A
SPDIF OUT N/A 0X08 (8) 0x10 (16) N/A N/A 0X0D (DET B) TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_TYPE
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AUDIODIFF * AUDIODIFF
CODEC INPUT SIGNAL PATHS TABLE_PHYSICAL_ASSIGNMENT_ITEM
SPKROUTDIFF * SPKROUTDIFF
FUNCTION CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT
D
I215 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_P 52 53 54
SPDIF IN 0X07 (7) 0x0F (15) N/A 0X09 (DET A)
D INTERNAL MIC ARRAY 0X06
0X05
(6)
(5)
0X0E
0X12
(14,LEFT & RIGHT)
(18,LEFT)
N/A N/A I216
I217
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIO
AUDIO
AUD_LO1_L_N
AUD_LO1_L_C_P
52 53 54
53
EXTERNAL MIC 0X06 (6) 0X0D (13,V22,B,LEFT) Lynx POINT GPIO 16 Lynx POINT GPIO 5 (RCVR INT) I218 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_C_N 53
Lynx POINT GPIO 3 (PERIPH DET)
I211 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_P 52 53 55
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_N 52 53 55

I212
OTHER DETECT AUD_LO1_R_C_P
I210 AUDIO_DIFFPAIR AUDIODIFF AUDIO 53
FUNCTION CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT I209 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_C_N 53
MULTIPLE SPKR VENDORS N/A N/A N/A 0X0C (DET C) I208 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_L_P 52 54
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_L_N 52 54

I206
I207 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_R_P 52 55
I204 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_R_N 52 55
I205 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LINC_P 55
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LINC_N 55

I203
I220 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RINC_P 55
I219 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RINC_N 55
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LIN_P 55

I222
I221 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LIN_N 55
I224 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RIN_P 55
I223 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RIN_N 55

80 59 52 =PP5V_S0_AUDIO
I226 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LINC_P 54
I225 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LINC_N 54

SPEAKERID SPEAKERID
I227 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RINC_P 54
R68101 R6811
1
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RINC_N 54
100K 100K I229
AUD_LAMP_LIN_P
1% 1% I228 AUDIO_DIFFPAIR AUDIODIFF AUDIO 54
1/16W 1/16W
MF-LF MF-LF I230 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LIN_N 54
402 2 2 402
I264 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RIN_P 54
C 57 IN AUD_SPKR_VENDOR_ID_L AUD_SPKR_VENDOR_ID_R IN 57 I263 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RIN_N 54

C
R68121 R6813
1
100K 100K
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402 PORT C DETECT(SPEAKER MISMATCH)
SPEAKERID SPEAKERID
58 52 OUT AUD_SENSE_A I236 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INL_P 53
AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INL_N 53

I238
SPEAKERID
I237 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INR_P 53
R6816 SPEAKERID AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INR_N 53
100K 2 I239
1
R6894 1
I240 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RWFR_OUT_P 55 57
1% 10K I241 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RWFR_OUT_N 55 57

1/16W 1%
MF-LF 1/16W I242 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RTWT_OUT_P 55 57
402 MF-LF
402 2 I243 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RTWT_OUT_N 55 57
I244 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LWFR_OUT_P 54 57
80 59 52 =PP5V_S0_AUDIO I246 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LWFR_OUT_N 54 57
SPEAKERID I245 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_P 54 57

NC AUD_PORTC_DET_L
1 C6810 I247 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_N 54 57
0.1UF
10%
16V
2 X7R-CERM
0402 AUD_MIC_INL_P
I326 AUDIO_DIFFPAIR AUDIODIFF AUDIO 52 56
Q6800 D 6
I327 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_INL_N 52 56
SSM6N15AFE I328 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HS_MIC_RC_P 56
SPEAKERID SOT563
CRITICAL I329 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HS_MIC_RC_N 56
SPEAKERID
U6800 SPEAKERID
L6802 I254 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HS_MIC_P 56
MAX9119_POS 3 5 MAX9119EXK-T R6820 FERR-1000-OHM G S 1

B
AUD_HS_MIC_N
B
2 I255 AUDIO_DIFFPAIR AUDIODIFF AUDIO 56
SC70-5 33 AUD_J1_MIC_P
I324 AUDIO_DIFFPAIR AUDIODIFF AUDIO 56
1 MAX9119_OUT 1 2 SPKR_MATCH_DRV_R 1 2 SPKR_MATCH_DRV
I325 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_J1_MIC_N 56
5% 0402
MAX9119_NEG 4 1/16W
2 MF-LF
402
80 59 52 =PP5V_S0_AUDIO
SPEAKERID
R68141
226K 58 56 52 GND_AUDIO_CODEC
1%
1/16W
MF-LF
402 2 SPEAKERID
R6817
37.4K2
1
1%
SPEAKERID 1/16W
SPEAKERID MF-LF
R68151 1 C6811
402
75K 2.2UF
1% 10%
1/16W 16V
MF-LF 2 X7R-CERM
402 2 805
PAGE TITLE
AUDIO: Speaker ID
DRAWING NUMBER SIZE

REVISION
R
13.0.0
68 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.425V "G3Hot" Regulator
D Switching freq: 409 kHz = 13.5

L6901
D
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
MLB to AC-DC Connector 138S0676 138S0691 C6905
TABLE_ALT_ITEM
80 =PP12V_G3H_REG_3V42_G3H
CRITICAL
1 C6906 1 C6907 1 C6902 94 P3V42G3H_BOOST
J6900 1UF 1UF 10UF
43650-0603 10%
25V
10%
25V
10%
25V R6901
1
F-RT-TH 2 X6S-CERM 2 X6S-CERM 2 X6S 150K 1 C6903
3
1 0402 0402 0805 1% 0.22UF
1/16W VIN BOOST 10%
2 MF-LF 16V CRITICAL
3
PP12V_G3H_ACDC 80
2 402 U6900 2 CERM
402 L6901
LT3470AED 33UH PP3V42_G3H_REG 80
4 DFN Vout = 3.425
94 P3V42G3H_SHDN_L 8 SHDN* SW 4 94 P3V42G3H_SW 1 2 250mA max output
5 EMC EMC CRITICAL (Switcher limit)
6 BIAS 2 CDPH4D19FHF-SM
J6900.4:3mm J6900.5:3mm J6900.4:4mm NOSTUFF 7 NC
C6911 C6912 C6913 NC
1
10UF
1
1000PF
1
1000PF
R6902
1
1 C6901 FB 1
10% 5% 5%
49.9K 1000PF THRM
1%
2 16V
X5R-CERM 2 25V
CERM 2 25V
CERM 1/16W
MF-LF
5%
25V
2 CERM
GND PAD 1 C6904 R6903
1 1 C6905
22PF 348K 22UF
9
0805 0402 0402
2 402 0402 5% <Ra> 1% 20%
50V 6.3V
2 CERM 1/16W 2 X5R-CERM1
0402 MF-LF 0603
2 402
94 P3V42G3H_FB
R6904
1
200K
C <Rb> 1%
1/16W
MF-LF
C
MLB to AC-DC Supplemental Signal Connector 2 402
SILK_PART=PwrSig
CRITICAL Vout = 1.25V * (1 + Ra / Rb)
J6901
53780-8606
M-RT-SM
7
R6911 80 66 64 61 =PP3V3_S0_VRD
100
45 OUT PWR_BTN 1 2 PWR_BTN_R 1
5% 2
1/16W 2 1
C6914 1 MF-LF
402
D6911 91 50 OUT SNS_ACDC_N 3 R6913
1UF 6.8V-100PF 91 50 SNS_ACDC_P 4 10K
OUT 5%
10%
6.3V
CERM 2
402 1
402
BURSTMODE_EN_R_L
SMC_ACDC_ID
5
6
1/16W
MF-LF
2 402
12V S5 FET CRITICAL
Q6970
60 45 OUT IRFH3702TRPBF
PQFN
8 60 45 SMC_ACDC_ID
R6912
S
=PP12V_G3H_FET_P12V_S5 PP12V_S5_FET
C6916
1
1 80 OUT 80
1K
65 45 IN BURSTMODE_EN_L 1 2 1UF
10%
5% 6.3V
C6915
G
1 1/16W 2 CERM 2
0.1UF MF-LF
402
D6912 402
10% 6.8V-100PF
4
16V
X7R-CERM 2 402
0402
1
1 C6970
0.1UF
10%
16V
2 X7R-CERM
FET_EN_P12V_S5_R
0402
B B
1
VCC R6972
1
49.9K
U6970
SLG5AP022-200030V
1%
1/16W
MF-LF
Input: 2.4V to 5.5V 2 TDFN 2 402
45 44 IN SMC_PM_G2_EN ON D 5
3 CRITICAL 7
NC NC G FET_EN_P12V_S5
SMC_PM_G2_EN IS PULLED DOWN ON SMC PAGE S 6
PG 8 PM_PGOOD_FET_P12V_S5 70
OUT
THRM
GND PAD
9
PAGE TITLE
Power Connectors / VReg G3Hot

DRAWING NUMBER SIZE

REVISION
R
13.0.0
69 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCC S0 Regulator 80 62 =PP5V_S0_REG_CPUVCC_S0

Pull-ups 1
OC trip point: 114 A 1
R7000 93 61 REG_PWM_CPUVCC_1_R R7026 1
0
2 REG_PWM_CPUVCC_1 62 93 (pu 2)
PPVCCIO_S0_CPU OUT
18 8 6 2.2
5 E10 5%
1/16W
5%
1/16W
MF-LF
402
Switching freq: 403 kHz = C7017 1 NOSTUFF
MF-LF
REG_PWM_CPUVCC_2_R R7027 1
0
2 REG_PWM_CPUVCC_2 (pu 2)
R7003 2 402 93 61 OUT 62 93
0.1UF 1 1 1 REG_VCC_U7000 5% MF-LF
10% R7017 R7018 R7019 93 61
1/16W 402
16V 54.9 90.9 110 0
X7R-CERM 2
0402 1% 1% 1% 1 C7000 93 61 REG_PWM_CPUVCC_3_R R7028 1 2 REG_PWM_CPUVCC_3 OUT 62 93 (pu 2)
Compensation and feedback 1/16W 1/16W 1/16W 10UF 5% MF-LF
MF-LF MF-LF MF-LF 20%
AGND_CPU 1/16W 402
D 93 61 REG_CPUVCC_COMP
REG_CPUVCC_DVC 61 93
93 81 62 61
93 61 8 CPU_VIDSCLK
PLACE_NEAR=U7000.15:12.7mm
2 402 2 402 2 402
PLACE_NEAR=U7000.13:12.7mm
2 16V
X6S-CERM
0603 61 REG_PWM_CPUVCC_4_R R7029 1
0
2 REG_PWM_CPUVCC_4 OUT 82 (pu 2) D
5% MF-LF
CPU_VIDALERT_L 1/16W 402
25
93 61 8
1 C7031 1 C7030 1 CPU_VIDSOUT
NOSTUFF
68PF 0.0012UF R7037 93 61 8
5% 10% 1.82K VCC
2 50V 2 50V 1%
COG-CERM
0402
CERM
0402 1/16W
MF-LF
U7000
CPUVCC_COMP_RC 2 402 ISL6372
93
CPUVCC_DVC_RC 93 (pgood) 61 REG_CPUVCC_PGOOD 11 VR_RDY QFN FS_FDVID 24 REG_CPUVCC_FDVID 61 93 (straps)
1 CRITICAL
R7030 93 61 REG_CPUVCC_MEMVRSEL 26 MEMVRSEL EN_PWR_OVP 3 PM_EN_REG_CPUVCC_S0 70
7.15K 1 C7037 Pull-ups 2 REG_CPUVCC_TMX 18 1M
1% 0.0012UF (straps) 93 61 TMX_DRP_DE_TC R70141
1/16W 10% 20 VIN- 1 93 REG_CPUVCC_VIN 2
MF-LF 93 61 REG_VCC_U7000 (straps) 93 61 REG_CPUVCC_IMX IMADR_BTRM
2 402
50V
2 CERM To feedback 15 VIN+ 2 1% MF-LF PP12V_S0_CPUVCC_FLT 62 93
0402 (pu 1) 93 61 8 IN CPU_VIDSCLK SVCLK 1/16W 402
REG_CPUVCC_FB 61 93
14 29
NOSTUFF NOSTUFF NOSTUFF (pu 1) 93 61 8 OUT CPU_VIDALERT_L SVALERT* PWM1 REG_PWM_CPUVCC_1_R 61 93
NOSTUFF 1 1 1 1 CPU_VIDSOUT 13 27 REG_PWM_CPUVCC_2_R

1 1 C7033 R7021 R7022 R7023 R7024 (pu 1) 93 61 8 BI SVDATA PWM2 61 93
R7031 1 C7038 0 0 0 0 PWM3 30 REG_PWM_CPUVCC_3_R 61 93
1.07K 390PF 5% 5% 5% 5% (vsen in) 93 61 REG_CPUVCC_VSEN 5 VSEN
1% 10% 0.0012UF 1/16W 1/16W 1/16W 1/16W PWM4 28 REG_PWM_CPUVCC_4_R 61
50V 10%
1/16W 2 X7R-CERM 50V MF-LF MF-LF MF-LF MF-LF 4
MF-LF 2 CERM 2 402 2 402 2 402 2 402 93 61 REG_CPUVCC_RGND RGND
2 402
0402
0402 10 ISEN1- 37 REG_ISENVCC_1_NR IN 62 93
93 61 REG_PWM_CPUVCC_1_R 93 61 REG_CPUVCC_DVC DVC_MEM
93 CPUVCC_FB_R_1 CPUVCC_FB_RC 93 CPUVCC_FB_RC_2 93
8 ISEN1+ 38 REG_ISENVCC_1_P IN 62 93
93 61 REG_PWM_CPUVCC_2_R (fb in) 93 61 REG_CPUVCC_FB FB
1 1 NOSTUFF REG_PWM_CPUVCC_3_R REG_CPUVCC_PSICOMP 7 ISEN2- 33 REG_ISENVCC_2_NR
R7032 R7033 1 93 61 (psi comp) 93 61 PSICOMP IN 62 93
324 249 R7038 61 REG_PWM_CPUVCC_4_R ISEN2+ 34 REG_ISENVCC_2_P IN 62 93

1% 1% 3.83K (hf comp) 93 61 REG_CPUVCC_HFCOMP 6 HFCOMP
1/16W 1/16W 1%
MF-LF MF-LF 1/16W 9 COMP ISEN3- 39 REG_ISENVCC_3_NR IN 62 93
(comp out) REG_CPUVCC_COMP
2 402 2 402 MF-LF 93 61
ISEN3+ 40 REG_ISENVCC_3_P
2 402 IN 62 93
AGND_CPU 61 62 81 93 (straps) 93 61 REG_CPUVCC_NPSI 22 AUTO_NPSI

93 CPUVCC_FB_R_2 ISEN4- 35 REG_ISENVCC_4_NR IN 81
(imon out) REG_CPUVCC_IMON 12 IMON ISEN4+ 36 REG_ISENVCC_4_P

C7034 To PSI comp
93 61 48 IN 82
R7034
C 2.2NF
1 2 93 CPUVCC_PSICOMP_RC 1
787
2 REG_CPUVCC_PSICOMP 61 93
93 61 REG_VCC_U7000 93 61 REG_CPUVCC_MEMVRSEL
(vr hot out) 61 REG_CPUVCC_VRHOT_L 16 VR_HOT* RSET 23 REG_CPUVCC_RSET 93 C
1% REG_CPUVCC_TM 21 TM_EN_OTP OPEN1 17
10% 1/16W
93 61
NC
10V
X5R-CERM
MF-LF NOSTUFF OPEN2 19 NC
402
0201 1
R7039 OPEN3 32 NC
To VSense To HF comp 0 R70091
R7035 R7036 5% 0 GND THRM_PAD
1
R7016
10 2.1K 1/16W 5%
1 2 93 61 REG_CPUVCC_VSEN 1 2 REG_CPUVCC_HFCOMP 61 93 MF-LF 1/16W Tie to GND for VR12.5 10K
31
41
1% NOSTUFF 1% 2 402 MF-LF
402 2 OMIT 1%
1/16W
1/16W 1/16W MF-LF
MF-LF 1 C7035 MF-LF U7000.41:6MM
402 402 2 402
0.01UF 93 61 REG_CPUVCC_DVC XW7000
20% 93 81 62 61 AGND_CPU SM
16V
2 X7R-CERM 1 2 AGND_CPU 61 62 81 93
0402
AGND_CPU 61 62 81 93
Voltage sense input IMON output Temp measurement
OMIT
R7150.1:25MM 93 61 REG_VCC_U7000 93 61 REG_VCC_U7000
=PPCPUVCC_S0_CPU
XW7042 R7042
80 48 10 8 6 SM
1K Straps
1 2 93 SNS_VCC_XW_P 1 2
R70521 R70901
5% 1.69M 1K
1/16W 1% 5% 93 61 REG_VCC_U7000
MF-LF 1/16W 1/16W
402 NO_XNET_CONNECTION=TRUE MF-LF MF-LF
Sense from CPU R7040 R7041 To voltage sense 0402 2 To sense amps 402 2
0 10 NOSTUFF
93 8 IN CPU_VCCSENSE_P 1 2 93 CPU_VCCSENSE_R_P 1 2 REG_CPUVCC_VSEN 61 93 REG_CPUVCC_IMON OUT 48 61 93 REG_CPUVCC_TM 61 93
1 1 1 1
R7001 R7003 R7005 R7007
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF 1
NOSTUFF
C7048 R70501 1 C7050
0.0047UF
1 1 C7090
0.1UF
158K
1% 1%
124K
1%
150K
5%
0 B
402 402
0.0012UF 402 10% 10% 1/20W 1/20W 1/20W 1/20W
NO_XNET_CONNECTION=TRUE 10%
50V
1%
1/16W
25V
2 CERM RT7090 16V
2 X7R-CERM ICCMAX = 75A MF
2 201
MF
2 201
MF
2 201
MF
2 0201
R7045 R7046 2 CERM
0402
MF-LF
402 2 0402 6.8K 0402
0 10 0603 93 61 REG_CPUVCC_IMX
93 9 IN CPU_VCCSENSE_N 1 2 93 CPU_VCCSENSE_R_N 1 2 REG_CPUVCC_RGND 61 93
93 CPUVCC_IMON_R 2 93 61 REG_CPUVCC_FDVID
5% 5%
OMIT 1/16W 1/16W 1 C7041 1 C7046 93 61 REG_CPUVCC_TMX
XW7042.2:3MM MF-LF
402
MF-LF
402 0.0012UF 0.0012UF R70511 AGND_CPU 61 62 81 93
REG_CPUVCC_NPSI
XW7047 R7047
10% 10% 30.9K
93 61
SM 2 50V
CERM 2 50V
CERM 1%
1K 0402 0402 1/16W NOSTUFF
1 2 93 SNS_VCC_XW_N 1 2 MF-LF 1 1 1 1
5% AGND_CPU 61 62 81 93
402 2 R7002 R7004 R7006 R7008 1 C7001
1/16W AGND_CPU 61 62 81 93 44.2K 0 147K 249K 0.047UF
MF-LF 1% 5% 1% 1%
402 1/20W 1/20W 1/20W 1/20W 10%
16V
MF MF MF MF 2 X5R
2 201 2 0201 2 201 2 201 0201
AGND_CPU 61 62 81 93
Power good VRHot to ProcHot

R7093
0
61 REG_CPUVCC_VRHOT_L 1 2 CPU_PROCHOT_L OUT 6 44 45 86
80 66 64 60 =PP3V3_S0_VRD
5%
1/16W
1
R7098 MF-LF
402
1 C7091
10K 47PF
5% 5% Per Intel Shark Bay PDG
50V
1/16W 2 CERM
A MF-LF
2 402
402
SYNC_MASTER=J16_ROSSANA SYNC_DATE=07/29/2013 A
61 REG_CPUVCC_PGOOD PM_PGOOD_REG_CPUVCC_S0 71
PAGE TITLE
MAKE_BASE=TRUE OUT
VReg CPU VCC Cntl
DRAWING NUMBER SIZE

REVISION
R
13.0.0
70 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Filtered 12V Rail L7100
0.36UH-30A-0.6MOHM
80 =PP12V_S0_REG_CPUVCC_S0 1 2 PP12V_S0_CPUVCC_FLT 61 62 93
SDP110808MR36MF-TH
80 62 61 =PP5V_S0_REG_CPUVCC_S0
93 62 61 PP12V_S0_CPUVCC_FLT
EMC EMC
EMC EMC CRITICAL CRITICAL CRITICAL CRITICAL Q7110.5:3MM Q7110.5:3MM
CPU Phase 1 Q7110.5:3MM Q7110.5:3MM
1 C7118 1 C7119 CRITICAL 1
C7110 1
C7111 1 C7112 1 C7113 1 C7114 1 C7115
U7110.7:3MM 93 REG_BOOT_CPUVCC_1_RC 1000PF 1000PF Q7110 180UF 180UF 10UF
20%
10UF
20%
1UF
10% 10%
1UF
20% 20%
D
1 C7125
1.0UF R71161 1 C7116
5%
25V
2 CERM
5%
25V
2 CERM
IRF6811STRPBF
SQ
1
NC
2 16V
POLY
TH1
2 16V
POLY
TH1
16V
2 X6S-CERM
0603
16V
2 X6S-CERM
0603
2 25V
X6S-CERM
0402
2 25V
X6S-CERM
0402 D
7
10% 0 0.22UF 0402 0402 D
16V 10% 2
2 X7R VCC 5% 25V NC
0603 1/10W 2 X7R 5
U7110 MF-LF
603 2
0603
4 G 6 CRITICAL
ISL6627
DFN 3 S
CRITICAL
R7110
93 61 REG_PWM_CPUVCC_1 4 PWM CRITICAL BOOT 2 93 REG_BOOT_CPUVCC_1 0.0005
IN
L7110 1%
1W
230NH-45A-0.29MOHM
R7114 9 EN UGATE 1 93 REG_UGATE_CPUVCC_1 MF
0612
1
0 2
1 2 93 PPCPUVCC_S0_SENSE_1 2 1 PPCPUVCC_S0_REG OUT 62 80
93 REG_TD_1 3 TD PHASE 10 93 REG_PHASE_CPUVCC_1 CTX66-SM 4 3
5% NCNC NOSTUFF REG_ISENVCC_1_P OUT 61 93
1/20W 8 NC LGATE 6 93 REG_LGATE_CPUVCC_1
MF NC 1 C7117 NO_XNET_CONNECTION=TRUE
201 0.0022UF U7000.38:3MM
THRM
GND
NOSTUFF PAD 10% 1 C7121
1
2
8
7
50V
R7115 2 CERM
5
NO_XNET_CONNECTION=TRUE220PF
11
CRITICAL 402
360K 2 D C7121.2:2MM 10%
1 Q7111 REG_SNUBBER_CPUVCC_1
50V
2 X7R-CERM
5% 649135PBF
93
R7121 0402
1/20W G DIRECTFET_S3C 1.02K
MF 4 93 REG_ISENVCC_1_N 1 2 REG_ISENVCC_1_NR OUT 61 93
201 1 NOSTUFF
S R7117 NO_XNET_CONNECTION=TRUE 1%
C7121.1:2MM 1/16W
1 MF-LF
5% 1 C7120 402
1/8W 0.1UF
5
6
3
MF-LF 10%
2 805 16V
2 X7R-CERM
0402
80 62 61 =PP5V_S0_REG_CPUVCC_S0 AGND_CPU 61 62 81 93
EMC EMC
CPU Phase 2
C U7130.7:3MM 1
EMC
Q7130.5:3MM
C7138 1
EMC
Q7130.5:3MM
C7139 CRITICAL 1
CRITICAL
C7130 1
CRITICAL
C7131 1
CRITICAL
C7132 1
CRITICAL
C7133 1
Q7130.5:3MM
C7134 1
Q7130.5:3MM
C7135 C
93 REG_BOOT_CPUVCC_2_RC 1000PF 1000PF Q7130 180UF 180UF 10UF 10UF 1UF 1UF
1 C7145 5% 5% IRF6811STRPBF
20%
2 16V
20%
2 16V
20%
2 16V
20%
2 16V
10%
2 25V
10%
2 25V
1.0UF C7136 2 25V 2 25V X6S-CERM X6S-CERM X6S-CERM X6S-CERM
10% R71361 1
CERM CERM
SQ
1
POLY
TH1
POLY
TH1 0603 0603 0402 0402
NC
7
16V
2 X7R 0 0.22UF 0402 0402 D
5% 10% 2
0603 VCC 25V NC
1/10W 2 X7R 5
U7130 MF-LF
603 2 0603
4 G 6 CRITICAL
ISL6627
DFN 3 S
CRITICAL
R7130
IN
L7130 1%
1W
230NH-45A-0.29MOHM
R7134 9 EN UGATE 1 93 REG_UGATE_CPUVCC_2 MF
0612
1
0 2
5% NCNC NOSTUFF REG_ISENVCC_2_P OUT 61 93
1/20W 8 NC LGATE 6 93 REG_LGATE_CPUVCC_2
201 U7000.34:3MM
THRM 0.0022UF
GND
1
2
8
7
R7135 2 50V
5
11
CERM
CRITICAL 402
360K 2 D C7141.2:2MM 10%
50V2 X7R-CERM
5% 649135PBF
93
R7141 0402
201 1 NOSTUFF
S R7137 NO_XNET_CONNECTION=TRUE 1%
C7141.1:2MM 1/16W
1 MF-LF
5% 1 C7140 402
1/8W 0.1UF
5
6
3
MF-LF 10%
2 805 2 16V
X7R-CERM
0402
=PP5V_S0_REG_CPUVCC_S0 AGND_CPU
B
80 62 61 61 62 81 93
B
EMC EMC
CPU Phase 3 EMC
Q7150.5:3MM
EMC
Q7150.5:3MM
CRITICAL CRITICAL CRITICAL CRITICAL Q7150.5:3MM Q7150.5:3MM
1 C7158 1 C7159 CRITICAL 1
C7150 1
C7151 1 C7152 1 C7153 1 C7154 1 C7155
U7150.7:3MM 93 REG_BOOT_CPUVCC_3_RC 1000PF 1000PF Q7150 180UF 180UF 10UF
20%
10UF
20%
1UF
10% 10%
1UF
20% 20%
1 C7165 5% 5% IRF6811STRPBF 2 16V 2 16V
16V
2 X6S-CERM
16V
2 X6S-CERM
25V
2 X6S-CERM
25V
2 X6S-CERM
1.0UF R7156 1 1 C7156 2 25V
CERM 2 25V
CERM
SQ
1
POLY
TH1
POLY
TH1 0603 0603 0402 0402
NC
7
10% 0 0.22UF 0402 0402 D

2 16V
X7R VCC 5% 10% 2
NC
0603 1/10W 2 25V
X7R 5
U7150 MF-LF
603 2 0603
4 6
G CRITICAL
ISL6627
DFN 3 S
CRITICAL
R7150
IN
L7150 1%
1W
UGATE 1 230NH-45A-0.29MOHM
R7154 9 EN 93 REG_UGATE_CPUVCC_3 MF
0612
1
0 2
5% NCNC REG_ISENVCC_3_P 61 93
1/20W 8 NC LGATE 6 93 REG_LGATE_CPUVCC_3 NOSTUFF OUT
201 0.0022UF U7000.40:3MM
THRM
GND
1
2
8
7
R7155 2 50V
5
11
CRITICAL CERM
360K 2 D 402 10%
C7161.2:2MM
50V2 X7R-CERM
5% 649135PBF
93
R7161 0402
201 NOSTUFF
1 NO_XNET_CONNECTION=TRUE 1%
S R7157 C7161.1:2MM 1/16W
1 MF-LF
5% 1 C7160 402
A 1/8W 0.1UF
A
3
5
6
MF-LF
CPU Output Decoupling 2 805
10%
2 16V
SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013
X7R-CERM PAGE TITLE
80 62 PPCPUVCC_S0_REG
0402
AGND_CPU 61 62 81 93
VReg CPU VCC Phases
DRAWING NUMBER SIZE
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL Apple Inc. 051-9889 D

1 1 1 1 1 1 REVISION
C7180 C7181 C7182 C7183 C7184 C7185 R
13.0.0
270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM
20% 20% 20% 20% 20% 20% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V
TANT TANT TANT TANT TANT TANT THE INFORMATION CONTAINED HEREIN IS THE
CASE-D2 CASE-D2 CASE-D2 CASE-D2 CASE-D2 CASE-D2 PROPRIETARY PROPERTY OF APPLE INC.
71 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VDDQ (1.5V / 1.35V) S3 Regulator

OC trip point: 30.4 A VDDQ = R7336 + 0.65625
8 E5 * Rds(Q7310) L7310 * f(switch)
3 A VTT (FIXED)
10 mA VTTREF (FIXED)
D Switching freq: 500 kHz 80 =PP12V_S5_REG_VDDQ_S3 D
CRITICAL CRITICAL
C7310 1 C7311 1 EMC EMC
180UF 180UF Q7310.1:3MM Q7310.1:3MM
20%
16V 2
20%
16V 2
1 C7342 1 C7343 1 C7344 1 C7345 1 C7346 1 C7347
POLY POLY 1UF 1UF 10UF 10UF 1UF 1UF
TH1 TH1 10% 10% 20% 20% 10% 10%
25V 25V 16V 16V 25V 25V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
80 =PP5V_S4_REG_VDDQ_S3 0402 0402 0603 0603 0402 0402
80 =PPVDDQ_S3_LDO_DDRVTT
R73001
2.2 C7301 1
5% 10UF
1/8W 20%
MF-LF 6.3V 2
805 2 X5R
603 92 REG_BOOT_VDDQS3_RC 92 REG_UGATE_VDDQS3_R
EMC EMC
R73161 1 C7316
0.1UF
R73111 L7310.2:8MM L7310.2:8MM
C7300 1 0 10% 0 CRITICAL 1 C7340 1 C7341
2.2UF 5% 25V 5% 1000PF 1000PF
2
1/10W 2 X6S 1/10W
10%
16V 2 MF-LF 0402 MF-LF Q7310 5% 5%
X5R VLDOIN 603 2 603 2 CSD58872Q5D 2 25V
CERM 2 25V
CERM
603 SON5X6 VIN 1 0402 0402
3 TG
92 REG_V5IN_U7300 12 V5IN CRITICAL VBST 15 92 REG_BOOT_VDDQS3 CRITICAL
DRVH 14 REG_UGATE_VDDQS3 VSW 6 L7310
70 PM_EN_LDO_DDRVTT_S0 17 S3
U7300 SW 13
92
92 REG_PHASE_VDDQS3 4 TGR 7 1.0UH-27A-1.05MOHM

IN
PM_EN_REG_VDDQ_S3 16 S5
TPS51916 8 92 REG_PHASE_VDDQS3_L 1 2 PPVDDQ_S3_REG
70 IN OUT 80
QFN
DRVL 11 92 REG_LGATE_VDDQS3 SDP1182-SM CRITICAL CRITICAL
92 REG_VDDQS3_VREF 6 VREF 5 BG NOSTUFF
PGOOD 20 REG_VDDQS3_PGOOD 63
1 C7317
1
C7320 1
C7321 1 C7322
<Ra> VDDQSNS 9 92 REG_VDDQS3_VDDQSNS 330UF-0.009OHM 330UF-0.009OHM 10UF
92 63 REG_VDDQS3_REFIN 8 REFIN PGND 1000PF 20% 20% 20%
C OMIT_TABLE VTT 3 PPDDRVTT_S0_LDO OUT 80

5%
25V 2 2V
POLY
2 2V
POLY
2 6.3V
X5R
C
9
2 CERM 603
C7330 1
R7330 1 92 REG_VDDQS3_MODE 19 MODE VTTSNS 1 92 LDO_DDRVTTS0_SNS 0402
CASE-D2-HF CASE-D2-HF
0.1UF 10K 92 REG_VDDQS3_TRIP 18 TRIP 1 2
CRITICAL
10% 1% SM REG_SNUBBER_VDDQS3 92
16V
X7R-CERM 2 1/16W VTTREF 5 92 REG_VDDQS3_VTTREF 1 C7325
0402 MF-LF
402 2
XW7325 22UF Critical: NOSTUFF
C7325.1:6MM 20%
VTT THRM
PGND GND GND PAD 2 6.3V
X5R-CERM-1 Need copper around Q7310 1
R7317
OMIT 603
to sink heat 0.499
<Rb>
10
21
C7327 1
CRITICAL
1%
1/10W
R73311 1 C7331 1
R7335 R73361 0.22UF MF
49.9K 0.01UF 1K 44.2K
10%
16V
C7326 1
2 603 OMIT
1% 10% 1% 1% CERM 2 22UF L7310.2:10MM
1/16W 50V
2 X7R-CERM 1/16W 1/16W 402 20%
MF-LF 0402 MF-LF MF-LF
6.3V
X5R-CERM-1 2 XW7310
402 2 2 402 402 2 603 SM
1 2
92 AGND_VDDQS3
OMIT
Vout = 1.8 * (Rb / (Ra + Rb))
2 U7300.21:4MM
J16IG: 1.35V XW7300

SM
J16G: 1.5V 1 80 69 =PP3V3_S4_PWRCTL
J17: 1.5V 1
Margining support R7340
20K
5%
22 IN DDRREG_FB REG_VDDQS3_REFIN 63 92 1/16W
MAKE_BASE=TRUE MF-LF
TABLE_5_HEAD
2 402
63 REG_VDDQS3_PGOOD PM_PGOOD_REG_VDDQ_S3 OUT 70
TABLE_5_ITEM
MAKE_BASE=TRUE
114S0335 1 RES,16.5K,402 R7330 VDDQ:P1V35
B B
TABLE_5_ITEM
114S0315 1 RES,10K,402 R7330 VDDQ:P1V5
A SYNC_MASTER=J16_ROSSANA SYNC_DATE=06/17/2013 A
PAGE TITLE
VReg VDDQ S3
DRAWING NUMBER SIZE

REVISION
R
13.0.0
73 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH/GPU/TBT (1.05V) S0 Regulator
Switching freq: 500 kHz OC trip point: 16.3 A = R7450 * 8.5 E-6
DCR(L7410)
FSEL STRAP SW FREQ

D GND 300 kHz D
VCC 1 MHz
100k to GND 600 kHz
FLOAT 500 kHz
80 =PP12V_S0_REG_P1V05_S0
80 =PP5V_S0_REG_P1V05_S0 CRITICAL CRITICAL CRITICAL CRITICAL

1
C7409 1
C7410 1 C7411 1 C7412
180UF 180UF 10UF
20%
10UF
20%
20% 20%
1 1 16V 16V
R7400 R7401 2 16V
POLY
2 16V
POLY
2 X6S-CERM 2 X6S-CERM
10 2.2 TH1 TH1 0603 0603
92 79 IN SNS_GPU_PEX_IOVDD_P 5% 5%
1/8W 1/8W
MF-LF MF-LF
SNS_GPU_PEX_IOVDD_N 805 2
92 79 IN 2 805
92 REG_BOOT_P1V05S0_RC
92 REG_VCC_U7400 REG_PVCC_U7400 92
R74161 1 C7416
C7400 1 1 C7401 0 0.1UF EMC EMC
5% 10%
1UF 2.2UF 1/10W 2 16V
10% 10% MF-LF
X7R-CERM Q7410.1:3MM Q7410.1:3MM
16V 16V 0402
X5R 2 2 X5R 603 2 1 C7480 1 C7481
402 603 1UF 1UF
10% 10%
C NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
2 25V
X6S-CERM
0402
2 25V
X6S-CERM
0402 C
13
14
<Ra> <Ra> 92 REG_UGATE_P1V05S0_R
R74301 1
R7435 VCC PVCC 1
3.01K 3.01K R7411 CRITICAL
1%
1/16W
1%
1/16W
U7400 0
5%
MF-LF MF-LF ISL95870 1/10W Q7410
402 2 2 402 UTQFN
MF-LF
603 2
CSD58872Q5D
70 PM_EN_REG_P1V05_S0 3 EN BOOT 12 92 REG_BOOT_P1V05S0 SON5X6 VIN 1 DCR(L7410) = 1.05 +/- 10% MOHM
IN 3 TG
6 CRITICAL CRITICAL
92 REG_P1V05S0_FB FB UGATE 11 92 REG_UGATE_P1V05S0 VSW 6 L7410
<Rb> 4 1.0UH-27A-1.05MOHM
1
92 REG_P1V05S0_SREF SREF PHASE 10 92 REG_PHASE_P1V05S0 4 TGR 7
R7436 8 92 REG_PHASE_P1V05S0_L 1 2 PP1V05_S0_REG OUT 80
2.74K 92 64 REG_P1V05S0_VO 8 VO LGATE 15 92 REG_LGATE_P1V05S0
1% C7440 1 SDP1182-SM
1/16W
MF-LF 0.047UF
10% 92 64 REG_P1V05S0_OCSET 7 OCSET 5 BG C7418 1 1
R7418 CRITICAL CRITICAL CRITICAL
2 402 16V 1000PF 200 1 1 1 1 C7423
X7R-CERM 2 64 REG_P1V05S0_PGOOD 9 PGOOD PGND 5% 5%
C7420 C7421 C7422
0402 NOSTUFF 25V 330UF-0.009OHM 330UF-0.009OHM 330UF-0.009OHM 10UF
CERM 2 1/10W
20% 20% 20% 20%
9
2 0402 MF-LF 6.3V
92 REG_P1V05S0_RTN RTN C7417 1
2 603 2 2V
POLY
2 2V
POLY
2 2V
POLY
2 X5R
0.001UF CASE-D2-HF CASE-D2-HF CASE-D2-HF 603
92 REG_P1V05S0_FSEL 5 FSEL 10%
50V
GND PGND X7R-CERM 2
<Rb> 0402
NOSTUFF 1
R74311 R7460
1
16
2.74K
C7430 1 1 C7435 0
92 REG_SNUBBER_P1V05S0 Note:
1% 10PF 10PF 5% Regulator requires
1/16W 5% 5% 1/16W NOSTUFF
50V 50V
MF-LF C0G-CERM 2 2 C0G-CERM MF-LF a minimum load to
402 2 0402 0402 402 2 R74171 prevent noise in the
2.2
5% audio frequencies
92 AGND_P1V05S0 1/10W
MF-LF
603 2
U7400.1:1MM
B Vout = 0.5 * (1 + Ra / Rb) XW7400
SM
2
B
1
L7410.1:3MM
R74501
2.21K R7450.2:3MM
1%
1/16W
MF-LF C7450
402 2 0.47UF
1 2
L7410.2:4MM
10% 1
25V R7451
80 66 61 60 =PP3V3_S0_VRD X7R 2.21K
To regulator: 0603 1%
1 1/16W
R7480 REG_P1V05S0_OCSET
MF-LF
20K
92 64
2 402
5%
1/16W 92 64 REG_P1V05S0_VO
MF-LF
2 402
64 REG_P1V05S0_PGOOD PM_PGOOD_REG_P1V05_S0 OUT 70 71

MAKE_BASE=TRUE
A SYNC_MASTER=J16_ROSSANA SYNC_DATE=07/29/2013 A
PAGE TITLE
VReg PCH/GPU/TBT 1V05 S0

DRAWING NUMBER SIZE

REVISION
R
13.0.0
74 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S5 Regulator 5V S4 Regulator

R7618 * 10 E-6
OC trip point: 12.5 A = R7658 * 10 E-6
DCR(L7610) OC trip point: 14.1 A =
DCR(L7650)
1
Switching freq: 356 kHz = 1
170 E-12 * R7633 Switching freq: 356 kHz =
170 E-12 * R7673
D 80 =PP12V_S5_REG_P3V3P5V_S5
D
C7610 1 1
C7650 1
C7651
180UF 180UF 180UF
20% 20% 20%
16V 2 2 16V 2 16V
POLY POLY POLY
TH1 TH1 TH1
1
R7603
1
5%
1/8W
MF-LF
2 805
EMC EMC EMC EMC

Q7610.2:3MM Q7610.2:3MM 94 REG_VIN_U7600 Q7650.5:3MM Q7650.5:3MM
C7642 1 C7643 1 1 C7682 1 C7683
1UF 1UF 1UF 1UF
10% 10% 10% 10%
25V 25V 2 25V 2 25V
X6S-CERM 2 X6S-CERM 2 PP5V_S5_LDO X6S-CERM X6S-CERM
0402 0402 OUT 80 0402 0402
5
1
1 C7601 R7602
2.2 D CRITICAL
4.7UF
EMC EMC 20%
6.3V
5%
1/8W
4 G
Q7650 EMC EMC
L7610.1:8MM L7610.1:8MM 2 CERM MF-LF FDMC0225 L7650.2:4MM L7650.2:4MM
C7640 1 C7641 1 603 2 805 MLP3.3X3.3 1 C7680 1 C7681
C 1000PF
5%
25V
1000PF
5%
25V 2
94 REG_VCC2_U7600
1 C7602 1 C7603 S 5%
1000PF
2 25V
5%
1000PF
2 25V
C
CERM 2 CERM 2 CRITICAL 94 REG_VCC1_U7600 94 REG_BOOT_P5VS4_RC CERM CERM
0402 0402
DCR(L7610) = 11.2 MOHM (TYP) / 12.5 MOHM (MAX) 1UF 1UF DCR(L7650) = 6.2 MOHM (TYP) / 6.9 MOHM (MAX) 0402 0402
CRITICAL
Q7610 C7600 1
10%
2 16V
10%
2 16V
1 2 3
CRITICAL
FDMS3602S X5R X5R 1
R7656 1 C7656
L7610 POWER56 1UF 402 402 L7650
1 10% 0 0.1UF
2.2UH-10A-12.5MOHM 16V 10% 2.2UH+/-20%-0.0069OHM-16A
X5R 2 5% 25V
1 2 (reg_phase_p3v3s5) 7 402 1/10W 2 X6S (reg_phase_p5vs4) 1 2
80 OUT PP3V3_S5_REG PHASE MF-LF 0402
PP5V_S4_REG OUT 80
PAB0705AR-SM 2 603 PIC1005H-SM
4
CRITICAL CRITICAL NOSTUFF NOSTUFF CRITICAL CRITICAL
VCC1
VCC2
C7622 1
C7621 1 C7620 1 C7618 C7617 1 1 C7616 6
1 C7657 C7658
1
C7660 1
C7661 1 C7662
10UF 150UF 150UF 0.01UF R7618 0.001UF 0.1UF 18 LDO5 VIN 17 0.001UF R7658 27.0NF 330UF 330UF 10UF
20% 20% 20% 15.8K 10% 10% 10% 9.76K 20% 20% 20%
6.3V 2 50V 2 25V 2 50V 2 6.3V
X5R
6.3V 2
POLY
6.3V 2
POLY
1 2 1 2
CERM 2 X6S U7600 FCCM 3 REG_U7600_FCCM
CRITICAL 5 X7R-CERM
1 2 1 2 2 6.3V
POLY-TANT
2 6.3V
POLY-TANT X5R
603 B1A-SM-1 B1A-SM-1
10%
1%
1/16W
402 0402
5 4 3 ISL62383CRTZ
65
Q7655 0402 1%
1/16W 10%
CASE-D3L-SM CASE-D3L-SM 603
16V
X7R-CERM
MF-LF 65 REG_P3V3S5_PGOOD 7 PGOOD1 QFN PGOOD2 1 REG_P5VS4_PGOOD 65 FDMC0223S D MF-LF 10V
X5R
402 REG_BOOT_P3V3S5_RC 94 MLP3.3X3.3 REG_SNUBBER_P5VS4 94 402
0402 402
94 REG_SNUBBER_P3V3S5 94 REG_UGATE_P3V3S5 14 UGATE1 UGATE2 22 94 REG_UGATE_P5VS4 4 G
NOSTUFF
NOSTUFF 1 REG_BOOT_P3V3S5 15 BOOT1 CRITICAL BOOT2 21 REG_BOOT_P5VS4 1
OMIT R7616 94 94
R7657 OMIT
R7617 1 0 13 PHASE1 S 0.499
L7610.1:6MM 2 1
R7619 5% 94 REG_PHASE_P3V3S5 PHASE2 23 94 REG_PHASE_P5VS4 1% R76591 2 L7650.2:3MM
0.499 1/10W 1/10W
XW7610 15.8K 1% MF-LF
16 LGATE1 MF 9.76K XW7650
SM 1% 1/10W 2 603
94 REG_LGATE_P3V3S5 LGATE2 20 94 REG_LGATE_P5VS4 1 2 3 2 603 1% SM
1/16W MF 1/16W
MF-LF 603 2 MF-LF
1 2 402
94 REG_P3V3S5_ISEN 10 ISEN1 ISEN2 26 94 REG_P5VS4_ISEN 402 2 1
94 REG_P3V3S5_OCSET 11 OCSET1 OCSET2 25 94 REG_P5VS4_OCSET

(reg_p3v3s4_isen) (reg_p5vs4_isen)
94 REG_P3V3S5_VOUT 9 VOUT1 VOUT2 27 94 REG_P5VS4_VOUT
(reg_p3v3s4_ocset) (reg_p5vs4_ocset)
94 REG_P3V3S5_FB 8 FB1 FB2 28 94 REG_P5VS4_FB
(reg_p3v3s4_vout) (reg_p5vs4_vout)
B <Ra>
94 REG_P3V3S5_FSET 6 FSET1
12 EN1
FSET2 2 94 REG_P5VS4_FSET
<Ra> B
R76301 R76321 EN2 24 1
R7672 1
R7670
45.3K 976 THRM
976 75K
1% 1% PAD PGND NOSTUFF 1% 1%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF 1 C7633 1
R7633 1 C7673 1
R7673 1 C7675 MF-LF MF-LF
29
19
402 2 402 2 0.01UF 0.01UF 0.001UF 2 402 2 402
10% 16.5K 10% 16.5K 10%
16V 1% 16V 1% 50V
REG_P3V3S5_VOUT_R 94 2 X7R-CERM 1/16W 2 X7R-CERM 1/16W 2 X7R-CERM 94 REG_P5VS4_VOUT_R
<Rb> 0402 MF-LF 0402 MF-LF 0402 <Rb>
C7632 2 402 2 402 C7672
R76311 1 1 1
R7671
10.0K 1000PF 1000PF 10K
0.5% 5% 5% 1%
1/16W 25V 2 25V
MF CERM 2 CERM 1/16W
MF-LF
0402 0402
402 2 2 402
Vout = 0.6 * (1 + Ra / Rb) Vout = 0.6 * (1 + Ra / Rb)

70 IN PM_EN_REG_P3V3_S5
NOSTUFF
R7600 70 IN PM_EN_REG_P5V_S4
1K
NOSTUFF 2 1 REG_U7600_FCCM 65
5%
Q7600 1/16W
SSM6L36FE MF-LF
402
SOT563 D 3 REG_U7600_FCCM_R 80 65 =PP3V3_S5_VRD
P-CH
=PP5V_S5_PWRCTL 65 69 80
1
NOSTUFF R7680
This circuit toggles the Vreg 20K
between PWM and ultrasonic DCM R76011 5%
10K 1/16W
modes based on load requirements 65 BURSTMODE_EN 5 G 5% MF-LF
2 402
A
1/16W
80 69 65 =PP5V_S5_PWRCTL 4 S
MF-LF
402 2 65 REG_P5VS4_PGOOD PM_PGOOD_REG_P5V_S4
MAKE_BASE=TRUE OUT 70 SYNC_MASTER=J16_MLB_IG
PAGE TITLE
D 6 BURSTMODE_EN
BURSTMODE_EN_L Vreg Mode
65
80 65 =PP3V3_S5_VRD
VReg 3.3V S5/5V S4
DRAWING NUMBER SIZE
0 PWM 1
R7640 Apple Inc. 051-9889 D
1 DCM 2 G 20K REVISION
60 45 IN BURSTMODE_EN_L 5%
1/16W
MF-LF
R
13.0.0
1 S 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
N-CH THE INFORMATION CONTAINED HEREIN IS THE
65 REG_P3V3S5_PGOOD PM_PGOOD_REG_P3V3_S5 OUT 71 PROPRIETARY PROPERTY OF APPLE INC.
MAKE_BASE=TRUE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
76 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU VDDQ S0 REGULATOR

OC trip point: 15.8 A = R7791 * 8.5 E-6
DCR(L7760)
Switching freq: 300 kHz
FSEL STRAP SW FREQ

GND 300 kHz
D VCC 1 MHz
D
100k to GND 600 kHz
=PP12V_S0_REG_GPU_VDDQ_S0
FLOAT 500 kHz 80 =PP5V_S0_REG_GPU_VDDQ_S0
80
CRITICAL CRITICAL
R77501 1
R7751
1
C7759 1
C7760
10 2.2 180UF 180UF
SNS_GPUVDDQ_P 20% 20%
94 74 IN 5% 5% 2 16V 2 16V
1/8W 1/8W POLY POLY
MF-LF MF-LF TH1 TH1
94 74 IN SNS_GPUVDDQ_N 805 2 2 805
94 REG_BOOT_GPUVDDQ_RC
94 REG_VCC_U7750 94 REG_PVCC_U7750
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE R77661 1 C7766
<Ra> <Ra> 0.1UF
1 1
1 C7751 2.2 10%
R7780 R7785 2.2UF 5%
1/10W
16V
2 X7R-CERM
2.32K 2.32K 10% MF-LF EMC EMC
1% 1% 2 16V 603 2 0402 Q7760.2:4MM Q7760.2:4MM
X5R
1/16W
MF-LF
1/16W
MF-LF C7750 1 603 1 C7761 1 C7762
402 2 2 402 1UF 1UF 1UF
10% 10% 10%
16V 2 25V 25V
2 X6S-CERM 2 X6S-CERM
19
20
X5R 0402 0402
402
VCC PVCC
U7750 2
CRITICAL
ISL95870AH DCR(L7760) = 5.6 MOHM (TYP) / 6.5 MOHM (MAX)
15 EN UTQFN Q7760
70 IN PM_EN_REG_GPU_VDDQ_S0 BOOT 18 94 REG_BOOT_GPUVDDQ
FDMS3602S CRITICAL
REG_GPUVDDQ_FB 10 FB
CRITICAL
UGATE 17 REG_UGATE_GPUVDDQ 1 POWER56 L7760
94 94
1.0UH-20%-15A-0.0065OHM
C 94 REG_GPUVDDQ_SREF 7 SREF PHASE 16 94 REG_PHASE_GPUVDDQ PHASE 7 1
PIC0605H-SM
2 PP1V5R1V35_S0_GPU_REG OUT 80 C
REG_GPUVDDQ_VO 12 VO LGATE 1 REG_LGATE_GPUVDDQ NOSTUFF
C7790 1 R77871
94 66 94
1 C7767 C7768 1 1
R7768 CRITICAL CRITICAL
0.047UF 301K 94 66 REG_GPUVDDQ_OCSET 11 OCSET 6 1000PF 200 1
C7770 1
C7771 1 C7772
10% 1% 0.001UF 5% 5%
16V 1/16W 10% 25V 330UF-0.009OHM 330UF-0.009OHM 10UF
X7R-CERM 2 MF-LF 66 REG_GPUVDDQ_PGOOD 14 PGOOD 2 50V CERM 2 1/10W
MF-LF 20% 20% 20%
X7R-CERM 0402 6.3V
0402 402 2 0402 2 603 2 2V 2 2V 2 X5R
POLY POLY
94 REG_GPUVDDQ_RTN 4 RTN 3 4 5 CASE-D2-HF CASE-D2-HF 603
REG_SNUBBER_GPUVDDQ 94
94 REG_GPUVDDQ_FSEL 13 FSEL
NOSTUFF
REG_GPUVDDQ_SET0 8 SET0 1
94 66
R7767
NOSTUFF NOSTUFF 2.2 L7760.1:3MM
<Rb> <Rb> 94 REG_GPUVDDQ_SET1 9 SET1 5%
R7781 1 1
R7786 1 C7785
1/10W R77911
C7780 1 R77881 1
R7790 6 VID0 MF-LF
12.1K R7791.2:3MM
10PF 2.74K 2.74K 10PF 150K 2 603 1%
1% 1% 5% 0
5%
50V 1/16W 1/16W 2 50V
C0G-CERM
1%
1/16W 5% 5 VID1 1/16W
MF-LF C7791
C0G-CERM 2 MF-LF MF-LF
0402 MF-LF 1/16W 402 2 0.012UF
0402 402 2 2 402 402 2 MF-LF
2 402 R7794 1 2
L7760.2:3MM
0 GND PGND
94 REG_GPUVDDQ_SET1_R 1 2 10% 1
3 25V R7792
2
5% X7R 12.1K
R77891 1/16W
MF-LF To regulator: 402 1%
27K 402 1/16W
1% MF-LF
94 66 REG_GPUVDDQ_OCSET 2 402
1/16W
MF
402 2
78 IN FBVDD_ALTVO XW7750
SM 94 66 REG_GPUVDDQ_VO
94 AGND_GPUVDDQ 2 1
Vout = 0.5 * (1 + Ra / Rb) U7750.3:5MM
GPIO_16 VID 1 VID 0 GPU VDDQ
0 0 1.5 V
1 0 1.35 V
B B
80 64 61 60 =PP3V3_S0_VRD
1
R7793
Margining support 20K
NOSTUFF 5%
1/16W
R7788.1:6.35MM MF-LF
2 402
R7755
0 66 REG_GPUVDDQ_PGOOD PM_PGOOD_REG_GPU_VDDQ_S0 OUT 70
22 IN VREFMRGN_FRAMEBUF_BUF 1 2 REG_GPUVDDQ_SET0 66 94 MAKE_BASE=TRUE
5%
1/20W
MF
201
PAGE TITLE
VReg GPU VDDQ

DRAWING NUMBER SIZE

REVISION
R
13.0.0
77 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU Core S0 Regulator

OC trip point: 66.79 A
2.65 E9 80 67 =PPVIN_S0_GFXIMVP
Switching freq: 300 kHz =
R7814 + 768.5 1
C7828 1
C7827
0.001UF 0.001UF
1
C7820 1
C7821 1
C7822 C7823 1
C7824 1
C7825 1
C7826 1
10% 10% 180UF 180UF 180UF 1UF

10%
1UF
10%
1UF
10%
1UF
10%
50V 50V 20% 20% 20%
2 2 25V 25V 25V 25V
X7R-CERM X7R-CERM 2 16V 2 16V 2 16V X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2
0402 0402 POLY POLY POLY
TH1 TH1 TH1 0402 0402 0402 0402
8
D 80 =PP5V_S0_GFXIMVP D
CRITICAL
Q7830
IRF6802SDTRPBF
1
PLACE_NEAR=U7800.25:1mm R7800 94 REG_BOOT_GPUCORE_2_RC 2 G DIRECTFET-SA
C7802 1 10 CRITICAL
1UF 5%
C7830 S
10%
1/16W
1
R7898
MF-LF CRITICAL
25V 0.22UF 0.00075
3
X6S-CERM
0402
2
2
402
10%
16V
L7830 1%
1W 25A max per phase
CERM 2 0.36UH-30A-0.6MOHM MF PPGPUCORE_S0_REG 80
PPVIN_S0_GFXIMVP_R 1 402 0612
94
R7830 1 94 2 PPVCORE_S0_GFX_PH22 1
R7801 0 NCNC
1 5% SDP110808MR36MF-TH 4 3
1 2 94 PP5V_S0_GFXIMVP_VDD 1/10W NOSTUFF
MF-LF
5% 1 C7835 94 REG_GPUCORE_ISNS2_P 94 67 REG_GPUCORE_ISNS2_N
1
2
7
2
603 CRITICAL CRITICAL CRITICAL CRITICAL
1/16W PLACE_NEAR=U7800.16:1mm PLACE_NEAR=U7800.17:1mm 1 1
1000PF C7861 C7862 1 1
MF-LF
402 C7801 1 1
C7800 D 5% C7863 C7864
470UF 470UF
1UF 0.22UF 2 25V
CERM R7831
1
R7833
1 1
R7834 20% 20%
470UF 470UF
20% 20%
10% 10% 0402 10K 1K 1.00 2 2V 2 2V
25V 16V POLY-AL POLY-AL 2 2V 2 2V
2 2 REG_SNUBBER_GPUCORE_2 94 1% 1% 1% POLY-AL POLY-AL
X6S-CERM CERM 4 G 1/20W 1/20W 1/20W
SM SM SM SM
0402 402
(GND_REG_GPUCORE_AGND) Q7831 S
1
R7835
MF
201
2
MF
201
2 2
MF-LF
0201
649135PBF 1
DIRECTFET_S3C 5% REG_GPUCORE_ISUMN 67
CRITICAL 1/8W 94
MF-LF REG_GPUCORE_ISUMP
3
5
6
R7840 2 805
67
94
147K NOSTUFF C7831
1 2
16
25
17
0.22UF
1%
1/20W VDD VCCP VIN Line Width & DIDT R7832 1 1 2
MF 10K
201
U7800 on all DIDT nets 1%
20%
1/20W
6.3V
R7818 ISL62882C MF
201
X5R
30.1K TQFN 2 0201
1 2 REG_GPUCORE_RBIAS 3 RBIAS 353S3679
=PPVIN_S0_GFXIMVP 67 80 REG_GPUCORE_ISNS1_N 67 94
1%
1/20W REG_GPUCORE_NTC 5 NTC CRITICAL
BOOT2 30 94 REG_BOOT_GPUCORE_2
C C
MF
6
201
67 REG_GPUCORE_PGOOD 1 PGOOD UGATE2 29 94 REG_UGATE_GPUCORE_2 CRITICAL
D
Q7830
67 REG_GPUCORE_VR_TT_L 4 VR_TT* PHASE2 28 94 REG_PHASE_GPUCORE_2 IRF6802SDTRPBF
1 G DIRECTFET-SA
40 CLK_EN* 94 REG_BOOT_GPUCORE_1_RC
C7816 1 1
C7817 1
R7814 S
CRITICAL
470PF 330PF 8.06K

1 C7819 67 GFXIMVP_VID<0> 31 VID0 LGATE2 26 94 REG_LGATE_GPUCORE_2 C7865 1
CRITICAL
R7899
0.00075
5% 10%
1000PF
4
50V
NP0-C0G-CERM 2 2
50V
X7R-CERM
1%
1/16W 5% 67 GFXIMVP_VID<1> 32 VID1 0.22UF
10%
L7860 1%
1W
0402 0402
NOSTUFF
MF-LF
402
25V
2 CERM 67 GFXIMVP_VID<2> 33 VID2
VSSP2 27
16V
2
0.36UH-30A-0.6MOHM MF
2 CERM 0612
94 REG_GPUCORE_COMP_R 0402 1 2
C7818 1
67 GFXIMVP_VID<3> 34 VID3 1
402 94 PPVCORE_S0_GFX_PH1
2 1
R7813 1 22PF R7860 NCNC SDP110808MR36MF-TH
5%
67 GFXIMVP_VID<4> 35 VID4 0
4 3
10K 100V NOSTUFF
1% 2 67 GFXIMVP_VID<5> 36 VID5 5%
C0G-CERM 1/10W 1 C7867 94 67 REG_GPUCORE_ISNS1_N
1
2
7
1/16W
MF-LF
0402-1
67 GFXIMVP_VID<6> 37 VID6 ISEN2 10 94 REG_ISEN_GPUCORE_2 MF-LF 94 REG_GPUCORE_ISNS1_P
402 2
603 1000PF
2 R7877 D 5%
78 IN REG_GPUCORE_PSI_L 1 2 67 REG_GPUCORE_PSI_R_L 2 PSI* BOOT1 19 94 REG_BOOT_GPUCORE_1 2 25V
CERM R7861
1
R7863
1 1
R7864
0 201 0402
REG_SNUBBER_GPUCORE_1 94 10K 1K 1.00
1
R7816 67 REG_GPUCORE_DPSLP_EN 39 DPRSLPVR UGATE1 20 94 REG_UGATE_GPUCORE_1 G 1% 1% 1%
4 1/20W 1/20W 1/20W
49.9 1 MF MF MF-LF
1% 70 IN PM_EN_REG_GPUCORE_S0 38 VR_ON PHASE1 21 94 REG_PHASE_GPUCORE_1 S R7878 201
2
201
2 2
0201
1/16W
MF-LF
1
402 94 REG_GPUCORE_VW 6 VW LGATE1A 23 94 REG_LGATE_GPUCORE_1 CRITICAL 5% REG_GPUCORE_ISUMN 67 94
2 1/8W
MF-LF REG_GPUCORE_ISUMP
6
3
REG_GPUCORE_FB_SNS_R 67 94
R7815 1 NO_XNET_CONNECTION=TRUE 94 REG_GPUCORE_COMP 7 COMP LGATE1B 24
NC 2 805
301 1
C7840
NOSTUFF
C7866
REG_GPUCORE_FB2 VSSP1
1%
1/16W
5600PF
94 9 FB2 22
Q7861 R7862 1
0.22UF
10% 94 REG_GPUCORE_FB 8 FB 1 2
MF-LF
402 2
25V
ISEN1 11 94 REG_ISEN_GPUCORE_1 649135PBF 10K
2 CERM
402 CKPLUS_WAIVE=PdifPr_badTerm DIRECTFET_S3C 1%
20%
12 VSEN 1/20W
ISUM+ 15 94 67 REG_GPUCORE_ISUMP MF
6.3V
X5R
201
2 0201
13 RTN
1
NOSTUFF 1 C7810 REG_GPUCORE_ISNS2_N
R7817 48 GFXIMVP6_IMON 18 IMON ISUM- 14 94 REG_GPUCORE_ISUMN_R 5600PF 67 94
OUT
B 49.9
1%
1/20W
MF
94 79 IN SNS_GPU_CORE_P THRM
PAD 1
R7810
1.24K
2
10%
2 10V
CERM-X7R
0201 REG_GPUCORE_ISUMN 67 94
B
2
201
94 79 IN SNS_GPU_CORE_N XW7800
NOSTUFF
41
NO_XNET_CONNECTION=TRUE 1%
SM C7812 1 1/20W
REG_GPUCORE_FB_GND_R R7812 1 1
C7813 2
PLACE_NEAR=U7800.41:3mm
1 0.1UF
MF
201
NOSTUFF
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE 10K 0.1UF 10% 1
C7811
NOSTUFF
1%
10% 6.3V R7811
NOSTUFF NOSTUFF CERM-X5R 2 0.1UF
1
C7841 1/20W 2
6.3V
CERM-X5R 0201 94 REG_GPUCORE_ISUMP_C 1
1.15K
2 10%
5600PF C7815 1 1
C7814 MF
201
0201
2
6.3V
10% 2 CERM-X5R
10V 1000PF 1000PF 1%
0201
2 10% 10% 1/20W
CERM-X7R MF
16V 16V
0201 2 2 201
X7R-CERM X7R-CERM
0201 0201
94 GND_REG_GPUCORE_AGND
GPU VCORE VID STRAPS
80 67 =PP3V3_S0_GFX3V3BIAS DEFAULT = 0.9 V
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF 80 67 =PP3V3_S0_GFX3V3BIAS

1 1 1 1 1 1 1
R7843 R7844 R7845 R7846 R7847 R7848 R7849 NOSTUFF NOSTUFF
10K 10K 10K 10K 10K 10K 10K 1 1 1
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
R7872 R7873 R7876
R7866 MF MF MF MF MF MF MF 499 100K 100K
78 GPU_VCORE_VID0 1 2
201
2
201
2
201
2
201
2
201
2
201
2
201
2
80 78 69
=PP3V3_S0_PWRCTL 1%
1/20W
5%
1/20W
5%
1/20W
IN
0 201 MF MF MF
R7867 201 201 201 Do not config
78 IN GPU_VCORE_VID1 1 2 67 GFXIMVP_VID<0> 2 2 2
0 201 R7868 67 GFXIMVP_VID<1>

78 IN GPU_VCORE_VID2 1 2 67 REG_GPUCORE_VR_TT_L PSI_L = HIGH & DPSLP_EN = HIGH
R7869 0 201 67 GFXIMVP_VID<2> 1
R7865 67 REG_GPUCORE_PSI_R_L
78 IN GPU_VCORE_VID3 1 2 67 GFXIMVP_VID<3> 10K
0 201 5% 67 REG_GPUCORE_DPSLP_EN
A 78 IN GPU_VCORE_VID4
R7871
1
0
R7870
2
201
67
67
GFXIMVP_VID<4>
GFXIMVP_VID<5> 2
1/20W
MF
201 SYNC_MASTER=J16_ROSSANA SYNC_DATE=06/17/2013 A
78 GPU_VCORE_VID5 1 2 67 GFXIMVP_VID<6>
PAGE TITLE
IN
0 201
1 1 1 1
NOSTUFF
1
NOSTUFF
1 1
NOSTUFF
1 1
VReg GPU Core
R7850 R7851 R7852 R7853 R7854 R7855 R7856 REG_GPUCORE_PGOOD PM_PGOOD_REG_GPUCORE_S0 R7874 R7875 DRAWING NUMBER SIZE
10K
1%
10K
1%
10K
1%
10K
1%
10K
1%
10K
1%
10K
1%
67
MAKE_BASE=TRUE
OUT 70
100K
5%
100K
5% Apple Inc. 051-9889 D
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W REVISION
MF
201
2
MF
201
2
MF
201
2
MF
201
2
MF
201
2
MF
201
2
MF
201
2 2
MF
201
2
MF
201
R
13.0.0
78 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_HEAD
TABLE_5_ITEM
OMIT_TABLE CRITICAL PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
152S1668 1 IND,PWR,33UH,20%,10A,35MOHM L8100 CRITICAL PART NUMBER
OMIT/table L8100 due to late sourcing change, did not want footprint change
CRITICAL D8100
POWERDI5-TO277A
TABLE_ALT_ITEM
Add 152s1668 (Cyntec) directly for next program L8100 1

371S0648 371S0694 D8100 BLC Switch Diode ACOUSTICS E-NOISE COMPONENTS
BKLT_BOOST
33UH-20%-10A-0.0351OHM 68 97
97 68 PP12V_S0_BKLT_PWR
1 2 97 BKLT_PHASE 3
IHLP6767GZ-IHLP4040DZ11-SM
CRITICAL K NOSTUFF NOSTUFF 2 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D8101 1 C8100 1 C8101 1 C8102 1 C8103 1 C8104 1 C8105 1 C8106 1 C8107 1 C8108 1 C8109 1 C8110 1 C8111 1 C8112 1 C8113 1 C8114 1 C8115 1 C8116 1 C8117 1 C8118 1 C8119 1 C8197 1 C8190
SOD-323 10UF 10UF 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF PDS5100H 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
SBR130S3 25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
A 0805 0805 0805 0805 0402 0402 0402 0402 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2 1206-2
PGND_BKLT
D
68 97
NOSTUFF PGND_BKLT 68 97
D
1
R8109
4.7
97 68 PP12V_S0_BKLT_PWR 97 68 PP12V_S0_BKLT_PWR_R 5% 97 68 BKLT_BOOST
1/4W
MF-LF CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C8151 1 C8152 1 C8153 1 C8154 2 1206
1UF 1UF 1UF 1UF
1 C8140 1 C8141 1 C8142 1 C8143 1 C8144 1 C8145
10% 10% 10% 10% 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF
10% 10% 10% 10% 10% 10%
25V
2 X7R
25V
2 X7R
25V
2 X7R
25V
2 X7R 97 BKLT_SNUBBER 100V
2 X7R 100V
2 X7R 100V
2 X7R 100V
2 X7R 100V
2 X7R 100V
2 X7R
805 805 805 805 0603 0603 0603 0603 0603 0603
PGND_BKLT 68 97 PGND_BKLT 68 97
1 2 6 7 PGND_BKLT 68 97
XW8102
CRITICAL D CRITICAL SM
R8104 Q8100 97 BKLT_FB_XW 2 1
97
68 BKLT_BOOST
97 68 PP12V_S0_BKLT_PWR 1 0.05 2 PP12V_S0_BKLT_PWR_R 68 97
BKLT_GATE_R 5 G IRF6645PBF NOSTUFF
1% 0402 1/16W MF
97
DIRECTFET-SJ 1 C8127
0 PP5V_S0_BKLT_R S 100PF
47 IN =SMB_DP_BLC_SCL R8140 1 2 NOSTUFF
97 68
5%
402 5% 1/16W MF-LF
68 PP3V3_S0_BKLT_VDDIO_R 3 4 100V 1
R8124 1 C8121
=SMB_DP_BLC_SDA R8141 1 0
2 NOSTUFF
97
R8107
2 C0G-CERM
0 100PF
1 C8123 1 C8125
47 IN 402 5% 1/16W MF-LF 0
0603-1 5% 100PF 100PF 97 68 BKLT_BOOST
1 2 97 BKLT_SW_R 5%
1/10W
100V
2 C0G-CERM 5% 5%
MF-LF 0603 2 100V
C0G-CERM
100V
2 C0G-CERM CRITICAL CRITICAL CRITICAL CRITICAL
5%
47 IN =I2C_BKLT_SCL R8100 1 0
2 BKLT_SCL 68 97
R8106 1
1/10W
MF-LF 1CRITICAL
2 603 0603 0603 1 C8191
2.2UF
1 C8192
2.2UF
1 C8193
2.2UF
1 C8194
2.2UF
402 5% 1/16W MF-LF 0 R8108 1 C8120 1 C8122
22
23
0 603 10% 10% 10% 10%
R8101 1 C8124
8
5% 0.05 1
47 IN =I2C_BKLT_SDA 2 BKLT_SDA 68 97 1/8W NOSTUFF 100PF 100PF 100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
402 5% 1/16W MF-LF MF-LF 1 C8126
1%
1W
97 BKLT_FB_R 5% 5% 100PF 1206-2 1206-2 1206-2 1206-2
VDDIO VLDO VIN 805 2 100V 100V 5% PGND_BKLT68
1000PF MF 2 C0G-CERM 2 C0G-CERM 100V 97
OMIT_TABLE 5% 2 2512 0603 0603 2 C0G-CERM
XW8103 U8100 50V
2 C0G-CERM 1
R8110 0603
SM LLP 603 XW8101 97 68 BKLT_ISEN1
LGND_BKLT 1M NOSTUFF NOSTUFF
LP8561B0SQ
97 68 2 1 SM
1% CRITICAL CRITICAL CRITICAL CRITICAL
68 BKLT_SHUTDOWN 7 SD GD 6 97 BKLT_GATE 97 68 BKLT_SW_N 2 1
97
68 PGND_BKLT 1/16W 1 C8195 1 C8196 1 C8198 1 C8199
MF-LF 97 68 BKLT_ISEN2
XW8104 24 97 BKLT_SW_P 2 402 2.2UF 2.2UF 2.2UF 2.2UF
SM ISENSE 10% 10% 10% 10%
C 97 68 PGND_BKLT 2 1
97 BKLT_ISET 3 ISET
FB 21 97 BKLT_FB
1
5%
C8160
33PF
97 68 BKLT_ISEN3 2 100V
X7R
1206-2
100V
2 X7R
1206-2
100V
2 X7R
1206-2
100V
2 X7R
1206-2
PGND_BKLT68
C
XW8105 97 BKLT_FLT 20 FILTER 12 BKLT_ISEN1
100V
2 C0G-CERM BKLT_ISEN4
97
SM OUT1 68 97
1 97 68
97 68 DGND_BKLT 2 1 R8111 0603

TABLE_ALT_HEAD
68 BKLT_VSYNC_R 19 VSYNC OUT2 13 BKLT_ISEN2 68 97 330K PART NUMBER

1% 97 68 BKLT_ISEN5
1/8W TABLE_ALT_ITEM
97 68 BKLT_SCL 10 SCLK OUT3 14 BKLT_ISEN3 68 97 MF 138S0810 138S0839 2.2UF_CAP BLC OUTPUT CAPS
2 0402 97 68 BKLT_ISEN6
97 68 BKLT_SDA 11 SDA OUT4 16 BKLT_ISEN4 68 97
97 68 PGND_BKLT
TABLE_ALT_ITEM
LVDS_BKLT_PWM_RC 2 PWM OUT5 17 BKLT_ISEN5 68 97 371S0748 371S0731 D8101 INPUT DIODE
68 40 BKLT_EN 4 EN OUT6 18 BKLT_ISEN6 68 97

IN
1 ISENSE_GND
NOSTUFF 1 1
C8128 1 R8123 R8105 CRITICAL
10K 12.4K
5 GND_GD
33PF 1% 1%
9 GND_S
15 GND_L
5%
50V 1/16W 1/16W
CERM 2 MF-LF MF-LF THRM
402 2 402 2 402 PAD
97 68 DGND_BKLT
25
97 68 BKLT_SW_N
97 68 LGND_BKLT
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
97 68 PGND_BKLT
DGND_BKLT
Q8105 Q8106 Q8107 Q8108 Q8109 Q8110
1
97 68 SI3440DVT1GE3 BKLT_ISEN1_R SI3440DVT1GE3 BKLT_ISEN2_R SI3440DVT1GE3 BKLT_ISEN3_R SI3440DVT1GE3 BKLT_ISEN4_R SI3440DVT1GE3 BKLT_ISEN5_R SI3440DVT1GE3 BKLT_ISEN6_R 68 97
R8103 TSOP 1 TSOP 1 TSOP 1 TSOP 1 TSOP 1 TSOP 1
270K 2 2 2 2 2 2
5%
1/16W 5 5 5 5 5 5
MF-LF
2 402 97 68 PP12V_S0_BKLT_PWR 3 6 3 6 3 6 3 6 3 6 3 6
B 97
BKLT_FLT_RC
R8150 1 97 68 BKLT_ISEN1 4 97 68 BKLT_ISEN2 4 97 68 BKLT_ISEN3 4 97 68 BKLT_ISEN4 4 97 68 BKLT_ISEN5 4 97 68 BKLT_ISEN6 4 B
1 C8130 100K
1 C8129 330PF
1%
1/10W
4700PF 10% MF-LF
5% 50V 603 2 TABLE_ALT_HEAD
50V 2 X7R-CERM
2 CERM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
603 0402 PART NUMBER
97 68 PGND_BKLT TABLE_ALT_ITEM

TABLE_ALT_HEAD
CRITICAL
R8152 DGND_BKLT 68 97 FB8100 376S1071 376S1073 ALL Short Protection FET PART NUMBER
0 600-OHM-25%-0.5A-0.40OHM
BKLT_VSYNC BKLT_VSYNC_R
TABLE_ALT_ITEM TABLE_ALT_ITEM
40 1 2 68 155S0831 155S0797 ALL FB8100 to FB8107 376S1121 376S1116 Q8102 BLC Inrush FET
402 5% 1/16W MF-LF
97 68 BKLT_ISEN6_R 1 2 TABLE_ALT_ITEM
740S0145 740S0146 F8100 BLC Fuse

0603
NOSTUFF FB8101 CRITICAL
1
R8153 600-OHM-25%-0.5A-0.40OHM
CRITICAL CRITICAL Q8102 CRITICAL
10K CRITICAL AON6407_001
BKLT_ISEN5_R 1 2
FB8108
1% 97 68
J8100 F8100 CRITICAL DFN5X6
R8130
1/16W
MF-LF FB8102 CRITICAL
0603
504050-1091 6AMP-32V R8112 FERR-600-OHM-3A SYM-VER-2
1 2 402 600-OHM-25%-0.5A-0.40OHM
F-RT-SM
=PP12V_S0_BKLT 1 2 97 PP12V_BKLT_SNS 10.0052 PP12V_BKLT_FUSED 1 97 2 PP12V_S0_BKLT_FILT 3 S PP12V_S0_BKLT_PWR 68 97
80 =PP5V_S0_BKLT 1 2 11 80
5% BKLT_ISEN4_R 1 2 1% 1206 2 D 5
1/16W GND 97 68
0603-1 1/4W
MF-LF 97 68 PP5V_S0_BKLT_R 0603 1 MF
NOSTUFF
1
CRITICAL 1206
402 FB8103 LED_RETURN_6 1
R8121
600-OHM-25%-0.5A-0.40OHM 97 2 1 C8171 G NOSTUFF
C8131 1 C8132 1 C8133 1
LED_RETURN_5 3 0.1UF 71.5K
1UF 0.01UF 0.1UF 1 2
97
10% 1% 4 1 C8137
97 LED_RETURN_4 4 25V 1/16W
10% 10% 10% 0603 2 X6S MF-LF 100PF
25V 2 16V 16V 5%
X7R X7R-CERM 2 X7R-CERM 2 FB8104 97 BKLT_BOOST_1 5 NOSTUFF 0402 2 402
0603 0402 0402 97 68 BKLT_BOOST600-OHM-25%-0.5A-0.40OHM R8120 2 50V
CERM
97 BKLT_BOOST_2 6
DGND_BKLT 0402
68 97 CRITICAL
1 2 97 LED_RETURN_3 7 NOSTUFF BKLT_EN_L 1 147K 2 BKLT_EN_DIV
0603 97 LED_RETURN_2 8 Q8101 1%
CRITICAL FB8105 SSM3K15AMFVAPE D 3 1/16W
MF-LF
97 LED_RETURN_1 9
R8131
600-OHM-25%-0.5A-0.40OHM VESM 402
R8122
1
A
80 =PP3V3_S0_BKLT_VDDIO 1
1 2
97 68 BKLT_ISEN3_R 1
0603
2
97 68 PGND_BKLT
10
0
5%
1/16W
CRITICAL FB8106 12 MF-LF PAGE TITLE
5% PP3V3_S0_BKLT_VDDIO_R
1/16W
MF-LF
402
97 68
600-OHM-25%-0.5A-0.40OHM 1 G S 2 2 402 LCD Backlight Driver (LP8561)
97 68 BKLT_ISEN2_R 1 2
BKLT_EN BKLT_SHUTDOWN DRAWING NUMBER SIZE
C8134 1 C8135 1 C8136 1
CRITICAL FB8107
0603
68 40 IN 68

1UF 0.01UF 0.1UF REVISION
10% 10% 10% 600-OHM-25%-0.5A-0.40OHM
25V
X7R 2
16V
X7R-CERM 2
16V
X7R-CERM 2
R
13.0.0
0603 0402 0402 97 68 BKLT_ISEN1_R 1 2
DGND_BKLT 68 97 0603
81 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S4 FET 3.3V S0 FET 3V3 S0 SSD 5V S0 FET

80 71 70 69 =PP3V3_S5_PWRCTL 80 =PP5V_S4_PWRCTL
80 65 =PP5V_S5_PWRCTL
SSD:Y
D 1 C8400
1 C8410
0.1UF
1 C8420
0.1UF
D
0.1UF 10% 10%
10% 16V 16V
2 X7R-CERM 2 X7R-CERM
2 16V
X7R-CERM 0402 0402
0402
1
VDD VDD
U8410 U8420
4
CRITICAL
5_VDD SLG5AP304V SLG5AP304V
TDFN TDFN
P3V3_S0_SSD_FET_RAMP 7 3 =PP3V3_S5_FET_P3V3_S0 P5V_S0_FET_RAMP 7 3 =PP5V_S4_FET_P5V_S0
U8400 CAP CRITICAL D 69 80 CAP CRITICAL D 80
SLG5AP439 70 69 IN PM_EN_FET_P3V3_S0 2 ON SSD:Y S 5 PP3V3_S0_SSD_FET OUT 80 69 IN PM_EN_FET_P5V_S0 2 ON S 5 PP5V_S0_FET OUT 69 80

TDFN 70
PM_EN_FET_P3V3_S4 3 ON_MOS1 ON_MOS2 5 PM_EN_FET_P3V3_S0 SSD:Y
70 IN IN 69 70 GND GND
12 CAP_MOS2 10
C8411 1 C8421 1
8
FET_RAMP_P3V3_S4 CAP_MOS1 FET_RAMP_P3V3_S0 0.0047UF 0.0047UF
10% 10%
80 OUT PP3V3_S4_FET 13 MOS1_S MOS2_S 8 PP3V3_S0_FET OUT 69 80
25V
CERM 2 4nF corresponds to
25V
CERM 2 4nF corresponds to
80 =PP3V3_S5_FET_P3V3_S4 1 MOS1_D MOS2_D 6 =PP3V3_S5_FET_P3V3_S0 69 80
0402
2.2V / ms ramp rate
0402 2.2V / ms ramp rate
IN IN
THRM 1 C8402
C8401 1 GND PAD
0.0047UF 0.0022UF
10%
11
15
10% 50V
25V 2 CERM
CERM 2 402
0402
C 5V HDD FET C
5V / 3V3 S0 PGOODs 80 69 =PP5V_S0_FET_P5V_HDD
1 C8460
0.1UF
10%
80 71 70 69 =PP3V3_S5_PWRCTL 2 16V
X7R-CERM
0402
1 C8440
1
0.1UF
10%
16V VDD
2 X7R-CERM
CRITICAL 8 0402 U8460
VCC SLG5AP304V
U8440
SOT833 P5V_S0_HDD_FET_RAMP 7 CAP
TDFN
D 3 =PP5V_S0_FET_P5V_HDD 69 80
CRITICAL
08
74LVC2G08GT/S505
PM_EN_FET_P5V_S0 1 7 PM_PGOOD_FET_P5V_S0 OUT HDD_PWR_EN 2 ON S 5
70 69 IN A1 Y1 70 18 14 IN
PP5V_S0_FET 2
80 69
5
B1 GND
3
70 69 IN PM_EN_FET_P3V3_S0
A2 Y2 PM_PGOOD_FET_P3V3_S0 OUT 70
C8461 1
8
PP3V3_S0_FET 6 0.0047UF
80 69
B2 10%
25V
GND CERM 2
0402
4
PP5V_S0_HDD_FET OUT 80
B B
VDDQ (1.5V) S0 FET 12V S0 FET CRITICAL

80 70 =PP12V_S5_PWRCTL Q8450
CRITICAL 649135PBF
Q8430 1 C8430 DIRECTFET_S3C
649135PBF 0.1UF
Max avg current:9.0A (FIX ME!!) 10%
Max peak current:11.3A (ME TOO!) DIRECTFET_S3C 2 16V 7
X7R-CERM
0402 8 6
7 80 =PP12V_G3H_FET_P12V_S0
2 5
PP12V_S0_FET
S
8 6 3 OUT 80
1
2 5
G
D
=PPVDDQ_S3_FET_VDDQ_S0 PP1V5_S0_FET
S
80 3 OUT 80
1
4
G
P12V_S0_FET_GATE_R
80 78 67 =PP3V3_S0_PWRCTL 1 C8450
4
0.1UF 1 C8451
10%
1
16V 0.022UF
1
1 VCC 2 X7R-CERM
R8430 0402 VCC
X7R
2 10%
5%
22K U8430 U8450 R8453
1
50V
0402
SLG5AP004
A
1/16W =PP3V3_S4_PWRCTL
MF-LF
2 402 5D DFN
ON 2 PM_EN_FET_REG_P1V5_S0 IN 70
70 IN PM_EN_FET_P12V_S0
Input: 2.4V to 5.5V 2
ON
SLG5AP036
TDFN
D 5 5%
1/16W
0
R84521
63 80
SYNC_MASTER=MASTER
PAGE TITLE
MF-LF 47K
P1V5_S0_FET_GATE
PM_PGOOD_FET_REG_P1V5_S0
7G
8 PG
CRITICAL S6
1
R8451 NC
3 NC CRITICAL G 7 P12V_S0_FET_GATE 2 402 5%
1/16W FET-Controlled S0 and S4
81 70 OUT NC 3 NC 6
MF-LF
402 2 DRAWING NUMBER SIZE
100K S
THRM
5%
1/16W Apple Inc. 051-9889 D
PAD GND MF-LF PG 8 PM_PGOOD_FET_P12V_S0 OUT 70 REVISION
2 402 13.0.0
9
R
THRM
GND PAD
4

84 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5 Enable S0 Enables
80 69 =PP12V_S5_PWRCTL
80 71 70 69 =PP3V3_S5_PWRCTL
1
R8590
68K
5% 14 74LVC08
1/16W 10 TSSOP-HF
MF-LF 71 45 44 36 21 12 IN PM_SLP_S3_L
2 402 8 PM_EN_FET_P12V_S0
U8500 OUT 69
D
60 PM_PGOOD_FET_P12V_S5 PM_EN_REG_P3V3_S5 OUT
MAKE_BASE=TRUE
65 63 IN PM_PGOOD_REG_VDDQ_S3 9 08
7
D
1
R8591
33K
5%
1/16W
MF-LF 80 71 70 69 =PP3V3_S5_PWRCTL
2 402
R85021
33K
5%
S4 Enables
1/16W
MF-LF
402 2
14 74LVC08
PU_U8500 13 TSSOP-HF R8530
80 71 70 69 =PP3V3_S5_PWRCTL 11
100
U8500 PM_EN_S0_R 1 2 PM_EN_FET_P5V_S0 OUT 69
12 MAKE_BASE=TRUE
69 IN PM_PGOOD_FET_P12V_S0 08 5%
1/16W =TBT_S0_EN OUT 29 30
1 C8500 7
MF-LF
402
0.1UF NOSTUFF
Note: 10%
16V
2 X7R-CERM C8501 1
Halt power sequencing at S5 0402 0.47UF
10%
if there is no processor. 6.3V
CERM-X5R 2
Remove Q8500 to circumvent 402
PLACE_SIDE=BOTTOM
or short gate to source.
14 74LVC08
44 32 12 IN PM_SLP_S5_L 1 TSSOP-HF R8531
3
0
PM_EN_S4 PM_PGOOD_FET_P5V_S0 1 2 PM_EN_FET_P3V3_S0
2
U8500 69 IN OUT 69
80 71 70 69 =PP3V3_S5_PWRCTL 08 5%
1/16W
EXT_GPU:YES 1 1 MF-LF
7 R8510 R8511 402
R85001 R85011 5%
33
5%
33
C 100K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
NOSTUFF
R8534 C
0
402 2 402 2 1 2 PM_EN_REG_CPUVCC_S0 OUT 61 70
PM_EN_REG_P5V_S4 OUT 65
CPU_SKTOCC 5% NOSTUFF
1/16W
EXT_GPU:YES PM_EN_FET_P3V3_S4 OUT 69 MF-LF
1 C8522
402 0.47UF
D 3 PLACE_SIDE=BOTTOM 10%
NOSTUFF NOSTUFF 6.3V
Q8500 1 C8510 1 C8511 21 IN MEMVTT_EN PM_EN_LDO_DDRVTT_S0 OUT 63
2 CERM-X5R
402
SSM3K15AMFVAPE 0.47UF 0.47UF MAKE_BASE=TRUE
10% 10%
1 G S 2
VESM 6.3V
2 CERM-X5R
402
6.3V
2 CERM-X5R
402
S0 GPU SEQUENCING(EXT GFX ONLY)
EXT_GPU:YES
CPU_SKTOCC_L
6 IN R8537
0
70 69 IN PM_PGOOD_FET_P3V3_S0 1 2 PM_EN_REG_GPUCORE_S0 OUT 67
tau (RC delay, ms): 0.0 0.0
5%
1/16W
MF-LF
402
R8538
0
S4 USB Enable 67 IN PM_PGOOD_REG_GPUCORE_S0 1
5%
1/16W
MF-LF
2 PM_EN_REG_GPU_VDDQ_S0 OUT 66
402
R8520 EXT_GPU:YES
0
PM_PGOOD_REG_P5V_S4 1 2 PM_EN_USB_PWR
70 65 IN
5%
1/16W
OUT 42 43
S0 PCH Sequencing
MF-LF NOSTUFF OMIT_TABLE
402 R8533
1 C8520 1.5K TABLE_5_HEAD
0.47UF 70 69 IN PM_PGOOD_FET_P3V3_S0 1 2 PM_EN_FET_REG_P1V5_S0 OUT 69 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
10%
B 6.3V
2 CERM-X5R
402
5%
1/16W
MF-LF
402
1
IG
C8524
116S0070 1 RES,1.5K,0402,5% R8533 IG
TABLE_5_ITEM
TABLE_5_ITEM
B
1UF 116S0004 1 RES,0OHM,0402,5% R8533 EXT_GPU:YES
10%
10V
2 X6S-CERM
IG
0402
Rail definitions
R8513 Platform: All processor non-Core and non-Graphics (5 V, 3.3 V, 1.5 V, 1.05V for PCH/TBT/GPU)
S4 TBT S4 Port Enable 1
0
5%
2 PM_EN_FET_P1V35_S0 OUT 82 Uncore: VDDQ
1/16W
MF-LF
80 30 29 28 27 26 IN =PP3V3_S4_TBT =TBTAPWRSW_EN OUT 29
402 Notes on sequencing requirements
=TBTBPWRSW_EN 30
Intel:
OUT
1. No hard specification on platform rails
IG R8514
0 2. SMC guarantees timing on PCH DPWROK and PWROK
82
PM_PGOOD_FET_P1V35_S0 1 2
IN 3. VCC3_3 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC3V3 ramping to 2.6V
5%
PM_PGOOD_REG_GPU_P1V35_S0
1/16W 4. VCC1_5 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC1V5 ramping to 1.35V
MF-LF
402 5. VCC may power down before VCC3_3, VCC3_3 must ramp down to 2.6V within 35ms
EXT_GPU:YES R8515 6. VCC may power down before VCC1_5, VCC1_5 must ramp down to 1.35V within 35ms
0 CKPLUS_WAIVE=UNCONNECTED_PINS NVIDIA:
S3 VDDQ Enable 66 IN
PM_PGOOD_REG_GPU_VDDQ_S0 1 2
5% 74LVC08 1. 3V3_S0 must ramp first
1/16W 14
MF-LF
10 TSSOP-HF 4. VDDQ MUST RAMP AFTER GPU_CORE
402 5. PEX_VDD with IFPC/D/E/F_IOVDD (1.05V) must ramp after VDDQ
9
U8600 8 PM_EN_REG_P1V05_S0_R OUT 70
6. All rails must reach their target voltages in more than 40 uS
81 69 IN PM_PGOOD_FET_REG_P1V5_S0 08
80 71 70 69 =PP3V3_S5_PWRCTL
7
CKPLUS_WAIVE=UNCONNECTED_PINS
A 44 12 IN PM_SLP_S4_L 4
14 74LVC08
TSSOP-HF R8536
0
SYNC_MASTER=MASTER SYNC_DATE=05/01/2013 A
6 PM_EN_REG_VDDQ_S3 PM_EN_REG_P1V05_S0_R 1 2 PM_EN_REG_P1V05_S0 PAGE TITLE
U8500 63
OUT
PM Regulator Enables
70 IN OUT 64
70 65 PM_PGOOD_REG_P5V_S4 5 08 5%
IN
1/16W
7 MF-LF NOSTUFF DRAWING NUMBER SIZE
402
1 C8523 Apple Inc. 051-9889 D
0.47UF REVISION
10%
2 6.3V
CERM-X5R
R
13.0.0
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R8535 THE INFORMATION CONTAINED HEREIN IS THE

0 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PM_PGOOD_REG_P1V05_S0 1 2 PM_EN_REG_CPUVCC_S0
71 64 IN
5%
OUT 61 70
85 OF 123
1/16W SHEET
MF-LF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 IV ALL RIGHTS RESERVED 70 OF 97
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ALL_SYS_PWRGD,PCH_PWROK & SYS_PWROK Generation

PCH Power Goods Resume Reset
Intel Doc# 29517 Maho Bay PDG, Section 22.13
Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8
Note:
To PCH The iMac J16/J17 designs does not support Deep Sx modes so both DPWROK and
RSMRST# signals are shorted together
D 80 71 70 69 =PP3V3_S5_PWRCTL
BYPASS=U8601:5MM
PM_PCH_APWROK OUT 12
Second Requirements:
D
1
C8605 Power on:
0.1UF Asserted at least 10 ms after all suspend well power is valid
20%
10V
2 CERM
To PCH Power off or loss of AC:
402 PM_PCH_PWROK OUT 12 18 20 39 Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V
=PP3V3_S5_PWRCTL 69 70 71 80 MAKE_BASE=TRUE
Second to allow PCH to switch suspend well to battery without excessive loading
74LVC1G08GW
SOT353 NO STUFF
PM_PGOOD_REG_P1V05_S0 1
5 R8624
1 1 C8621
70 64 IN B 10K 0.1UF
4 5% 10%
2
U8601Y 1/16W
MF-LF 2 16V
X7R-CERM
PM_SLP_S3_L
PM_PGOOD_SLP_S3_P1V05_S0
70 45 44 36 21 12 IN A 0402
2 402
3 BYPASS=U8600:5MM Method:
1
C8620 The SMC guarantees proper assertion and de-assertion of RSMRST# for
0.1UF NO STUFF normal operation via PM_DSW_PWRGD.
20%
2
10V
CERM
R8621 1
R8622
1
RSMRST# is asserted when power good from regulator is de-asserted in the
402 0 0
5% 5% event AC is lost. Power good de-assertion should happen quickly enough
1/16W 1/16W
MF-LF MF-LF to meet Intel spec.
402 2 2 402 CKPLUS_WAIVE=UNCONNECTED_PINS
14 74LVC08
4 TSSOP-HF 74LVC08
14
6 PM_PGOOD_ALL 13 TSSOP-HF R8625 To PCH
U8600 1K
PM_PGOOD_REG_CPUVCC_S0 5 11 PM_PCH_SYS_PWROK_R PM_PCH_SYS_PWROK To SMC
61 IN 08 U8600 1 2
OUT 12 18 45
PLACE_SIDE=BOTTOM 12 08 5% 71 65 PM_PGOOD_REG_P3V3_S5 S5_PWRGD 44

7 PLACE_NEAR=U1100.W31:7MM
Third IN OUT
1/20W MAKE_BASE=TRUE
MF
BYPASS=U8600:5MM 7 201
1
C8622
2.2UF
C 2
10%
6.3V
X5R
Delay=10ms From SMC
C
402
14 74LVC08
45 44 IN PM_DSW_PWRGD 1 TSSOP-HF R8635 To PCH
3
0
PM_RSMRST_PCH_L_R 1 2 PM_RSMRST_PCH_L
2
U8600 OUT 12 18
71 65 IN PM_PGOOD_REG_P3V3_S5 08 5%
1/16W
MF-LF
7 402
44 21 3 OUT ALL_SYS_PWRGD
MAKE_BASE=TRUE
To SMC, for 99ms delay
ALL_SYS_PWRGD must remain low for
5ms minimum after all rails are valid
45 44 28 IN
SMC_DELAYED_PWRGD
B B
PAGE TITLE
PM Power Good
DRAWING NUMBER SIZE

REVISION
R
13.0.0
86 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
Page Notes
U8700
- =PP3V3_GPU_VDD33
NV-GK107
BGA
(1 OF 10)
AN12 AK14
86 72 PEG_R2D_P<0> PEX_RX0 PEX_TX0 PEG_D2R_C_P<0> 72 86
AM12 AJ14
86 72 PEG_R2D_N<0> PEX_RX0* PEX_TX0* PEG_D2R_C_N<0> 72 86
(NONE)
POLARITY SWAPS INTENDED ON LANES,SEE NOTES AT DIFF PAIRS.
(NONE)
ALL LANES ARE ALSO REVERSED, SEE ALIASES ON CSA 102 86 72 PEG_R2D_P<1> AN14
AM14
PEX_RX1
PEX_RX1*
PEX_TX1
PEX_TX1*
AH14
AG14
PEG_D2R_C_P<1> 72 86
D
86 72 PEG_R2D_N<1> PEG_D2R_C_N<1> 72 86
D
AP14 AK15
C8720 0.22UF
1 2
C8736 0.22UF
1 2
86 81 PEG_R2D_C_P<0> PEG_R2D_N<0> 72 86 86 81 PEG_R2D_C_P<8> PEG_R2D_N<8> 72 86 AP15 AJ15
20% 6.3V X5R 0201 20% 6.3V X5R 0201 86 72 PEG_R2D_N<2> PEX_RX2* PEX_TX2* PEG_D2R_C_N<2> 72 86
Polarity swapped!! Polarity swapped!!
C8721 0.22UF C8737 0.22UF
PEG_R2D_C_N<0> 1 2 PEG_R2D_P<0> PEG_R2D_C_N<8> 1 2 PEG_R2D_P<8>
86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AN15 AL16
C8722 0.22UF
1 2
C8738 0.22UF
1 2
86 81 PEG_R2D_C_P<1> PEG_R2D_P<1> 72 86 86 81 PEG_R2D_C_P<9> PEG_R2D_N<9> 72 86
AM15 AK16
20% 6.3V X5R 0201 20% 6.3V X5R 0201
Polarity swapped!!
C8723 0.22UF C8739 0.22UF
PEG_R2D_C_N<1> 1 2 PEG_R2D_N<1> PEG_R2D_C_N<9> 1 2 PEG_R2D_P<9>
86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AN17 AK17
C8724 0.22UF
1 2
C8740 0.22UF
1 2
86 81 PEG_R2D_C_P<2> PEG_R2D_P<2> 72 86 86 81 PEG_R2D_C_P<10> PEG_R2D_P<10> 72 86 AM17 AJ17
20% 6.3V X5R 0201 20% 6.3V X5R 0201
C8725 0.22UF C8741 0.22UF

PEG_R2D_C_N<2> 1 2 PEG_R2D_N<2> PEG_R2D_C_N<10> 1 2 PEG_R2D_N<10>
86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AP17 AH17
C8726 0.22UF
1 2
C8742 0.22UF
1 2
86 81 PEG_R2D_C_P<3> PEG_R2D_P<3> 72 86 86 81 PEG_R2D_C_P<11> PEG_R2D_P<11> 72 86 AP18 AG17
C8727 0.22UF C8743 0.22UF

86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AN18 AK18
C8728 0.22UF
1 2
C8744 0.22UF
1 2
86 81 PEG_R2D_C_P<4> PEG_R2D_P<4> 72 86 86 81 PEG_R2D_C_P<12> PEG_R2D_P<12> 72 86 AM18 AJ18
C8729 0.22UF C8745 0.22UF

86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AN20 AL19
C8730 0.22UF
1 2
C8746 0.22UF
1 2
86 81 PEG_R2D_C_P<5> PEG_R2D_N<5> 72 86 86 81 PEG_R2D_C_P<13> PEG_R2D_N<13> 72 86
C 86 81 PEG_R2D_C_N<5>
C8731 0.22UF
1
20%
2
6.3V X5R 0201
Polarity swapped!!
PEG_R2D_P<5> 72 86 86 81 PEG_R2D_C_N<13>
C8747 0.22UF
1
20%
2
6.3V X5R 0201
Polarity swapped!!
PEG_R2D_P<13> 72 86
86 72 PEG_R2D_N<7> AM20
PEX_RX7* PEX_TX7* AK19 PEG_D2R_C_N<7> 72 86
C
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AP20 AK20
C8732 0.22UF
1 2
C8748 0.22UF
1 2
86 81 PEG_R2D_C_P<6> PEG_R2D_P<6> 72 86 86 81 PEG_R2D_C_P<14> PEG_R2D_P<14> 72 86 AP21 AJ20
C8733 0.22UF C8749 0.22UF

86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AN21 AH20
C8734 0.22UF
1 2
C8750 0.22UF
1 2
86 81 PEG_R2D_C_P<7> PEG_R2D_P<7> 72 86 86 81 PEG_R2D_C_P<15> PEG_R2D_P<15> 72 86 AM21 AG20
C8735 0.22UF C8751 0.22UF

86 81 72 86 86 81 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AN23 AK21
AM23 AJ21
C8755 0.22UF C8771 0.22UF

1 2 1 2 AP23 AL22
86 72 PEG_D2R_C_N<0>
20% 6.3V X5R 0201
PEG_D2R_P<0> 81 86 86 72 PEG_D2R_C_N<8>
20% 6.3V X5R 0201
PEG_D2R_P<8> 81 86 86 72 PEG_R2D_P<11> PEX_RX11 PEX_TX11 PEG_D2R_C_P<11> 72 86
AP24 AK22
Polarity swapped!! Polarity swapped!! 86 72 PEG_R2D_N<11> PEX_RX11* PEX_TX11* PEG_D2R_C_N<11> 72 86
C8756 0.22UF C8772 0.22UF
PEG_D2R_C_P<0> 1 2 PEG_D2R_N<0> PEG_D2R_C_P<8> 1 2 PEG_D2R_N<8>
86 72 81 86 86 72 81 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
C8757 0.22UF C8773 0.22UF

1 2 1 2 AN24 AK23
86 72 PEG_D2R_C_P<1>
20% 6.3V X5R 0201
PEG_D2R_P<1> 81 86 86 72 PEG_D2R_C_N<9>
20% 6.3V X5R 0201
PEG_D2R_P<9> 81 86 86 72 PEG_R2D_P<12> PEX_RX12 PEX_TX12 PEG_D2R_C_P<12> 72 86
AM24 AJ23
Polarity swapped!! 86 72 PEG_R2D_N<12> PEX_RX12* PEX_TX12* PEG_D2R_C_N<12> 72 86
C8758 0.22UF C8774 0.22UF
PEG_D2R_C_N<1> 1 2 PEG_D2R_N<1> PEG_D2R_C_P<9> 1 2 PEG_D2R_N<9>
86 72 81 86 86 72 81 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
C8759 0.22UF C8775 0.22UF

1 2 1 2 AN26 AH23
PEX_RX13 PEX_TX13
B
PEG_D2R_C_P<2> PEG_D2R_P<2> PEG_D2R_C_P<10> PEG_D2R_P<10> PEG_R2D_P<13> PEG_D2R_C_P<13>
B
86 72 81 86 86 72 81 86 86 72 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AM26 AG23
C8760 0.22UF C8776 0.22UF
PEG_D2R_C_N<2> 1 2 PEG_D2R_N<2> PEG_D2R_C_N<10> 1 2 PEG_D2R_N<10>
86 72 81 86 86 72 81 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
C8761 0.22UF C8777 0.22UF

1 2 1 2 AP26 AK24
86 72 PEG_D2R_C_P<3>
20% 6.3V X5R 0201
PEG_D2R_P<3> 81 86 86 72 PEG_D2R_C_P<11>
20% 6.3V X5R 0201
PEG_D2R_N<11> 81 86 86 72 PEG_R2D_P<14> PEX_RX14 PEX_TX14 PEG_D2R_C_P<14> 72 86
AP27 AJ24
Polarity swapped!! 86 72 PEG_R2D_N<14> PEX_RX14* PEX_TX14* PEG_D2R_C_N<14> 72 86
C8762 0.22UF C8778 0.22UF
PEG_D2R_C_N<3> 1 2 PEG_D2R_N<3> PEG_D2R_C_N<11> 1 2 PEG_D2R_P<11>
86 72 81 86 86 72 81 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
C8763 0.22UF C8779 0.22UF

1 2 1 2 AN27 AL25
86 72 PEG_D2R_C_P<4> PEG_D2R_P<4> 81 86 86 72 PEG_D2R_C_P<12> PEG_D2R_P<12> 81 86 86 72 PEG_R2D_P<15> PEX_RX15 PEX_TX15 PEG_D2R_C_P<15> 72 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
AM27 AK25
C8764 0.22UF C8780 0.22UF
PEG_D2R_C_N<4> 1 2 PEG_D2R_N<4> PEG_D2R_C_N<12> 1 2 PEG_D2R_N<12>
86 72 81 86 86 72 81 86 PLACE_NEAR=U8700.AJ26:8MM
20% 6.3V X5R 0201 20% 6.3V X5R 0201
R8702
200
C8765 0.22UF C8781 0.22UF 96 PEX_TSTCLK_O_PL 1 2
1 2 1 2 AL13 AJ26
86 72 PEG_D2R_C_N<5>
20% 6.3V X5R 0201
PEG_D2R_P<5> 81 86 86 72 PEG_D2R_C_P<13>
20% 6.3V X5R 0201
PEG_D2R_P<13> 81 86 86 11 IN PEG_CLK100M_P PEX_REFCLK PEX_TSTCLK_OUT NOSTUFF
1% MF
AK13 AK26
Polarity swapped!! 86 11 IN PEG_CLK100M_N PEX_REFCLK* PEX_TSTCLK_OUT* 1/20W 201 PLACE_NEAR=U8700.AP29:8MM
C8766 0.22UF C8782 0.22UF 96 PEX_TSTCLK_O_NG
86 72 PEG_D2R_C_P<5> 1 2 PEG_D2R_N<5> 81 86 86 72 PEG_D2R_C_N<13> 1 2 PEG_D2R_N<13> 81 86
R8700 R8705
20% 6.3V X5R 0201 20% 6.3V X5R 0201 GPU_RESET_L 0 GPU_RESET_R_L 2.49K
AJ12 AP29
78 20 IN
1 2 PEX_RST* PEX_TERMP 96 GPU_PEX_TERMP 1 2
C8767 0.22UF C8783 0.22UF MF 5% 1/20W 201 1%

PEG_D2R_C_P<6> 1 2 PEG_D2R_P<6> PEG_D2R_C_P<14> 1 2 PEG_D2R_P<14> 1/20W
86 72 81 86 86 72 81 86 AK12
20% 6.3V X5R 0201 20% 6.3V X5R 0201
11 OUT PEG_CLKREQ_L PEX_CLKREQ* MF
201
C8768 0.22UF C8784 0.22UF

1 2 1 2 AG12
86 72 PEG_D2R_C_N<6> PEG_D2R_N<6> 81 86 86 72 PEG_D2R_C_N<14> PEG_D2R_N<14> 81 86
AJ11 PEX_SVDD_3V3 =PP3V3_GPU_VDD33 77 78 79 80
20% 6.3V X5R 0201 20% 6.3V X5R 0201
NC PEX_WAKE*
C8769 0.22UF C8785 0.22UF

PEG_D2R_C_N<7> 1 2 PEG_D2R_N<7> PEG_D2R_C_P<15> 1 2 PEG_D2R_P<15>
86 72 81 86 86 72 81 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
C8770 0.22UF C8786 0.22UF

PEG_D2R_C_P<7> 1 2 PEG_D2R_P<7> PEG_D2R_C_N<15> 1 2 PEG_D2R_N<15>
86 72 81 86 86 72 81 86
20% 6.3V X5R 0201 20% 6.3V X5R 0201
PAGE TITLE
KEPLER PCI-E
DRAWING NUMBER SIZE

REVISION
R
13.0.0
87 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
OMIT_TABLE Power aliases required by this page:
- =PPVCORE_GPU
- =PP1V35_GPU_FBVDDQ
=PPVCORE_GPU U8700 =PPVCORE_GPU

80 79 73
NV-GK107 73 79 80
BGA
(10 OF 10)
AA12 V17
AA14 V18
AA16 V20
(NONE)
AA19 V22
D
AA21 W12 BOM options provided by this page:
D
=PPVCORE_GPU 73 79 80
AA23 W14 (NONE)
AB13 W16
VDD
AB15 W19
AB17 W21
AB18 W23
AB20 Y13
AB22 Y15
CRITICAL CRITICAL AC12 Y17
1 1 1 1 1 1 1 1
C8861 C8884 C8862 C8874 C8879 C8866 C8867 C8868
AC14 Y18
47UF 47UF 22UF 22UF 22UF 4.7UF 4.7UF 4.7UF
20% 20% 20% 20% 20% 20% 20% 20%
AC16 Y20
6.3V 4V 6.3V 4V 4V 6.3V 6.3V 6.3V
2 X5R 2 X6S
2 X5R-CERM1 2 X6S-CERM
2 X6S-CERM
2 X5R-CERM1
2 X5R-CERM1
2 X5R-CERM1
0805 0805 0603 0603 0603 402 402 402
AC19 Y22
AC21
U1
AC23 NC
U2
M12 NC
U3
M14
U4
NC
M16 NC
U5
M19 NC
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL U6
1
C8869 1
C8870 1
C8871 1
C8872 1
C8873 1
C8875 1
C8876 1
C8877 1
C8878 1
C8880 M21 NC
U7
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF M23 NC
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% U8
2
6.3V
2
6.3V
2
4V
2
4V
2
4V
2
4V
2
4V
2
4V
2
4V
2
4V N13 NC
X5R-CERM1 X5R-CERM1 X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM V1
402 402 0603 0603 0603 0603 0603 0603 0603 0603 N15 NC
V2
N17
VDD NC
V3
N18 NC
V4
N20 NC
V5
N22 NC
V6
P12
V7
NC
C CRITICAL
1
C8881
4.7UF
1
CRITICAL
C8885
4.7UF
P14
P16
V8
W2
NC
NC C
10% 10% P19 NC
4V 4V W3
2 X6S-CERM
2 X6S-CERM P21 NC
0603 0603 W4
P23 NC
W5
R13 NC
W7
R15 XVDD NC
W8
R17 NC
Y1
R18 NC
Y2
R20 NC
Y3
R22
Y4
NC
1 C8891 1 C8892 1 C8893 1 C8894 1 C8882 1 C8883 1 C8898 1 C8899 T12 NC
Y5
0.1UF
10%
0.1UF
10%
0.1UF
10%
0.1UF
10%
0.1UF
10%
0.1UF
10%
0.1UF
10%
0.1UF
10%
T14 NC
Y6
2 16V
X7R-CERM
2 16V
X7R-CERM
2 16V
X7R-CERM
2 16V
X7R-CERM
2 16V
X7R-CERM
2 16V
X7R-CERM
2 16V
X7R-CERM
2 16V
X7R-CERM
T16 NC
Y7
0402 0402 0402 0402 0402 0402 0402 0402
T19 NC
Y8
T21 NC
AA1
T23 NC
AA2
U13 NC
AA3
GPU VCORE DE-COUPLING U15 NC
AA4
U17 NC
AA5
U18 NC
AA6
U20 NC
AA7
U22 NC
AA8
V13 NC
V15
B B
GPU FB DE-COUPLING
OMIT_TABLE
80 76 75 73 =PP1V35_GPU_FBVDDQ
1 1
U8700
C8825 C8826 1
C8801 1
C8802
=PP1V35_GPU_FBVDDQ
NV-GK107 =PP1V35_GPU_FBVDDQ
80 76 75 73 73 75 76 80
20UF 20UF 10UF 10UF BGA
20% 20%
4V 4V 20% 20% (7 OF 10)
2 X5R-CERM 2 X5R-CERM 2
4V
2
4V
AA27 H18
X5R X5R
0402 0402
402 402
AA30 H19
AB27 H20
AB33 H21
AC27 H22
AD27 H23
AE27 H24
1 C8805 1 C8806 1 C8807 1 C8832 1
C8811 1
C8812 1
C8813 1
C8831 AF27 H8
4.7UF 4.7UF 4.7UF 4.7UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 10% 10% 10% 10% AG27 H9
6.3V 6.3V 6.3V 6.3V 25V 25V 25V 25V
2 X5R-CERM1
2 X5R-CERM1
2 X5R-CERM1
2 X5R-CERM1
2 X7R
2 X7R
2 X7R
2 X7R B13 L27
402 402 402 402 0603 0603 0603 0603
B16 M27
FBVDDQ FBVDDQ
B19 N27
E13 P27
E16 R27
A
E19 T27
1 C8822
0.1UF
1 C8823
0.1UF
1 C8824
0.1UF
1 C8830
0.1UF
H10
H11
T30
T33
SYNC_MASTER=J16_DG
PAGE TITLE
2
10%
16V
X7R-CERM
0402
2
10%
16V
X7R-CERM
0402
2
10%
16V
X7R-CERM
0402
2
10%
16V
X7R-CERM
0402
H12
H13
V27
W27
KEPLER CORE/FB POWER
DRAWING NUMBER SIZE
H14 W30
H15 W33
REVISION
H16 Y27 R
13.0.0
88 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
NOTE:GDDR5 MODE H MAPPING
96 75 74 FB_A0_RESET_L 96 75 74 FB_A1_RESET_L Power aliases required by this page:
- =PP1V35_GPU_S0_FB
- =PP1V05_GPU_PEX_IOVDD
OMIT_TABLE
1 1
R9050 R9051
U8700 10K 10K OMIT_TABLE Signal aliases required by this page:
NV-GK107 1%
1/20W
1%
1/20W (NONE)
BGA
(3 OF 10) 2
MF
201
2
MF
201 U8700
L28
MEM INTERFACE A U30
NV-GK107 BOM options provided by this page:
96 75 BI FB_A0_DQ<0> FBA_D0 FBA_CMD0 FB_A0_CS_L OUT 75 96 BGA (NONE)
96 75 FB_A0_DQ<1> M29
FBA_D1 FBA_CMD1 T31 FB_A0_A<3> 75 96
(4 OF 10)
BI OUT MEM INTRERFACE B
L29 U29 G9 D13
96 75 BI FB_A0_DQ<2> FBA_D2 FBA_CMD2 FB_A0_A<2> OUT 75 96 96 76 BI FB_B0_DQ<0> FBB_D0 FBB_CMD0 FB_B0_CS_L OUT 76 96
D 96 75
96 75
BI
BI
FB_A0_DQ<3>
FB_A0_DQ<4>
M28
N31
FBA_D3
FBA_D4
FBA_CMD3
FBA_CMD4
R34
R33
FB_A0_A<4>
FB_A0_A<5>
OUT
OUT
75 96
75 96 =PP1V35_GPU_S0_FB 74 80
96 76
96 76
BI
BI
FB_B0_DQ<1>
FB_B0_DQ<2>
E9
G8
FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
E14
F14
FB_B0_A<3>
FB_B0_A<2>
OUT
OUT
76 96
76 96
L9001
30-OHM-25%-5A-0.01-OHM MIN_LINE_WIDTH=0.6 MM
D
P29 U32 F9 A12 MIN_NECK_WIDTH=0.2 MM
96 75 BI FB_A0_DQ<5> FBA_D5 FBA_CMD5 FB_A0_WE_L
OUT 75 96 96 76 BI FB_B0_DQ<3> FBB_D3 FBB_CMD3 FB_B0_A<4> OUT 76 96 =PP1V05_GPU_PEX_IOVDD 1 2 VOLTAGE=1.05V PP1V05_GPU_FB_PLL_AVDD
R29 U33 F11 B12 80 79 74 74
96 75 BI FB_A0_DQ<6> FBA_D6 FBA_CMD6 FB_A0_A<7>
OUT 75 96
1 1
96 76 BI FB_B0_DQ<4> FBB_D4 FBB_CMD4 FB_B0_A<5>
OUT 76 96
0603
P28 U28 R9052 R9053 G11 C14 CRITICAL
96 75 BI FB_A0_DQ<7> FBA_D7 FBA_CMD7 FB_A0_A<6> OUT 75 96 96 76 BI FB_B0_DQ<5> FBB_D5 FBB_CMD5 FB_B0_WE_L OUT 76 96
10K 10K ESR = 0.05OHM
J28 V28 F12 B14 1 1 1 1
96 75 BI FB_A0_DQ<8> FBA_D8 FBA_CMD8 FB_A0_ABI_L
OUT 75 96 1% 1% 96 76 BI FB_B0_DQ<6> FBB_D6 FBB_CMD6 FB_B0_A<7>
OUT 76 96 C9001 C9002 C9003 C9004
1/20W 1/20W
H29 V29 G12 G15 20UF 1.0UF 0.1UF 0.1UF
96 75 BI FB_A0_DQ<9> FBA_D9 FBA_CMD9 FB_A0_A<8> OUT 75 96 MF MF 96 76 BI FB_B0_DQ<7> FBB_D7 FBB_CMD7 FB_B0_A<6> OUT 76 96
20% 20% 10% 10%
201 201
J29 V30 2 2 G6 F15 4V 6.3V 16V 16V
96 75 BI FB_A0_DQ<10> FBA_D10 FBA_CMD10 FB_A0_A<0> OUT 75 96 96 76 BI FB_B0_DQ<8> FBB_D8 FBB_CMD8 FB_B0_ABI_L OUT 76 96 2 X5R-CERM
2 X5R
2 X7R-CERM
2 X7R-CERM
H28 U34 F5 E15
96 75 BI FB_A0_DQ<11> FBA_D11 FBA_CMD11 FB_A0_A<1> OUT 75 96 96 76 BI FB_B0_DQ<9> FBB_D9 FBB_CMD9 FB_B0_A<8> OUT 76 96
0402 0201-1 0402 0402
G29 U31 E6 D15

96 75 BI FB_A0_DQ<12> FBA_D12 FBA_CMD12 FB_A0_RAS_L
OUT 75 96 96 75 74 FB_A0_CKE_L 96 76 BI FB_B0_DQ<10> FBB_D10 FBB_CMD10 FB_B0_A<0>
OUT 76 96
E31 V34 F6 A14
96 75 BI FB_A0_DQ<13> FBA_D13 FBA_CMD13 FB_A0_RESET_L
OUT 74 75 96 96 76 BI FB_B0_DQ<11> FBB_D11 FBB_CMD11 FB_B0_A<1>
OUT 76 96
E32 V33 F4 D14
96 75 BI FB_A0_DQ<14> FBA_D14 FBA_CMD14 FB_A0_CKE_L
OUT 74 75 96 96 76 BI FB_B0_DQ<12> FBB_D12 FBB_CMD12 FB_B0_RAS_L
OUT 76 96
F30 Y32 96 75 74 FB_A1_CKE_L G4 A15
96 75 BI FB_A0_DQ<15> FBA_D15 FBA_CMD15 FB_A0_CAS_L
OUT 75 96 96 76 BI FB_B0_DQ<13> FBB_D13 FBB_CMD13 FB_B0_RESET_L
OUT 74 76 96
C34 AA31 E2 B15
96 75 BI FB_A0_DQ<16> FBA_D16 FBA_CMD16 FB_A1_CS_L
OUT 75 96 96 76 BI FB_B0_DQ<14> FBB_D14 FBB_CMD14 FB_B0_CKE_L
OUT 74 76 96
D32 AA29 F3 C17
OUT 75 96 96 76 BI FB_B0_DQ<15> FBB_D15 FBB_CMD15 FB_B0_CAS_L
OUT 76 96 L9002
B33 AA28 C2 D18 30-OHM-25%-5A-0.01-OHM MIN_LINE_WIDTH=0.6 MM
96 75 BI FB_A0_DQ<18> FBA_D18 FBA_CMD18 FB_A1_A<2> OUT 75 96 96 76 BI FB_B0_DQ<16> FBB_D16 FBB_CMD16 FB_B1_CS_L OUT 76 96 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
96 75 FB_A0_DQ<19> C33
FBA_D19 FBA_CMD19 AC34 FB_A1_A<4> 75 96 96 76 FB_B0_DQ<17> D4
FBB_D17 FBB_CMD17 E18 FB_B1_A<3> 76 80 79 74
=PP1V05_GPU_PEX_IOVDD 1 2 PP1V05_GPU_FB_DLL_AVDD 74
BI OUT BI OUT 96
F33 AC33 D3 F18 0603
OUT 75 96 96 76 BI FB_B0_DQ<18> FBB_D18 FBB_CMD18 FB_B1_A<2>
OUT 76 96 CRITICAL
F32 AA32 C1 A20
96 75 BI FB_A0_DQ<21> FBA_D21 FBA_CMD21 FB_A1_WE_L OUT 75 96 =PP1V35_GPU_S0_FB 74 80 96 76 BI FB_B0_DQ<19> FBB_D19 FBB_CMD19 FB_B1_A<4> OUT 76 96 ESR = 0.05OHM
1 1 1
H33 AA33 PLACE_NEAR=U8700.H26:8MM
B3 B20 C9008 C9009 C9005
96 75 BI FB_A0_DQ<22> FBA_D22 FBA_CMD22 FB_A1_A<7> OUT 75 96
1
NOSTUFF 96 76 BI FB_B0_DQ<20> FBB_D20 FBB_CMD20 FB_B1_A<5> OUT 76 96
20UF 1.0UF 0.1UF
96 75 FB_A0_DQ<23> H32
FBA_D23 FBA_CMD23 Y28 FB_A1_A<6> 75 96
R9058 96 76 FB_B0_DQ<21> C4
FBB_D21 FBB_CMD21 C18 FB_B1_WE_L 76 96
20% 20% 10%
BI OUT BI OUT 4V 6.3V 16V
P34 Y29 1.33K 2 2 2
B5 B18 X5R-CERM X5R X7R-CERM
96 75 BI FB_A0_DQ<24> FBA_D24 FBA_CMD24 FB_A1_ABI_L
OUT 75 96 1% 96 76 BI FB_B0_DQ<22> FBB_D22 FBB_CMD22 FB_B1_A<7>
OUT 76 96 0402 0201-1 0402
1/20W
P32 W31 C5 G18
OUT 75 96 MF 96 76 BI FB_B0_DQ<23> FBB_D23 FBB_CMD23 FB_B1_A<6>
OUT 76 96
201
P31 Y30 2 A11 G17
OUT 75 96 96 76 BI FB_B0_DQ<24> FBB_D24 FBB_CMD24 FB_B1_ABI_L
OUT 76 96
P33 AA34 C11 F17
OUT 75 96 FB_VREF 74 96 76 BI FB_B0_DQ<25> FBB_D25 FBB_CMD25 FB_B1_A<8>
OUT 76 96
L31 Y31 D11 D16
96 75 BI FB_A0_DQ<28> FBA_D28 FBA_CMD28 FB_A1_RAS_L
OUT 75 96 PLACE_NEAR=U8700.H26:8MM PLACE_NEAR=U8700.H26:8MM 96 76 BI FB_B0_DQ<26> FBB_D26 FBB_CMD26 FB_B1_A<0>
OUT 76 96
L34 Y34 1
NOSTUFF NOSTUFF B11 A18
96 75 FB_A0_DQ<29> FBA_D29 FBA_CMD29 FB_A1_RESET_L 74 75 96 96 76 FB_B0_DQ<27> FBB_D27 FBB_CMD27 FB_B1_A<1> 76 96
FB PLL & DLL VDD
C
BI OUT R9059 BI OUT
C C9060
1
L32 Y33 D8 D17
96 75 BI FB_A0_DQ<30> FBA_D30 FBA_CMD30 FB_A1_CKE_L
OUT 74 75 96 1.33K
0.1UF
96 76 BI FB_B0_DQ<28> FBB_D28 FBB_CMD28 FB_B1_RAS_L
OUT 76 96
1%
L33 V31 A8 A17
96 75 BI FB_A0_DQ<31> FBA_D31 FBA_CMD31 FB_A1_CAS_L
OUT 75 96 1/20W
10%
6.3V
96 76 BI FB_B0_DQ<29> FBB_D29 FBB_CMD29 FB_B1_RESET_L
OUT 74 76 96
MF 2
AG28 CERM-X5R C8 B17
96 75 BI FB_A1_DQ<0> FBA_D32 R30 2
201 96 76 BI FB_B0_DQ<30> FBB_D30 FBB_CMD30 FB_B1_CKE_L OUT 74 76 96
AF29 FBA_CLK0 FB_A0_CLK_P
OUT 75 96
0201
B8 E17
96 75 BI FB_A1_DQ<1> FBA_D33 R31 96 76 BI FB_B0_DQ<31> FBB_D31 FBB_CMD31 FB_B1_CAS_L
OUT 76 96
AG29 FBA_CLK0* FB_A0_CLK_N
OUT 75 96 F24
96 75 BI FB_A1_DQ<2> FBA_D34 AB31 96 76 BI FB_B1_DQ<0> FBB_D32 D12 96 76 74 FB_B0_RESET_L 96 76 74 FB_B1_RESET_L
AF28 FBA_CLK1 FB_A1_CLK_P
OUT 75 96 G23 FBB_CLK0 FB_B0_CLK_P
OUT 76 96
96 75 BI FB_A1_DQ<3> FBA_D35 AC31 96 76 BI FB_B1_DQ<1> FBB_D33 E12
AD30 FBA_CLK1* FB_A1_CLK_N OUT 75 96 E24 FBB_CLK0* FB_B0_CLK_N OUT 76 96
96 75 BI FB_A1_DQ<4> FBA_D36 96 76 BI FB_B1_DQ<2> FBB_D34 E20 1 1
AD29 G24 FBB_CLK1 FB_B1_CLK_P OUT 76 96 R9054 R9055
96 75 BI FB_A1_DQ<5> FBA_D37 P30 96 76 BI FB_B1_DQ<3> FBB_D35 F20
AC29 FBA_DQM0 FB_A0_DBI_L<0>
BI 75 96 D21 FBB_CLK1* FB_B1_CLK_N
OUT 76 96 10K 10K
96 75 BI FB_A1_DQ<6> FBA_D38 F31 FB VREF GEN (TEST ONLY) 96 76 BI FB_B1_DQ<4> FBB_D36 1% 1%
AD28 FBA_DQM1 FB_A0_DBI_L<1>

BI 75 96
E21 1/20W 1/20W
96 75 BI FB_A1_DQ<7> FBA_D39 F34 96 76 BI FB_B1_DQ<5> FBB_D37 E11 MF MF
AJ29 FBA_DQM2 FB_A0_DBI_L<2>

BI 75 96 G21 FBB_DQM0 FB_B0_DBI_L<0>
BI 76 96
2
201
2
201
96 75 BI FB_A1_DQ<8> FBA_D40 M32 96 76 BI FB_B1_DQ<6> FBB_D38 E3
AK29 FBA_DQM3 FB_A0_DBI_L<3>
BI 75 96 F21 FBB_DQM1 FB_B0_DBI_L<1>
BI 76 96
96 75 BI FB_A1_DQ<9> FBA_D41 AD31 96 76 BI FB_B1_DQ<7> FBB_D39 A3
AJ30 FBA_DQM4 FB_A1_DBI_L<0>
BI 76 96
96 75 BI FB_A1_DQ<10> FBA_D42 AL29 96 76 BI FB_B1_DQ<8> FBB_D40 C9
AK28 FBA_DQM5 FB_A1_DBI_L<1> BI 75 96 D27 FBB_DQM3 FB_B0_DBI_L<3> BI 76 96
96 75 BI FB_A1_DQ<11> FBA_D43 AM32 96 76 BI FB_B1_DQ<9> FBB_D41 F23
AM29 FBA_DQM6 FB_A1_DBI_L<2>
BI 76 96
96 75 BI FB_A1_DQ<12> FBA_D44 AF34 96 76 BI FB_B1_DQ<10> FBB_D42 F27
AM31 FBA_DQM7 FB_A1_DBI_L<3>
BI 75 96 E27 FBB_DQM5 FB_B1_DBI_L<1>
BI 76 96 =PP1V35_GPU_S0_FB 74 80
96 75 BI FB_A1_DQ<13> FBA_D45 96 76 BI FB_B1_DQ<11> FBB_D43 C30
AN29 E29 FBB_DQM6 FB_B1_DBI_L<2>
BI 76 96
96 75 BI FB_A1_DQ<14> FBA_D46 M30 96 76 BI FB_B1_DQ<12> FBB_D44 A24
AM30 FBA_DQS_RN0 NC F29 FBB_DQM7 FB_B1_DBI_L<3>
BI 76 96
96 75 BI FB_A1_DQ<15> FBA_D47 H30 96 76 BI FB_B1_DQ<13> FBB_D45 1 1
AN31 FBA_DQS_RN1 NC E30 R9056 R9057
96 75 BI FB_A1_DQ<16> FBA_D48 E34 96 76 BI FB_B1_DQ<14> FBB_D46 D9 10K 10K
AN32 FBA_DQS_RN2 NC D30 FBB_DQS_RN0 NC
96 75 BI FB_A1_DQ<17> FBA_D49 M34 96 76 BI FB_B1_DQ<15> FBB_D47 E4
1% 1%
AP30 FBA_DQS_RN3 NC A32 FBB_DQS_RN1 NC

1/20W 1/20W
96 75 BI FB_A1_DQ<18> FBA_D50 AF30 96 76 BI FB_B1_DQ<16> FBB_D48 B2

MF MF
AP32 FBA_DQS_RN4 NC C31 FBB_DQS_RN2 NC 2

201
2
201
96 75 BI FB_A1_DQ<19> FBA_D51 AK31 96 76 BI FB_B1_DQ<17> FBB_D49 A9

AM33 FBA_DQS_RN5 NC C32 FBB_DQS_RN3 NC
96 75 BI FB_A1_DQ<20> FBA_D52 AM34 96 76 BI FB_B1_DQ<18> FBB_D50 D22
AL31 FBA_DQS_RN6 NC B32 FBB_DQS_RN4 NC 96 76 74 FB_B0_CKE_L
96 75 BI FB_A1_DQ<21> FBA_D53 AF32 96 76 BI FB_B1_DQ<19> FBB_D51 D28
AK33 FBA_DQS_RN7 NC D29 FBB_DQS_RN5 NC
96 75 BI FB_A1_DQ<22> FBA_D54 96 76 BI FB_B1_DQ<20> FBB_D52 A30
AK32 A29 FBB_DQS_RN6 NC
96 75 BI FB_A1_DQ<23> FBA_D55 M31 96 76 BI FB_B1_DQ<21> FBB_D53 B23 96 76 74 FB_B1_CKE_L
FBA_DQS_WP0 FBB_DQS_RN7
B
FB_A0_EDC<0>
B NC
AD34 IN 75 96 C29
96 75 BI FB_A1_DQ<24> FBA_D56 G31 96 76 BI FB_B1_DQ<22> FBB_D54
AD32 FBA_DQS_WP1 FB_A0_EDC<1>
IN 75 96 =PP1V35_GPU_S0_FB 74 80
B29
96 75 BI FB_A1_DQ<25> FBA_D57 E33 96 76 BI FB_B1_DQ<23> FBB_D55 D10
AC30 FBA_DQS_WP2 FB_A0_EDC<2> IN 75 96 B21 FBB_DQS_WP0 FB_B0_EDC<0> IN 76 96
96 75 BI FB_A1_DQ<26> FBA_D58 M33 96 76 BI FB_B1_DQ<24> FBB_D56 D5
AD33 FBA_DQS_WP3 FB_A0_EDC<3>
IN 75 96 C23 FBB_DQS_WP1 FB_B0_EDC<1>
IN 76 96
96 75 BI FB_A1_DQ<27> FBA_D59 AE31 96 76 BI FB_B1_DQ<25> FBB_D57 C3
AF31 FBA_DQS_WP4 FB_A1_EDC<0>
IN 75 96 A21 FBB_DQS_WP2 FB_B0_EDC<2>
IN 76 96 MEM VREFC & VREFD SWITCH
96 75 BI FB_A1_DQ<28> FBA_D60 AK30 1
NOSTUFF 1
NOSTUFF 96 76 BI FB_B1_DQ<26> FBB_D58 B9
AG34 FBA_DQS_WP5 FB_A1_EDC<1> IN 75 96 R9003 R9002 C21 FBB_DQS_WP3 FB_B0_EDC<3> IN 76 96
96 75 BI FB_A1_DQ<29> FBA_D61 AN33 96 76 BI FB_B1_DQ<27> FBB_D59 E23
AG32 FBA_DQS_WP6 FB_A1_EDC<2> IN 75 96 60.4 60.4
B24 FBB_DQS_WP4 FB_B1_EDC<0> IN 76 96
96 75 BI FB_A1_DQ<30> FBA_D62 AF33 1% 1% 96 76 BI FB_B1_DQ<28> FBB_D60 E28
AG33 FBA_DQS_WP7 FB_A1_EDC<3>
IN 75 96 1/20W 1/20W
C24 FBB_DQS_WP5 FB_B1_EDC<1>
IN 76 96
96 75 BI FB_A1_DQ<31> FBA_D63 MF MF 96 76 BI FB_B1_DQ<29> FBB_D61 B30 76 75 OUT FB_SW_LEG
K27 2
201
2
201
B26 FBB_DQS_WP6 FB_B1_EDC<2>
IN 76 96
K31 FB_DLL_AVDD PP1V05_GPU_FB_DLL_AVDD 74 96 76 BI FB_B1_DQ<30> FBB_D62 A23 CRITICAL
96 75 OUT FB_A0_WCLK_P<0> FBA_WCK01 U27 C26 FBB_DQS_WP7 FB_B1_EDC<3> IN 76 96
L30 FBA_PLL_AVDD PP1V05_GPU_FB_PLL_AVDD 74 96 76 BI FB_B1_DQ<31> FBB_D63 Q9065
96 75 OUT FB_A0_WCLK_N<0> FBA_WCK01*
FBA_DEBUG R28 GPU_FBA_DEBUG0 96 76 FB_B0_WCLK_P<0> F8
FBB_WCK01 3 D SSM3K15AMFVAPE
H34 1 OUT H17
96 75 OUT FB_A0_WCLK_P<1> FBA_WCK23 AC28 R9070 E8 FBB_PLL_AVDD 74 PP1V05_GPU_FB_PLL_AVDD VESM
J34 FBA_DEBUG GPU_FBA_DEBUG1 96 76 OUT FB_B0_WCLK_N<0> FBB_WCK01*
96 75 OUT FB_A0_WCLK_N<1> FBA_WCK23* 100 G14
J27 5% A5 FBB_DEBUG0 GPU_FBB_DEBUG0 74
AG30 FB_CAL_PD_VDDQ FB_CAL_PD_VDDQ 74 96 1/20W 96 76 OUT FB_B0_WCLK_P<1> FBB_WCK23 G20
96 75 OUT FB_A1_WCLK_P<0> FBA_WCK45 H27 MF A6 FBB_DEBUG1 GPU_FBB_DEBUG1 74
1 1
AG31 FB_CAL_PU_GND FB_CAL_PU_GND 74 96
R9001 2
201 96 76 OUT FB_B0_WCLK_N<1> FBB_WCK23* C9006 C9007
96 75 OUT FB_A1_WCLK_N<0> FBA_WCK45* H25 96 FB_CAL_TERM_GND PLACE_NEAR=U8700.H25:8MM
H26 1.0UF 0.1UF 2 S G 1
FB_CAL_TERM_GND 1 2
NOSTUFF D24 FB_VREF FB_VREF 74
AJ34 96 76 OUT FB_B1_WCLK_P<0> FBB_WCK45 20% 10% GPU_ALT_VREF IN 78
96 75 OUT FB_A1_WCLK_P<1> FBA_WCK67 E1
60.4 1% 1/20W MF 201
D25 C12 2
6.3V
X5R
2
6.3V
CERM-X5R
AK34 FB_CLAMP FB_CLAMP PLACE_NEAR=U8700.E1:8MM 96 76 OUT FB_B1_WCLK_N<0> FBB_WCK45* FBB_CMD_RFU0 NC 0201-1 0201
96 75 OUT FB_A1_WCLK_N<1> FBA_WCK67* R9061 C20 1
R32 10K B27 FBB_CMD_RFU1 NC R9060
J30 FBA_CMD_RFU NC
1 2 96 76 OUT FB_B1_WCLK_P<1> FBB_WCK67
NC FBA_WCKB01 AC32 C27
10K
J31 FBA_CMD_RFU NC MF 1% 1/20W 201 96 76 OUT FB_B1_WCLK_N<1> FBB_WCK67* 5%
NC FBA_WCKB01* 1/20W
F1 D6 MF
J32 FB_VDDQ_SENSE SNS_GPUVDDQ_P
OUT 66 94
NC FBB_WCKB01 2 201
NC FBA_WCKB23 D7
J33 F2 NC FBB_WCKB01*
NC FBA_WCKB23* FB_GND_SENSE SNS_GPUVDDQ_N OUT 66 94
C6
AH31 NC FBB_WCKB23
NC FBA_WCKB45 B6
AJ31 NC FBB_WCKB23*
NC FBA_WCKB45* PLACE CLOSE TO BGA
A
F26
FBB_WCKB45
A
=PP1V35_GPU_S0_FB
AJ32
FBA_WCKB67
1
R9071 NC 74 80
NC FB_CAL_PU_GND =PP1V35_GPU_S0_FB E26
FBB_WCKB45* SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013
AJ33
FBA_WCKB67*
96 74 74 80
100 NC
NC 5% PAGE TITLE
1
R9004
1
R9005 2
1/20W
MF
201
NC
NC
A26
A27
FBB_WCKB67
FBB_WCKB67* 1
NOSTUFF 1
NOSTUFF
KEPLER FRAME BUFFER I/F
NOSTUFF R9006 R9007 DRAWING NUMBER SIZE
PLACE_NEAR=U8700.H27:8MM
40.2
1%
1/20W
40.2
1%
1/20W
PLACE_NEAR=U8700.J27:8MM 60.4
1%
60.4
1% Apple Inc. 051-9889 D
MF MF 1/20W 1/20W REVISION
2
201
2
201
2
MF
201
2
MF
201
R
13.0.0
FB_CAL_PD_VDDQ 74 96 THE INFORMATION CONTAINED HEREIN IS THE
74 GPU_FBB_DEBUG0 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
74 GPU_FBB_DEBUG1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
90 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
U9200 U9250
This memory device is in Mirrored Mode. 32MX32-1.5GHZ-MFH
- =PP1V5R1V35_S0_FB_VDD 32MX32-1.5GHZ-MFL BGA
BGA K4G10325FG-HC03
Signal aliases required by this page: K4G10325FG-HC03
K11 (1 OF 2) P13
(NONE)
H11 D2 96 74 IN FB_A1_A<2> BA0/A2 DBI1* FB_A1_DBI_L<1>
BI 74 96
96 74 IN FB_A0_A<2> BA0/A2 DBI0* FB_A0_DBI_L<0> BI 74 96
H10 D13
K10 (1 OF 2) D13 96 74 IN FB_A1_A<5> BA1/A5 DBI2* FB_A1_DBI_L<2> BI 74 96
BOM options provided by this page: 96 74 IN FB_A0_A<5> BA1/A5 DBI1* FB_A0_DBI_L<1> BI 74 96
H11 P2
K11 P13 96 74 IN FB_A1_A<4> BA2/A4 DBI0* FB_A1_DBI_L<0> BI 74 96
K10 D2
H10 P2 96 74 IN FB_A1_A<3> BA3/A3 DBI3* FB_A1_DBI_L<3> BI 74 96
96 74 IN FB_A1_A<7> H4 A8/A7 DQ0 U4 FB_A1_DQ<0> BI 74 96

CK TERMINATION - A0 PLACE_NEAR=U9200.J11:8MM 96 74 FB_A0_A<7> K4 A8/A7 DQ0 A4 FB_A0_DQ<0> 74 96
IN BI K5 U2
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE FB_A1_A<1> A9/A1 DQ1 FB_A1_DQ<1>
D FB_A0_CLK_P
R9201
40.2 FBA0_CK_MID
R9202
40.2 FB_A0_CLK_N
96 74
96 74
IN
IN
FB_A0_A<1>
FB_A0_A<0>
H5
H4
A9/A1
A10/A0
DQ1
DQ2
A2
B4
FB_A0_DQ<1>
FB_A0_DQ<2>
BI
BI
74 96
74 96
96 74
96 74
IN
IN FB_A1_A<0> K4
H5
A10/A0 DQ2 T4
T2
FB_A1_DQ<2>
BI
BI
74 96
74 96 D
75 74 1 2 1 2 74 75 96
K5 B2 80 76 75 73 =PP1V35_GPU_FBVDDQ 96 74 IN FB_A1_A<6> A11/A6 DQ3 FB_A1_DQ<3>
BI 74 96
96 96 74 IN FB_A0_A<6> A11/A6 DQ3 FB_A0_DQ<3> BI 74 96
J3 N4
1% FBA 1% FBA J3 E4 96 74 IN FB_A1_CKE_L CKE* DQ4 FB_A1_DQ<4> BI 74 96
1/20W 1/20W 96 74 IN FB_A0_CKE_L CKE* DQ4 FB_A0_DQ<4>
BI 74 96
N2
MF
FBA MF
E2 OMIT_TABLE DQ5 FB_A1_DQ<5> BI 74 96
201 201 OMIT_TABLE DQ5 FB_A0_DQ<5> BI 74 96
J12 M4
PLACE_NEAR=U9200.J12:8MM
1 C9290 J12 F4 1
96 75 74 IN FB_A1_CLK_P CK DQ6 FB_A1_DQ<6>
BI 74 96
0.01UF 96 75 74 IN FB_A0_CLK_P CK DQ6 FB_A0_DQ<6> BI 74 96 R9254 J11 M2
10% J11 F2 96 75 74 IN FB_A1_CLK_N CK* DQ7 FB_A1_DQ<7> BI 74 96
10V 96 75 74 IN FB_A0_CLK_N CK* DQ7 FB_A0_DQ<7> BI 74 96 1K L12 U11
2 X5R-CERM G12 A11 5% 96 74 IN FB_A1_CS_L CS* DQ8 FB_A1_DQ<8> BI 74 96
0201 96 74 IN FB_A0_CS_L CS* DQ8 FB_A0_DQ<8> BI 74 96 1/20W
G12 U13
L12 A13 MF 96 74 IN FB_A1_WE_L WE* DQ9 FB_A1_DQ<9> BI 74 96
96 74 IN FB_A0_WE_L WE* DQ9 FB_A0_DQ<9> BI 74 96 201
2 G3 T11
L3 B11 96 74 IN FB_A1_CAS_L CAS* DQ10 FB_A1_DQ<10> BI 74 96
96 74 IN FB_A0_CAS_L CAS* DQ10 FB_A0_DQ<10> BI 74 96 FBA L3 T13
G3 B13 96 74 IN FB_A1_RAS_L RAS* DQ11 FB_A1_DQ<11> BI 74 96
96 74 IN FB_A0_RAS_L RAS* DQ11 FB_A0_DQ<11> BI 74 96
J13 N11
J13 E11
FB_A1_ZQ ZQ DQ12 FB_A1_DQ<12> BI 74 96
FB_A0_ZQ ZQ DQ12 FB_A0_DQ<12>
BI 74 96
J1 N13
J1 E13
FB_A1_MF MF (MF=1) DQ13 FB_A1_DQ<13> BI 74 96
1
FB_A0_MF MF (MF=0) DQ13 FB_A0_DQ<13> BI 74 96
J10 M11
R9200 J10 F11
FB_A1_SEN SEN DQ14 FB_A1_DQ<14>
BI 74 96
FB_A0_SEN SEN DQ14 FB_A0_DQ<14> BI 74 96
J2 M13
120 FBA 1 J2 F13 1 1 96 74 IN FB_A1_RESET_L RESET* DQ15 FB_A1_DQ<15> BI 74 96
1% R9204 1 96 74 IN FB_A0_RESET_L RESET* DQ15 FB_A0_DQ<15>
BI 74 96
R9250 R9253 A11
1/20W R9203 U11 DQ16 FB_A1_DQ<16> BI 74 96
MF 120 FBA DQ16 FB_A0_DQ<16> BI 74 96 120 120
201 2 1% 120 FBA 1% 1% 96 74 FB_A1_ABI_L J4 ABI* DQ17 A13 FB_A1_DQ<17> 74 96
J4 ABI* U13 IN BI
1/20W 1% 96 74 IN FB_A0_ABI_L DQ17 FB_A0_DQ<17> BI 74 96 1/20W 1/20W
B11
MF 1/20W
T11 MF MF DQ18 FB_A1_DQ<18> BI 74 96
201 2 MF DQ18 FB_A0_DQ<18> BI 74 96 201 201
R2 B13
201
2 C2 T13 FBA 2 FBA 2 96 74 BI FB_A1_EDC<0> EDC0 DQ19 FB_A1_DQ<19> BI 74 96
96 74 BI FB_A0_EDC<0> EDC0 DQ19 FB_A0_DQ<19> BI 74 96
R13 E11
C13 N11 96 74 BI FB_A1_EDC<1> EDC1 DQ20 FB_A1_DQ<20> BI 74 96
C13 E13
R13 N13 96 74 BI FB_A1_EDC<2> EDC2 DQ21 FB_A1_DQ<21> BI 74 96
C2 F11
R2 M11 96 74 BI FB_A1_EDC<3> EDC3 DQ22 FB_A1_DQ<22> BI 74 96
F13
M13 DQ23 FB_A1_DQ<23> BI 74 96
DQ23 FB_A0_DQ<23>
BI 74 96
A4
U4 DQ24 FB_A1_DQ<24> BI 74 96
DQ24 FB_A0_DQ<24> BI 74 96
P4 WCK01 A2
CK TERMINATION - A1 PLACE_NEAR=U9250.J11:8MM
D4 WCK01 U2 96 74 IN FB_A1_WCLK_P<0> DQ25 FB_A1_DQ<25>
BI 74 96
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE 96 74 IN FB_A0_WCLK_P<0> DQ25 FB_A0_DQ<25> BI 74 96
P5 WCK01* B4
R9251 R9252 D5 WCK01* T4 96 74 IN FB_A1_WCLK_N<0> DQ26 FB_A1_DQ<26> BI 74 96
96 74 IN FB_A0_WCLK_N<0> DQ26 FB_A0_DQ<26>
BI 74 96
B2
96
FB_A1_CLK_P 40.2 FBA1_CK_MID 40.2 FB_A1_CLK_N 96 T2 DQ27 FB_A1_DQ<27> BI 74 96
74 1 2 1 2 74 DQ27 FB_A0_DQ<27> 74 96
C
BI D4 WCK23 E4
C 75
FBA 1%
1/20W
MF
1%
1/20W
MF
FBA
75
96 74
96 74
IN FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>
P4 WCK23
P5 WCK23*
DQ28
DQ29
N4
N2
FB_A0_DQ<28>
FB_A0_DQ<29>
BI 74 96
74 96
96 74
96 74
IN
IN
FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1> D5 WCK23*
DQ28
DQ29 E2
FB_A1_DQ<28>
FB_A1_DQ<29>
BI
BI
74 96
74 96
IN BI F4
201
1
FBA 201
M4 DQ30 FB_A1_DQ<30> BI 74 96
PLACE_NEAR=U9250.J12:8MM C9291 DQ30 FB_A0_DQ<30> BI 74 96
F2
0.01UF M2 DQ31 FB_A1_DQ<31> BI 74 96
10%
DQ31 FB_A0_DQ<31> BI 74 96
10V
2 X5R-CERM
0201
U9200 NC A5
U9250 NC A5 NC
PLACE_NEAR=U9250.J12:8MM NC 32MX32-1.5GHZ-MFH A12/RFU/NC J5 FB_A1_A<8>
32MX32-1.5GHZ-MFL A12/RFU/NC J5 FB_A0_A<8>
IN 74 96
BGA NC U5
IN 74 96
BGA NC U5 K4G10325FG-HC03 NC
K4G10325FG-HC03 NC
=PP1V35_GPU_FBVDDQ C5 (2 OF 2) B5
80 76 75 73
75 73 =PP1V35_GPU_FBVDDQ C5 B5
80 76 (2 OF 2) L11 L5
C10 B10
80 76 75 73 =PP1V35_GPU_FBVDDQ L14 L10 80 76 75 73 =PP1V35_GPU_FBVDDQ
D11 D10 FBA FBA FBA
FBA FBA FBA 1
C9250 1
C9251 1
C9252 P11 P10
1 1 1 G1 G5
1 FBA
C9200 C9201 C9202 4.7UF 4.7UF 4.7UF R5 T5 1
FBA
4.7UF 4.7UF 4.7UF G4 G10 R9230 20% 20% 20% R9280
20% 20% 20% 549 2
6.3V
2
6.3V
2
6.3V R10 T10 549
2
6.3V
2
6.3V
2
6.3V G11 H1 1%
X5R-CERM1 X5R-CERM1 X5R-CERM1
MIN_LINE_WIDTH=0.25 MM 1% PLACE_NEAR=U9250.J14:8MM
MIN_LINE_WIDTH=0.25 MM 1/20W
402 402 402 C10 B10 MIN_NECK_WIDTH=0.1 mm 1/20W
402 402 402 G14 H14 MIN_NECK_WIDTH=0.1 mm MF MF
VDD VSS 201 D11 VSS D10 201
L1 K1 2 VDD 2
G1 G5
L4 K14
FB_A0_VREFC FBA FBA FBA G4 G10 FB_A1_VREFC
FBA FBA FBA L11 L5 75
1
C9253 1
C9254 1
C9255 75
1
C9203 1
C9204 1
C9205 G11 OMIT_TABLE H1 PLACE_NEAR=U9250.J14:8MM
L14 L10 PLACE_NEAR=U9200.J14:8MM
4.7UF 4.7UF 4.7UF
4.7UF 4.7UF 4.7UF 20% 20% 20% G14 H14 FBA
20% 20% 20% P11 P10 2
6.3V
2
6.3V
2
6.3V FBA PLACE_NEAR=U9250.J14:8MM
2
6.3V
2
6.3V
2
6.3V
FBA 1 PLACE_NEAR=U9200.J14:8MM
X5R-CERM1 X5R-CERM1 X5R-CERM1 L1 K1 FBA 1
X5R-CERM1 X5R-CERM1 X5R-CERM1 R5 T5 1
C9231 R9231 1 402 402 402 1
C9281 R9281 1
402 402 402
1.33K R9234 L4 K14 1.33K R9284
R10 T10 820PF 1% 931 820PF 1% 931
10% 10%
50V 1/20W 1% 50V 1/20W 1%
2 MF 1/20W 2 MF 1/20W
OMIT_TABLE CERM
201 MF B1 CERM
201 MF
B1 0402 2 FBA FBA FBA FBA 0402 2
FBA 2 201 1 1 1 1 E10 2 201
1
FBA 1
FBA 1
FBA 1
FBA B3 PLACE_NEAR=U9200.J14:8MM FBA C9256 C9257 C9258 C9259
C9206 C9207 C9208 C9209 1.0UF 1.0UF 1.0UF 1.0UF F1
FB_SW_LEG FB_SW_LEG
B 2
1.0UF
20%
6.3V
X5R 2
1.0UF
20%
6.3V
X5R 2
1.0UF
20%
6.3V
X5R 2
1.0UF
20%
6.3V
X5R
B12
B14
IN 74 75 76
2
20%
6.3V
X5R
0201-1
2
20%
6.3V
X5R
0201-1
2
20%
6.3V
X5R
0201-1
2
20%
6.3V
X5R
0201-1
F3
F12 A1
IN 74 75 76
B
0201-1 0201-1 0201-1 0201-1 D1 A1
F14 C14 PLACE CLOSE TO U9250
D3 A3
G2 E1
D12 A12
FBA FBA FBA FBA G13 E3 =PP1V35_GPU_FBVDDQ
FBA FBA FBA FBA D14 A14 PLACE CLOSE TO U9200 1 C9260 1 C9261 1 C9262 1 C9263 80 76 75 73
1
C9210 1
C9211 1
C9212 1
C9213 H3 E12
E5 C1 1.0UF 1.0UF 1.0UF 1.0UF
1.0UF 1.0UF 1.0UF 1.0UF 20% 20% 20% 20% H12 E14
20% 20% 20% 20% E10 C3 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V X5R X5R X5R X5R K3 F5
X5R X5R X5R X5R F1 C4 0201-1 0201-1 0201-1 0201-1 FBA
0201-1 0201-1 0201-1 0201-1 B3 F10 PLACE_NEAR=U9250.A10:14MM
F3 C11 MIN_LINE_WIDTH=0.25 MM
K12 H2 1 R9282
F12 C12 MIN_NECK_WIDTH=0.1 mm
=PP1V35_GPU_FBVDDQ
80 76 75 73
L2 H13 549
F14 C14 1%
FBA FBA FBA FBA L13 K2 1/20W
FBA FBA FBA FBA G2 E1 1 C9264 1 C9265 1
C9266 1
C9267 MF
1 C9214 1 C9215 1 C9216 1 C9217 M1 A3 FB_A1_VREFD 201
G13 E3 FBA 1.0UF 1.0UF 0.1UF 0.1UF VDDQ 75
2
1.0UF 1.0UF 0.1UF 0.1UF VDDQ 20% 20% 10% 10% M3 K13
20% 20% 10% 10% H3 E12 PLACE_NEAR=U9200.A10:8MM
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
X5R X5R CERM-X5R CERM-X5R M12 M5 PLACE_NEAR=U9250.A10:14MM
X5R X5R CERM-X5R CERM-X5R H12 E14 1 R9232 0201-1 0201-1 0201 0201
0201-1 0201-1 0201 0201 M14 M10
K3 F5 549
1% N5 N1
K12 F10 1/20W PLACE_NEAR=U9250.A10:15MM
MF N10 N3 1
L2 VSSQ H2 FB_A0_VREFD R9283 1
75
2 201 FBA FBA FBA FBA P1 N12 PLACE_NEAR=U9250.A10:14MM
1 C9282 1 C9283 1.33K R9285
FBA FBA FBA FBA L13 H13 1
C9268 1
C9269 1
C9270 1
C9271 1% 931
1 C9218 1 C9219 1 C9220 1 C9221 B12 N14 820PF 820PF 1/20W 1%
M1 K2 0.1UF 0.1UF 0.1UF 0.1UF VSSQ 10% 10% MF 1/20W
0.1UF 0.1UF 0.1UF 0.1UF 10% 10% 10% 10% P3 R1 2
25V
2
25V
201 MF
10% 10% 10% 10% M3 K13 2
6.3V
2
6.3V
2
6.3V
2
6.3V X7R-CERM X7R-CERM 2 201
2
6.3V
2
6.3V
2
6.3V
2
6.3V CERM-X5R CERM-X5R CERM-X5R CERM-X5R P12 R3 0201 0201 FBA 2 FBA
CERM-X5R CERM-X5R CERM-X5R CERM-X5R M12 M5 0201 0201 0201 0201 FBA FBA
0201 0201 0201 0201
FBA FBA P14 R4 FB_SW_LEG 74 75 76
M14 M10 1
PLACE_NEAR=U9200.A10:8MM IN
FBA R9233 1 T1 A12 PLACE_NEAR=U9250.A10:14MM
N5 N1 1 1 FBA R9235
C9232 C9233 1.33K T3 R11
N10 N3 820PF 820PF 1% 931
1/20W 1%
T12 R12
A
10% 10%
FBA FBA FBA FBA
1 FBA
C9222
0.1UF
1 FBA
C9223
0.1UF
1 FBA
C9224
0.1UF
1 FBA
C9225
0.1UF
P1
P3
N12
N14
2
25V
X7R-CERM
0201
2
25V
X7R-CERM
0201
MF
2 201
2
1/20W
MF
201
1
C9272
0.1UF
1
C9273
0.1UF
1
C9274
0.1UF
1
C9275
0.1UF
T14 R14 SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013 A
10% 10% 10% 10% B14 U1 PAGE TITLE
2
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
P12
P14
R1
R3 PLACE_NEAR=U9200.A10:14MM PLACE_NEAR=U9200.A10:8MM
FB_SW_LEG IN 74 75
76
2
6.3V
CERM-X5R
0201
2
6.3V
CERM-X5R
0201
2
6.3V
CERM-X5R
0201
2
6.3V
CERM-X5R
0201
D1
D3
U3
U12
GDDR5 Frame Buffer A
T1 R4 DRAWING NUMBER SIZE
T3 R11
PLACE_NEAR=U9200.A10:8MM
D12 U14
D14 A14 REVISION
T12 R12
T14 R14
E5 C1 R
13.0.0
C3 NOTICE OF PROPRIETARY PROPERTY: BRANCH
U1
75 FB_A1_VREFC J14 VREFC C4 THE INFORMATION CONTAINED HEREIN IS THE
75 FB_A0_VREFC J14 VREFC U3 PROPRIETARY PROPERTY OF APPLE INC.
75 FB_A1_VREFD A10 C11 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
FB_A0_VREFD A10 U12
75
U10 VREFD U14
U10 VREFD C12 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
92 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
U9300 U9350
This memory device is in Mirrored Mode. 32MX32-1.5GHZ-MFH
- =PP1V5R1V35_S0_FB_VDD 32MX32-1.5GHZ-MFL BGA
BGA K4G10325FG-HC03
Signal aliases required by this page: K4G10325FG-HC03
K11 (1 OF 2) P13
(NONE)
H11 D2 96 74 IN FB_B1_A<2> BA0/A2 DBI1* FB_B1_DBI_L<1>
BI 74 96
96 74 IN FB_B0_A<2> BA0/A2 DBI0* FB_B0_DBI_L<0> BI 74 96
H10 D13
K10 (1 OF 2) D13 96 74 IN FB_B1_A<5> BA1/A5 DBI2* FB_B1_DBI_L<2> BI 74 96
BOM options provided by this page: 96 74 IN FB_B0_A<5> BA1/A5 DBI1* FB_B0_DBI_L<1> BI 74 96
H11 P2
K11 P13 96 74 IN FB_B1_A<4> BA2/A4 DBI0* FB_B1_DBI_L<0> BI 74 96
(NONE) 96 74 IN FB_B0_A<4> BA2/A4 DBI2* FB_B0_DBI_L<2> BI 74 96
K10 D2
H10 P2 96 74 IN FB_B1_A<3> BA3/A3 DBI3* FB_B1_DBI_L<3> BI 74 96
96 74 IN FB_B0_A<3> BA3/A3 DBI3* FB_B0_DBI_L<3> BI 74 96
96 74 IN FB_B1_A<7> H4 A8/A7 DQ0 U4 FB_B1_DQ<0> BI 74 96

CK TERMINATION - B0 96 74 FB_B0_A<7> K4 A8/A7 DQ0 A4 FB_B0_DQ<0> 74 96
PLACE_NEAR=U9300.J11:8MM IN BI K5 U2
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE FB_B1_A<1> A9/A1 DQ1 FB_B1_DQ<1>
D FB_B0_CLK_P
R9301
40.2 FBB0_CK_MID
R9302
40.2 FB_B0_CLK_N
96 74
96 74
IN
IN
FB_B0_A<1>
FB_B0_A<0>
H5
H4
A9/A1
A10/A0
DQ1
DQ2
A2
B4
FB_B0_DQ<1>
FB_B0_DQ<2>
BI
BI
74 96
74 96
96 74
96 74
IN
IN FB_B1_A<0> K4
H5
A10/A0 DQ2 T4
T2
FB_B1_DQ<2>
BI
BI
74 96
74 96 D
76 74 1 2 1 2 74 76 96
K5 B2 96 74 IN FB_B1_A<6> A11/A6 DQ3 FB_B1_DQ<3>
BI 74 96
96 96 74 IN FB_B0_A<6> A11/A6 DQ3 FB_B0_DQ<3> BI 74 96
J3 N4
FBB 1% 1%
FBB J3 E4 96 74 IN FB_B1_CKE_L CKE* DQ4 FB_B1_DQ<4> BI 74 96
1/20W 1/20W 96 74 IN FB_B0_CKE_L CKE* DQ4 FB_B0_DQ<4>
BI 74 96
80 76 75 73 =PP1V35_GPU_FBVDDQ OMIT_TABLE N2
MF FBB MF OMIT_TABLE E2 DQ5 FB_B1_DQ<5> BI 74 96
201
1
201 DQ5 FB_B0_DQ<5> BI 74 96
J12 M4
PLACE_NEAR=U9300.J12:8MM C9390 J12 F4 96 76 74 IN FB_B1_CLK_P CK DQ6 FB_B1_DQ<6>
BI 74 96
0.01UF 96 76 74 IN FB_B0_CLK_P CK DQ6 FB_B0_DQ<6> BI 74 96
J11 M2
10% J11 F2 1 96 76 74 IN FB_B1_CLK_N CK* DQ7 FB_B1_DQ<7> BI 74 96
96 76 74 IN FB_B0_CLK_N CK* DQ7 FB_B0_DQ<7> BI 74 96 R9354
2
10V FB_B1_CS_L L12 CS* DQ8 U11 FB_B1_DQ<8>
X5R-CERM
96 74 FB_B0_CS_L G12 CS* DQ8 A11 FB_B0_DQ<8> 74 96
1K 96 74 IN BI 74 96
0201 IN BI 5% G12 U13
L12 A13 1/20W 96 74 IN FB_B1_WE_L WE* DQ9 FB_B1_DQ<9> BI 74 96
96 74 IN FB_B0_WE_L WE* DQ9 FB_B0_DQ<9> BI 74 96
MF G3 T11
L3 B11 201 96 74 IN FB_B1_CAS_L CAS* DQ10 FB_B1_DQ<10> BI 74 96
96 74 IN FB_B0_CAS_L CAS* DQ10 FB_B0_DQ<10> BI 74 96 2
L3 T13
G3 B13 FBB 96 74 IN FB_B1_RAS_L RAS* DQ11 FB_B1_DQ<11> BI 74 96
96 74 IN FB_B0_RAS_L RAS* DQ11 FB_B0_DQ<11> BI 74 96
J13 N11
J13 E11
FB_B1_ZQ ZQ DQ12 FB_B1_DQ<12> BI 74 96
FB_B0_ZQ ZQ DQ12 FB_B0_DQ<12>
BI 74 96
J1 N13
FBB J1 E13
FB_B1_MF MF (MF=1) DQ13 FB_B1_DQ<13> BI 74 96
1
FB_B0_MF MF (MF=0) DQ13 FB_B0_DQ<13> BI 74 96
J10 M11
R9300 J10 F11
FB_B1_SEN SEN DQ14 FB_B1_DQ<14>
BI 74 96
FBB FB_B0_SEN SEN DQ14 FB_B0_DQ<14> BI 74 96
J2 M13
120 1 J2 F13 1 1 96 74 IN FB_B1_RESET_L RESET* DQ15 FB_B1_DQ<15> BI 74 96
1% R9304 FBB 1
96 74 IN FB_B0_RESET_L RESET* DQ15 FB_B0_DQ<15>
BI 74 96
R9350 R9353 A11
1/20W R9303 U11 DQ16 FB_B1_DQ<16> BI 74 96
MF 120 DQ16 FB_B0_DQ<16> BI 74 96 120 120
201 2 1% 120 1% 1% 96 74 FB_B1_ABI_L J4 ABI* DQ17 A13 FB_B1_DQ<17> 74 96
J4 ABI* U13 IN BI
1/20W 1% 96 74 IN FB_B0_ABI_L DQ17 FB_B0_DQ<17> BI 74 96 1/20W 1/20W
B11
MF 1/20W
T11 MF MF DQ18 FB_B1_DQ<18> BI 74 96
201 2 MF DQ18 FB_B0_DQ<18> BI 74 96 201 201
R2 B13
201
2 C2 T13 FBB 2 FBB 2 96 74 BI FB_B1_EDC<0> EDC0 DQ19 FB_B1_DQ<19> BI 74 96
96 74 BI FB_B0_EDC<0> EDC0 DQ19 FB_B0_DQ<19> BI 74 96
R13 E11
C13 N11 96 74 BI FB_B1_EDC<1> EDC1 DQ20 FB_B1_DQ<20> BI 74 96
C13 E13
R13 N13 96 74 BI FB_B1_EDC<2> EDC2 DQ21 FB_B1_DQ<21> BI 74 96
C2 F11
R2 M11 96 74 BI FB_B1_EDC<3> EDC3 DQ22 FB_B1_DQ<22> BI 74 96
F13
M13 DQ23 FB_B1_DQ<23> BI 74 96
DQ23 FB_B0_DQ<23>
BI 74 96
A4
U4 DQ24 FB_B1_DQ<24> BI 74 96
DQ24 FB_B0_DQ<24> BI 74 96
P4 WCK01 A2
CK TERMINATION - B1 PLACE_NEAR=U9350.J11:8MM
D4 WCK01 U2 96 74 IN FB_B1_WCLK_P<0> DQ25 FB_B1_DQ<25>
BI 74 96
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE 96 74 IN FB_B0_WCLK_P<0> DQ25 FB_B0_DQ<25> BI 74 96
P5 WCK01* B4
R9351 R9352 D5 WCK01* T4 96 74 IN FB_B1_WCLK_N<0> DQ26 FB_B1_DQ<26> BI 74 96
96 74 IN FB_B0_WCLK_N<0> DQ26 FB_B0_DQ<26>
BI 74 96
B2
96
FB_B1_CLK_P 40.2 FBB1_CK_MID 40.2 FB_B1_CLK_N 96 T2 DQ27 FB_B1_DQ<27> BI 74 96
74 1 2 1 2 74 DQ27 FB_B0_DQ<27> 74 96
C
BI D4 WCK23 E4
C 76
FBB 1%
1/20W
MF
1%
1/20W
MF
FBB
76
96 74
96 74
IN FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>
P4 WCK23
P5 WCK23*
DQ28
DQ29
N4
N2
FB_B0_DQ<28>
FB_B0_DQ<29>
BI 74 96
74 96
96 74
96 74
IN
IN
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1> D5 WCK23*
DQ28
DQ29 E2
FB_B1_DQ<28>
FB_B1_DQ<29>
BI
BI
74 96
74 96
IN BI F4
201
1
FBB 201
M4 DQ30 FB_B1_DQ<30> BI 74 96
C9391 DQ30 FB_B0_DQ<30> BI 74 96
F2
0.01UF M2 DQ31 FB_B1_DQ<31> BI 74 96
10%
DQ31 FB_B0_DQ<31> BI 74 96
10V
2 X5R-CERM
0201
U9300 NC A5
U9350 NC A5 NC
NC 32MX32-1.5GHZ-MFH A12/RFU/NC J5 FB_B1_A<8>
32MX32-1.5GHZ-MFL A12/RFU/NC J5 FB_B0_A<8>
IN 74 96
BGA NC U5
IN 74 96
BGA NC U5 K4G10325FG-HC03 NC
K4G10325FG-HC03 NC
=PP1V35_GPU_FBVDDQ C5 (2 OF 2) B5
80 76 75 73
75 73 =PP1V35_GPU_FBVDDQ C5 B5
80 76 (2 OF 2) L11 L5
C10 B10 80 76 75 73 =PP1V35_GPU_FBVDDQ
L14 L10
D11 D10 80 76 75 73 =PP1V35_GPU_FBVDDQ FBB FBB FBB FBB
FBB FBB FBB 1
C9350 1
C9351 1
C9352 P11 P10
1
C9300 1
C9301 1
C9302 G1 G5 FBB 1
4.7UF 4.7UF 4.7UF R5 T5 R9380
4.7UF 4.7UF 4.7UF G4 G10 1 20% 20% 20%
MIN_LINE_WIDTH=0.25 MM 549
20% 20% 20% R9330 2
6.3V
2
6.3V
2
6.3V R10 T10 1%
2
6.3V
2
6.3V
2
6.3V G11 H1 549 PLACE_NEAR=U9300.J14:8MM
1/20W
1%
402 402 402 C10 B10 MF
402 402 402 G14 H14 1/20W
VDD VSS MIN_LINE_WIDTH=0.25 MM
D11 VSS D10 2 201
MIN_NECK_WIDTH=0.1 mm MF
L1 K1 VDD
2 201 G1 G5
L4 K14 FB_B1_VREFC
FBB FBB FBB G4 G10 76
FBB FBB FBB L11 L5 FB_B0_VREFC 1
C9353 1
C9354 1
C9355 PLACE_NEAR=U9350.J14:14MM
1
C9303 1
C9304 1
C9305 OMIT_TABLE 76 G11 H1
L14 L10 FBB 4.7UF 4.7UF 4.7UF
4.7UF 4.7UF 4.7UF 20% 20% 20% G14 H14 FBB FBB
20% 20% 20% P11 P10 6.3V 6.3V 6.3V 1
2
6.3V
2
6.3V
2
6.3V PLACE_NEAR=U9300.J14:8MM 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 L1 K1 1 FBB
C9381 R9381 1
X5R-CERM1 X5R-CERM1 X5R-CERM1 R5 T5 FBB 1
FBB 402 402 402
1.33K R9384
402 402 402 1
C9331 R9331 1
R9334
L4 K14 820PF 1% 931 PLACE_NEAR=U9350.J14:14MM
R10 T10 1.33K 10% 1/20W 1%
820PF 1% 931 OMIT_TABLE 50V
2 CERM MF 1/20W
10%
1/20W 1% 0402 2 201 MF
2
50V
MF 1/20W B1 201
B1 CERM
FBB FBB FBB FBB 2
0402 2 201 MF
1 1 1 1 E10 PLACE_NEAR=U9350.J14:14MM
1
FBB 1
FBB 1
FBB 1
FBB B3 2 201 C9356 C9357 C9358 C9359
C9306 C9307 C9308 C9309 PLACE_NEAR=U9300.J14:8MM
1.0UF 1.0UF 1.0UF 1.0UF F1
FB_SW_LEG IN 74 75 76
B 2
1.0UF
20%
6.3V
X5R 2
1.0UF
20%
6.3V
X5R 2
1.0UF
20%
6.3V
X5R 2
1.0UF
20%
6.3V
X5R
B12
B14 PLACE_NEAR=U9300.J14:8MM
FB_SW_LEG IN 74 75 76
2
20%
6.3V
X5R
0201-1
2
20%
6.3V
X5R
0201-1
2
20%
6.3V
X5R
0201-1
2
20%
6.3V
X5R
0201-1
F3
F12 A1
B
0201-1 0201-1 0201-1 0201-1 D1 A1
F14 C14 PLACE CLOSE TO U9350
D3 A3
G2 E1
D12 A12 PLACE CLOSE TO U9300
FBB FBB FBB FBB G13 E3
FBB FBB FBB FBB D14 A14 1
C9360 1
C9361 1
C9362 1
C9363 =PP1V35_GPU_FBVDDQ
1
C9310 1
C9311 1
C9312 1
C9313 H3 E12 80 76 75 73
E5 C1 1.0UF 1.0UF 1.0UF 1.0UF
1.0UF 1.0UF 1.0UF 1.0UF =PP1V35_GPU_FBVDDQ 20% 20% 20% 20% H12 E14
20% 20% 20% 20% E10 C3 80 76 75 73 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V X5R X5R X5R X5R K3 F5
X5R X5R X5R X5R F1 C4 0201-1 0201-1 0201-1 0201-1
0201-1 0201-1 0201-1 0201-1 B3 F10
F3 C11 FBB
K12 H2
F12 C12 1
FBB L2 H13 R9382
F14 C14 MIN_LINE_WIDTH=0.25 MM 549 PLACE_NEAR=U9350.A10:14MM
1
FBB FBB FBB FBB L13 K2 MIN_LINE_WIDTH=0.25 MM 1%
FBB FBB FBB FBB G2 E1 R9332 1
C9364 1
C9365 1
C9366 1
C9367 1/20W
1 C9314 1 C9315 1 C9316 1 C9317 549 M1 A3 MF
G13 E3 1%
1.0UF 1.0UF 0.1UF 0.1UF VDDQ 201
1.0UF 1.0UF 0.1UF 0.1UF VDDQ 1/20W
20% 20% 10% 10% M3 K13 76 FB_B1_VREFD 2
20% 20% 10% 10% H3 E12 MF 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V FB_B0_VREFD X5R X5R CERM-X5R CERM-X5R M12 M5
X5R X5R CERM-X5R CERM-X5R H12 E14 2 201 0201-1 0201-1 0201 0201
76 PLACE_NEAR=U9350.A10:14MM
0201-1 0201-1 0201 0201 M14 M10
K3 F5
N5 N1
K12 F10
N10 N3 FBB FBB
L2 VSSQ H2 FBB 1
FBB FBB FBB FBB FBB P1 N12 FBB R9383 1
FBB FBB FBB FBB L13 H13 1
C9368 1
C9369 1
C9370 1
C9371 1
C9382 1
C9383 1.33K R9385
1 C9318 1 C9319 1 C9320 1 C9321 FBB 1
FBB B12 N14 1% 931
M1 K2 FBB R9333 1 0.1UF 0.1UF 0.1UF 0.1UF VSSQ 820PF 820PF 1/20W 1%
0.1UF 0.1UF 0.1UF 0.1UF 1

C9332 1
C9333 1.33K R9335 10% 10% 10% 10% P3 R1 10% 10%
MF 1/20W
10% 10% 10% 10% M3 K13 1% 931 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
25V
2
25V
201 MF
2
6.3V
2
6.3V
2
6.3V
2
6.3V 820PF 820PF 1/20W 1%
PLACE_NEAR=U9300.A10:14MM CERM-X5R CERM-X5R CERM-X5R CERM-X5R P12 R3 PLACE_NEAR=U9350.A10:14MM X7R-CERM X7R-CERM 2
CERM-X5R CERM-X5R CERM-X5R CERM-X5R M12 M5 10% 10% MF 1/20W
0201 0201 0201 0201 0201 0201 2 201
0201 0201 0201 0201
2
25V
2
25V
201 MF P14 R4
M14 M10 X7R-CERM X7R-CERM 2 FB_SW_LEG
0201 0201 2 201 T1 A12 IN 74 75 76
N5 N1
FB_SW_LEG OUT 74 75 76
T3 R11
N10 N3 PLACE_NEAR=U9300.A10:15MM PLACE_NEAR=U9300.A10:14MM PLACE_NEAR=U9300.A10:14MM
T12 R12
A 1 FBB
C9322 1 FBB
C9323 1 FBB
C9324 1 FBB
C9325
P1
P3
N12
N14
1 FBB
C9372
0.1UF
1 FBB
C9373
0.1UF
1 FBB
C9374
0.1UF
1 FBB
C9375
0.1UF
T14 R14 SYNC_MASTER=J16_DG SYNC_DATE=04/21/2013 A
0.1UF 0.1UF 0.1UF 0.1UF 10% 10% 10% 10% B14 U1 PAGE TITLE
2
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
2
10%
6.3V
CERM-X5R
0201
P12
P14
R1
R3
2
6.3V
CERM-X5R
0201
2
6.3V
CERM-X5R
0201
2
6.3V
CERM-X5R
0201
2
6.3V
CERM-X5R
0201
D1
D3
U3
U12
GDDR5 Frame Buffer B
T1 R4 DRAWING NUMBER SIZE
T3 R11
D12 U14
D14 A14 REVISION
T12 R12
T14 R14
E5 C1 R
13.0.0
C3 NOTICE OF PROPRIETARY PROPERTY: BRANCH
U1
76 FB_B1_VREFC J14 VREFC C4 THE INFORMATION CONTAINED HEREIN IS THE
76 FB_B0_VREFC J14 VREFC U3 PROPRIETARY PROPERTY OF APPLE INC.
76 FB_B1_VREFD A10 C11 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
FB_B0_VREFD A10 U12
76
U10 VREFD U14
U10 VREFD C12 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
93 OF 123
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU_IFPA_IOVDD GPU_IFPB_IOVDD GPU_IFPC_IOVDD GPU_TESTMODE
PD FOR AUX CHANNELS (FOR NVIDIA) DISABLE PHYs A, B & C FOR K70 77 77 77 77 Page Notes
95 77 41 DP_INT_EG_AUX_P Power aliases required by this page:
DP_INT_EG_AUX_N 1 1 1 1
95 77 41
R9601 R9602 R9603 R9608 - =PP3V3_GPU_IFPB_IOVDD - =PP1V05_GPU_IFPCD_IOVDD
10K 10K 10K 10K - =PP1V8_GPU_IFPA_IOVDD - =PP1V05_GPU_IFPEF_IOVDD
1 1
OMIT_TABLE 1% 1% 1% 1%
DP_TBTSNK0_EG_AUXCH_P 77
R9614 R9613 CRITICAL
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
- =PP1V8_GPU_DPLL - =PP3V3_GPU_VDD33
100K 100K 201 201 201 201 - =PP1V05_GPU_DPLL

DP_TBTSNK0_EG_AUXCH_N 2 2 2 2
77 1% 1%
1/20W
MF
1/20W
MF
U8700 - =PP3V3_GPU_IFPX_PLLVDD
2
201
2
201 NV-GK107 Signal aliases required by this page:
1 1 BGA
R9615 R9616 (5 OF 10) (NONE)
100K 100K GPU_IFPA_IOVDD AG8 AM6 PD FOR RSET
1% 1% 77 IFPA_IOVDD IFPA_TXC NC
D 2
1/20W
MF
201
2
1/20W
MF
201
77
77
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
77
77
GPU_IFPB_IOVDD
GPU_IFPC_IOVDD
AG9
AF6
IFPB_IOVDD
IFPC_IOVDD
IFPA_TXC* AN6
AP3
NC
GPU_IFPAB_PLLVDD
77
GPU_IFPX_PLLVDD
77
IFPD_RSET
77
IFPEF_RSET
77
- J31:YES D
PP1V05_GPU_IFPD_IOVDD AG6 IFPA_TXD0 NC PLACE_NEAR=U8700.AN2:5MM PLACE_NEAR=U8700.AD6:5MM - J5:YES
77 IFPD_IOVDD AN3 1 1 1 1
PP1V05_GPU_IFPEF_IOVDD AC7 IFPA_TXD0* NC R9604 R9619 R9606 R9607
1 1
77 IFPE_IOVDD AN5
R9617 R9618 PP1V05_GPU_IFPEF_IOVDD AC8 IFPA_TXD1 NC 10K 10K 1K 1K
77 IFPF_IOVDD AM5 1% 1% 1% 1%
100K 100K IFPA_TXD1* NC 1/20W 1/20W 1/20W 1/20W
1% 1% MF MF MF MF
AH8 AL6
1/20W 1/20W 77 GPU_IFPAB_PLLVDD IFPAB_PLLVDD IFPA_TXD2 NC 2
201
2
201
2
201
2
201
MF MF
AJ8 AK6
2
201
2
201
NC IFPAB_RSET IFPA_TXD2* NC
AJ6
AF7 IFPA_TXD3 NC
77 GPU_IFPX_PLLVDD IFPC_PLLVDD AH6
AF8 IFPA_TXD3* NC
NC IFPC_RSET
AJ9
PP3V3_GPU_IFPX_PLLVDD AG7 IFPB_TXC NC
80 79 78 77 72 =PP3V3_GPU_VDD33 77 IFPD_PLLVDD AH9
IFPD_RSET AN2 IFPB_TXC* NC PP1V05_GPU_SP_PLLVDD PP1V05_GPU_VID_PLLVDD
77 IFPD_RSET 79 77 77
1 1 AP6 MAKE_BASE=TRUE
R9625 R9626 PP3V3_GPU_IFPX_PLLVDD AB8 IFPB_TXD4 NC
100K 100K 77 IFPEF_PLLVDD AP5 77 DP_TBTSNK0_EG_AUXCH_P DP_TBTSNK0_AUXCH_C_P 26 95
IFPEF_RSET AD6 IFPB_TXD4* NC MAKE_BASE=TRUE
5% 5%
77 IFPEF_RSET AM7 77 DP_TBTSNK0_EG_AUXCH_N DP_TBTSNK0_AUXCH_C_N 26 95
1/20W 1/20W
IFPB_TXD5 NC MAKE_BASE=TRUE
NOSTUFF MF MF
AL7
2
201
2
201
IFPB_TXD5* NC
80 79 78 77 72 =PP3V3_GPU_VDD33 NOSTUFF AN8 77 DP_TBTSNK1_EG_AUXCH_P DP_TBTSNK1_AUXCH_C_P 26 95
IFPB_TXD6 NC MAKE_BASE=TRUE
R4 AM8 77 DP_TBTSNK1_EG_AUXCH_N DP_TBTSNK1_AUXCH_C_N 26 95
1 1
31 OUT DP_TBTSNK0_DDC_CLK I2CA_SCL IFPB_TXD6* NC MAKE_BASE=TRUE
R9624 R9623 DP_TBTSNK0_DDC_DATA R5
I2CA_SDA IFPB_TXD7 AK8
4.7K 4.7K
31 BI NC
AL8
1% 1% R9629 R9630 IFPB_TXD7* NC OMIT_TABLE
1/20W 1/20W
100K 100K
MF MF 1 2 1 2 AG3
2
201
2
201 5% MF 5% MF IFPC_AUX_I2CW_SCL NC U8700
1/20W 201 1/20W 201 AG2
IFPC_AUX_I2CW_SDA* NC NV-GK107
R2 Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other
BGA
GPU_SSC_SMB_CLK I2CC_SCL AK1
R3 IFPC_L0 NC 80 77 =PP3V3_GPU_MISC (6 OF 10)
GPU_SSC_SMB_DAT I2CC_SDA AJ1 J8 P6
IFPC_L0* NC GPIO0 GPU_GPIO_0
BI 78
AJ3 K8 M3
IFPC_L1 NC GPIO1 GPU_GPIO_1 BI 78
80 79 78 77 72 =PP3V3_GPU_VDD33
C DDC MAPPING
---------------------
IFPC_L1*
IFPC_L2
AJ2
AH3
NC
NC
L8
M8
VDD33 GPIO2
GPIO3
L6
P5
GPU_GPIO_2
GPU_GPIO_3
BI
BI
78
78
C
T4 AH4 P7
I2CA -> IFPE DDC 96 78 OUT GPU_SMB_CLK I2CS_SCL IFPC_L2* NC GPIO4 GPU_GPIO_4
BI 78
T3 AG5 H6 L7
I2CB -> IFPF DDC 96 78 BI GPU_SMB_DAT I2CS_SDA IFPC_L3 NC NC ROM_CS* GPIO5 GPU_GPIO_5
BI 78
AG4 H4 M7
I2CC -> Not used IFPC_L3* NC 96 78 OUT GPU_ROM_SCLK ROM_SCLK GPIO6 GPU_GPIO_6
BI 78
(was ext SSC cntl) H5 N8
80 79 78 77 72 =PP3V3_GPU_VDD33 AK3 96 78 IN GPU_ROM_SI ROM_SI GPIO7 GPU_GPIO_7
BI 78
IFPD_AUX_I2CX_SCL DP_INT_EG_AUX_P BI 41 77 95 H7 M1
AK2 PLACE_NEAR=U8700.J1:5MM 96 78 OUT GPU_ROM_SO ROM_SO GPIO8 GPU_GPIO_8 BI 78
1 1 IFPD_AUX_I2CX_SDA* DP_INT_EG_AUX_N
BI 41 77 95
R9609 M2
CRITICAL R9627 R9628 GPIO9 GPU_GPIO_9
BI 78
100K 100K AM1 40.2K J1
L9604 L1
5% 5%
IFPD_L0 DP_INT_EG_ML_P<0>
OUT 41 95 1 2 MULTI_STRAP_REF MULTI_STRAP_REF0_GND GPIO10 GPU_GPIO_10
BI 78
330-OHM-1.2A AM2 M5
1/20W
MF
1/20W
MF
IFPD_L0* DP_INT_EG_ML_N<0>
OUT 41 95 0.1% GPIO11 GPU_GPIO_11
BI 78
1/20W
1 2 AM3 GPU_TESTMODE AK11 N3
80 =PP3V3_GPU_IFPX_PLLVDD PP3V3_GPU_IFPX_PLLVDD 77 201
2 2
201
IFPD_L1 DP_INT_EG_ML_P<1>
OUT 41 95 MF 77 TESTMODE GPIO12 GPU_GPIO_12

Apple Imac 21.5 A1418 Apple J16 820-3482, 051-9889 r13.0.0 - Electronicforum

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8 7 6 5 4 3 2 1

LAST_MODIFIED=Sat Aug 10 21:13:36 2013

D Page Contents Sync Page Contents Sync D

5 CPU DMI/PEG/FDI/RSVD J17 53 AUDIO: HEADPHONE AMP J16_MLB_IG

6 CPU Clock/Misc/JTAG/CFG J17 54 AUDIO: LEFT SPKR AMP J16_MLB_IG

9 CPU Ground J17 57 Audio: Spkr/Mic Conn. J16_MLB_IG

11 PCH RTC/HDA/JTAG/SATA/CLK J17 59 AUDIO: Speaker ID J16_MLB_IG

12 PCH DMI/FDI/PM/GFX/PCI J17 60 Power Connectors / VReg G3Hot J16_MLB_IG

14 PCH GPIO/MISC/NCTF J17 62 VReg CPU VCC Phases J16_DG

16 PCH Grounds J17 64 VReg PCH/GPU/TBT 1V05 S0 J16_DG

17 PCH DECOUPLING 65 VReg 3.3V S5/5V S4

20 Project Chipset Support MASTER 68 LCD Backlight Driver (LP8561) J16_MLB_IG

21 CPU Memory S3 Support J17 69 FET-Controlled S0 and S4 MASTER

23 DDR3 SO-DIMM Connector A J16_MLB_IG 71 PM Power Good J16_MLB_IG

24 DDR3 SO-DIMM CONNECTOR B J16_MLB_IG 72 KEPLER PCI-E J16_DG

25 DDR3 ALIASES AND BITSWAPS J16_MLB_IG 73 KEPLER CORE/FB POWER J16_DG

26 Thunderbolt Host (1 of 2) J16_MLB_IG 74 KEPLER FRAME BUFFER I/F J16_DG

28 Thunderbolt Power Support J16_MLB_IG 76 GDDR5 Frame Buffer B J16_DG

29 Thunderbolt Connector A J16_MLB_IG 77 KEPLER EDP/DP/GPIO J16_DG

30 Thunderbolt Connector B J16_MLB_IG 78 KEPLER GPIOS,CLK & STRAPS J16_DG

31 TBT DDC Crossbar J16_DG 79 KEPLER PEX PWR/GNDS J16_DG

32 AIRPORT/BT J16_MLB_IG 80 Power Connectors/Aliases MASTER

33 SATA/SSD Connectors MASTER 81 Signal Aliases MASTER

35 ETHERNET PHY (CAESAR IV) J16_MLB_IG 83 Functional / ICT Test J16_DG

36 Ethernet Support & Connector J16_MLB_IG 84 J16 RULE DEFINITIONS J16_DG

38 Camera Controller J16_MLB_IG 86 CPU PCIe Constraints J16_NICK

39 Camera Controller Support J16_MLB_IG 87 PCH PCIe/DMI Constaints J16_DG

40 Internal DP Support J16_MLB_IG 88 SATA/FDI/XDP Constraints J16_NICK

41 Internal DP MUXing J16_DG 89 PCH and BR Constraints J16_NICK

43 EXTERNAL USB PORTS C & D J16_MLB_IG 91 SMBus/Sensor Constraints J16_TONY

45 SMC Support J16_TONY 93 CPU VReg Constraints J16_DG

48 I and V Sense J16_TONY 96 GDDR5/GPU Constraints J16_NICK

Apple Inc. 051-9889 D

Main BOM Variants Bar Code Labels / EEEE #’s

BOM NUMBER BOM NAME BOM OPTIONS TABLE_5_HEAD

825-7896 1 MLB LABEL,2D EEEE_F9RW CRITICAL EEEE:F9RW

Schematic / PCB #’s

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

BOM GROUP BOM OPTIONS 820-3482 1 PCBF,MLB,J16 PCB CRITICAL J16

GPU & VRAM

DEVEL_SENSORS AP_ISNS:Y,HDD_IVSNS:Y,TEMPSNSDEV 337S4427 1 IC,GPU,NV,GK107-GX,PS,926MHZ,2.5GHZ U8700 CRITICAL GPU:107GX

J16_PRODUCTION AP_ISNS:N,HDD_IVSNS:N 333S0630 4 IC,GDDR5,2GBIT,64MX32,5GBPS,GEMMA-DIE U9200,U9250,U9300,U9350 CRITICAL FB:BOTH_HYNIX

333S0695 4 IC,GDDR5,2GBIT,64MX32,5GBPS,B-DIE U9200,U9250,U9300,U9350 CRITICAL FB:BOTH_ELPIDA

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

377S0147 377S0126 ALL USB Diode Array

377S0124 377S0057 ALL TVS

376S0975 376S1081 ALL P/NCh dual FET

155S0578 155S0367 ALL 120OHM EMI BEAD

128S0368 128S0365 ALL 150UF AL POLY

128S0298 128S0293 ALL 330 UF AL POLY

197S0464 197S0477 Y9700 27 MHz GPU Xtal

197S0466 197S0477 Y9700 27 MHz GPU Xtal

197S0479 197S0478 Y4200 12 MHz Cam. Xtal

B 337S4541 1 IC,LPT-D,SR198Z87,C2,PRQFCBGA708,23X22MM U1100 CRITICAL

Single-source 1uF 402

338S1113 1 IC,TBT,CR-4C,B1,PRQ,CIO,288 12X12 FC-CSP U2800 CRITICAL TABLE_ALT_ITEM

138S0648 138S0652 ALL 4.7uF GFX decoupling

138S0746 138S0705 ALL 10uF alt;Audio

Programmable Parts 138S0715 138S0740 ALL 4.7uF GFX decoupling

TABLE_5_HEAD 107S0254 107S0241 ALL 5mOhm Sense Resistor

TABLE_5_ITEM 107S0250 107S0248 ALL 3mOhm Sense Resistor

335S0807 1 IC,64 MBIT SPI SERIAL FLASH U5210 CRITICAL BOOTROM:BLANK

338S1159 1 IC,SMC12-A3,40MHZ/50MIPS,SCPL FW,157BGA U5000 CRITICAL SMC:BLANK

AP_CLKREQ_L P37 PCIECLKRQ2/GPIO20/SMI