Vlsi Design Flow

Step 1: Prepare an Requirement Specification

Step 2: Create an Micro-Architecture Document.

Step 3: RTL Design & Development of IP's

Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting

Errors/Analyze whether the RTL is Synthesis friendly.

Step 4a: Perform Cycle-based verification(Functional) to verify the protocol

behaviour of the

RTL

Step 4b: Perform Property Checking , to verify the RTL implementation and the
specification

understanding is matching.

Step 5: Prepare the Design Constraints file (clock

definitions(frequency/uncertainity/jitter),I/O

delay definitions, Output pad load definition, Design False/Multicycle-paths) to

perform

Synthesis, usually called as an SDC synopsys_constraints, specific to synopsys

synthesis Tool

(design-compiler)

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for
which synthesis

needs to be targeted for, which has the functional/timing information available for
the

standard-cell library and the wire-load models for the wires based on the fanout
length of the

connectivity), RTL files and the Design Constraint files, So that the Synthesis tool
can perform

the synthesis of the RTL files and map and optimize to meet the design-constraints

requirements. After performing synthesis, as a part of the synthesis flow, need to

build
scan-chain connectivity based on the DFT(Design for Test) requirement, the
synthesis tool

(Test-compiler), builds the scan-chain.

7: Check whether the Design is meeting the requirements

(Functional/Timing/Area/Power/DFT)

after synthesis.

Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is
meeting the

power targets.

Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check
whether the

design is meeting the functional requirements.

Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm

that the

synthesis Tool has not altered the functionality.

Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format)
file and

synthesized netlist file, to check whether the Design is meeting the timing-
requirements.

Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is
built based

on the DFT requirement.

1 / 3Vlsi Design Flow

Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog

format) and

the SDC (constraints file) is passed as input files to the Placement and Routing Tool
to perform

the back-end Actitivities.

Step 9: The next step is the Floor-planning, which means placing the IP's based on
the

connectivity,placing the memories, Create the Pad-ring, placing the

Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper
accessibility for

Package routing), meeting the SSN requirements(Simultaneous Switching Noise)

that when the

high-speed bus is switching that it doesn't create any noise related acitivities,
creating an

optimised floorplan, where the design meets the utilization targets of the chip.

Step 9a : Release the floor-planned information to the package team, to perform the
package

feasibility analysis for the pad-ring .

Step 9b: To the placement tool, rows are cut, blockages are created where the tool
is prevented

from placing the cells, then the physical placement of the cells is performed based
on the

timing/area requirements.The power-grid is built to meet the power-target's of the

Chip .

Step 10: The next step is to perform the Routing., at first the Global routing and
Detailed

routing, meeting the DRC(Design Rule Check) requirement as per the fabrication
requirement.

Step 11: After performing Routing then the routed Verilog netlist, standard-cells
LEF/DEF file is

taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the
SPEF

format(Standard parasitics Exchange Format), and the SPEF file is generated.

Step 12: Check whether the Design is meeting the requirements

(Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement

and

Routing step.

Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the
design has met
the power targets.

Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether
the design is

meeting the functional requirement .

Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that
the place &

route Tool has not altered the functionality.

Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist
file, to

check whether the Design is meeting the timing-requirements.

Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is
built

based on the DFT requirement, Peform the Fault-coverage with the DFT tool and
Generate the

ATPG test-vectors.

Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)

2 / 3Vlsi Design Flow

Step 12g: Perform DRC(Design Rule Check) verfication called as Physical-

verification, to

confirm that the design is meeting the Fabrication requirements.

Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takes
a routed

netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it
SPICE-S)

and compare that the two are matching.

Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design
is meeting

the ERC requirement.

Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed
and
proper guarding is there in case if we have both analog and digital portions in our
Chip. We

have seperate Power and Grounds for both Digital and Analog Portions, to reduce
the

Substrate-noise.

Step 12k: Perform seperate STA(Static Timing Analysis) , to verify that the Signal-
integrity of

our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics
including

coupling capacitances values), are fed to the tool. This check is important as the
signal-integrity

effect can cause cross-talk delay and cross-talk noise effects, and hinder in the

functionality/timing aspects of the design.

Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-
stand the

static and dynamic power-drops with in the design and the IR-drop is with-in the
target limits.

Step 13: Once the routed design is verified for the design constraints, then now the
next step is

chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files
which the fab

can understand, GDS file.

Step 15: After the GDS file is released , perform the LAPO check so that the
database released

to the fab is correct.

Step 16: Perform the Package wire-bonding, which connects the chip to the
Package.
Analogy Vlsi Building

VLSI flow was evolved similar to the flow involved in Building Construction.Now let
us dwelve in

to the constuction flow to better understand the VLSI Chip design flow development.

When ever we start to construct a building, we will have an architecture, how the
building

should look like , the exterior looks and all, similar to that we will be designing an
architecture in

the chip-design, based on the requirement of the product, what the product is
addressed for and

whom to serve what needs, the so called specification, will having the modules.

Now lets go in to the implementation part of both the Building & Chip.

We at first come with the floorplan of the building, similarly we come with the
floorplan of the

Chip, Based on the connectivity/accessibility/vaasthu we place our rooms, similarly

we have the

constraints to place the blocks. Like we build the building with bricks, for Chip
Design we have

libraries, which are like pre-designed bricks, for a specific functionality.

Now let us try to understand the power-structure or electrical connectivity in our

Building.

Initially we have an Electrical plan for our building, where we have a requirement
that all our

electrical gadgets needs to get power. Similar to that we have a Chip power
requirement, The

required power is supplied through the power-pads, over a ring like topology to
have a uniform

distribution across all corners of the chip, and the supply has to reach all the
standard-cells(bricks for Chip-Designing).,this is called as power-grid topology in the

Chip-Design, now the requirement is how well we design our Power-grid, to reduce
the IR-drop

so that our standard-cells get proper power requirement.

I would not make justice, if I dont discuss about clock and clock-tree in the Chip-
Design flow.

We have synchronous way of designing and asynchronous way of designing(difficult

to verify).

Majority

of chips follow Synchronous way of coding, for which Static Timing Analysis is
possible. For the

relevancy of the flops the clock to those flops should reach at the same time from
the crystal,

with in some skew targets with in the chip.In order to make this happen, a step
called as

clock-tree is performed after power-grid is created.

1 / 2Analogy Vlsi Building

Let us try to visualize the concept behind Place & Route in Chip Design. We need to
undergo lot

of modelling concepts, to understand the process of Chip-Designing. To have a

better

understanding of this concept of place and route, let us assume a society where
people who are

speaking different languages are living , and let us visualize that people talking of
the same

languages are living in a community, then the communication is much easier ,

similar way in the

chip-designing, the standard-cells who are having design relation-ships, are placed
closer in the

Placement flow this concept is called as regioning. Now with in the regioning, of the
groups of
the standard-cells, the cells which are really sharing data, has to placed close-by so
that there

timing is achieved and well optimized.This step is called placement, Connectivity

across the

standard-cells is called as routing, the challenge is having optimized or reduced

wire-lengths.

Now let us try to try to understand the concept behind signal integrity in the Chip-
Design , often

called us SI Effect. As our process is shrinking day by day, and our silicon-realestate
is costly,

we try to accommodate more and more standard-cells in the limited area, so the
cells are

placed in very close proximity, so the switching of one can have an impact over the
others

behaviour, which can make the path to be faster or slower, this issue is called as

signal-integrity. So similar way in our construction in order to maintain the integrity

with in the

house(neighbour free-zone), within the limited zone of modurality, we try to create

fences,

across buildings, similarly we can think of a concept called as Shielding, the high
frequency

signal net with the power-nets running across. We perform spacing across the
buildings, similar

way we can perform spacing across the nets, which are in close proximities.

In order to validate the silicon from the manufacturability issues, the concept in the
Chip

Desigining is Design for Test( DFT ). One of the DFT techniques is scan-chain. To
understand

the concept of the scan-chain, we can visualize that we have a front-door entry and
a back-door

exit, and a person passes from the front-door and exits from the back-door exit of
the building,
that we are sure that there is no blocking within the rooms in the building, to make
that person

stuck , similar to this analogy the flip-flops are connected to-gether creating a scan-
chain and

test-input values are passed from the scan-chain input of the chip and expected
data is

visualized in the scan-chain output of the chip, then the assumption is the chip is
free from

manufacturability issues like stuck-at faults(stuck-at one or stuck at zeros).

This is just a tip-of an ice-berg...