Deadbeat control method for single-phase UPS
inverters with compensation of computation delay
O.Kukrer
H.Komurcugil
Abstract: In existing deadbeat control techniques
for single-phase UPS inverters, the pulse width of
the inverter output voltage is limited by the
computation time of the controlling processor.
This limits the utilisation of the DC source
voltage and slows the response of the control
system. A deadbeat control technique is presented
which eliminates these limitations by allowing the
application of the newly computed pulse width
with time delay. During this delay, the previously
applied pulse width is preserved until it is updated
by the new pulse width. This method requires the
use of a load-dependent reference function for the
inverter output voltage. However, the error in the
load voltage caused by using a fixed reference
function is shown to be negligible. Computer
simulations are performed to verify the
theoretical results and for comparison with
existing methods. Experimental results are also
presented to support the theoretical con-
siderations.
1 Introduction
With the development of power semiconductor devices
that can switch at very high speeds, feedback control
techniques have been considered for inverters in UPS
systems. Classical open-loop techniques of obtaining
sinusoidal output voltages (e.g. sinusoidal PWM) are
incapable of providing a satisfactory response with
nonlinear or fast-changing loads.
Feedback control approaches for UPS inverters can
be broadly classified as continuous-time [1, 2] and dis-
crete-time [3–8]. Continuous-time control strategies are
implemented using analogue techniques and are not as
reliable as discrete-time stategies. The instantaneous
feedback control technique [1] has a reasonably fast
transient response. However, this approach has the dis-
advantage that harmonics are generated in the output
voltage at frequencies around the switching frequency.
Discrete-time control strategies are mostly based on
the deadbeat control theory [3–8]. For single-phase
inverter systems, the pulse width in a switching interval
which would drive the output voltage to a specified
© IEE, 1999
IEE Proceedings online no. 19990215
Paper first received 16th December 1997 and in revised form 6th July
1998
The authors are with the Department of Electrical and Electronic Engi-
neering, Eastern Mediterranean University, G. Magosa, Mersin 10, Tur-
key
IEE Proc.-Electr. Power Appl., Vol. 146, No. 1, January 1999
sinusoidal reference is computed on-line [3–5]. The
voltage pulse is subsequently applied to the output fil-
ter as soon as its computation is complete. A disadvan-
tage of this approach is that the maximum pulse width
is limited by the computation time of the processor.
The two-level PWM technique [5] improves the time
made available for computation. Alternatively, for a
given computation time, the switching frequency can be
increased to almost twice that with the three-level tech-
nique [3]. These approaches have yet another drawback
concerning the dynamics of the closed-loop system.
Analysis of this approach reveals that there are two
poles in the feedback system. One pole is located at the
origin at the rated load, with the gains calculated at the
rated load. The second pole has a magnitude of slightly
less than unity. Owing to this pole, even though the
deadbeat response of the voltage could be obtained, the
response of the other state variable (capacitor current)
is very slow and oscillatory. The oscillations of the
capacitor current during transients may give rise to
undesirable electromagnetic interference (EMI) prob-
lems. This deteriorates the overall performance of the
system.
In this paper, a discrete-time deadbeat control strat-
egy is proposed that completely eliminates the compu-
tation delay problem. With this approach, the time
made available to the processor is considerably greater
than with existing methods. Therefore, much higher
switching frequencies are possible. Basically, this con-
trol strategy depends on the application of the manipu-
lated inverter voltage with a delay in the sampling
interval, while the previously applied inverter voltage is
preserved until then. Deadbeat control is applied to all
the state variables of the system to locate all poles at
the origin. Although this gives rise to the problem of a
changing reference function for the inverter voltage as
the load changes, it is shown that the change is very
small and can be tolerated. Computer simulations are
performed to verify the theoretical results and for com-
parison with established methods. Experimental results
are also presented to show the effectiveness of the pro-
posed method for practical systems.
Fig.1 Single-phase UPS inverter with resistive load
123
2 Control method
2.1 System modelling
The discrete-time deadbeat control method is devel-
oped here. Fig. 1 shows a single-phase bridge inverter
with an LC-filter at its output. The load is assumed to
be resistive R. With the capacitor voltage v and the cur-
rent i as state variables, the state equation of the sys-
tem is
where x = [v i]T, u = vi and
Eqn. 1 can be discretised in an interval [t1, t2] in which
the input vi is constant as follows:
where
where U is the 2 × 2 identity matrix. In eqn. 2 it is
assumed that the inverter output voltage vi is averaged.
Let v* and i* be the reference functions for the capac-
itor voltage and current, respectively. If we define error
variables as
then the equation for the error variables becomes
Fig. 2 shows a switching interval [kT, (k + 1)T] , where
T is the sampling period. The control voltage vi(kT) for
the kth sampling interval is assumed to be applied after
a time delay γT. Control computations are assumed to
be completed within this delay period. While the com-
putations are performed, it is assumed that the control
voltage vi [(k – 1)T] for the previous sampling interval
is applied to the filter.
Fig.2 Switching strategy in sampling interval
The pulse width of the actual inverter output voltage
is calculated as
The error at the end of the kth sampling interval is
obtained as
124
where
If we define a new state variable as
then the system in eqn. 6 can be put into the following
form:
or
where
and F = F(T). Controllability of the system in eqn. 9
has to be established first. The controllability matrix of
this system is
The matrix operations in eqn. 10 can be performed to
give
Using the definitions in eqn. 6, this becomes
where g = g(T) and is defined in eqn. 2.
Mo has rank equal to 3 if, and only if, the 2 × 2
matrix eA(1–γ)T [g Fg] is nonsingular. Note that the
…
latter matrix is the controllability matrix of the system,
with no delay in the application of the manipulated
variable, which is nonsingular. Hence, the system in
eqn. 9 is completely state-controllable.
2.2 Control strategy
Assume that linear state feedback of the form
is applied to the system in eqn. 9. The closed-loop sys-
tem state equation is
Since the system is state-controllable, poles of the
closed-loop system can be placed at any desired loca-
tions. For deadbeat control, all the poles are required
to be at the origin. Ackermann’s formula [9] can be
used to find the gains that satisfy this requirement as
The gains are normally calculated for the rated load of
the inverter (Ro). As the load resistance changes, poles
of the closed-loop system would shift away from the
origin. The robustness of the control system depends
on the sensitivity of the poles to load variations. It is
not possible to obtain analytically the loci of the poles
as the load changes, since the system is of the third
IEE Proc.-Electr. Power Appl., Vol. 146, No. 1, January 1999
order. (In Section 4, loci are computed for a sample
system chosen for computer simulations.)
2.3 Extension to general load
The proposed control strategy can be easily modified
for a general load, following a procedure similar to one
proposed elsewhere [8]. Here, a brief outline of this
modification is described.
A general load (linear or nonlinear) can be repre-
sented by the current iL(t) it draws from the capacitor
(current source load). The system in eqn. 2 with such a
load would be described by
where hL is a vector that is a function of the load cur-
rent. Note that in this model R would be taken as
infinity. The control law in eqn. 13 is then modified as
where ∆vi′ is a correction term introduced to take care
of the load current. The closed-loop system becomes
where D is a vector that is a function of the load cur-
rent, and Fc is the closed-loop system matrix in
eqn. 14. If eqn. 18 is written for three consecutive sam-
pling intervals, we obtain
If the first element of the vector z(k + 1) is equated to
zero (for the deadbeat control of output voltage v),
then ∆vi′ (k) can be solved from the resulting equation
in terms of its previous values.
3 Reference functions
The reference functions for the state variables and the
inverter voltage (x* and vi*) are given by the following
equation (resistive load case):
Since the output voltage v is required to follow a speci-
fied reference v*, this reference is specified first. The
references for the capacitor current i and the inverter
voltage vi can then be solved from eqn. 20. Solution of
this equation would result in complicated expressions
for i*(k) and vi*(k). On the other hand, continuous-time
approximations can be utilised if the sampling fre-
quency is much higher than the fundamental output
frequency. Given that
then we obtain
where ω = 1/√(LC).
Note that the inverter voltage reference is a function
of the load resistance R. This implies that, in order to
be able to apply this reference, R must be measured on-
line and vi*(k) be calculated as R changes. Even though
this could be accomplished with the proposed control
IEE Proc.-Electr. Power Appl., Vol. 146, No. 1, January 1999
strategy, this would increase the computation time and
restrict the switching frequency. To overcome this diffi-
culty, we make the observation that the second term in
eqn. 23 can be made small if ωL << R. This condition
can be met by a suitable design of the system. vi* can
then be calculated at Ro and stored in the controller
memory.
The error in the output voltage resulting from this
approximation when the load resistance changes (R ≠
Ro) can be calculated using the state equation (eqn. 24)
for the total variables:
in which the matrices F, c and d are computed at R ≠
Ro. Reference functions for the case R = Ro are given
by
where o denotes that these quantities are computed at R
= Ro. Now assume that the reference functions are
evaluated for R = Ro using eqn. 25 and then fixed.
Then, using eqn. 24, eqn. 25 and the definitions in
eqn. 3, the state equation for the errors for the case R
≠ Ro is
Substituting the feedback law in eqn. 13, the closed-
loop system becomes
where
and f*(k) contains the terms with the reference func-
tions in eqn. 26. In eqn. 27 note that the matrices Fe
and B are evaluated at R, and the gain vector Kn is
evaluated at Ro. Eqn. 27 can be solved to obtain the
steady-state errors in the state variables and the
inverter voltage. However, analytical solution of
eqn. 27 is quite tedious, and the results would be diffi-
cult to interpret.
On the other hand, the steady-state errors can be
estimated by making continuous-time approximations.
The phasor equation for the filter-load system with R ≠
Ro in the steady-state can be written as
When R = Ro, the phasor equation is
Substituting eqn. 29 in eqn. 28 gives
125
∆Vi can be eliminated in eqn. 30 using the control comparison of total harmonic distortions (δ) and fun-
equation (eqn. 13). In the steady-state eqn. 13 can be damental amplitudes of these waveforms with Hua’s
written in terms of phasors as [5]. δ is defined as

where k1, k2 and k3 are the elements of Kn. Also note

that

Then, solving for ∆V

A sample calculation given below and simulation

results show that this error is negligibly small.

4 Computer simulations
Fig.4 Load voltage waveform for R = 2 Ω
Hua’s inverter system [5] is chosen for the comparison
of simulation results. The parameters of this system are
Vs = 40V, Vm = 15V, L = 500µH, C = 200µF, fs =
9.0kHz and Ro = 2Ω. The gains are computed for R =
Ro and γ = 0.5 as k1 = –7.6072, k2 = –7.4918 and k3 =
–0.7657.

Fig.5 Load voltage waveform for R = 2000 Ω

It can be observed that the deadbeat control approach

here (DCCD) has superior steady-state performance
over existing deadbeat control approaches. Total har-
monic distortions are considerably lower, and funda-
mental amplitudes are more accurate. Furthermore, the
error caused by using a fixed reference function for the
inverter voltage is negligible. The theoretical error in
the output voltage for R = 2000Ω is calculated using
eqn. 33 as

The load voltage amplitude and phase shift with

respect to V* for this case are 15.023V and 1.01°,
respectively. Note that the computed load voltage
waveform confirms the estimation of error in the load
voltage.

Table 1: Computed total harmonic distortions (δ) and

Fig.3 Root loci of closed-loop deadbeat control system
fundamental amplitudes of load voltage
a R > Ro, b R < Ro
DCCD Two-level method

Fig. 3 shows the loci of the closed-loop poles as R δ(%) V1 (V) δ(%) V1 (V)
changes. When R is less than 0.8Ω, the system becomes R = 2Ω 0.12 14.99 0.54 15.6
overdamped and the model used for feedback control
becomes invalid. Hence, this case is excluded from this R = 2000Ω 0.10 15.04 0.51 15.6
analysis. The loci clearly show that the system stays
stable for all possible values of the load resistance. Fig. 6 shows the response of the load voltage to a
Figs. 4 and 5 show the load voltages with R = Ro = nonlinear load . The load is a triac-controlled resistive
2Ω and R = 2000Ω, respectively. Table 1 shows the load, with firing angles of 86° and 266° in the positive
126 IEE Proc.-Electr. Power Appl., Vol. 146, No. 1, January 1999
and negative half-cycles, respectively. The total har-
monic distortion of voltage is 8.1%, compared with
Hua’s 6.4% [5]. The reason for higher values of δ here
is the greater change in load voltage resulting from the
delayed application of the control voltage vi(k) . On the
other hand, the response time is considerably shorter
than Hua’s [5]. This improvement is because the pulse
width is only restricted by the sampling period.
Fig.6 Load voltage and current waveforms for nonlinear load
Fig.7 Experimental load voltage waveform for R = 2 Ω
Fig.8 Experimental load voltage waveform for R = 2000 Ω
IEE Proc.-Electr. Power Appl., Vol. 146, No. 1, January 1999
5 Experimental results
Operation of the proposed control strategy was experi-
mentally verified on a microcontroller-based system. A
16MHz Intel 87C196KR microcontroller was used to
control the inverter. PWM control signals were accu-
rately generated using the PWM mode of the micro-
controller’s peripheral transaction server (PTS).
Experimental results were obtained that correspond to
the simulation cases. Figs. 7, 8 and 9 show the experi-
mental output voltage waveforms for the R = 2Ω, R =
2000Ω and the triac load cases, respectively. It can be
observed that the experimental results are in good
agreement with the simulation results. In Fig. 9, note
that the transient response of the voltage is quite simi-
lar to the simulation. Total harmonic distortions of
these waveforms were measured as 1.5%, 1.7% and
11.0%, respectively. The experimental distortions are
higher than the simulation values because of the addi-
tional distortion caused by noise disturbances in the
practical system. The distortion caused by noise is
noticeable on the experimental waveforms.
Fig.9 Experimental load voltage waveform for nonlinear load
Fig.10 Experimental load voltage waveform for nonlinear load in open-
loop operation
Fig. 10 shows the output voltage waveform for open-
loop operation of the inverter with the nonlinear load.
The distortion of this voltage is unacceptably large,
127
showing the effectiveness of closed-loop control for
such loads.
6 Conclusions
Deadbeat control of single-phase UPS inverters with
delayed application of the control voltage has been
described. This approach allows the use of much higher
sampling frequencies than existing deadbeat control
strategies. Since higher frequencies are possible with the
proposed method, the output filter size can be reduced
for the same output waveform distortion by increasing
the sampling frequency. Furthermore, the time made
available to the controlling processor is increased, lead-
ing to the possibility of more functions being imple-
mented on the processor with reduced hardware
complexity.
The mathematical model obtained for the proposed
control system is observed to involve a load-dependent
reference function for the inverter output voltage.
However, the use of a fixed reference evaluated at the
rated load is seen to lead to a negligible error in the
load voltage.
Computer simulation results are compared with
those of similar deadbeat control strategies. The
approach presented here leads to improved steady-state
performance. Transient response to nonlinear loads is
faster, but has greater undershoot or overshoot in load
128
voltage, resulting from the delay in the application of
control. Theoretical and simulation results have been
verified through experiments.
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