I2C Master/Slave - APB Controller Data Sheet

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I2C Master/Slave Controller

With APB Interface

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I2C Master/Slave - APB Controller Data Sheet
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Copyright © 2005, Arasan Chip Systems, Inc. All Rights Reserved.

Copyright Notice

Arasan Chip Systems copyrights this specification. No part of this specification may be
reproduced in any form or means, without the prior written consent of Arasan Chip Systems.

Disclaimer

This specification is preliminary and is subject to change at any time without notice. Arasan Chip
Systems assumes no responsibility for any errors contained herein.

Questions and/or comments may be directed to:

Arasan Chip Systems, Inc.

1150, North First Street, Ste #211,
SANJOSE, CA – 95112, USA.
Tel: (408) 985 - 9495 x106
Fax: (408) 985 - 4268
Email: support@arasan.com
http://www.arasan.com/

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Table of Contents

1. FEATURES .................................................................................................................... 4
1.1 I2C Standard Specification Compliant ..................................................................... 4
1.2 APB Bus Specification Compliance ......................................................................... 4
2 Introduction...................................................................................................................... 4
3. I2C - APB Bridge Block Diagram .................................................................................. 5
4. Functional Blocks Description: ...................................................................................... 6
4.1 APB Bridge Block .................................................................................................... 6
4.2 Register Block........................................................................................................... 6
4.3 Clock Generator ........................................................................................................ 6
4.4 Transmit Receive Control Logic............................................................................... 6
4.5 FIFO.......................................................................................................................... 6
4.6 I2C Master Interface ................................................................................................. 6
4.7 I2C slave Interface .................................................................................................... 6
5.0 Register Details............................................................................................................. 7
6.0 Signal Interfaces ........................................................................................................... 7
6.1 I2C Interface PINS: .................................................................................................. 7
6.2 APB INTERFACE PINS: ......................................................................................... 8
7 Verification ...................................................................................................................... 8
8 Deliverables ..................................................................................................................... 8

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1. FEATURES

1.1 I2C Interface

•Compliant with I2C specification Version 2.1
•Supports a simple bi-directional 2-wire bus for efficient for inter-IC control
•Programmable as I2C Master mode
•Programmable as I2C slave mode
•Supports a Clock generation circuitry to derive I2C clock from APB clock
•Supports various operational frequencies from 100 KHZ to 400 KHZ.
•1024x8 bits register space is memory mapped to external I2C Master.

1.2 APB Interface

•Compliant with AMBA [Rev2.0] for easy integration with SOC implementations
•Supports APB bus for varying frequency range from 1 to 95MHZ.
•Supports Bus mastering DMA modes.
•Device states are read by periodic polling mechanism.
•Has 1024X 8 FIFO to accelerate the data transfers from and to I2C and APB.
•1024x8 bits register space is mapped to APB memory.

2 Introduction
The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces
to the APB bus on the system side and the I2C bus. The APB interface is used to easily integrate the
Bridge Controller for any SOC implementation.

The APB - I2C is a master/slave interface that enables synchronous serial communication with the other
master or slave I2C peripherals having I2C compatible interface. The controller performs the following
functions:

•Parallel-to-serial conversion on data written to an internal 8bit wide, 1024 deep FIFO.
•serial-to-parallel conversion on received data, buffering it in a similar 8-bit wide, 1024 deep FIFO

Device states are read by the APB using status registers that reflect the completion of I2C transfers.

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3. I2C - APB Bridge Block Diagram

I2C Master/Slave - APB Controller

I2C Clock I2C Master

Generator Interface

APB Bus I2C I2C

APB
(8-bit) Interface
FIFO Transceiver
Bridge Registers
8 x 1024

I2C Slave
Interface

The figure above shows the block diagram of the APB-I2C Bridge Controller. The block has an APB inter-
face to read and write registers. The I2C interface in master mode initiates data transfer to the external I2C
slave devices and in slave mode receives the data from the external I2C master. The I2C interface handles
the serializing and de-serializing of data to the I2C interface from and to APB interface.

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4. Functional Blocks Description:

4.1 APB Bridge

The APB interface block is primarily used for programming the registers on the I2C controller and to
transmit and receive data from the I2C master/slave devices.

4.2 Registers
The operational registers are used to program the controller and also to give the status of the design. The
registers are programmed using the APB interface and are used by the I2C controller to control the I2C
interface.

4.3 Clock Generator

The clock generator contains a counter. The counter is used to generated a divide signal and generate the
I2C clock as required by the user by programming the divisor registers.

4.4 I2C Transceiver

The transmit and receive logic contains the state machines to receive and send data in the I2C protocol
format.

4.5 FIFO
This FIFO is 8 bit wide and 1024 bit deep. It is filled by the APB controller and sent to the external I2C
device by the I2C controller during a transmit operation.
The same FIFO is filled by the I2C controller and read by the APB controller during a receive operation.

4.6 I2C Master Interface

When APB - I2C IP is programmed as the I2C master interface, the APB controller initiates read and write
transfers through command registers and watches the completion of the task by polling the status
registers. The amount of data to be transferred or read is predetermined by the APB controller and is
programmed in the data length registers. Data to be read or written in the external I2C device is addressed
using data port registers. This block throttles the data flow between the I2C interface and the APB
controller in master mode.

4.7 I2C slave Interface

When the APB - I2C IP is programmed as the I2C slave interface, the APB controller polls the status
register to know whether a read or write is happening in the I2C interface. When a read or write is
completed the APB controller takes away the data from the FIFO by reading the data length registers and
address registers to map the register locations. This block throttles the data flow between the I2C interface
and the APB controller in slave mode.
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5.0 Register Details

The following sections describe each register.

APB Register
Address Register Name Register Type
Offset
0x0000 Command Register R/W
0x0001 Programmable I2C Address Register LSB R/W
0x0002 Programmable I2C Address Register MSB R/W
0x0003 Data Port Register R/W
Ox0004 Status Register RO
0x0005 Divisor Register R/W
0x0006 Mode Register R/W
0x0007 Address Register LSB RO
0x0008 Address Register MSB RO
0x0009 Data Length Register RO
0x000A Data Length Register RO
0x000B APB status Register RO

6.0 Signal Interfaces

6.1 I2C Interface PINS:

Power up
Pin Name Direction Pin Description
Value
SCL B Serial EEPROM Clock: Hi-Z
This open-drain output drives the clock to the serial
EEPROM. A pull-up is required for this signal.
SDA B Serial EEPROM Address/Data: Hi-Z
This open-drain bi-directional signal is used to transfer
address and data serially to and from the EEPROM. A
pull-up is required for this signal.

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6.2 APB INTERFACE PINS:

Pin Name Direction Pin Description Power up Value

PRDATA [7:0] O Output 8 bit data bus Hi-Z

PWDATA [7:0] I Input 8 bit data bus Hi-Z
PADDR [7:0] I Input 8 bit Address lines Hi-Z
PENABLE I Input Processor Enable data lines Hi-Z
PSEL I Input Processor select same as chip select Hi-Z
PWRITE I Input Write Enable Hi-Z
P_CLK I Input APB processor clock This is also used as a
reference clock for the SEEPROM interface.

7 Verification
Silicon Proven on multiple Arasan and Customer Silicons.

8 Deliverables
•The full IP package complete with:
•Verilog HDL
•Synopsis synthesis scripts
•Test Environment and test scripts
•APB - I2C controller’s Userguide with full programming interface and parameterization instructions.

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