Lecture 5: Instruction Set Architectures - II Instruction Types

• ALU Operations
• Last Time
– arithmetic (add, sub, mult, div)
– Introduction to ISAs
– logical (and, or, xor, srl, sra)
• Today – data type conversions (cvtf2d, cvtf2i)
– HW#2 assigned Sunday, due 2/15 • Data Movement
– Instruction types – memory reference (lb, lw, sb, sw)
– Memory operations – register to register (movi2fp, movf)
– Control flow operations • Control - what instruction to do next
– Instruction formats – tests/compare (slt, seq)
– branches and jumps (beq, bne, j, jr)
– Case study ISAs – MIPS, others
– support for procedure call (jal, jalr)
– Reading for next time: handout #2
– operating system entry (trap)
• Hair - string compare!

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Addressing Modes
Driven by Program Usage Addressing Modes
• Stack relative for locals
double x[100] ; // global Memory and arguments
SP Memory
void foo(int a) { // argument a, j: *(R30+x)
j j
int j ; // local a a
for(j=0;j<10;j++) • Short immediates (small
x[j] = 3 + a*x[j-1] ; constants)
Stack Stack
3
bar(a);
} • Long immediates (global
addressing)
procedure array reference
x &x[0], &bar: 0x3ac1e400 x
• Indexed for array
constant argument references
bar *(R4+R3) bar

foo foo
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Addressing Mode Summary Control Instructions

• Implicit control on each
instruction
#n immediate
PC ← PC + 4 LOOP: LOAD R1 <- (R5+R2)
(0x1000) absolute
• Unconditional jumps ADD R3 <- R3 + R1
Rn Register ADD R2 <- R2 + 4
PC ← X (direct)
(Rn) Register indirect CMP R4 <- R2 == 8
PC ← PC + X (PC relative) JNE R4, LOOP
-(Rn) predecrement
X can be constant or
(Rn)+ postincrement register
*(Rn) Memory indirect • Conditional jumps (branches)
*(Rn)+ postincrement PC ← PC + ((cond) ? X : 4)
d(Rn) Displacement (b,w,l)
• Predicated instructions
d(Rn)[Rx] Scaled
• Conditions
– flags
– in a register
VAX 11 had 27 addressing modes (why?) – fused compare and branch

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 Conditional Branching Support for Procedures
• Compute condition first • Branch and Link
– Condition codes Z N C O – store return address in reg and jump
CMP R1, R2 JALR Rdest: Rx ← PC + 4, PC ← Dest

negative
carry
zero

overflow
BGE LOOP
• Forces CMP and BR to be adjacent
• Subroutine call
– Condition in GP register
– push return address on stack and jump
CMP R3, R1, R2 R3 ZNCO
JAL foo
PC
BGE R3, LOOP Return Here
• Enables parallelism of comparisons • CALLP (VAX)
– Condition in “condition” register – push return address
Cn C2 C1 C0
– set up stack frame
• Fuse condition check and branch – save registers
foo
BGE R1, R2, LOOP – ...
– reduces instruction count, but complicates pipelining

UTCS, CS352, S07 Lecture 5 7 UTCS, CS352, S07 Lecture 5 8

Instruction Formats Variable-Length Instructions

• Different instructions need to • Variable-length instructions
specify different information give more efficient encodings
– return – no bits to represent unused
R: rd ← rs1 op rs2 fields/operands 8
– increment R1
6 5 5 5 11 – can frequency code Op
– R3 ← R1 + R2
– jump to 64-bit address Op RS1 RS2 RD func operations, operands, and
addressing modes 8 4 4
• Frequency varies Op R M
– Examples
– instructions I: ld/st, rd ← rs1 op imm, branch
• VAX-11, Intel x86 (byte
– constants 6 5 5 16 8 4 4 4 4 4 4
variable)
– registers Op RS1 RD Const Op R M R M R M
• Intel 432 (bit variable)
• Can encode • But - can make fast 8 4 4 32
J: j, jal
– fixed format implementation difficult Op R M Disp
6 26
– small number of formats – sequential determination of
Op Const
– byte/bit variable location of each operand VAX instrs: 1-53 bytes!
Fixed-Format (MIPS)

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Compromise: A Few Good Formats Constant Encoding

• Gives much better code • Integer constants
density than fixed-format – mostly small
– important for embedded – positive or negative 6 VAX short literal
-32 to 31
processors • Bit fields Op

• Simple to decode – contiguous field of 1s within

6 5 5 5 1 10 32bits (64 bits) 5 5
• Examples: Op R1 R2 R3 Const • Other E S Symbolics 3600
– ARM Thumb, MIPS 16
– addresses, characters, Bit Fields
6 5 5 symbols
• Another approach Op R1 R2
• A good architecture 00000001111111111000000000000000
– On-the fly instruction – uses a few bits to encode the
4 4 4 4
decompression (IBM most common.
Op R1 R2 R3
CodePack) – allows any constant to be
generated (table reference)

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 MIPS ISA MIPS ISA (a visual)

• 32 GP Integer registers (R0-31) – 32 bits each

– R0=0, other registers governed by conventions (SP, FP, RA, etc.)
PC
• 32 FP registers (F0-F31) R: rd ← rs1 op rs2
– 16 double-precision (use adjacent 32-bit registers) 6 5 5 5 11
• 8, 16, and 32 bit integer data types R31
Op RS1 RS2 RD func
• Load/Store architecture (no memory operations in ALU ops)
• Simple addressing modes I: ld/st, rd ← rs1 op imm, branch
R1
– Immediate R1 ← 0x23
R0 6 5 5 16
– Displacement R2 ← d(Rx) ….. 0(R3), 0x1000(R0)
Op RS1 RD Const
• Simple fixed instruction format (3 types), 90 instructions
• Fused compare and branch F30 F31 J: j, jal
• “ISA” has pseudo instruction that are synthesized into simple 6 26
sequences (ie. rotate left rol = combination of shift and mask)
F2 F3 Op Const
• Designed for fast hardware (pipelining) + optimizing compilers
F0 F1
Fixed-Format

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MIPS: Software conventions for Registers MIPS arithmetic instructions

0 zero constant 0 16 s0 callee saves Instruction Example Meaning Comments
add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible
1 at reserved for assembler . . . (caller can clobber)
subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible
2 v0 expression evaluation & 23 s7 add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible
add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions
3 v1 function results 24 t8 temporary (cont’d)
subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions
4 a0 arguments 25 t9 add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions
5 a1 26 k0 reserved for OS kernel multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product
multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product
6 a2 27 k1
divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder
7 a3 28 gp Pointer to global area Hi = $2 mod $3
divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder
8 t0 temporary: caller saves 29 sp Stack pointer
Hi = $2 mod $3
... (callee can clobber) 30 fp frame pointer Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi
15 t7 31 ra Return Address (HW) Move from Lo mflo $1 $1 = Lo Used to get copy of Lo

Plus a 3-deep stack of mode bits. Which add for address arithmetic? Which add for integers?
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Multiply / Divide MIPS logical instructions

• Start multiply, divide Instruction Example Meaning Comment

– MULT rs, rt and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND
– MULTU rs, rt General or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR
xor xor $1,$2,$3 $1 = $2 Å $3 3 reg. operands; Logical XOR
– DIV rs, rt Registers
nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR
– DIVU rs, rt and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant
• Move result from multiply, divide or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant
xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant
– MFHI rd
shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant
– MFLO rd shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant
HI LO
• Move to HI or LO shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)
– MTHI rd shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable
shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable
– MTLO rd shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

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 MIPS data transfer instructions MIPS Compare and Branch

Instruction Comment • Compare and Branch

SW 500(R4), R3 Store word – BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch
SH 502(R2), R3 Store half – BNE rs, rt, offset <>
SB 41(R3), R2 Store byte • Compare to zero and Branch
– BLEZ rs, offset if R[rs] <= 0 then PC-relative branch
LW R1, 30(R2) Load word – BGTZ rs, offset >
LH R1, 40(R3) Load halfword – BLT <
LHU R1, 40(R3) Load halfword unsigned – BGEZ >=
LB R1, 40(R3) Load byte – BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31)
LBU R1, 40(R3) Load byte unsigned – BGEZAL >=
• Remaining set of compare and branch take two instructions
LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16)
• Almost all comparisons are against zero!

Why need LUI? LUI R5

R5 0000 … 0000

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MIPS jump, branch, compare instructions Details of the MIPS instruction set
Instruction Example Meaning
• Register zero always has the value zero (even if you try to write it)
branch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100
Equal test; PC relative branch • Branch/jump and link put the return addr. PC+4 into the link register (R31)
branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100 • All instructions change all 32 bits of the destination register (including lui,
Not equal test; PC relative lb, lh) and all read all 32 bits of sources (add, sub, and, or, …)
set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; 2’s comp. • Immediate arithmetic and logical instructions are extended as follows:
set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0 – logical immediates ops are zero extended to 32 bits
Compare < constant; 2’s comp. – arithmetic immediates ops are sign extended to 32 bits (including addu)
set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0 • The data loaded by the instructions lb and lh are extended as follows:
Compare less than; natural numbers – lbu, lhu are zero extended
set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0 – lb, lh are sign extended
Compare < constant; natural numbers
• Overflow can occur in these arithmetic and logical instructions:
jump j 10000 go to 10000
– add, sub, addi
Jump to target address
jump register jr $31 go to $31 • It cannot occur in
For switch, procedure return – addu, subu, addiu, and, or, xor, nor, shifts, mult, multu, div, divu
jump and link jal 10000 $31 = PC + 4; go to 10000
For procedure call

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Memory Organization Alignment

• Some architectures restrict addresses that can

• Four components specified by ISA:
be used for particular size data transfers!
– Smallest addressable unit of memory (byte? halfword? – Bytes accessed at any address
word?) (addressibility)
– Halfwords only at even addresses
– Maximum addressable units of memory (doubleword?)
– Words accessed only at multiples of 4
– Alignment

– Endianness
unaligned word access

0x1004 0x1000

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 Endianness Data Types

• How are bytes ordered within a word? • How the contents of • Most general purpose
memory and registers are computers support several
– Little Endian (Intel/DEC) interpreted types
• Can be identified by – 8, 16, 32, 64-bit
3 2 1 0 – tag – signed and unsigned
0x1003 0x1002 0x1001 0x1000 – use – fixed and floating
• Driven by application
– Big Endian (IBM/Motorola) – Signal processing int 0x8a1c
• 16-bit fixed point
(fraction)
0 1 2 3 str “abcd”
– Text processing
0x1000 0x1001 0x1002 0x1003
• 8-bit characters
– Today - most machines can do either (configuration
– Scientific computing Examples of tags (ie. Symbolics machine)
register)
• 64-bit floating point

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Example: 32-bit Floating Point Summary

• Type specifies mapping • ISA: memory and instructions
from bits to real numbers
(plus symbols) • MIPS as an example
1 8 23
– format – Read more details in Appendix A
s exp mantissa
• S, 8-bit exp, 23-bit
mantissa
• Next Time
– interpretation
• mapping from bits to
– ISA design principles
abstract set – Interaction between the ISA and the compiler
• Reading assignment – Handout #2
v = ( !1) S " 2 ( E !127 ) " 1. M
– operations
• add, mult, sub, sqrt, div

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