PROJECT REPORT

INVERTER DESIGN FOR 2001 FUTURE ENERGY

CHALLENGE

College of Engineering and Computer Science

University of Central Florida
Orlando, FL 32816

Tel (407) 823-0185

Fax. (407) 823-6334
batarseh@mail.ucf.edu

Student Team Members :

Joy Mazumdar
Manasi Soundalgekar
Duy Bui
Nancy Saldhana
Bassem Khoury
Steven Pugh

Advisor: Dr. Issa Batarseh

15th June, 2001

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 Signature Page

The following students comprised the Future2001 EnergyChallenge team from the
University of Central Florida under the guidance of Dr Issa Batarseh.

Advisor :

( Dr Issa Batarseh ) Date

Students :

( Joy Mazumdar )

( Manasi Soundalgekar )

( Duy Bui )

( Nancy Saldhana )

( Bassem Khoury )

( Steven Pugh )

Power Electronics group at the University of Central Florida wishes to thank IEEE
PELS, DOE and the other organizers of Future 2001 Energy Challenge Competition
for providing its students the opportunity to participate in this project.
 TABLE OF CONTENTS

List of figures

1.0 Introduction

2.0 Theory of Design Rationale

2.1 Design specifications for the 1.5kW prototype

2.2 DC-DC Converter Stage Design

2.2.1 Basic circuit operation of DC-DC stage

2.2.2 Design of transformer stage for DC-DC conversion

2.2.3 Output inductor design for DC-DC stage

2.2.4 Design of DC bus capacitor bank

2.3 PWM DC-AC Inverter Stage Design

2.3.1 Basic half-bridge inverter circuit with resistive load

2.3.2 Half-bridge inverter circuit with resistive inductive load

2.3.3 PWM Concept

2.3.4 Output voltage

2.3.5 Dead time

2.4 Output LC filter design

2.5 Input circuits, EMI filtering, fusing and transient protection

2.6 Output Overload Protection

2.7 DSP Control Design

2.8 Design of the heat sinks

2.9 RC snubber circuit design

 2.10 Component values for 10kW inverter system

3.0 Manufacturing Issues

3.1 Electrical mounting and termination

3.2 PCB trace selection

3.3 Heat sink issues

3.4 Wiring considerations

4.0 Educational Impact

4.1 About UCF

4.2 Power Electronics progress at UCF

4.3 Student participation in the project

4.4 Project development stages

4.5 Educational benefits

5.0 Inverter Operating Instructions

6.0 Simulation results and experimental setup

7.0 Cost Evaluation Spreadsheet

8.0 References

9.0 Appendix

A. DSP Sampling cycle

B. ORCAD schematic for PCB layout

C. Pspice schematic circuit for 1.5kW and 10kW inverter system

D. Devices and IC datasheets

List of figures:

Fig1 (a) Block diagram of the proposed inverter system, (b) Circuit diagram of the proposed

inverter

Fig2 Flat-topped pulse current

Fig3 (a) Half-bridge Inverter under resistive load, (b) Switching and output voltage waveform

Fig4 (a) Half-bridge with inductive- resistive load, (b) Equivalent circuit, (c) Steady state

waveforms

Fig5 SPWM and Inverter Output Voltage

Fig6 Single SPWM pair of pulses

Fig7 Inverter control scheme

Fig8 (a)Waveforms for correction of dead time, (b) Inverter leg

Fig9 Input protection circuit

Fig10 RC Snubber Circuit

Fig11 Thermal resistance

Fig12 Power panel schematic

Fig13 Differential Voltage and current waveform under normal resistive load

Fig14 Phase 1 and Phase 2 voltage waveform

Fig15 DC positive and negative bus voltage

Fig16 Maximum voltage stress across switches MOSFET1, MOSFET2, IGBT1, IGBT2, IGBT3

and IGBT4

Fig17 Load current waveform under unbalanced load conditions

Fig18 Output Filter Capacitor voltage waveform under unbalanced load conditions

Fig19 Output Filter Inductor current waveform under unbalanced load conditions

Fig20 Voltage feedback waveform for DSP

Fig 21 Current feedback waveform for DSP

Fig 22 Voltage and current waveforms for 10kW system

1.0 Introduction

In this report, a design for a high power density 10kW inverter circuit is presented for conversion of

energy from DC fuel cells to AC power to be used mainly for domestic utility applications. The

configuration is achieved using a high frequency dc-dc push-pull converter at the input side followed by a

full-bridge PWM inverter and a low-pass filter at the output side. Due to the simplified power stage and

the application of DSP-based sinusoidal pulse width modulation technique, output voltage Total

Harmonic Distortion (THD) is reduced and a relatively smaller overall inverter size is achieved. The

proposed practical circuit operates from a 48V DC fuel cell input and outputs a regulated 120V AC, 60Hz

sinusoidal voltage having 3-wire configuration[4]. A complete circuit analysis, design and cost evaluation

is presented and supported by PSPICE simulation results. As per competition guidelines, a low power

inverter has been redesigned, tested and prototyped, to deliver a 1.5kW load. Operating waveforms,

printed circuit board layout and measured efficiency of the actual circuit are also presented.

2.0 Theory of Design Rationale

This project will explore the possibility of making alternate sources of energy utility interactive by means

of low cost power electronic interface (DC-AC inverter). The constraint towards the above scheme is the

input DC voltage from alternate forms of energy is very rarely stable hence the design of the proposed

interface has to produce an AC output, which is independent of the input fluctuations[3]. The PWM

inverter will be digitally controlled using a commercial DSP chip for AC voltage and frequency

regulation. The implementation of the DSP will have a current controller, voltage controller and a feed

forward controller. The input voltage from the renewable forms of energy will be 48VDC with fluctuation

limit of 42-72V DC. The output voltage will be 110/220VAC @60Hz clean sine wave suitable for home

applications. Since the inverter is for residential use, low cost, high reliability and safety are essential

design issues.

2.1 Design Specifications for the 1.5kW prototype [1]

Input Voltage Range : 42-72 VDC

Output Voltage : Single-phase 120/240VAC RMS, 3-wire output

1
 Output Frequency : 60Hz ± 0.1Hz

Output Power Range : 2 x 750Watts continuous

Efficiency : > 90%

Line and Load regulation : 5%

Total Harmonic Distortion : < 5%

Input Current limit : 55 Amps

Switching Frequency : 50kHz for push pull and 15kHz for inverter bridge

Operating temperature : 10° C - 40° C

DSP Controls : TMS320F240 Evaluation module

Communication Interface : RS232

2.2 DC-DC Converter Stage Design [14]

A block and circuit diagram for the proposed inverter implementation is shown in Fig. (a) and the circuit
schematic is shown in Fig 1(b).

I dc
+ iac
Push-Pull Inverter Low-Pass
Vdc stage Stage Filter
v ac
− DC-DC AC-DC

Fig 1(a): Block diagram representation of the proposed inverter system

D1 R1 L1
T1
Q3 Q5

n1 n2 D2 C1
15 KHz 15 KHz
R3

iTr
Q4 Q6
n1 R4 15 KHz 15 KHz
n2 C2
Cin D3
Vdc

Fuel
Cell Q1 Q2
50kHz 1 50kHz
D4 R2 L2
L3 L4

C3 C4

Load Load

Load Iac
Vac
Fig 1(b): Circuit diagram of the proposed inverter system

2
To reduce the size of the system transformer, the first stage will consist of a high frequency push-pull dc-

dc converter. The second stage consists of two half-bridge inverters arranged in a full bridge

configuration. The control technique used in the second stage is sinusoidal PWM. The third stage

represents the low pass filter with passive components, due to the relatively high attenuation of the low

harmonic components for the output voltage waveform. The input stage consists of power devices Q1

and Q2, transformer T1, inductor L1, L2 and dc bus capacitors C1 and C2. The dc push-pull converter

boosts the bus voltage to 240VDC for the inverter to produce 110VAC. The output inverter stage

consists of power devices Q3 - Q6, output inductors L3, L4 and capacitors C3 and C4. Using the well-known

sinusoidal PWM technique, this circuit generates a sine wave output voltage.

2.2.1 Basic Circuit Operation of DC-DC stage

The push pull converter belongs to the feed-forward converter family. With reference to Fig. 1(b), when

Q1 switches on and Q2 is off, current flows through the 'upper' half of T1's primary and the magnetic field

in T1 expands. The expanding magnetic field in T1 induces a voltage across T1 secondary, the polarity is

such that D2, D4 is forward biased and D1, D3 is reverse biased. D2 conducts and charges the output

capacitor C2 via L2 and D4 conducts and charges the output capacitor C1 via L1. The components L1, L2

and C1, C2 form a LC filter network. When Q1 turns off, the magnetic field in T1 collapses, and after a

period of dead time (dependent on the duty cycle of the PWM drive signal), Q2 conducts, causing the

current to flow through the 'lower' half of T1's primary and the magnetic field in T1 expands. Now the

direction of the magnetic flux is opposite to that produced when Q1 conducted. The expanding magnetic

field induces a voltage across T 1 secondary, the polarity is such that D1, D3 are forward biased and D2, D4

are reverse biased. D1 conducts and charges the output capacitor C1 via L1 and D3 conducts and charges

the output capacitor C2 via L2. After a period, Q1 conducts and the cycle repeats.

There are two important considerations to be made when it comes to the design of the push - pull

converter:

3
 1. Both transistors must not conduct simultaneously, as this would effectively short-circuit the

supply. Hence, the conduction time of each transistor must not exceed half of the total period for

one complete cycle; otherwise, the conduction will overlap.

2. The transformer magnetic flux must be bi-directional; otherwise the transformer may saturate,

and cause destruction of Q1 and Q2. This requires that the individual conduction times of Q1 and

Q2 are exactly equal and the two halves of the center-tapped transformer primary be magnetically

identical.

These design considerations must be handled by the control, drive circuit and the transformer.

The average output voltage, Vout , equals the average of the waveform applied to the LC filter:

n2
Vout = Vin f S ( Ton,sw1 + Ton,sw 2 ) (1)
n1

where,

Vout = Average output voltage - Volts

Vin = Average supply voltage - Volts

n2 = number of secondary turns of the center -tap transformer T 1

n1 = number of primary turns of the center -tap transformer T 1

f S = Switching frequency of MOSFETs Q1 and Q2 - Hertz

Ton,sw1 = on time period of Q1 Seconds

Ton,sw 2 = on time period of Q2 Seconds

The control circuit monitors and controls the duty cycle of the drive waveforms to Q1 and Q2. If Vin

increases, the control circuit will reduce the duty cycle accordingly, so as to maintain a constant output.

Likewise, if the load is reduced and Vout rises the control circuit will act in the same way. Conversely, a

decrease in Vin or increase in load will cause the duty cycle to be increased. Following given is the

derivation of all the inverter parameters.

4
Relations between primary current, output power, and input voltage:

Since the maximum average input power Pin is 1.8kW and if we assume the efficiency of the push-pull

converter to be 90%, then the average output power Pout of the DC-DC stage is 1.65kW.

Pout = 0.9 Pin (2)

It can be seen that, the average input power may be given as,

Pin = VDCmin ( 0. 5 I pft ) (3)

where VDCmin is the minimum DC input voltage, 0.5 is the duty cycle and I pft is the flat-topped pulse

current as shown in Fig (2). The flat-topped pulse current is defined as ramp on a step. The flat-topped

pulse current appears at the transformer center tap.

i Tr

I pft

t
Fig 2: Flat-topped pulse current

The relationship in Equation (3) is valuable since, it gives the equivalent peak flat-topped primary current

pulse amplitude in terms of what is known at the outset, the minimum DC input voltage and total input or

output power. This value is needed to help us select the MOSFET. Finally, for the MOSFET selection the

maximum voltage stress that the MOSFET has to handle should be known.

Maximum voltage stress of the MOSFETs:

It can be shown that the maximum voltage stress across the MOSFET is given by the following formula,

Vms = 1. 3( 2VDCmax ) (4)

where VDCmax is the maximum input DC voltage.

The maximum stress voltage is 30% above twice the maximum DC input voltage. Maximum stress

comes from the so-called leakage inductance spikes, these come about because there is an effective small

5
inductance (leakage inductance) Ll in series with each half primary. At the instant of turnoff, current in

the MOSFET falls rapidly at rate di causing a positive-going spike of amplitude E ls = Ll di at the bottom
dt dt

end of the leakage inductance. The leakage spike may be as much as 30% more than twice the maximum

DC input voltage.

Using the given design specifications, we carry on with the following stress voltage calculations.

Pin = VDCmin ( 0. 5 I pft )

( 1.11Pout )
I pft = = 87 amps at 50% duty cycle (5)
0 .5VDCmin

I RMS = I pft D = 61 amps at 50% duty cycle (6)

Vrms = 1. 3( 2VDCmax ) = 187 Volts at 50 % duty cycle

MOSFET Conduction losses

( 0. 4T ) Pout
PDC = I pft Von = 0.4 Ipft Von = 0624
. (7)
T VDCmin

MOSFET Switching losses

2VDCmax TS I pft TS P V T
Pt ( a c ) = I pft + 2Vdc = 3.12 out DCmax S (8)
2 T 2T VDCmin T

where,

TS = tvr = tcf is the transition time.

tvr = voltage rise time from 0 to 2VDCmax .

tcf = current fall time from I pft to 0

The total MOSFET loss consists of switching loss Pt ( a c ) and conduction loss PDC and is given by

Pout T s 0.624 Pout

Ptotal = Pt ( ac ) + Pdc = 3 .12 V DC max + (9)
V DC min T V DC min

6
2.2.2 Design of transformer stage for DC-DC[15]

The push-pull DC-DC converter design is one of the most critical issues in this project. The detailed
design is explained as below based on the following design parameters:
Vnom = 48V (nominal input dc voltage)

Vmin = 42V (minimum input dc voltage)

Vmax = 72V (maximum input dc voltage)

Vout = 240V (dc bus voltage)

I out = 6 A (dc current)

f S = 50kHz (push-pull switching frequency)

Bm = 0.13T (maximum operating flux density)

η = 90% (efficiency)

Ku = 0.4 (window utilization factor)

Vd = 1 (diode voltage drop)

Dmax = 0.5 (maximum duty cycle)

Tr = 25o C (maximum temperature rise)

Skin depth of the wire is δ in cm

6.62
δ= (10)
fS

δ = 0.03 cm
Wire diameter is 2δ

D = 2δ = 0.059 cm
Bare wire area is Aw in sq cm

πD 2
Aw = = 2.754 ⋅10−3 cm2 (11)
4
Based on Aw calculated above, choose wire size AWG 23, heavy insulation copper wire

Output Power Pout of the converter is given by

Pout = I out (Vout + Vd ) (12)

Pout = 1446watts

7
The total apparent power is Papp in VA is given by

2
Papp = Pout ( + 2) (13)
η

Papp = 4317VA

Electrical coefficient Ke

Here we have K f and Bac given by,

K f = 4 (waveform coefficient for square wave)

Bac = 0.3 Bmax

The electric coefficient, K e , can be obtained from the following relation,

Ke = 0.145K 2f f S2 B2sc ⋅10−4 (14)

resulting in the following value of K e

Ke = 882.18

Based on Kg, we select our core. Kg is given by,

Pt
Kg = (15)
2Ke

K g = 2 .447 cm5

Selection of Core

Based on the value of core geometry, ferrite core from Magnetics Inc, OP 45530-EC is a suitable E core

for the above application. The PC bobbin used is PC-B5530-FA.

Datasheet of OP 45530-EC Core:

H W L G MPL Wtfe Wtcu MLT Ac Wa Ap At Perm AL

cm cm cm cm cm gms gms cm cm2 cm2 cm4 cm2 mH
5.51 4.59 5.48 3.70 12.3 255 172.1 12.2 4.130 3.956 16.339 147.2 2300 5640

The core geometry of the above core is 2.206504 cm5. AL is defined in mH/1000. For more information
refer to [15].

8
Primary turns N p

It can be shown that Np is obtained from the following relation.

Vmin ⋅10 4
Np = (16)
f S AC Bm K f

N p = 3. 911

To avoid the possibility of core saturation, we choose 6 turns for the primary winding. Under normal

operating conditions, the input current is assumed to be around 40A. The worst case input current is 55A.

Assuming a current density of 450A/cm2, the primary wire bare area is calculated as,

40 Dmax
Awp = (17)
450

Awp = 0.063 cm2

For the primary winding, choose 3 strands of AWG 14 heavy insulation copper wire.

Secondary turns Ns

N p ( Vout + Vd ) 1
NS = ( 1+ ) (18)
Vmin 100

NS = 22.668

33 turns for were selected for secondary. Under normal operating conditions, the DC output current is

assumed to be around 6A. Assuming a current density of 450A/cm2, the primary wire bare area is

calculated as,

I out Dmax
Aws = (19)
450

Aws = 9.428 ⋅10 −3 cm2

For the secondary winding, 3 strands of AWG 23 heavy insulation copper wire were chosen.

2.2.3 Output inductor design of DC – DC stage

This inductor is required since the input is a voltage source and the DC capacitors also act as a voltage

source. Hence, the inductor acts as a current link between two voltage sources. For the purpose of charge

9
and voltage balancing in the DC capacitors, we require a coupled inductor. The inductance value can be

calculated based on the MOSFET switching frequency and duty cycle as given by,

DVout
L= (20)
2 f S ∆I o

where D = 0.5 , L1=L2=L. L1 and L2 are the coupled inductors. Vout is the average output voltage, fs is the

switching frequency, ∆Io is the output current ripple (assume to be 10% of output current). Based on 1:5

transformer ratio, i.e. output voltage of the push- pull is 240V, and using 750W power rating for each

stage, L = 2 mH. The inductor was constructed using a powder iron core (26 material).

Construction of the coupled inductor[15]

The selection of the core was based on the following two main design parameters

• Inductance L required with DC bias = 2mH

• DC current = 6A

Based on the calculation of the product LI2, Micrometals E220-26 iron powder E core was found suitable.

Datasheet of E 220-26 E core:

H W L G MPL Wtfe Wtcu MLT Ac Wa Ap At Perm AL

cm cm cm cm cm gms gms cm cm2 cm2 cm4 cm2 mH
5.54 3.86 5.61 3.83 13.2 333.9 167.9 11.6 3.6 4.079 14.684 141.3 75 275

The core geometry of the above core is 1.827264 cm5. AL is defined in mH/1000.
The required number of turns, N, can be calculated as

L
N = 10 3 (21)
AL

N=85.28 turns

where, AL =mH/1000turns and L=inductance in mH.

We have chosen N=90 turns for the required inductance.

For calculation of the wire size, the bare wire area required @ 450A/cm2, Awb, is obtained from,

I out D
Awb = (22)
450

Awb = 0.0094 cm2

10
Hence AWG 18 heavy insulation copper wire is suitable for the inductor. Since the inductor is coupled,

the construction requires 2 strands of AWG 18 wire wound 90 times inside a pair of E220-26 core.

2.2.4 Design of DC bus capacitors

It is assumed that all the energy for the inverter is supplied by the DC capacitor bank. The ripple

frequency at the DC capacitor will be twice the switching frequency, i.e. 100kHz. These are bulk

capacitors and the ripple voltage across it is assumed to be 1% of maximum value. The value of the

capacitors can be calculated using the following formula,

2 Pout
C= (23)
( 2 f S )(V12 − V22 )

where

V1 =max ripple capacitance voltage

V2 = min ripple capacitance voltage

The DC bulk capacitors are chosen to be 560uF/ 500V.

2.3 PWM DC-AC Inverter Stage Design[14]

Since the inverter is the most important aspect in this design, a detailed steady state analysis is presented

for the half bridge inverter topology, which is used in our circuitry. The analysis presents the equations

and supporting waveforms.

2.3.1 Basic half-bridge inverter circuit resistive load

To illustrate the basic concept of a dc-to-ac inverter circuit we consider a half-bridge voltage-source

inverter circuit under resistive load as shown in Fig. 3 (a). Its switching waveforms for S1, S2 and the

result output voltage are shown in Fig. 3 (b).

11
 S1
Vdc
R iO

νo -

+
Vdc S2

(a)

S1

S2

νo

+Vdc
t
T/2
-Vdc
T

(b)
Fig.3 (a) Half-bridge Inverter under resistive load.(b) Switching and output voltage waveform.

The circuit operation is very simple since S1 and S2 are switched on and off alternatively at 50% duty

cycle as shown in the switching waveform in Fig. 3 (b). This shows that the circuit generates a square ac

voltage waveform across the load from a constant dc source. The voltages, Vdc and –Vdc are across R

when S1 ON while S2 OFF and when S2 is ON while S1 is OFF, respectively. One observation to be

made here is that the frequency of the output voltage is equal to f = 1/T and is determined by the

switching frequency. This is true as long as S1 and S2 are switched complementarily. Moreover, the rms

value of the output voltage is simply Vdc. Hence, to control the rms value of the output voltage we must

control the rectified Vdc voltage source. Another observation is that the load power factor is unity since

we have purely resistive load. That is rarely encountered in practical application.

12
Finally, we should note that in practice the above circuit does not require two equal dc voltage sources as

shown in Fig. 3 (a). Instead, large splitting capacitors are used to produce two equal dc voltage sources.

The two capacitors are equal and very large so that RC is much larger than the half-switching period. This

will guarantee that the mid-point, a, between the capacitors has a fixed potential at one-half of the supply

voltage Vdc.

2.3.2 Inductive-Resistive load

Figure 4 (a) shows a half-bridge inverter under inductive resistive load with the equivalent circuit and the

output waveforms shown in Fig. 4 (b) and (c), respectively.

iD1
Vdc Q1 D1

R iO L
- νo +
iD2
Vdc
Q2 D2

(a)

+
t
ν 0 T/2 T
+V dc in
νin
νo

-V dc0 t
T/2 T iL
-
IL(T/2)
a'
t1
t
IL(0) Q1
Q2
D1 D2
(b)
(c)

Fig. 4 (a) Half-bridge inverter with inductive resistive load.

(b) Equivalent circuit and (c) Steady state waveforms.

13
With Q1 and Q2 switched complementary each at 50% duty cycle with switching frequency f , then the

load between terminal a and a ′ is excited by square voltage waveform vin (t) of amplitudes

+ V dc and − Vdc as shown in Fig. 5 (b), i.e. vin (t) is defined as follows:

+ V 0 ≤ t < T 2
vin (t ) =  dc  (24)
− V dc T 2 ≤ t < T

The switches are implemented by using conventional SCR (that require external forced commutation

circuit) or fully controlled power switching devices such as IGBTs, GTOs, BTJs or MOSFETs. Notice

from the load current i L direction, these switches must be bi-directional. Assume the inverter operates in

steady state and its inductor current waveform is shown in Fig. 4(c) for 0 < t < t1 ,the inductor current is

negative which means while Q1 is ON the current actually flows in the reverse direction, i.e. in the body

diode of the bi-directional switch Q1. At t = t1 , the current flows through the transistor Q1 as shown. At

t = T 2 , when S2 is turned ON, since the current direction is positive, the flyback diode, D2, turns ON

until t = T 2 + t1 when Q2 starts conducting.

2.3.3 PWM Basic concept

One of the problems facing the power electronic design engineers is how to reduce harmonic content in

inverter circuits. Having multiple pulses in each of the half cycle of an inverter output normally provides

control over both the harmonic content and the rms value of the voltage across the load. The process of

varying the width of these pulses is known as Pulse Width Modulation (PWM). This method of control,

PWM, can be divided into two classes, depending on the modulation techniques: Non-sinusoidal PWM

and Sinusoidal PWM.

Multiple Pulse (Uniform) Pulse-Width-Modulation

In the uniform PWM technique, multiple pulses are generated, each one having the same width and are

modulated equally to control the output voltage. In order to reduce the harmonic content in the single-

pulse inverter, we can apply several pulses within each half cycle of the output voltage. The number of

14
pulses increases when the control period decreases or its frequency, fs, increases. K is the number of Ts

periods in one half of the output period, To. The frequency of the reference signal sets the frequency of

the output voltage fo. It can be noticed as the magnitude modulation index, M, varies from 0 to 1, the

width of each pulse varies from 0 to π / k, i.e.

To k 1  1  f 
kTs = à = à k =   s 
2 f s 2 fo  2  f o 

The ratio between the carrier frequency and the output frequency is known as Frequency Modulation

Index, M f , defined as

fs
Mf = (25)
fo

1
Hence, k is given by, k= Mf (26)
2

Notice that when k = 1, it is a special case where M f = 2.

Sinusoidal PWM Waveforms

In Sinusoidal Pulse Width Modulation, SPWM, multiple pulses are generated, each having different

width time. The width of each pulse is varied in proportion to the instantaneous integrated value of the

required fundamental component at the time of its event. In other words, the pulse width becomes a

sinusoidal function of the angular position. The repetition frequency of the output voltage will be a

frequency higher than the fundamental. In applying SPWM, the lower order harmonics of the modulated

voltage wave are highly reduced in contrast to the use of uniform pulse width modulation.

In SPWM the output voltage signal can be obtained by comparing a control signal, vcont , against a

sinusoidal reference signal, vref , at the desired frequency as shown in Fig 5. At the first half of the output

period, output voltage takes a positive value (+ Vdc ), whenever the reference signal is greater than the

15
control signal. At the same way, at the second half of the output period, the output voltage takes a

negative value (- Vdc ) whenever the reference signal is less than the control signal.

The control frequency f cont determines the number of pulses per half of cycle for the output voltage

signal. Also, the output frequency f o is determined by the reference frequency f ref . The modulation

index Ma is defined as the ratio between the sinusoidal magnitude and the control signal magnitude.

V p , ref
Ma = (27)
V p ,cont

To obtain a vary train of pulses, each pulse has to vary proportional to the necessary fundamental

component precisely at the time when this pulse occurs. The frequency of the output waveform needs to

be higher than the frequency of the fundamental component. By varying the width of each pulse, the

inverter is able to produce different levels of output voltage for the corresponding pulse event.

1
1 f ref
v p ,cont (t) fcont v p ,ref (t)
V p ,cont
V p ,ref

π wt
2π

vo (t)

Vdc

π wt
2π

− Vdc
To

Figure 5. SPWM and Inverter Output Voltage.

16
Calculation of the output voltage as Fourier series expansion

The calculation of the SPWM output voltage is the same as it was done with UPWM output voltage.

However, for SPWM the width of each pulse varies according to its position. The expression for the

output voltage is obtained using a Fourier series transformation for vo , given by,

∞
vo (t) = Vo + ∑ (a
n =1, 2Κ
n cos nwt + bn sin nwt ) (28)

Since the inverter output voltage is an odd function, only odd harmonics exist.

The calculation the output voltage harmonic components can be done using one single pair of pulses as

shown in Fig 6.

v o (t )

θ wi
V dc

θi + π θ 'i + π

ωt
π 2π
θi θ 'i
− V dc
θ wi
To

Figure 6 Single SPWM pair of pulses.

1 2π
π ∫0
V n,i = vo ( wt ) sin( nwt )d ( wt )

1  
θi +θ wi π +θ i +θ wi

V n,i = 
π  ∫ VDC sin( nwt )d (wt ) + ∫ − V DC sin( nwt ) d ( wt ) 

θ i π +ϑ i

V DC  
θ +θ i wi π +θ +θ i wi

V n,i =  ∫ sin( nwt )d ( wt ) − ∫ sin( nwt )d (wt )

π  θ i π +θ  i

V n,i
V
nπ
{
= DC (− cos nwt ) |θθ +θ −( − cos nwt ) |θθ ++θπ +π
i
i
wi i
i
wi
}
= DC {− cos n(θi + θwi ) + cos n(θi ) + cos n(π + θi + θwi ) − cos n (θi + π )}
V
V n,i
nπ

 x + y  x − y
Using this trigonometric relationship: cos x − cos y = − 2 sin  sin 
 2  2 

17
Factoring through, we obtain the harmonic component for a single pair of pulses,

 2V   θ   θ   θ 
V n,i =  DC  sin n wi sin nθi + wi  − sin nθi + wi + π  
 nπ   2    2   2 

Adding the contribution from all other pulses, the ith component of vo is given by,

k
 2V   θ   θ   θ 
V n = ∑  DC  sin n wi sin nθi + wi  − sin nθi + wi + π  
i =1  nπ   2   2   2 

where, θi is the starting angle of the ith pulse, and θwi is the pulse width at the corresponding angular

position. Next we estimate θw for each ith pulse.

Inverter controller scheme is shown in Fig. 7 [10].

S1
C1 +
Vdc
PWM Lb Vo
Vdc
S2 Io
+
C2 Vdc Co RL
OFF

Verr
+ + PWM1
GATE
PI 1 PI 2
_ _ PWM2 DRIVE
Vout Iout

Voltage
ADCIN
and
current
TMS320F240EVM
sense
ADCIN amplifier

Figure 7:Inverter control scheme

The inverter modulates a dc bus voltage, Vdc, into a cycle-by-cycle average output voltage. The amplitude

of the inverter output voltage is directly proportional to the commanded duty cycle of the inverter and the

amplitude of the dc bus voltage Vdc. It can range from + Vdc to - Vdc. Current mode control is used for this

PWM inverter. Current mode control is a two-loop control system that simplifies the design of the outer

18
voltage control loop and improves UPS performance in many ways, including better dynamics and a feed

forward characteristic that could be used to compensate DC bus ripple and dead-time effect, etc.

2.3.4 The Output Voltage

It can be shown that the average output voltage over TS period is given by,

Vo ,ave. = maV dc 0 < ma ≤ 1 (29)

The rms value for the i th pulse is given by,

θ i +θ width
1
Vo ,rms = ∫ 2kV dωt
2

2π
dc
θi

k
Vo ,rms = Vdc θwidth (30)
π

ma
we have θwidth = π , hence, Eq. (30) becomes,
k

k πma
Vo ,rms = V dc = V dc ma (31)
π k

The rms of the output voltage is a function of the modulation index ma.

2.3.5 Dead Time Compensation[13]

Normally PWM is generated by sampling the required signal at the corners of the sawtooth wave giving

samples s1 and s2. From these samples the desired output voltage should go low at 'a' and high at 'b'. If

the current is positive the output voltage follows the edges of T1. When the output current is negative the

output voltage follows the edges of T2 which are adjusted as shown to match the PWM intersections

again at 'a' and 'b'. To implement the deadtime 'd' when both switches are OFF the additional edges at 'c'

and 'e' must be generated. One means of implementing a dead-time is to generate a nominal signal Tn

from which T1 and T2 are formed. For this scheme, T1 follows Tn but any turn-on is delayed by 'd'. T2

follows the inverse of Tn but any turn-on is delayed by 'd'.

19
 Fig 8: Waveforms for correction of dead time

The desired Tn for both directions of current is illustrated in the diagram and is generated by

Positive sawtooth edge

compare sawtooth with Vph for i>0 ; compare sawtooth with Vph- for i<0

Negative sawtooth edge

compare sawtooth with Vph+ for i>0 ; compare sawtooth with Vph for i<0

The sawtooth is usually between voltages corresponding to DC bus voltage Vs and for a desired deadtime

2d
'd' the value of the offset is ε = VS
T

Including this correction to regular sampled PWM will give exact correction to deadtime error provided

the current is continuous. For natural sampled PWM, the correction will not be exact but differences will

be less than the difference between natural and regular PWM.

2.4 Output LC filter design[11,13]

A proper designing of the LC filter can result in a great reduction of the inverter output harmonics and

hence provide very clean power for the load. The designing of the LC filter is based on the Inverter output

voltage and the minimum reactive power of the filter. The design procedure involves some assumptions:

20
 • The source DC voltage is ripple free

• All power devices behave ideally

• The load is linear

• Series resistance of the capacitance is negligible

As the exact voltage drop across the filter inductance is difficult to determine, it is assumed negligible.

Thus, rms inverter output voltage is equal to the rms load voltage based on this assumption, the

modulation index can be calculated as

Vo
d= 2 (32)
Ed

From the value of the modulation index, the constant K, which has been derived from the Fourier analysis

of the output voltage, can be calculated as given below.

1
 2 15 4 64 5 5 6  2
 d − 4 d + 5π d − 4 d 
K=  (33)
 1440 
 

The optimum value of the filter inductance can be calculated as

 1
 2
V  Ed  
2
Ed  f 
L f = o K 1 + 4π 2  r  K  (34)
 f  V
I o f S  Vor,avg  S or,avg  
 


From the value of the filter inductance, the filter capacitance can be calculated as

Ed
Cf = K (35)
L f f S2Vor,avg

where,

E d is the input DC voltage to the inverter stage , V o is the output rms voltage , V or,avg is the average

output voltage , f r is the fundamental output frequency , f S is the switching frequency , L f is the filter

inductance , C f is the filter capacitance

21
Using the value of E d to be 240V and the output RMS voltage to be 120VAC, we find the value of

required L to be 1.7mH and the value of capacitance to be 4.7uF. These values give the corner frequency

of the LC filter to be 1.7kHz. As far as the corner frequency selection is concerned, since we are

regulating the low frequency current and voltage, we need to filter out the high frequency content. Given

that the switching frequency is 15kHz, the corner frequency should be 10-20 times lower than that

(~1.5kHz) to be able to extract the fundamental frequency. On the other hand, we do not want to attenuate

the fundamental frequency (60Hz). So, we need a need a corner frequency of 10 times higher than that

(~600Hz). Given these constraints, the corner frequency should be <1.5Khz and >600Hz. Half way in

between will gives ~1kHz corner frequency. This does approximately match with the range of value,

which we derived from the theoretical calculations. Hence, we choose the filter inductance value to be

2mH and the capacitance value to be 17.5uF.

2.5 Input Circuits, filtering, fusing and transient protection

Input Filtering

Capacitors C1, C2, C3 and Balun transformer T1 form an input Balun filter [13]. A Balun filter is used to

attenuate common mode noise generated by the converter and reflected back onto the power bus. The Pi

(¼) filter, which will suppress differential mode noise. The filter components are chosen such that it

presents the highest impedance at the converter switching frequency. The inductance value of the Balun

transformer chosen is 8uH. This is manufactured by using 10 turns of AWG 18 heavy insulation copper

wire wound on E220-26 micrometals iron powder core. The value of the capacitors chosen is

220uF/100V. Practically speaking, this type of filter can reduce noise levels by about 10 to 12 dB.

Input Fusing

As a general rule, the input lines to any power converter should be fused. The fuse will limit input power

in the event of a catastrophic failure within the converter or the system the converter is supplying power

to. The chosen fuse should be a slow-blow type with a current rating approximately 200% of the full load

input current to the converter (for wide input range converters, 200% of the maximum input current must

22
be used). Having a slow-blow type will allow the converter short circuit protection circuitry time to react

to transient fault conditions. For our application, an 80A fuse semiconductor fuse is chosen for input

protection.

Input Transient Protection

The avalanche Zener D2, clamps the input to a safe level in the event of a power line transient. The

energy contained within the transient is dissipated across the surge suppresser.

+Vin D1 Fuse
8uH

+ + +
D2 C1 C2 C3
220nF/100V 220nF/100V 220nF/100V

-Vin
8uH

Fig 9: Input protection circuit and output filter

2.6 Output Overload protection

Although the use of filtering will prevent excessive current at power ON, under normal conditions, the

best way to prevent overload at output is to use a fuse with sufficient tolerance to inrush current, so that it

won't blow at power ON. A 15A semiconductor fuse is selected for the output phases.

2.7 DSP Control Design[2,5,6,10]

Today’s low-cost, high-performance DSP controllers, such as the Texas Instruments (TI) TMS320F240,

provide an improved and cost effective solution for inverter design. The F240 has integrated peripherals

specifically chosen for embedded control applications. These include Analog-to-Digital converters (A/D),

PWM outputs, timers, protection circuitry, serial communications, and other functions. High CPU

bandwidth and the integrated power electronic peripherals of these devices make it possible to implement

a complete digital control of inverters. Most instructions for the F240, including multiplication and

accumulation (MAC) as one instruction, are single cycle. Therefore, multiple control algorithms can be

23
executed at high speed, making it possible to achieve the required high sampling rate for good dynamic

response. This also makes it possible to implement multiple control loops of the inverter in a single chip

and increase integration and lower system cost. Digital control also brings the advantages of

programmability, immunity to noise, and eliminates redundant voltage and current sensors for each

controller. With fewer components, the system requires less engineering time, and it can be made smaller

and more reliable. The extra DSP bandwidth is available for implementing more sophisticated algorithms,

as well as communications to host systems and I/O devices such as LCD displays. DSP programmability

means that it is easy to update systems with enhanced algorithms for improved reliability.

Features of the TMS320F240 System:

The table shown below gives a list of the TI chip parameters and their corresponding values.

Parameter Name TMS320F240EVM

MIPS 20
Frequency ( MHz) 20
RAM ( words ) 544
Flash (words ) 16K
Boot Loader available Flash
External Memory Interface Yes
PWM Channels 12
10 bit A-D ( # channels ) 16
Conversion Time (us) 6.1 us
Timers 3
Total Serial ports 2

Features

• High-performance Static CMOS Technology

• Includes the T320C2xLP Core CPU

Object Compatible with the TMS320C2xx

Source Code Compatible with TMS320C25

Upwardly Compatible with TMS320C5x

132-Pin Plastic Quad Flat Package (PQ Suffix)

50-ns Instruction Cycle Time

24
• Industrial and Automotive Temperature Available

• Memory

544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM

16K Words × 16 Bits of On-Chip Program ROM ('C240)/Flash EEPROM ('F240)

224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K

I/O, and 32K Global Memory Space)

• Event-Manager Module

12 Compare/Pulse-Width Modulation (PWM) Channels

Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Up and

Up/Down Counting

Three 16-Bit Full-Compare Units with Deadband

Three 16-Bit Simple-Compare Units

Four Capture Units (Two with Quadrature Encoder-Pulse Interface Capability)

• Dual 10-Bit Analog-to-Digital Conversion Module

• 28 Individually Programmable, Multiplexed I/O Pins

• Phase-Locked-Loop (PLL)-Based Clock Module

• Watchdog Timer Module (With Real-Time Interrupt)

• Serial Communications Interface (SCI) Module

• Serial Peripheral Interface (SPI) Module

• Six External Interrupts (Power Drive Protect, Reset, NMI, and Three Maskable Interrupts)

• Four Power-Down Modes for Low-Power Operation

• Scan-Based Emulation

• Development Tools Available:

Texas Instruments (TITM) ANSI C Compiler, Assembler/Linker, and C-Source Debugger

Scan-Based Self-Emulation (XDS510TM )

25
 Third-Party Digital Motor Control and Fuzzy-Logic Development Support

Sampling Cycle

Eight circuit parameters are sensed and processed by the DSP controller, based on which the control loop
functions. The circuit parameters are listed as follows:

• Input voltage to the converter Vin

• Input current Iin

• Upper DC capacitor voltage, V+

• Upper DC capacitor voltage, V-

• Inductor current for bridge leg 1, IL1

• Capacitor voltage for bridge leg 1, VC1

• Inductor current for bridge leg 2, IL2

• Capacitor voltage for bridge leg 2, VC2

The detailed operation of the DSP sampling cycle is explained in the Appendix A.

2.8 Design of heatsinks

The first step in the designing of heat sinks is to determine the total thermal resistance between junction to

ambient and the accordingly determine the thermal resistance of the heatsink. Thermal resistance of a heat

sink can be approximated to

50
Rsa = (36)
A

Where Rsa is the thermal resistance of the heatsink and A is the total surface area of the heatsink in cm2.

Based on the selection of the power devices, the area of the heatsinks required can be calculated. For

example, for the MOSFET selected IRFP260N,

Rcs = 0.24 oC/W (thermal resistance between case and sink)

26
Rjc = 0.4 oC/W (thermal resistance between junction and case)

T jmax = 175 oC (maximum junction temperature)

T a = 40 oC (Operating ambient temperature)

The relationship between power dissipation and temperature is given by,

T jmax − Ta
R ja = (37)
PD

where,

P D = 121 Watt (Power dissipation at ambient temperature based on 55A current and RDSON = 0.04Ω)

Rja = 1.116 oC/W (thermal resistance between junction and ambient)

The thermal resistance between heat sink and ambient is given by, Rsa ,

Rsa = R ja − R jc − R cs (38)

Rsa = 0.476 oC/W (thermal resistance between heatsink and ambient )

Therefore, area of the heatsink required based on equation 21 is 10.5 cm2.

A suitable heatsink is Digikey part no 294-1025-ND. The dimensions of this heatsink are 35.05mm x

6.35mm x 44.45mm. Similarly, the other heatsinks are chosen.

2.9 Design of the RC snubber

Power semiconductors are the heart of power electronics equipment. Snubbers are circuits, which are

placed across semiconductor devices for protection, improve performance and achieve one or more of the

following:

· Reduce or eliminate voltage or current spikes

· Limit dI/dt or dV/dt

· Shape the load line to keep it within the safe operating area (SOA)

· Transfer power dissipation from the switch to a resistor or a useful load

· Reduce total losses due to switching

· Reduce EMI by damping voltage and current ringing

The snubber circuit used is shown in Fig

27
To achieve significant damping CS > Cp , where Cp is the output capacitance of the switch. A good first

choice is to make CS equal to twice the sum of the output capacitance of the switch and the estimated

mounting capacitance. RS is selected so that RS=V / I . This means that the initial voltage step due to the

current flowing in RS is no greater than the clamped output voltage. The power dissipated in RS can be

estimated from peak energy stored in CS is

C sV 2
Ep = (39)
2
This is the amount of energy dissipated in R s when C s is charged and discharged so that the average

power dissipation, Pdiss , at a given switching frequency (fS) is

Pdiss = Cs V 2 fS (40)

Depending on the amount of ringing the actual power dissipation will be slightly higher than this.

For IRFP 260N, Coss = 603pF and an additional mounting capacitance of 40pF can be considered. Thus

the value of Cs should be 1286 pF. The resistance should be 4.7Ω.

For the IGBT, IRG4BC30UD, output capacitance is 73pF. Hence, snubber capacitance of 200pF is

suitable. The snubber resistance should be 47Ω.

2.10 Important component values designed for 10kw system

Based on the theory, mathematical calculations and simulation results of the 1.5kW inverter design, the

same topology has been extended to 10kW design. The following design values have been obtained.

Maximum voltage stress of the MOSFET’s : 250V ; Maximum current stress of the MOSFET’s : 329A

Maximum voltage stress of the IGBT’s : 500V ; Maximum current stress of the IGBT’s : 80A

DC capacitors : 2200uF/450V

Coupled inductor at the output of rectifier : 240uH at 45A

Output Filter Capacitor : 135uF/250V ; Output Filter Inductor : 180uH

For the transformer design, Magnetics Inc, ferrite U type core 49925 is suitable.

28
3.0 Manufacturing Issues

Presently a laboratory level prototype is being developed at the power electronic laboratory at UCF. For

the purpose of this competition, all the necessary manufacturibility has been addressed to meet the desired

specifications. The most important aspect was meeting the FCC Class A industrial requirements for

conducted and radiated EMI. The FCC ClassA standards considered for design is discussed in Table 1.

Frequency Radiated Emissions (10m) µ V/m

dBµ
(MHz) µ V/m
30-88 90 39
88-216 150 43.5
216-960 210 46
>960 300 49.5
Frequency Conducted Emissions dBµµV
(MHz) µV
0.45-1.705 1000 60
1.705-30 3000 69.5

Table 1: FCC Emission Limits for Class A Digital Devices

3.1 Electrical Mounting and Termination

As with any precision electronic device, proper mounting and electrical termination is necessary for the

trouble free and reliable operation of the circuit. Improper electrical termination can cause damage to the

electrical connectors, resulting in the inverter's failure. Improper mounting of the devices can create

stresses (both thermal and mechanical) within the inverter, possibly shortening the operation life of the

device.

3.2 PCB Trace selection

When a component is electrically mounted to a printed circuit board, there are essentially two methods of

actual mounting: soldering the component directly to the printed circuit board, and using a single socket

(or dual socket). Either method has its advantages and disadvantages; however, a socket method of

mounting may be preferred in a field repairable system. Direct soldering has the immediate advantage of

ease of manual mounting; however, it may suffer from service related, and automated assembly

drawbacks.

29
Not surprisingly, choosing a printed circuit board track size is slightly more complex than choosing a

specific wire gauge, given a particular current. In printed circuit board applications, the maximum

allowable temperature rise of the track becomes an important design consideration. Table 2 is a general

guideline for the current carrying capacity of different external, plated, printed circuit board track sizes

for different temperatures and copper sizes.

Temperature Rise 10oC 20oC 30oC

Copper 2 oz 2oz 2 oz
Trace Width (mil) Max Current (A) Max Current (A) Max Current (A)
.010 1.4 1.6 2.2
.015 1.6 2.4 3.0
.020 2.1 3.0 3.6
.025 2.5 3.3 4.0
.030 3.0 4.0 5.0
.050 4.0 6.0 7.3
.075 5.7 7.8 10.0
.100 6.9 9.9 12.5
.200 11.5 11.0 20.5
.250 12.3 20.0 24.5

Table 2: PCB trace selection guideline

As observed from the previous table, printed circuit boards cannot handle large currents unless proper

track width and copper weight is used. (for example, PC Board mounting for the input section carrying

about 40A is only recommended when specific care is taken such as a 3 oz. copper PCB with two 75 Mil

tracks handle the current ). A 10°C temperature rise is quite acceptable, however, a 45°C temperature rise

is not recommended for continuous use. Track width should be increased to carry the current and reduce

self-heating.

Another important point that requires mentioning concerns the presence of multiple pins for apparently

the same function. In order to eliminate possible damage to the power pins, each pin of the same function

should be externally wired in parallel to spread the current over the required number of pins.

3.3 Heat Sink Issues

The next issue concerning manufacturability is designing of proper heatsinks for the power devices and

IC’s. The reliability and longevity of any semiconductor device is (roughly) inversely proportional to the

30
square of the junction temperature change. Thus halving the junction temperature will result in

approximately 4 times the expected life of the component. The converse is also true! A worthwhile

increase in reliability and component life can be achieved by a relatively small reduction in operating

temperature, since these parameters increase exponentially as temperature is reduced. The whole process

of removing heat from a semiconductor's active area (the die or 'junction') involves many separate thermal

transfers. In order to see a meaningful result, we need a heat-input value and an ambient air temperature.

From these two basic elements, the entire heat flow can be established.

Fig. 10 shows the equivalent circuit for a heat sink illustrating the thermal resistances and junction

capacitors.

The thermal resistance between a transistor junction and the ambient air determines whether a heat sink is

adequate. This thermal resistance is defined as follows:

( T j − TA )
R ja =
P

where:

R ja = junction to ambient thermal resistance

T j = junction temperature

TA = ambient temperature

P = power dissipation

The thermal resistance of the package is a critical component of the overall thermal resistance, as shown

by the following formula:

R ja = R jc + Rca

where:

31
 T j − TC
R jc = junction to case thermal resistance =
P

Tc − TA
Rca = case to ambient thermal resistance =
P

When a heat sink is added to the package, the equation becomes more complex:

R j a ( H S ) = R jc + Rcs + Rsa

where:

Rcs = case to sink thermal resistance (this is the resistance of the epoxy, thermal grease, adhesive pad, etc.

Tc − THSB
that is used to create a thermal bond between the package and the heat sink) =
P

THSB − TA
Rsa = heat sink thermal resistance =
P

THSB = temperature at the heat sink base

Rth (j-case) Rth (case-hs) Rth (hs-amb)

Heat
Source
Cj C case C hs

Fig 10: Thermal resistance

An ambient temperature of 25 oC is a good starting point, and provides a safety margin for most domestic

systems, although as we shall see later on, it is important to design for worst case if reliability is to be

maintained. The primary aim of the heatsink design is to ensure that the total thermal resistance is kept to

the minimum possible value, and the entire design process looks at thermal resistance as the primary item

to be calculated. Only after this has been determined can the actual temperature of the transistor junction

be predicted. Aluminum oxide (anodized aluminum) is an excellent electrical insulator, and provides very

good heat transfer, but is fragile and easily damaged. Even a small scratch will generally allow an

32
electrical short circuit, and obtaining a consistently thick (relatively speaking) layer of oxide is difficult in

the extreme in mass produced heatsink extrusions.

One of the most common mistakes made, is to assume that if a little thermal compound is good, a lot

must be better. Absolutely not so! The amount of thermal compound should be exactly that amount which

ensures that an air-free join is made between the mating surfaces. If too much is applied it will cause an

increase in thermal resistance, since it is not that good at conducting heat. Generally speaking, any

electrical insulator is also a thermal insulator, so the thinner the final composite insulation - including

thermal "grease" - the better. The procedure applied by the students is - Apply a small quantity of the

thermal compound to one finger, then gently rub with the thumb to create an approximately even coating

on finger and thumb. Then rub the thermal compound onto a washer, held between thumb and finger,

ensuring that the coating is just thick enough to be opaque, but thin (and even) enough to ensure that the

contact will be absolute on both surfaces (transistor and heatsink). There is only one thing on a heatsink

that actually gets rid of heat to the surrounding air - surface area. The higher the surface area, the more

heat will be disposed of. Heat is lost to the air by two mechanisms, and both should be maximised for best

performance:

• Conduction / Convection

• Radiation

Conduction (and / or convection) requires that there is a continuous stream of air flowing past the fins of

the heatsink, which means that the fins should be vertical if at all possible. Horizontally oriented fins will

lose a vast amount of thermal transfer, since the air cannot flow through to the body of the heatsink.

Radiation requires that the surface has the maximum emissivity of heat, and this means that its colour is

important. Matte black heatsinks are the best for radiation, and will have a significantly better thermal

resistance than any other. This is one of the reasons that aluminum is so popular as a heatsink material - it

can be anodized, and black dye is then introduced into the porous layer of aluminum oxide.

33
3.4 Wiring Considerations:

One of the most important wiring considerations is that control wire and power wires should never run

parallel to each other. They should be at least 20cm apart and if possible wires should run perpendicular

to each other. For the control connection, shielded wire should be used and the shield should be connected

to earth at both ends of termination. Also since the control signal is 0-5V analog signal, the length of the

wire between the control terminals should not be more than 2m. This places a restriction on the distance

of between the inverter and the Fuel Cell. Furthermore, mounting of the boards inside the inverter cubicle

is of prime importance. It should be mounted firmly to reduce the risk of damage due to vibrations while

operation. The magnetic components and the driver circuit of the inverter should be designed such that it

produces minimum noise.

All the nuts, bolts and screws used should be of brass, which is light in weight and provides conduction

path for ESD to be grounded.

34
4.0 Educational Impact

4.1 About the university and college

The unparalleled growth and development of University of Central Florida's College of Engineering and

Computer Science is one of those community success stories that can make us all justifiably proud.

Chartered in 1963, the first students arrived in 1968, with initial enrollment numbering 188 in the College

of Engineering. In the Fall of 2000, engineering enrollment was about 4,300, placing UCF in the top 16

percent of all similar colleges in the United States. The charter-engineering faculty numbered eight,

today 150, plus about 30 from other colleges and institutes holding joint appointments in the College. The

College of Engineering and Computer Science has a vision for the future that is made possible through

the dedication of the administrators, faculty, and staff associates within the college who are committed to

the students whom they serve. Three minority and three women students were enrolled in the charter

class, today there are over 600 minority and 700 women. The college is the administrative arm of three

engineering Departments, (Civil and Environmental Engineering, Industrial Engineering and

Management Systems and Mechanical Materials and Aerospace Engineering), a School of Electrical

Engineering and Computer Science, an Engineering Technology Department, and two ROTC units.

There are nine baccalaureate degree programs, 16 masters programs, and eight Ph.D. programs within the

college.

4.2 Power Electronics Progress at UCF

UCF offers graduate and undergraduate level courses in Power Electronics as part of the Electrical

Engineering (EE) degree program. Power Electronics has been as a sub-track in the School of Electrical

Engineering and Computer Science at the University of Central Florida since 1991, when Dr. Batarseh

joined the institution. Two years ago, in order to highlight the importance of educational and research

activities in power electronics at UCF, Florida Power Electronics Center (FloridaPEC) was established.

Website is http://floridapec.engr.ucf.edu FloridaPEC’s objective is to carry out research and development

activities in the area of power electronics to improve efficiency, power density, performance and most

importantly make the systems practical and cost effective. The main objective for participating in the

35
Future Energy Challenge 2001 has been to bring an awareness among the budding undergraduate

engineering students about the present day energy situations and possible solutions that the field of power

electronics offers. We believe student participation in this project will allow them to experience first hand

the theoretical and experimental side of the field of power electronics, which provides a very attractive

career opportunity.

4.3 Student Participation in the project

Students having background in power electronics topics were chosen for this project. The team consists of

four undergraduate students and one Masters student. Three of the undergraduates are participating as

members of the capstone senior design project. The project provided the students a wonderful opportunity

to acquire necessary skills and design tools with a practical real life design problem.

The starting point of any project is a good and extensive literature review. The students did an extensive

literature review and that provided the students a good idea about the latest developments in the field of

inverters. Since the inverter was meant for domestic use, the prime goal was that the topology used should

be simple and easy to implement. Also it should be absolutely maintenance free.

The most challenging aspect in the topology chosen was the DC-DC push-pull converter. The presented

push-pull configuration is good for medium to high power applications is around 15kW maybe, beyond

which handling the high input current and keeping the ripples low becomes a tough task. Also making the

inverter compact was another major consideration for choosing the push-pull configuration. At the

proposal writing stage, we did propose to use two parallel half-bridge inverter stages to realize the three-

wire output configuration. That meant that we would have to use extra secondary winding and extra diode

bridge rectifier. However later we did modify the topology without having to put the additional circuitry.

Since this is an unfunded project for FloridaPEC, design optimization was of prime importance for cost

control. All the available resources were put to best possible use. The aim was to build a laboratory level

1.5kW prototype, which meets most of the designed specifications technically and commercially. Based

on the rules of the competition, if the prototype is selected for final testing, then the issues of packaging,

transportation will be taken care of.

36
Another very important thing from the educational point of view was not a single item has been out

sourced for manufacturing. Every item has been built in the laboratory including the main transformer,

inductors and the PC board.

4.4 Project Design Steps

After the components were designed and results verified mathematically, the following systematic

approach was followed:

Identification of vendors: Each student was given the task of identifying vendors for each of the

components, analyze their products, compare specs with other vendors, contact them for samples and

finally to try and match with the components already existing in our lab. This did provide the students the

opportunity to have conversations with technical experts from industry.

Procurement of components: All the components for this project are procured from Digikey. An online

account was established with Digikey for purchasing components and the students managed the same. At

end of each week, the list of expenditures was submitted to the administrative department for accounting

purposes. Therefore, cost over run was always kept in check.

Designing of magnetic components: A complete systematic design procedure was used for the

magnetics design. Companies like Magnetics and Micrometals did help the university by sourcing sample

cores and bobbins. The students using appropriate wire gauge wound the transformer and inductors. After

the winding, the proper air gap was adjusted and the cores were packed. An Impedance Analyzer was

used to test the values of the magnetic components and the measured values did match the expected

values. For example, the output filter inductor was designed for 2mH. The result from the impedance

analyzer showed Inductance = 1.9mH and the measured resistance was 0.2 ohms.

PCB Layout: The PCB layout was done using Layout Plus software from ORCAD. After finishing the

layout the PC board was etched in the lab by using the T-Tech PCB maker, model Quick circuit 5000.

Special attention was paid to the PCB trace thickness, separation of analog and digital and power signals

for minimizing EMC problems.

37
DSP software development: For this project the TMS320F240 evaluation module was used. This

evaluation module was already available in our lab and hence the same was used. The development of

software for this DSP requires lot of software development skills and is totally developed by the students.

The total software is still not complete, some parts needs to be modified further to meet all the

specifications and most importantly, the protection mechanism has to be fool proof.

4.5 Educational Benefits

Overall, the project provided a good learning experience for the five students in terms of providing:

• Technical multi-disciplinary design opportunity

• Opportunity for project planning and management

• Knowledge in manufacturing techniques

• Use of professional software packages like ORCAD, PowerSIM, PCB maker, …etc.

• How to manage expenses and reduce cost

• Learning means of effective resource utilization

• Team work and the importance of project cooperation

• Good technical and commercial Communication skills

• Realizing the acute power crisis we may face in the future and think of alternatives

• Model for senior design projects

38
5.0 Inverter Operating Instructions

Figure 11 below shows the complete panel schematics

BATTERY BATTERY FUELCELL

48V 12V 48V
_ + + - _ +

R2 NC

R1 NO

MCB1 AUX

MCB1
Relay R1

MCB2

Load
Fuse
DC Cap
Idc Iac
Push-Pull Inverter Stage Low-Pass
+ Transformer dc-ac Filter v ac
dc-dc
_
Vdc
IL
Vin PWM
Protection

PWM Vc
DSP
Iin
Analog
Output OR GATE

Inverter Fuel-cell
Relay R2
Fault Ready
Fig 11: Power panel schematic

Checklist before Powering Up

Observe all of the ESD measures when handling components.

Tighten–up all bolts and screws

Correctly, insert all connectors and lock/screw into place

Check the interconnection between the power and the control sections

Observe the power–on sequence as described below

39
If the unit is frequently powered–down and up, the DC link capacitors retains high voltage even when the

main supply to the inverter is OFF. Only discharge the unit at the DC link buses through a minimum of

10W.

All switches should be in OFF position

Ground all components and connect all of the shields.

Board Designations

A1 : Power Board : Houses the power devices and the power circuitry

A2 : Interface Board : Houses the feedback and the driver circuitry

A3 : DSP Evaluation Board

Power Up and Operation Guidelines

• Make the power connections

• Turn ON the power supply to the DSP evaluation board

• Turn the power supply for the interface board ( from the Battery bank )

• Put the Main Power supply MCB ON ( the battery supplies the Inverter )

• The auxiliary contact of the MCB turns the battery contactor ON.

• The main contactor coil is connected through the NC contact of a control relay, which is

controlled by the analog output of the DSP.

• Inverter starts up and the DSP generates a signal “ Inverter ON “. This signal is given to the Fuel

Cell Controller

• Inverter keeps running on battery till the fuel cell controller generates the signal “ Fuel Cell

Ready “

• Once the Inverter controller receives the ready signal from the Fuel Cell controller, the power

from the battery is cut off through a contactor, after a finite delay. This delay is programmable.

This feature ensures that the inverter actually runs from the fuel cell supply and not supported by

the battery. Battery is used only for back up supply.

40
• During operation, the “available power level” signal from the fuel cell controller is compared

with the “required power level “ signal of the inverter. Whenever “required power level” is

greater than “available power level”, the battery contactor turns ON.

• The control relay operates only when the Fuel Cell Ready signal (H = 5V) is received by the

inverter controller.

• Under any fault condition, the driving signal from the Inverter controller is inhibited and

“Inverter Trip “ signal is generated. This signal also drops out the battery contactor.

• Inverter Status is available through the 9-pin RS232 port and the same port can be used for

troubleshooting the inverter. Necessary software will be supplied.

41
6.0 Simulation and experimental results

The 1.5kw and 10kw circuit has been simulated using Pspice schematics. The simulation circuits are

shown in Appendix C.

480V pk-pk

Differential current for a resistive load of 35Ω

Fig 12: Differential Voltage and current waveform under normal resistive load

Fig 13: Phase 1 and Phase 2 voltage waveform

42
 Fig 14: DC positive and negative bus voltage

Fig 15 : Maximum voltage stress across switches : MOSFET1,MOSFET2,IGBT1,IGBT2,IGBT3,IGBT4

43
 Fig 16: Load current waveform under unbalanced load conditions

Fig 17: Output Filter Capacitor voltage waveform under unbalanced load conditions

Fig18: Output Filter Inductor current waveform under unbalanced load conditions

44
 Fig 19: Voltage feedback waveform for DSP

Fig 20: Current feedback waveform for DSP

Fig 21: Voltage and current waveforms for 10kW system

45
Experimental Result of 1.5Kw prototype output waveform

46
7.0 Cost Evaluation Spreadsheet

The modified cost evaluation spreadsheet prepared by the Organizing Committee is attached for both the

1.5kw prototype and 10kw system. A major factor in selection of the components is the rate of

obsolescence. Care has been taken to ensure that all the selected components especially the power devices

and the driver IC’s will be supplied by the respective companies for the next 10 years. Hence the

servicing of the product will not be affected even if the components are no longer produced.

In the cost evaluation spreadsheet, exact cost headers considered under the items Losses, Control and

Packaging is not very clearly explained. Hence we have considered $ 50 for the 1.5kw and $100 for the

10kw system under the item “Other”. This includes costs towards

• Protection Fuses, PCB Board

• Cables ( Control and Power )

• Battery Charger

• Surge suppressors

• EMI filter

• Sensors

• Terminal connectors ( ELMAX )

• Electricity, Telecommunication and stationary

The design of feedback circuitry and the DSP control scheme including software does not change with the

increase of power rating and hence the increase in cost towards these items is not proportional to power

rating. The costing principle followed should be “Activity based costing” as that is most logical for mass

production in a factory. The complete process of from the design table to the completed product is broken

up into activities and each activity is assigned a cost. The prototype is developed totally inside the school

lab and hence the spreadsheet calculation may not reflect the exact costing especially the magnetic

components.

47
 2001 FUTURE ENERGY CHALLENGE : 1.5kW COSTING

UNIVERSITY: University of Central Florida

NAME OF MAIN CONTACT: Dr Issa Batarseh
PROJECT NAME: EnergyChallenge 2001
DATE: 15th June, 2001

VOLT VOLT CUR CUR UNITEXTENDED

DEVICE QTY DESIG UNITMEASURE (Vpk) (Vrms) (Avg) (Arms) COST COST
DIODE 4 D1-D4 500 10 2.51 10.05
IGBT 4 Q3-Q6 600 20 4.86 19.44
MOSFET 4 Q1-Q2(2 Parallel) 200 45 8.65 34.58
CAP (ALUM) 2 C1,C2 560 uF 450 15.80 31.61
CAP (ALUM) 3 CIN 0.22 uF 100 0.10 0.31
CAP (FILM) 2 C3,C4 10 uF 400 7.98 15.96
POWER RESISTOR 4 R1-R4 50 W 2.64 10.56
CHOKE 3 L1,L2.L3 2000 UH 8 47.76 143.29
TRANSFORMER 1 T1 48 55 9.17 9.17
CONTACTORS 2 M1,M2 48 55 4.74 9.48
CONTACTORS 1 Relay 1 5 1 2.83 2.83
LOSSES 200 W 16.67 16.67
CONTROL 60.79
PACKAGING 45.59
OTHER (EXPLAIN) 50.00
TOTAL 460.33
 2001 FUTURE ENERGY CHALLENGE : 10kW COSTING

UNIVERSITY: University of Central Florida

NAME OF MAIN CONTACT: Dr Issa Batarseh
PROJECT NAME: EnergyChallenge 2001
DATE: 15th June, 2001

VOLT VOLT CUR CUR UNITEXTENDED

DEVICE QTY DESIG UNITMEASURE (Vpk) (Vrms) (Avg) (Arms) COST COST
DIODE 4 D1-D4 500 45 4.10 16.39
IGBT 4 Q3-Q6 600 50 11.98 47.91
MOSFET 6 Q1-Q2(2 Parallel) 200 100 14.57 87.42
CAP (ALUM) 2 C1,C2 2200 uF 400 48.84 97.68
CAP (ALUM) 3 CIN 0.22 uF 100 0.10 0.31
CAP (FILM) 2 C3,C4 120 uF 250 35.07 70.15
POWER RESISTOR 4 R1-R4 100 W 4.24 16.96
CHOKE 3 L1,L2.L3 180 UH 45 61.19 183.56
TRANSFORMER 1 T1 48 225 18.16 18.16
CONTACTORS 2 M1,M2 48 225 10.65 21.29
CONTACTORS 1 Relay 1 5 1 2.83 2.83
LOSSES 1000 W 83.33 83.33
CONTROL 129.20
PACKAGING 96.90
OTHER (EXPLAIN) 100.00
TOTAL 972.09
 References Cited

[1] Energy Challenge website http://www.energychallenge.org

[2] Ying-Yu Tzou; Shih-Liang Jung, “Full control of a PWM DC-AC converter for AC voltage regulation”,

Aerospace and Electronic Systems, IEEE Transactions on, Volume: 34 Issue: 4, Oct. 1998 Page(s): 1218 –1226

[3] Shireen, W.; Arefeen, M.S., “An utility interactive power electronics interface for alternate/renewable energy

systems”, Energy Conversion, IEEE Transactions on, Volume: 11 Issue: 3, Sept. 1996 Page(s): 643 –649

[4] Chiang, S.J.; Liaw, C.M., “Single-phase three-wire transformerless inverter”, Electric Power Applications,

IEEE Proceedings-, Volume: 141 Issue: 4, July 1994 Page(s): 197-205

[5] Venkataramanan, G.; Divan, D.M., “Pulse width modulation with resonant DC link converters”, Industry

Applications, IEEE Transactions on, Volume: 29 Issue: 1 Part: 1, Jan.-Feb. 1993 Page(s): 113 -120

[6] Gui-Jia Su; Ohno, T., “A new topology for single phase UPS systems”, Power Conversion Conference –

Nagaoka 1997, Proceedings of the, Volume: 2, 1997 Page(s): 913 -918 vol.2

[7] Mohan, N., Undeland, T., Robbin, W., (1995). Power Electronics: Converters, Applications, and Design. New

York. John Wiley & Sons, Inc.

[8] Rashid M. H., Power Electronics: Circuit Devices, and Applications. New Jersey.Prentice Hall 1993.

[9] Enrique A. Tenicela, “A Study of Pulse Width Modulation Techniques in Power Static Inverters ”, a thesis

submitted in partial fulfillment of the requirements for the Honors Program at UCF, Orlando, Florida.

[10] Texas Instrument website http://www.ti.com

[11] Pekik Dahono, A Purwadi and Qamaruzzaman, “ A LC Filter design for single phase PWM inverters”

[12] US Department of energy website http://www.energy.gov

[13] Powerdesigners Inc website http://www.powerdesigners.com

[14] Dr Issa Batarseh, “Introduction to Power Electronics”, chapter 4,5 and 9.

[ 15] Colonel Wm T Mclyman , "Magnetic Core Selection for Transformers and Inductors"
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