Académique Documents
Professionnel Documents
Culture Documents
Level to
L Pulse P
Converter
...output P produces a
Whenever input L goes
single pulse, one clock
from low to high...
CLK period wide.
unsynchronized Level to
user input
D Q D Q L Pulse P
FSM
CLK
00 01 11
L=0 Low input, High input,
Waiting for rise
Edge Detected!
Waiting for fall
L=1
P=0 P=1 P=0
L=0
L=0
“if L=0 at the clock edge, This is the output that results from
then stay in state 00.” this state. (Moore or Mealy?)
present state S
S1 = LS0
+
P = S1S0
S0 + = L
D Q
S1 + S1
Q
S+ Comb.
Comb. D Flip- Q
n Logic
Logic Flops
CLK
n
S
• Since outputs are determined by state and inputs, Mealy FSMs may
need fewer states than Moore FSM implementations
P
S+ S
L D Q
CLK Q
S
L L
P P
Clock Clock
State[0] State
1
D Q LIGHT
BUTTON D Q
CLK
STEPS:
1.Design lock FSM (block diagram, state transitions)
2.Write Verilog module(s) for FSM
lock
Clock
fsm_clock fsm
generator
unlock Unlock
reset button LED
Button
reset
Enter
RESET
1
1 0
0
1 0
0
“01011” 1 “0101” 1 “010”
Unlock = 1 Unlock = 0 Unlock = 0
6 states → 3 bits
6.111 Fall 2007 Lecture 7, Slide 11
Step 2: Write Verilog
module lock(clk,reset_in,b0_in,b1_in,out);
input clk,reset,b0_in,b1_in;
output out;
// generate output
assign out = ???;
// debugging?
endmodule
6.111 Fall 2007 Lecture 7, Slide 12
Step 2A: Synchronize buttons
// button -- push button synchronizer and level-to-pulse converter
// OUT goes high for one cycle of CLK whenever IN makes a
// low-to-high transition.
0 1
parameter S_010 = 3; RESET
Unlock = 0
“0”
Unlock = 0
“01”
Unlock = 0
parameter S_0101 = 4;
0
parameter S_01011 = 5; 1 0
0
“01011 ” 1 “0101 ” 1 “010”
reg [2:0] state, next_state; Unlock = 1
Unlock = 0 Unlock = 0
input clk,reset,b0_in,b1_in;
output out; output[3:0] hex_display;
D Q CLK2
CLK1 CLK1
6.111 Fall 2007 Lecture 7, Slide 17
Summary
• Modern digital system design:
– Hardware description language FPGA / ASIC
• Toolchain: Simulate
– Design Entry Synthesis Implementation
• New Labkit: Design Entry
(Verilog)
– Black-box peripherals
(modelsim)
Simulation
*.v
Synthesis
– Almost all functionality (xst)