A NEW COMPENSATION TECHNIQUE FOR TWO-STAGE CMOS

OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS

Mohammad Yavari, Hashem Zare-Hoseini, Mohammad Farazian, and Omid Shoaei

IC Design Lab, ECE Department, University of Tehran, Tehran 14395-515, Iran

E-mail: myavari@ut.ac.ir

ABSTRACT analyzed and a set of system parameters is also obtained.

Design procedure for this OTA with its proposed
This paper presents a new compensation method for fully compensation method is described in section (3). Section
differential two-stage CMOS operational (4) presents simulation results. Finally, conclusions are
transconductance amplifiers (OTAs). It employs a hybrid summarized in section (5).
cascode compensation scheme, merged Ahuja and
improved Ahuja style compensations, for fast settling. A 2. PROPOSED COMPENSATION TECHNIQUE
design procedure for minimum settling time of the
proposed compensation technique for a two-stage class Fig. 1 shows a two-stage class A/AB OTA structure [4].
A/AB OTA is described. To demonstrate the usefulness of The first stage is a folded cascode amplifier with PMOS
it, three design examples are considered. input transistors. The second stage is a class AB amplifier
with active current mirrors. Due to class AB operation of
1. INTRODUCTION this stage, slew limiting only occurs in the first stage
which results in low power consumption.
Design of high performance analog circuits is becoming
Vdd
increasingly challenging with the persistent trend toward
reduced supply voltages. The main bottleneck in an M4a
Vb4 Vb4
M4b
cmfb1
analog circuit is the operational amplifier. The realization N3 N3
Cs
of a CMOS operational amplifier that combines high dc Cs
M3a
Vb3 Vb3
M3b
outp
gain with high unity gain bandwidth has been a difficult outn N2 N2
in+ in-
problem especially in low voltage circuits. The high dc Vb2
M2a
M1a M1b
M2b
Vb2

gain requirement leads to multistage designs or cascoding Vout+

N1 N1
Vout-

Ca Vdd Vdd
of transistors with long channel devices biased at low Cl
Ca
Cl
current levels, whereas the high unity gain frequency outp
Vb1
outn

requirement calls for a single stage design with short

channel devices biased at high bias current levels. M5a M5b

Cascoding is a well-known means to enhance the dc gain

of an amplifier without degrading the high frequency
performance. But cascoding is not possible in the low
voltage circuits. Another technique to achieve both high
DC gain and unity gain bandwidth is to employ gain
boosting [1], [2]. But in this technique at least four
transistors should be cascoded at the output, which
decreases the output voltage swing. In the other hand, a
two-stage OTA can be used to satisfy the high dc gain
requirement for high-speed applications.
Design of two-stage opamps needs some forms of
compensation to maintain the stability. It has been shown
that the cascode compensation scheme yields a higher
amplifier bandwidth compared to the conventional miller
compensation [3]. In this paper a hybrid cascode
compensation technique is proposed which results in fast
settling in two-stage opamps.
In section (2) a two-stage class A/AB OTA structure
with new compensation method is considered and
Fig. 1: A two-stage class A/AB OTA with proposed
compensation method.
Frequency compensation is needed to maintain stability
in a two-stage amplifier. The standard miller
compensation has a pole splitting effect, which moves one
pole to a lower frequency and the other to a higher
frequency [5]. The two-stage amplifier shown in Fig. 1
employs the hybrid cascode compensation scheme,
merged Ahuja [3] and improved Ahuja style [6]
compensation methods, which creates two real poles, two
complex poles at a higher frequency, and three zeros. This
scheme of compensation yields a higher amplifier
bandwidth compared to the standard miller and
conventional cascode compensation techniques at the cost
of more complex design procedure for the settling
behavior of the amplifier. Since the proposed
compensation scheme creates an amplifier with four

0-7803-8163-7/03/$17.00 © 2003 IEEE ICECS-2003

539
closed-loop poles and three zeros, the design equations techniques are shown as a function of the total
become significantly more complicated than those of a compensation capacitance in Fig. 3. In these simulations
single-stage or conventional miller and cascode the small signal parameters shown in Table (1) have been
compensated two-stage amplifier. This implies that for used. The proposed compensation technique can give a
practical designs some form of computer optimization smaller settling time compared to the other alternatives.
constrained by the tradeoffs in the design equations will -8
x 10
4
be necessary.
3.5 0.01% settling error

v1 g m 2v 2 3
v2
Ca

Settling time [sec]

+ v3 2.5
− f vo − g m3 v 4
g m1v1
vin + C1 C2 Cs vo 2
− v4
1.5 Ahuja
C3 ( g m 4 + g m 5)v3 CL
Yao
Cs = 1pF
1 Cs = 2pF
Cs = 2.5pF
Fig. 2: Closed-loop small-signal equivalent circuit. 0.5
Cs = 3pF
3 4 5 6 7 8
Total compensation capacitance [F] x 10
-12

Fig. 2 shows the closed-loop small-signal equivalent

circuit for pole and zero analysis of the proposed OTA Fig. 3: Settling time with different compensation techniques.
shown in Fig. 1, where C1, C2, C3, and CL represent the
parasitic capacitances of nodes N1, N2, N3, and the output Table (1): Small-signal parameters.
node of the circuit shown in Fig. 1, respectively. f is the
feedback factor. To simplify the analysis, device output Parameter Value Parameter Value
resistances are assumed to be infinite. It should be noted gm1 4 mA/V C1 [pF] 0.206
that the effect of finite device resistance is to move the gm2 4.7 mA/V C2 [pF] 0.627
amplifier poles slightly to the left, which will slightly gm3 4.2 mA/V C3 [pF] 0.267
increase the bandwidth of the amplifier [7]. The node gm4 5.7 mA/V CL [pF] 4
equations of this circuit are as follows:
gm5 7.4 mA/V f 0.8

 g m1v1 + ( sC 1 + g m 2 ) v 2 + sC a (v 2 − vo ) = 0

sC 2 v 3 − g m 2 v 2 − g m3 v 4 = 0 3. DESIGN PROCEDURE

( sC 3 + g m3 + sC s ) v 4 − sC s vo = 0 (1)
( sC + sC + sC ) vo − sC v 2 + ( g + g )v3 − sC v 4 = 0 In order to investigate the settling behavior of the
 L a s a m4 m5 s proposed compensation technique a standard fourth order
v1 = vin − f vo system with the following transfer function is considered
The transfer function will be as follows:
k ( z p2 − s 2 )( s + c)
H (s) =
2
vo g m1 ( s C a C 2 − g m 2 g m ) ( g m3 + sC 3 + sC s ) ( s + a)(s + b)( s 2 + 2ζω n s +ω 2n )
= (2) (9)
vin s 4 d 4 + s 3 d 3 + s 2 d 2 + s d1 + d 0 k (γ 2ζ 2ω n2 − s 2 )(s + zζω n )
=
( s + αζω n )(s + βζω n )( s 2 + 2ζω n s +ω n2 )
where
g m = g m 4 + g m5 (3) where a = αζω n , b = βζω n , c = zζω n and z p = γζω n .

d 4 = C a2 C 2 ( C 3 + C s ) + C s2C 2 ( C 1 + C a ) There are six system parameters, α, β, γ, ωn, ζ and z in

(4) the transfer function. ωn and ζ are called natural frequency
− C 2 ( C L +C a + C s ) ( C 1 + C a )(C 3 + C s )
and damping factor, respectively. Fig. 4 shows the
d 3 = C a C 2 f g m1(C 3 + C s ) + C a2C 2 g m3 + C 2 C s2g m 2 description of these six system parameters by the location
− g m 2 C 2 (C L + C a + C s ) (C s + C 3 ) (5) of poles and zeros of the proposed compensation
− g m3 C 2 (C L + C a + C s ) (C 1 + C a ) technique in a practical implementation.
d 2 = f g m1g m3 C a C 2 − g m 2 g m C a (C 3 + C s )
(6) ζω n
− g m3 g m C s (C 1 + C a ) − g m 2 g m3 C 2 (C L + C a +C s )
d1 = − f g m1g m 2 g m (C 3 + C s ) − g m 2 g m3 g m C a zζω n
(7) 1 − ζ 2ω n
− g m 2 g m3 g m C s
α ζω n
d 0 = − f g m1 g m 2 g m3 g m . (8)
β ζω n
γ ζω n
γ ζω n
In order to verify the usefulness of the proposed
compensation technique, the settling time of Ahuja style,
improved Ahuja style, and the proposed compensation Fig. 4: Closed-loop pole and zero locations.

540
 In switched-capacitor circuits, the step response
determines the amplifier settling performance in the time
((α + β )ζ + 2ζ αβ )ω 3 3
n=
d1
d4
(19)
domain. It can be shown that the step response of the d0
above-mentioned fourth order system is as follows: α β ζ 2ω n4 = (20)
d4
g m3
z ζ ω n= . (21)
s(t ) = A cl { 1 − a1 × e −αζω nt − a 2 × e − βζω nt C s +C 3
 
+ a3 × e −ζω nt  a 4 × cos(ω n t 1 − ζ 2 )  (10) 50 50
  zeta = 0.7
zeta = 0.8
alpha
alpha
= 0.7
= 0.8
zeta = 0.9 alpha = 0.9
−ζω nt  2 
0 0
− a3 × e  a5 × sin(ω n t 1 − ζ )  }
zeta = 0.95 alpha = 0.95

Settling error [dB]

Settling error [dB]
alpha =1
  -50 (a) -50
(b)

Where Acl is the closed-loop gain and -100 -100

-150 -150
alpha = 1, beta = infinite, z = infinite zeta = 0.9, beta = infinite, z = infinite
β (z − α )
a1 = (11) -200
5 10 ω t 15 20
-200
5 10 15 20
2
z ( β − α )(1 − 2αζ + α 2ζ 2 ) ns ω nts

α (z − β )
a2 = (12) 50 50
z (α − β )(1 − 2 βζ 2 + β 2ζ 2 )
z = 0.7 beta = 0.7
z = 0.8 beta = 0.8
0 z = 0.9 beta = 0.9
αβζ z =1 0 beta = 0.949
a3 = Settling error [dB]

Settling error [dB]

2 2 2 2 2 2
(13) -50
(c) beta =1
z (1 − 2αζ + α ζ )(1 − 2 βζ +β ζ ) (d)

( )
-50
2 2 -100
a 4 = − zζ (α − 1)( β − 1)ζ − 1 + ζ
(14) -100
2 -150
+ (αζ − 1)(α + β − 2)ζ
{ ( )
alpha = 0.95, beta = infinite, zeta = 0.9 alpha = 0.95, z = 0.9, zeta = 0.9
-150
a5 = ( zζ 2 − 1) (α − 1)( β − 1)ζ 2 − 1 + ζ 2
-200 5 10 ω t 15 20
5 10 ω nts 15 20 ns

+ zζ 2 (1 − ζ 2 )(α + β − 2)
1
. } (15)
1−ζ 2
Fig. 5: Settling errors as a function of ω n t s for different values
of (a) ζ, (b) α, (c) z, and (d) β.
In the calculation of the step response it is assumed that
γ goes to infinity since in the practical cases the right and In these equations, the system parameters, α, β, z, ζ,
left-plane zp zero pair in the closed loop transfer function and ωn are known. The load and compensation
will be at much higher frequencies than the poles. capacitances, CL, Ca, and Cs are determined due to circuit
s(∞) − s (t s ) noise considerations. The parasitic capacitances, C1, C2,
The settling error as defined ε s = is
s (∞ ) and C3 are related to the device sizes. Also all of device
obtained by: transconductances can be expressed by transistor sizes.
So, these equations can be solved to determine the device
sizes using numerical calculations. However, these
ε s = a1 × e −αζω n t s + a 2 × e − βζω n t s
equations are very complex to solve. In order to achieve a
 
− a3 × e −ζω nt s  a 4 × cos(ω n t s 1 − ζ 2 )  (16) coarse design of the proposed opamp, some
  approximations are considered to simplify the solution of
 
+ a3 × e −ζω nt s  a5 × sin(ω n t s 1 − ζ 2 ) . the above-mentioned equations and also give an insight to
  them. In equations (4-7) the parasitic capacitances, C1,
This equation is very complex to intuitively explain how C2, and C3 are assumed to be much less than the other
to choose the system parameters to optimize the settling capacitances. In this case, equations (17-21) reduce to the
error. Therefore, numerical calculations are used. Fig. 5 following relations:
shows the settling error of the proposed compensation
technique for different values of the system parameters.
f g m1 g (C + C a )
The obtained system parameters for –120 dB settling error (α + β + 2) ω n ζ = − + m2 L
are α = 0.95 , ζ = 0.9 , z = 0.9 , β = 0.95 and ω n t s =17 . CL Ca CL
(22)
g m3(C L + C s )
The obtained system parameters for a specific settling +
error in a defined time can be used to determine the Cs CL
device parameters with the following equations: (2(α + β )ζ 2
+ αβζ 2 + 1 ω n2 = −) f g m1 g m3
Cs CL
(23)
d3 ( g m 2 + g m3) g m g g (C + C a + C s )
(α + β + 2) ω n ζ = (17) + + m 2 m3 L
d4 C2 CL Ca Cs CL
(2(α + β )ζ 2
+ αβζ 2 + 1 ω n2 = ) d2
d4
(18)

541
((α + β )ζ + 2ζ αβ ) ω
3 3
n =
f g m1 g m 2 g m
C 2 Ca C L
(24)
g m 2 g m 3 g m (C a + C s ) 0.4
+
C 2 Ca C s C L
0.2
f g m1 g m 2 g m3 g m

Voltage [V]
α β ζ 2ω n4 = (25)
C2 Ca Cs CL 0

g
z ζ ω n = m3 . (26) -0.2
Cs
-0.4 Proposed compensation method
In these equations, the transconductance of transistors Ahuja style
M1, M2, M3, and M4,5 and the parasitic capacitance of Improved Ahuja style (Yao)
-0.6
0 2 4 6 8 10
node N2, C2 are unknown and can be obtained by solving Time [sec] x 10
-9

them. Then one can run circuit level simulations to fine Fig. 6: Settling simulation results.
the obtained gate dimensions from system level
calculations. Table (2): Simulation results.

4. SIMULATION RESULTS Parameter Ahuja

Improved Proposed
Ahuja method
Power supply voltage 1.5-V 1.5-V 1.5-V
In order to demonstrate the usefulness of the proposed
DC gain [dB] 80.3 79 80
compensation technique, three different design examples
Unity gain bandwidth
with Ahuja style, improved Ahuja style, and the proposed [MHz]
137 151 167
compensation techniques were considered in the circuit Phase margin [degree] 75.5 89 73.5
level. At first, the system parameters of these design Compensation cap. 3 pF 3 pF 3 pF
examples were obtained using their settling error Load capacitance 4 pF 4 pF 4 pF
equations with numerical calculations. Then, their circuits Settling time (0.01%) 10.1 ns 12.4 ns 7.1 ns
were simulated in a 0.25-µm CMOS technology with Output swing [Vpp] 1.13 1.13 1.13
HSPICE. In these simulations, the OTAs were designed Input referred thermal
1.6×10-16 1.5×10-16 1.2×10-16
for a fully differential switched-capacitor integrator where noise [V2/Hz]
sampling, integrating and load capacitances are 2.5pF, Power consumption 8.9 mW 8.9 mW 8.9 mW
10pF and 2pF, respectively. The bootstrapped switches
proposed in [8] have been used in these designs. In Fig. 6
7. REFERENCES
the settling behavior of the proposed OTA with three
different compensation methods are shown. Simulation [1] K. Bult and G. J. G. M. Geelen, “A fast-settling CMOS
results are given in Table (2). opamp for SC circuits with 90-dB DC gain,” IEEE Journal
Solid-State Circuits, vol. 25, no. 6, 1379-1384, Dec. 1990.
5. CONCLUSIONS [2] K. Gulati and H.-S. Lee, “A high-swing CMOS telescopic
operational amplifier,” IEEE Journal Solid-State Circuits,
vol. 33, no. 12, pp. 2010-2019, Dec. 1998.
In this paper a new compensation technique for two-stage [3] B. Ahuja, “An improved frequency compensation
CMOS OTAs has been proposed. It employs merged technique for CMOS operational amplifiers,” IEEE Journal
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settling compared to conventional miller, Ahuja style, and [4] M. Yavari and O. Shoaei, “Very low-voltage, low-power
improved Ahuja style compensation techniques at the cost and fast-settling OTA for switched-capacitor applications,”
of more complex design procedure. A design procedure is in 14th IEEE International Conference on Microelectronics,
also considered for the proposed OTA. ICM, pp. 10-13, Dec. 2002.
[5] B. Razavi, Design of analog CMOS integrated circuits,
McGraw-Hill, 2000.
6. ACKNOWLEDGEMENT [6] L. Yao, M. Steyaert, and W. Sansen, “Fast-settling CMOS
two-stage operational transconductance amplifiers and their
This work was supported in part by a grant from the systematic design,” IEEE Symposium on Circuits and
University of Tehran research budget under the contract Systems, ISCAS, vol. 2, pp 839-842, May 2002.
number 612/3/816. [7] A. Feldman, High-speed, low-power sigma-delta
modulators for RF baseband channel applications, Ph.D.
Dissertation, University of California at Berkeley, 1997.
[8] M. Dessouky and A. Kaiser, “Very low-voltage digital
audio ∆Σ modulator with 88-dB dynamic range using local
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