Code No: 07A6EC03 R07 Set No.

2
III B.Tech II Semester Regular/Supplementary Examinations,May 2010
VLSI Design
Common to BME, ETM, E.CONT.E, ECE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain the principle of a DRAM cell.

(b) Give the schematic of a DRAM and explain how READ and WRITE opera-
tions are carried out. [4+12]

2. (a) Explain about Configurable Logic Blocks, CLBs.

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(b) What are FPGAs? Explain the principle and operation.

. c [8+8]

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3. Explain about Gate level verification and timning Reports pertaining to VLSI De-
sign. [16]

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4. Explain about various processing steps involved in IC Technology for the fabrication
of MOS ICS. [16]

5. Explain about NOR CMOS Logic.

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6. Draw the circuit for nMOS Inventer and explain its operation and characteristics.
[16]

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7. (a) Explain about system level Testing.
(b) Give the Architecture of a boundary scan test and explain the same. [6+10]

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8. (a) What is a tub tie? Explain this with an example.
(b) Draw Stick diagram for CMOS Inverter, giving explanation. [6+10]

?????

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Code No: 07A6EC03 R07 Set No. 4
III B.Tech II Semester Regular/Supplementary Examinations,May 2010
VLSI Design
Common to BME, ETM, E.CONT.E, ECE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain the principle of PLA. What are the advantages and disadvantages of
PLA’s.
(b) Explain about the applications of PLA’s. [10+6]

2. What are various design tools used in VLSI design? Explain them?

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3. (a) What are the advantages and disadvantages of Dynamic Logic? Explain.

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(b) Draw the basic structure of a Dynamic CMOS gate and explain the same.
[8+8]

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4. (a) With the help of sketches explain the principles of different types of diffusion’
Processes.

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(b) Explain about Fick’s laws of diffusion.

5. (a) Explain about Design Rule Check. Why is it employed?

[10+6]

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(b) For various processes in MOS IC fabrication, explain about Design Rules.
[8+8]

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6. (a) With the helpk of a schematic explain about Memory-self Test.
(b) What are the issues to be considered while implementing BIST? Explain.[8+8]

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7. (a) Draw the schematic and explain the principle and operation of Array Multi-
plier.
(b) Draw the schematic and explain the working of Tree Multiplier. [8+8]

8. (a) Derive the expression for figure of merit ω0 of MOSFETs.

(b) Explain about Body effect parameter ‘ν’ of MOSFETs. [8+8]

?????

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Code No: 07A6EC03 R07 Set No. 1
III B.Tech II Semester Regular/Supplementary Examinations,May 2010
VLSI Design
Common to BME, ETM, E.CONT.E, ECE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain about the concepts of Sheet Resistance.

(b) Derive the expression for time delay τSD in the case of MOSFET. [8+8]

help ofr stick diagram.

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2. Draw the logic diagram of zero/one dectector and explain its operation with the
[16]

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3. Explain about different steps involved in the IC fabrication briefly. [16]

4. (a) Explain about leakage current problems in MOSFETs.

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(b) Explain the terms Figure of Merit of MOSFET and output conductance, using
necessary equations.

5. Write notes on any TWO

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(a) DGT
(b) BIST

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(c) Boundary scan Testing.
tu [8×2=16]

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6. With a schematic explain about synthesis process.

7. (a) Explain about configurable FPGA based I/O blocks.

[16]

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(b) What are the various aspects to be considered in selecting a particular switch-
ing technology? Explain.

8. (a) Explain about the effect of scaling on MOSFET parameters

[10+6]

i. Channel Resistance.
ii. Transistor Delay
iii. Switching Energy
iv. Power Dissipation
(b) Explain about the difficulties arising due to scaling. [8+8]

?????

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Code No: 07A6EC03 R07 Set No. 3
III B.Tech II Semester Regular/Supplementary Examinations,May 2010
VLSI Design
Common to BME, ETM, E.CONT.E, ECE, EEE
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Explain about Stuck-at Faults and BIST pertaining to VLSI Testing. [16]

2. (a) Explain the principles of SRAM and DRAM.

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(b) What are the advantages of SRAM and DRAMs compare them in all respects.
[6+10]

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3. Draw the circuits for n-MOS, p-MOS and C-MOS Inverter and explain about their

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operation and compare them. [16]

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4. (a) What are the difficulties that arise due to MOS scaling? Explain.
(b) Explain the different types of design rules and give some examples. [8+8]

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5. (a) Explain about ‘Mapping Process’.
(b) What is the purpose of ‘constraints’ in synthesis process? Explain. [8+8]

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6. Draw the circuit for CMOS Inverter and explain the transfer characteristic using
necessary equations, and the different regions in the characteristic. [16]

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7. Compare PLAs, PALs, CPLDs, FPGAs, and standard cells in all respects. [16]

8. (a) What are the issues involved in driving large capacitor loads in VLSI circuit
designs? Explain.

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(b) Derive the expression for No. of stages N, for N - even and odd, to drive large
capacitor loads. [8+8]

?????