Timed Power Line Data Communication

A Thesis Submitted to the College of

Graduate Studies and Research
in Partial Fulfillment of the Requirements
for the Degree of Master of Science
in the Department of Electrical Engineering
University of Saskatchewan
Saskatoon, Saskatchewan, Canada

By

Kevin Wade Ackerman

© Copyright Kevin Wade Ackerman, January 2005. All rights reserved.
PERMISSION TO USE

In presenting this thesis, in partial fulfillment of the requirements for a degr

ee of Master
of Science from the University of Saskatchewan, the researcher agrees that the L
ibraries
of this University may make it freely available for inspection. The researcher f
urther
agrees that permission for copying of this thesis in any manner, in whole or in
part, for
scholarly purposes may be granted by the professor(s) who supervised this thesis
work.
In their absence, this permission can also be given by the Head of the Departmen
t, or
the Dean of the College of Graduated Studies and Research at the University of
Saskatchewan. Any copying, publication, or use of this thesis or parts thereof f
or
financial gain without the researcher s written permission is strictly prohibited
by law.
Due recognition shall be given to the researcher and to the University of Saskat
chewan
in any scholarly use which may be made of any material in this thesis.
Requests for permission to copy or to make other use of material in this thesis
in whole
or in part should be addressed to:
Head of the Department of Electrical Engineering
57 Campus Drive
University of Saskatchewan
Saskatoon, Saskatchewan, Canada
S7N 5A9
i
University of Saskatchewan
Timed Power Line Data Communication
Candidate: Kevin Ackerman
Supervisor: David E. Dodds
Supervisor: Carl McCrosky
M.Sc. Thesis Submitted to the
College of Graduate Studies and Research
ABSTRACT
With the ever increasing demand for data communication methods, power line
communication has become an interesting alternative method for data communicatio
n.
Power line communication falls into two categories: one for data transmission be
tween
sites in the power grid and the other for home or office networking. When consid
ering
home or office networking, existing methods are either too slow for tasks other
than
simple automation, or are very fast with a higher cost than necessary for the de
sired
function. The objective in this work is to develop a lower cost communication sy
stem
with an intermediate data transmission rate.
At first glance, power line communication looks like a good option because of th
e
availability of power outlets in every room of a building. However, the power co
nductors
were installed solely for the purpose of distributing 60 Hz mains power and, for
data
signals, they exhibit very high attenuation, variable impedance and there is rad
io
frequency shielding. Furthermore, many of the 60 Hz loads produce radio frequenc
y
interference that impedes data communication. Previous research has shown that m
uch of
the noise is time synchronous with the 60 Hz mains frequency and that the majori
ty of
data errors occur during these periods of high noise.
This work develops a power line communication protocol that coordinates transmis
sions
and uses only the predictable times of lower noise. Using a central control stra
tegy, the
power line 60 Hz mains signal is divided into 16 timeslots and each timeslot is
monitored
for errors. The central controller periodically polls all stations to learn whic
h timeslots
have low noise and it then controls all transmissions to make the best use of th
ese good
timeslots. The periodic polling allows the system to adapt to changes in electri
cal
loading and noise. This control strategy has been achieved with modest complexit
y and
laboratory measurements have shown throughput approaching 70% of the modem bit
rate.
ii
ACKNOWLEDGEMENTS

I wish to thank and acknowledge my two supervisors, Prof. David Dodds and Dr. Ca
rl
McCrosky. Without their expertise, guidance, and advice, the goals of this thesi
s would
have been much more difficult to obtain. Their efforts in providing me with cons
tant
feedback and encouragement are greatly appreciated. These are truly brilliant me
n who I
respect and admire.
I must also express my thanks to the University of Saskatchewan for the excellen
t faculty
and staff there. The institution has provided me with outstanding education that
will aid
me throughout my career. I would also like to thank the management, staff and ot
her
students at TRLabs. In particular, Garth Wells who helped greatly with the desig
n and
fabrication of hardware and Jack Hanson who provided guidance for me at TRLabs a
nd
while visiting a conference. I would also like to show appreciation for the stud
ents at
TRLabs that provided me with a pleasant working environment and often provided m
e
with help, in particular Bernie Boos and Bernardo Celaya who were always great t
o talk
to in a time when I needed some technical help or wanted to talk about things ot
her than
work.
I have been very fortunate to receive financial assistance from the University o
f
Saskatchewan, TRLabs, and the National Science and Engineering Research Council
of
Canada (NSERC). This financial assistance has made life a lot easier through my
years
of schooling.
Last and certainly not least, I thank my family and friends. My mom Elaine, brot
her
Brent and his fiancé Glenna, sister Shelly and her husband Larry and their three k
ids
Jayna, Dylan and Kaylin. All of you have always expressed great interest in my w
ork
even though I know sometimes it is quite hard to understand! However, my greates
t
supporter has been my amazing fiancé Kelly. Thank you for taking care of me when I m
sometimes too busy to! Without your love and support this task would have been m
uch
more difficult. Everything in life makes a lot more sense since we ve been togethe
r. I
love you.
iii
DEDICATION

This thesis is dedicated to my late father Ernie Ackerman. Since dad s passing in
early
2001, life hasn t been and never will be the same. Dad, I know that somewhere,
somehow you are looking down on me saying That s my boy .
iv
TABLE OF CONTENTS

PERMISSION TO USE...............................................................
...................................... i

ABSTRACT........................................................................
............................................... ii

ACKNOWLEDGEMENTS ...............................................................
.............................iii

DEDICATION......................................................................
............................................ iv

TABLE OF CONTENTS ..............................................................

................................... v

LIST OF FIGURES.................................................................
......................................viii

LIST OF TABLES .................................................................

........................................... x

LIST OF ABBREVIATIONS ..........................................................

............................... xi

1. Introduction.................................................................
.............................................. 1

1.1 Motivation For This Work....................................................

.............................. 1

1.2 System Proposal.............................................................

..................................... 2

1.3 Objectives Of The Thesis....................................................

................................ 4

2. Introduction to Power Line Communication ....................................

..................... 5

2.1 Communications Background...................................................

.......................... 6
2.1.1 Communications System Model [3] ..........................................
................. 6

2.1.2 Description of Important Performance Parameters...........................

.......... 8

2.2 Prior Art and Modern Methods................................................

........................... 9

2.2.1 X10.......................................................................
....................................... 9

2.2.2 Lonworks .................................................................

................................. 11

2.2.3 CEBus ....................................................................

................................... 12

2.2.4 HomePlug .................................................................

................................ 13

2.2.5 The Need for a Medium Speed Technology....................................

......... 15

2.3 The Channel.................................................................

..................................... 15

2.3.1 Attenuation...............................................................
................................. 16

2.3.2 Impedance.................................................................
................................ 17

2.4 Time Characteristics of Noise...............................................

............................ 18

2.4.1 Noise due to Office Load Devices..........................................

.................. 18

2.4.2 Noise in the Home Environment.............................................

.................. 21

2.4.3 Noise Frequency Spectrum..................................................

..................... 22
3. Design of a Protocol to Seek and Adapt to Power Line Noise ..................
.......... 23

3.1 The Need for a Protocol.....................................................

............................... 23

3.2 Choices in Designing a Protocol.............................................

.......................... 23

3.2.1 Distributed or Centralized Architecture...................................

................. 23

3.2.2 A Multiaccess Medium......................................................

....................... 24

v
3.2.3 Channel Sharing...........................................................
............................. 25

3.2.4 Messages and Packets......................................................

......................... 25

3.2.5 Efficient Use of the Channel..............................................

....................... 26

3.2.6 Error Detection...........................................................

............................... 27

3.2.7 Flow and Error Control....................................................

......................... 29

3.3 Review of Existing Multiple Access Protocols ...............................

................. 32

3.3.1 ALOHA.....................................................................
................................ 32

3.3.2 Slotted ALOHA ............................................................

............................ 33

3.3.3 CSMA/CD and CSMA/CA.......................................................

................ 33

3.3.4 Reservation Slotted ALOHA ................................................

.................... 35

3.4 Details of the Power Line Communication Protocol ...........................

............. 36

3.4.1 Designing a Centralized or Distributed System.............................

........... 37

3.4.2 Synchronizing to Zero Crossings and Using Timeslots.......................

..... 39

3.4.3 Timeslot Tables...........................................................

.............................. 40

3.4.4 Initiating Transmission ..................................................

........................... 42
3.4.5 Flow and Error Control....................................................
......................... 43

3.4.6 Packet Format ............................................................

............................... 44

3.4.7 Master and Slave State Diagrams ..........................................

................... 45

3.4.8 Protocol Operation Example................................................

..................... 47

4. Half Duplex Modem Design ....................................................

............................... 50

4.1 Bandwidth Considerations....................................................

............................ 50

4.2 Modulation..................................................................
...................................... 51

4.2.1 Choice of Modulation Scheme...............................................

................... 52

4.3 Universal Asynchronous Receive/Transmit (UART)..............................

......... 53

4.4 Hardware Implementation ....................................................

............................ 54

4.4.1 Personal Computer.........................................................

........................... 55

4.4.2 Zero Crossing Detector....................................................

......................... 55

4.4.3 MC68360 QUICC.............................................................

........................ 56

4.4.4 FSK Modulator ............................................................

............................. 56

4.4.5 Line Driver...............................................................

................................. 57
4.4.6 Bandpass Filter...........................................................
............................... 58

4.4.7 Demodulator ..............................................................

............................... 58

4.4.8 Line Coupler .............................................................

................................ 58

4.5 Software Implementation.....................................................

............................. 59

5. Protocol Performance.........................................................
.................................... 63

5.1 Data Transmission Performance...............................................

........................ 63

5.2 Adapting to BAD Timeslots ..................................................

........................... 70

5.3 Protocol Performance Tests .................................................

............................. 71

5.4 Testing in Various Environments ............................................

......................... 75

5.4.1 Creating different environments ..........................................

..................... 75

5.5 Optimizing the GOOD/BAD Error Threshold.....................................

............. 83

5.6 Other Factors that Affect the Channel ......................................

........................ 87

5.6.1 Time of Day ..............................................................

................................ 87

5.6.2 Distance between nodes....................................................

........................ 89

5.6.3 Effects of Signal Amplitude...............................................

....................... 91
vi
5.7 Protocol Drawbacks..........................................................
................................ 93

5.7.1 Multi-phase Network ......................................................

.......................... 93

5.7.2 Centralized vs. Distributed Architecture..................................

................. 94

5.7.3 Excess Overhead...........................................................

............................ 95

6. Conclusion ..................................................................
............................................. 97

6.1 Summary.....................................................................
...................................... 97

6.2 Conclusions.................................................................
...................................... 98

6.3 Future Work.................................................................

..................................... 99

6.3.1 Modulation................................................................
................................ 99

6.3.2 Selectable Bits Per Symbol................................................

..................... 100

6.3.3 Length of Timeslots ......................................................

.......................... 101

6.3.4 Amplitude Adapting........................................................

........................ 101

6.3.5 Breaker Panel Connection..................................................

..................... 102

6.3.6 Using Consecutive Timeslots ..............................................

................... 102

6.3.7 Other Protocol Considerations.............................................

................... 103
References......................................................................
............................................... 105

A. Hardware Pictures............................................................
.................................... 108

B. Federal Communications Commission Part 15....................................

.............. 112

C. MC68360 Code.................................................................
..................................... 114

D. XR2211 Data Sheet ...........................................................

.................................... 115

vii
LIST OF FIGURES

Figure 2.1 Communication system model. .........................................

................................ 6
Figure 2.2 X10 timing on 60 Hz waveform [5]. ...................................
............................ 10
Figure 2.3 X10 packet format [5]. ..............................................
...................................... 11
Figure 2.4 CEBus spread spectrum chirp [10].....................................
............................. 13
Figure 2.5 Attenuation vs. Frequency [1]. ......................................
.................................. 16
Figure 2.6 Impedance vs. Frequency [14]. .......................................
................................ 17
Figure 2.7 Measured noise in an office environment [1]..........................
........................ 19
Figure 2.8 Bit error test in an office environment [1]..........................
............................. 20
Figure 2.9 Bit error test in a home environment with a lamp dimmer [1]..........
.............. 21
Figure 2.10 Noise frequency spectrum ...........................................
.................................. 22
Figure 3.1 Data Throughput vs. Packet Size......................................
............................... 26
Figure 3.2 An arithmetic checksum...............................................
................................... 28
Figure 3.3 Stop-and-wait protocol. .............................................
...................................... 30
Figure 3.4 Sliding window protocol, sender s window [15]............................
............. 31
Figure 3.5 Reservation slotted ALOHA [20].......................................
............................. 36
Figure 3.6 Nodes at different points on the line have different channel characte
ristics... 38
Figure 3.7 Typical layout of home or office network.............................
.......................... 39
Figure 3.8 60 Hz power line cycle is divided into timeslots 0 through 15. ......
................ 40
Figure 3.9 Master and slave timeslot tables.....................................
................................. 41
Figure 3.10 Packet format.......................................................
.......................................... 44
Figure 3.11 Master state diagram................................................
...................................... 46
Figure 3.12 Slave state diagram.................................................
....................................... 46
Figure 3.13 Example of protocol operation. .....................................
................................ 49
Figure 4.1 Available spectrum for power line communication. ....................
................... 51
Figure 4.2 FSK Spectrum. .......................................................
......................................... 52
Figure 4.3 UART character format................................................
................................... 54
Figure 4.4 System block diagram for both master and slave.......................
..................... 55
Figure 4.5 Line driver. ........................................................
.............................................. 57
Figure 4.6 Line coupler.........................................................
............................................ 59
Figure 4.7 Master/Slave Communication Process...................................
......................... 61
Figure 4.8 CRC shift register implementation (transmitter and receiver). .......
................ 62
Figure 5.1 AC mains voltage and power line noise................................
.......................... 64
Figure 5.2 Byte and timeslot errors.............................................
...................................... 66
Figure 5.3 Graphical representation of timeslot errors. ........................
............................ 67
Figure 5.4 Probability of Error vs. Number of Timeslots used (out of 16). ......
............... 68
Figure 5.5 Efficiency vs. Number of Timeslots used (out of 16). ................
.................... 69
Figure 5.6 AC mains voltage, GOOD/BAD timeslots and received signal.............
......... 71
Figure 5.7 Success Probability vs. Message Length...............................
.......................... 73
Figure 5.8 Throughput vs. Message Length. ......................................
.............................. 75
Figure 5.9 Oscilloscope trace with Macintosh computer as a noise producing load.
....... 76
Figure 5.10 Throughput vs. Message Length with Macintosh computer as a noise

producing load. ................................................................

......................................... 78
Figure 5.11 Oscilloscope display with lamp dimmer in high position. ............
................ 79
Figure 5.12 Oscilloscope display with lamp dimmer in low position. .............
................ 80

viii
Figure 5.13 Throughput vs. Message Length with lamp dimmer in low position......
...... 81
Figure 5.14 Throughput vs. Message Length for generally noisy channel...........
............ 83
Figure 5.15 Throughput vs. Message Length to test adapting effectiveness........
............ 84
Figure 5.16 Error Threshold to Classify BAD vs. Message Length for a single time
slot.85
Figure 5.17 Station separation test setup ......................................
.................................... 89
Figure 5.18 Average Slot Error Ratio vs. Station Separation.....................
...................... 91
Figure 5.19 Average Timeslot Error Ratio vs. Signal Amplitude. .................
.................. 92
Figure 5.20 Three phase power line network......................................
.............................. 94
Figure 6.1 Concatenating timeslots..............................................
................................... 103
Figure A.1 Complete Hardware Setup..............................................
.............................. 108
Figure A.2 Close-up of hardware setup ..........................................
................................ 109
Figure A.3 Close-up view of project boxes ......................................
.............................. 110
Figure A.4 Myself (left) and my supervisor, Prof. David Dodds (right)...........
............. 111

ix
LIST OF TABLES

Table 5.1 Microprocessor report of timeslot errors. ............................

............................. 67
Table 5.2 Timeslot errors with Macintosh computer as a noise producing load. ...
.......... 77
Table 5.3 Timeslot error percentage with lamp dimmer in low position............
.............. 81
Table 5.4 Generally noisy channel timeslot error percentage.....................
...................... 82
Table 5.5 Average timeslot error percentages for night and day tests............
.................. 88
Table 5.6 Timeslot Error Ratio vs. Station Separation. .........................
........................... 90
Table 5.7 Timeslot Error Ratio vs. Amplitude. ..................................
.............................. 92

x
LIST OF ABBREVIATIONS
ac Alternating Current
ARQ Automatic Repeat Request
ACK Acknowledgement
BER Bit Error Rate
BPF Bandpass Filter
BW Bandwidth
CDMA Code Division Multiple Access
CRC Cyclic Redundancy Check
dB Decibels
FDMA Frequency Division Multiple Access
FSK Frequency Shift Keying
Hz Hertz
kb/s Kilo-bits per second
kHz Kilo-hertz (kilo = 103)
LSB Least significant bit
MAC Media Access Control
Mbps Mega-bits per second
MHz Mega-hertz (kilo = 106)
ms Millisecond (milli = 10-3)
MSB Most significant bit
PLC Power Line Communication
QAM Quadrature amplitude modulation
RTS/CTS Request to Send/Clear to Send
SNR Signal to Noise Ratio
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver Transmitter
xi
1. Introduction
1.1 Motivation For This Work
In the past twenty years, data networks have gone from being an experimental tec
hnology
to becoming a key tool for business and entertainment used by companies and home
s
worldwide. Companies use networks to transfer data files and share applications
between
computers, as well as to share access to network devices such as printers and
workstations. This demand by companies is large, but the demand for data
communication in the home is also becoming significant. Home users, who often ha
ve
more than one computer, are looking to data communication networks to share
information between computers. They are also looking to networks for the automati
on
of their home including applications such as security systems, network gaming, a
nd
controlling heating, air conditioning and other household appliances.
The design of a network should consider several factors, of which the two most i
mportant
are predicted network traffic and installation cost. The nature of traffic gener
ated by
applications such as email, streaming audio or video, file transfer, control sys
tems,
application or resource sharing, etc. predicts the type of service needed. The v
arious
types of traffic can have different throughput, data integrity, latency, and oth
er
requirements. A simple control system network that performs functions such as tu
rning
lights on and off, opening and closing the garage door, and controlling the air
conditioner
does not require high speeds. A high speed network would be much better utilized
by a
multiple computer network where there is a large amount of file and application
sharing
or video.
The cost factor refers to the installation cost of a network. High speed network
s often
require more expensive equipment than low speed networks, so for low speed netwo
rks it
is not economically smart to install high speed equipment. Installation cost is
also
affected by the actual setup of the network. Wireless equipment is becoming popu
lar
because it is simple to set up and provides high speed and high mobility (comput
ers can
access the network as long as they are within a certain distance of the access p
oint).
However, the wireless equipment may be too costly for low to medium speed
applications. Another solution is to use dedicated network cabling but this is a
lso a high
cost solution because retrofitting a home with the required cabling becomes a ti
me
consuming and expensive job. Also, once network cabling is installed in a home o
r
office, it does not lend itself easily to reconfiguration resulting in down time
when
location of network entities changes.
What is missing is a medium speed technology that is low cost and allows for eas
y and
ubiquitous network access. This thesis addresses a possible solution to the prob
lem of
mobility, ease of installation, and cost of networks by using the in-building po
wer
distribution system.
1.2 System Proposal
Using the in-building power distribution system as a communications medium can b
e
referred to as a power line network, and the advantage is that the wiring for the
network is already in place and thus there is no requirement for dedicated netwo
rk cable.
Power conductors have excellent coverage because every room in a building has po
wer
and thus the network is easy to access. If equipment has to be re-configured or
moved, it
is as simple as moving the equipment and plugging it in to the power line.
Another advantage is that any device that requires connection to the power line
also has
access to a network. The heating ventilation and air conditioning (HVAC), refrig
erator,
microwave oven, and various other appliances are devices which, with installed l
ogic,
could be controlled and communicate through the power line to make a smart home.
2
It would seem then that using the power line as a communications medium would re
nder
all other network strategies obsolete. If the medium was favorable for communica
tion,
this would perhaps be the case. However, it is difficult to communicate data eff
ectively
because the medium was not designed for data transmission. Attenuation, variable
impedance, and noise are three factors which make this a harsh medium, making it
difficult to achieve optimum signal transfer, low distortion, and high signal-to
-noise
ratios (SNR).
Several technologies have been explored to combat the harsh channel characterist
ics.
Low speed technology that is readily available only supports simple home automat
ion.
Most recently, high frequency modulation combined with sophisticated multiplexin
g and
error control coding techniques have been explored. This technology provides hig
h
speed, however, untwisted power wires radiate the signal and this causes interfe
rence
with radio communications. What is missing is a medium speed technology that can
support applications such as control of devices, network gaming, low resolution
image
sequences from cameras, security applications and several other applications. Th
e only
current power line communication method that can support these applications is t
he high
speed method, which provides much higher speeds than needed and carries a cost t
hat is
higher than necessary.
This thesis explores a method of providing medium speed communication while
minimizing complexity and cost by using timed transmission . Prior work has been
done in this area by Jack Hanson at the University of Saskatchewan and at
Telecommunications Research Laboratories [1]. While previous methods of power li
ne
communication use continuous time transmission, this proposed method is similar
to time
division multiple access (TDMA) in that users are given specific time periods (t
imeslots)
in which to transmit and receive while other timeslots are not used. This idea c
ame from
Hanson s work which observed that interference on the power line is synchronous an
d
stationary in position with respect to the 60 Hz mains signal [1]. Noise appears
only for
short intervals, causing a high number of bit errors for a short period of time.
These
noisy intervals should be avoided. By detecting when noisy timeslots occur and a
voiding
3
them, bit error ratios can be dramatically reduced. Also, during periods of low
noise, the
transmission bit rate can be increased to further improve the throughput of the
system.
1.3 Objectives Of The Thesis
This thesis has three main objectives. The first objective is to review previous
studies on
the power line as a transmission medium and previous and current methods of
communicating data on the power line. Included in this information will be the r
esults of
Hanson s research that indicates power line noise is synchronous and fixed in posi
tion
with respect to the zero crossings of the 60 Hz mains signal. The second objecti
ve is to
take advantage of this information by designing a protocol. First, general proto
col
requirements will be studied along with several existing communication protocols
. This
study will be used in order to aid in the design of a new protocol for timed pow
er line
communication. The third objective is to implement and test the performance of t
he
protocol. Two half-duplex modems will be built and data communication performanc
e
will be tested in various noise environments to observe the improvements obtaine
d by
using the new protocol. Message transmission success and throughput will be the
main
focus of the performance study.
4
2. Introduction to Power Line Communication
Power line communication, also known as PLC, uses existing power distribution wi
res to
communicate data. This, however, is not a new idea. In 1838 the first remote ele
ctricity
supply metering appeared and in 1897 the first patent on power line signaling wa
s issued
in the United Kingdom [2]. In the 1920's two patents were issued to the American
Telephone and Telegraph Company in the field of "Carrier Transmission over Power
Circuits". One would think that the long-ago conceived idea of power line
communications would be well developed by now. However, this is not the case bec
ause
the power line is not well suited for data communication.
There are two main applications for power line communication - one for broadband
Internet access to the home and the other for home and office networking. This w
ork
focuses on using power lines for home and office networking.
Home and office networks typically use Ethernet or wireless devices. Ethernet pr
ovides
high speed networking, but requires dedicated category 5 (CAT5) cabling which wo
uld
need to be installed in the home. Wireless devices are now becoming more popular
and
work quite well, but provide speeds that are excessive for simple applications.
Performance of wireless networks is also affected by line of sight obstructions
such as
walls. One major attraction of power line communication is the high availability
of
power outlets. The average North American home has an average of three power out
lets
per room resulting in choice of location and mobility as long as there is a power
socket, there is a connection to the network . The high node availability is why t
his
technology has tremendous market potential.
5
Power line communication technology has been slow to evolve because the lines we
re
designed solely for the purpose of 60 Hz main power distribution. Unfortunately,
power
lines are a rather hostile medium for data transmission. The medium has varying
impedance, considerable noise, and high attenuation all which can change as diff
erent
types of devices are connected to the electrical supply.
2.1 Communications Background
In order to better understand PLC, the following section provides an overview of
a
general communications system. This will include a discussion of the elements of
a
communications system, the methods for transmitting data, and performance measur
es.
2.1.1 Communications System Model [3]
Figure 2.1 shows a simplified model of a digital communications system. The over
all
objective of a communications system is to communicate information (the transmis
sion
of digital information this thesis considers) from a source to a destination ove
r some
channel.
Source ModulatorChannel
encoder
Channel

Figure 2.1 Communication system model.

Source and Destination: The source can be any digital source of information. If
the
source is analog such as speech, then an analog to digital converter must preced
e the
transmitter. At the receiving end, the decoded information is delivered to the d
estination.
Destination
Channel
decoder
Demodulator
6
The source may also compress redundant data, which minimizes the number of bits
transmitted over the channel, but can also create a loss of source information.
The data is
unpacked at the destination to either an exact replica of the source information
(lossless
data compression) or a distorted version (lossy data compression).
Channel Encoder and Channel Decoder: Channel coding reduces the bit error
probability by adding redundancy (extra check bits) to the bit sequence. The che
ck bits
are computed over a k-symbol input sequence to create an n-symbol output code
sequence. This determines the code rate Rc where Rc = k/n and Rc = 1. This is th
e ratio
of the number of actual data bits to the total number of bits transmitted. The c
hannel
decoder uses the extra bits to detect and possibly correct errors which occurred
during
transmission. The number of extra bits added depends on how much error detection
and
correction is needed. Channel coding (also known as error control coding) is a h
eavily
studied area. It is used to improve performance over noisy channels (such as the
power
line). Two major classes of codes exist: block codes and convolutional codes. Bl
ock
codes are implemented by combinational logic circuits. Reed-Solomon (RS) codes a
re a
popular block code. Convolutional codes (also known as tree codes or trellis cod
es) are
implemented by sequential logic circuits [4].
Channel Modulator and Channel Demodulator: The purpose of the modulator is to
take the encoded data and produce an analog signal suitable to propagate over th
e
channel. The data is converted from a stream of bits into an analog signal. An M
-ary
modulator takes a block of Y binary digits from the channel encoder to select an
d
transmit one of M analog waveforms at its disposal where M = 2Y and Y = 1. At th
e
receiver, the demodulator tries to detect which waveform was transmitted, and co
nvert
the analog information back to the sequence of bits. Modulation is typically per
formed
by varying the amplitude, the phase, or the frequency of a high-frequency carrie
r signal.
For example, if the input signal of the modulator is used to vary the amplitude
of the
carrier signal, the modulation is called Amplitude Shift Keying (ASK). There are
several
other modulation techniques including FSK (Frequency Shift Keying), PSK (Phase S
hift
Keying) and QAM (Quadrature Amplitude Modulation).
7
Channel: The channel can be any physical transmission medium including coaxial
cable, twisted pair, optical fibre, air, water, or for this work - the power lin
e. It is
important to know the characteristics of the channel, such as the attenuation an
d noise
level because these parameters directly affect the performance of the communicat
ion
system.
2.1.2 Description of Important Performance Parameters
Symbol Rate - This is the transmission rate or number of symbols per second from
the
modulator. If the signal duration is T seconds then the symbol rate is 1/T symbo
ls per
second. The symbol rate is also known as the baud rate [4].
Bits per second (bps) Also known as bit rate, bits per second is directly relate
d to the
symbol rate. If each symbol represents Y bits and the symbol rate is 1/T baud, t
hen the
bit rate is Y*(1/T) bps. On high quality channels it is easier to send more bits
with one
symbol, resulting in higher bps [4].
Bit Error Probability (Pb) Pb is the probability that a bit is incorrectly recei
ved at the
destination. This is an important performance measure for any digital communicat
ion
system that is affected by noise and the disturbances in the channel.
Bandwidth (BW) The range of frequencies used by the communication system. For a
specific communication method, the bandwidth needed is proportional to the symbo
l rate.
Bandwidth is a limited resource and is often constrained to a certain small rang
e.
Bandwidth Efficiency This is the ratio between the bit rate and the bandwidth of
a
communication system (bps/BW). Today a telephone system can achieve a bit rate o
f
56.6 kbps using a bandwidth of 4 kHz, so the bandwidth efficiency is 56.6/4 = 14
.15
bps/Hz.
8
Noise This is an unwanted signal on the channel that interferes with the desired
signal.
Noise on the power line is a sum of many different disturbances originating from
devices
such as television receivers, computers, and vacuum cleaners. The amount of nois
e can
drastically affect the quality of communication.
Attenuation When the signal is propagating from the transmitter to the receiver
the
signal gets attenuated (loses power). If the attenuation is high, the received s
ignal power
can become low and might not be detected. Attenuation is shown to be high on a p
ower
line, and this puts a restriction on the distance from the transmitter to the re
ceiver.
Signal to Noise Ratio (SNR) This is the ratio of received power to noise power.
A
higher SNR makes for easier communication because noise has a smaller effect on
the
signal. SNR is also affected by attenuation, which reduces signal power and thus
SNR.
SNR can be increased by using filters to reduce noise outside of the bandwidth o
ccupied
by the signal.
Diversity Used to reduce the error probability of harsh channels. Examples of di
versity
are time diversity and frequency diversity. In time diversity the same informati
on is
transmitted at different time instants with the idea that if the channel is bad
at some time
instance it might not be at another. Frequency diversity transmits the same info
rmation
in different frequency bands. It can be compared to having two antennas transmit
ting at
different frequencies; if one of them fails the other might work. Several variat
ions of
time and frequency diversity exist. This thesis explores a form of time diversit
y,
although not exactly as described above.
2.2 Prior Art and Modern Methods
2.2.1 X10
The X10 specification was designed for low-bandwidth signaling over power lines
within
the home. The product was developed by a company in Scotland - Pico Electronics
-
with the first shipped product to market in 1978. The patent on the standard has
since
9
expired and prices have fallen sharply. X10 applications include controlling lig
hts and
thermostats as well as devices like the stereo amplifier, garage door opener, te
levision
receiver and more [5].
The X10 system is simple and easy to use. It transmits over the electrical wirin
g using on
off keying (OOK). More precisely, it uses 120 kHz signal bursts, each one millis
econd
long. These signal bursts are synchronized to the zero crossings (both positive
and
negative) of the ac power line signal. The specification allows for a signal bur
st to be
within a maximum of 200 µs of the zero crossing point. Each bit transmitted occupi
es
two zero crossings; a binary 1 is represented by a burst followed by a no-burst,
while a
binary 0 is a no-burst followed by a burst. Also, each one millisecond burst is
equally
transmitted 3 times to coincide with the zero crossing point of all three phases
in a three
phase distribution system. Figure 2.2 shows the timing relationship of these bur
sts
relative to the zero crossing.

Figure 2.2 X10 timing on 60 Hz waveform [5].

An X10 packet, shown in Figure 2.3, encompasses eleven cycles of the power line.
It
begins with a start of packet identifier consisting of the sequence 'burst, burs
t, burst, no-
burst', which occupies the first two cycles (four zero crossings). The next four
cycles
represent the House Code, and the last five cycles represent a number code (1 th
rough 16)
or a Function Code (On, Off, etc.) This complete block is always transmitted twi
ce, with
3 power line cycles between each group of 2 codes. Hence the total number of pow
er
line cycles required to complete a transmission is 2*11 + 3 = 25 power line cycl
es [6].
10
Figure 2.3 X10 packet format [5].
With this simplicity also comes a low bit rate. 25 power line cycles are require
d to
transmit a frame - which consists of 11 bits. The resulting bit rate is then 60*
(11/25) =
26.4 bits/second. This bit rate is only useful for trivial applications, and is
much too slow
for transmission of audio, video, network gaming traffic, and other higher bandw
idth
network traffic. However, X10 is inexpensive and easy to use; hence it is a popu
lar
choice for basic home automation.
2.2.2 Lonworks
Lonworks is a network protocol created by Echelon Corporation [7] and is intende
d to
support communication between control devices or nodes. Each node in the network
a
switch, sensor, motor, motion detector, etc. - performs a simple task. The overa
ll
network performs a complex control application such as automating a building [5]
.
Early standards for the Lonworks protocol used spread spectrum modulation. Sprea
d
spectrum communication techniques can be used to improve performance in the pres
ence
of tonal noise (noise that is present at specific frequencies only). Spread spec
trum
improves performance by using a wider bandwidth for communication than what is
required. The amount of improvement depends on the available bandwidth, or in ot
her
words, the degree of spreading. It was first used with a bandwidth of 100 kHz -
400 kHz,
but this band was found to be too narrow to provide acceptable performance given
the
type of noise present on the power line. In addition, European regulations prohi
bit power
line signaling above 150 kHz due to potential interference with low frequency li
censed
radio services [8].
11
Instead, Echelon's latest product, the PLT-22 transceiver, operates using a nove
l Dual
Carrier Frequency mode along with Digital Signal Processing (DSP). The purpose o
f the
DSP is to provide adaptive carrier and data correlation, impulse noise cancellat
ion, tone
rejection, and low overhead error correction. The PLT-22 communicates using BPSK
with frequency ranges 125 kHz - 140 kHz (primary) and 110 kHz - 125 kHz (seconda
ry).
The primary frequency range is used unless impairments prevent successful
communication in this range. When this occurs, the PLT-22 automatically switches
to
the secondary frequency range. The PLT-22 communicates at a raw bit rate of 5 kb
ps.
This is much faster than X10, and hence more useful for more complex control of
electrical devices [9].
2.2.3 CEBus
In 1984, the Electronic Industries Alliance (EIA) Consumer Electronics Group beg
an an
effort whose goal was the formulation of a standard for a communication network
for
consumer products in the home. The standard came to be called the Consumer Elect
ronic
Bus (CEBus) [10]. The suite of specifications includes communication on many dif
ferent
types of medium including power line, twisted pair cable, coaxial cable, infrare
d, radio
frequency, and fibre optic. The suite of specifications was labeled EIA-600. The
full
specification was released in 1992.
This work is concerned with the physical layer coding employed by CEBus. CEBus u
ses
non return to zero (NRZ), pulse width encoding. There are four symbols: 1 , 0 , EOF,
EOP. These symbols are encoded using chirp spread spectrum in the bandwidth 100
kHz
to 400 kHz. In spread spectrum, the carrier signal frequency is swept over a ran
ge of
frequencies. CEBus employs a sequence of up and down frequency sweeps of the car
rier
that in total for one symbol occupies a period of 100 µs. This symbol interval is
the
shortest symbol time 1 , or unit symbol time. A 0.1 % margin of error is also defin
ed
(100 ns for 100 µs). Also, the time to transmit binary 1 is a unit symbol time (100 µs
),
while to transmit a binary 0, two unit symbol times are used (200 µs). For random
binary
12
data, the average symbol time is then 150 µs, for a bit rate of 7.5 kbps. A unit s
ymbol
time is shown in Figure 2.4.

Figure 2.4 CEBus spread spectrum chirp [10].

One other interesting note in the CEBus standard is coupling between power phase
s
within the home. There are two 60 Hz phases, L1 and L2, in a home that are 180 d
egrees
apart in phase. Home 120V electrical devices - appliances, lights, motors, etc.
- normally
connect to either L1 or L2. Only 240V devices that connect to L1 and L2 simultan
eously
provide a signal path between these two branches other than the minimal coupling
provided by the distribution transformer. Therefore, a CEBus 120V device on L1 m
ay
not communicate with a CEBus 120V device on L2 due to inadequate signal coupling
between L1 and L2. To help solve this problem, the CEBus standard says that a si
gnal
coupler should be placed between L1 and L2 when needed to improve signal propaga
tion
within the power line network [10].
2.2.4 HomePlug
HomePlug is a non-profit consortium founded in March 2000 by thirteen leading IT
companies who have a mutual interest in high-speed networking technologies over
power
lines. Its membership of now more than 80 companies includes companies specializ
ing
in semi-conductor manufacturing, hardware/software supply, and service. The goal
of
the consortium is to create an open specification for high speed power line netw
orking
technology and to promote new products to accelerate its adoption. In June 2001,
the
HomePlug v1.0 specifications were published.
13
The HomePlug specification is the most complex of all power line technologies. T
o
achieve higher bit rates, higher frequencies and bandwidth must be used than tha
t for
X10, Lonworks and CEBus as discussed above (whose frequencies are less than 500
kHz). HomePlug communicates using Orthogonal Frequency Division Multiplexing
(OFDM) in the 4.49 to 20.7 MHz frequency band. This method of multiplexing divid
es
up the available bandwidth into sub-bands. These sub-bands are mathematically
orthogonal, meaning that for the specific symbol rate they are placed at specifi
c intervals
in the frequency domain that minimizes interference between them. In the bandwid
th 0 -
25 MHz, there are 128 evenly spaced sub-carriers of which HomePlug uses 84, from
the
band 4.49 to 20.7 MHz (carriers 23-106 inclusive) [11].
Before forming a symbol to be transmitted, data bits are processed using several
error
control coding schemes. Data bits are modulated onto the sub-carriers using diff
erential
quadrature phase shift keying (DQPSK), or differential binary phase shift keying

(DBPSK). The Inverse Fast Fourier Transform (IFFT) is used at the transmitter to
create
individual channel waveforms. The whole process is reversed at the receiver [12]
.
In addition to this, HomePlug adapts to channel conditions. Special frames are s
ent and
analyzed by receivers to determine which of the 84 sub-carriers are available fo
r
communication. Tone Maps (TM) are then created and used by sender-receiver pairs
to
adapt to varying channel conditions. Only good sub-carriers are used for communi
cation.
Also, the modulation scheme can be changed (DBPSK or DQPSK), and the error-contr
ol
coding can be modified. Altogether, 139 distinct physical data rates are availab
le from
1Mbps to 14.1 Mbps [11].
Several manufacturers have demonstrated HomePlug technology and it looks promisi
ng.
Field tests with HomePlug V1.0 devices in 500 homes show that 80% of outlet pair
s were
able to communicate with each other at about 5 Mbps or higher, and 98% could sup
port
data rates greater than 1 Mbps [13]. The HomePlug alliance has announced plans f
or the
development of next generation specifications. Named HomePlug AV, the new
specification will be designed to support distribution of data and multimedia-st
reaming
14
entertainment including High Definition television (HDTV) and data rates of 100
Mbps
throughout the home [11].
The ability to adapt is the real strength of HomePlug. Obviously if the power li
ne
channel becomes harsh for communication, data rates will be slow, but reliabilit
y will be
maintained. Note that HomePlug employs a method of frequency diversity. It also
uses
complex error control coding and modulation techniques that are good for reliabi
lity, but
are computationally demanding, power consuming and expensive. HomePlug provides
high enough data rates for medium speed, but its complexity and cost is more tha
n
necessary.
2.2.5 The Need for a Medium Speed Technology
In the coming years, people are likely to use PLC to network anything that is el
ectrically
powered such as heating, ventilation, and air conditioning (HVAC). Different dev
ices
and applications will have different throughput requirements ranging from 10 bps
to 100
Mbps or more. Simple control of devices (turning lights on and off, controlling
thermostat, etc.) is achievable with low bit rates (< 5 kbps). High quality vide
o and high-
speed computer networking is at the opposite end of the spectrum requiring speed
s up to
100 Mbps.
From the different technologies given above one can see that there exists low co
st,
reliable systems (X-10, Lonworks, and CEBus) and that high speed systems exist u
sing
the HomePlug protocol. These systems work well for what they were designed, but
have
several drawbacks. There really isn t a device designed for medium speed (100 kbps t
o
1 Mbps). Therefore this thesis focuses on a low complexity, low cost medium spee
d
technology for power line communication using timed transmission .
2.3 The Channel
The characteristics of the channel must first be explored in order to design a t
imed
transmission protocol. Varying impedance, considerable noise, and high attenuati
on are
15
the main issues. Channel characteristics depend on the location of the transmitt
er and
receiver in the specific power line infrastructure and are both time and frequen
cy
dependent. Hence, the channel can be described as random time varying with a
frequency-dependent signal-to-noise ratio (SNR) over the communication bandwidth
[14].
2.3.1 Attenuation
Figure 2.5 shows attenuation measurements taken on a single power phase in the
Engineering building at the University of Saskatchewan by Hanson [1]. Measuremen
ts
were taken at outlets separated by 4 meters (13 feet) and 23 meters (75 feet).

Figure 2.5 Attenuation vs. Frequency [1].

The short distance measurement, performed on hallway outlets free of electrical
loads,
shows a relatively flat attenuation between 15 and 20 dB. The long distance
measurement, also free of electrical loads, shows attenuation between 33 and 43
dB with
some variation with frequency.
16
Also, branches (stubs) on power cables can create nulls in the transmission char
acteristic.
However, assuming stub lengths are less than 100 meters, nulls in the transmissi
on
characteristic which occur at a stub length of ./4 will not occur at frequencies
less than 1
MHz. (100 meter stub creates a null at 1 MHz, and shorter stubs create nulls at
> 1MHz).
2.3.2 Impedance
Power line impedance is important because a transmitter must match this impedanc
e over
the desired frequency range to avoid frequency dependent distortion of a broadba
nd
signal. Nicholson and Malack [14] measured line impedance in the frequency range
20
kHz to 30 MHz at 36 different commercial locations in the United States. They fo
und
that the characteristic impedance increased with frequency. The impedance, avera
ged
over all sites, was approximately 1 O at 20 kHz increasing to 100 O at 30 MHz. S
imilar
results were obtained in European countries and in Japan. Nicholson and Malack
explained that any variation from site to site was attributed to variations in l
oad
connected to the line. Figure 2.6 is extracted from their work to show the frequ
ency
range 50 to 500 kHz.

Figure 2.6 Impedance vs. Frequency [14].

17
2.4 Time Characteristics of Noise
Prior research by Hanson has also shown that the majority of noise on the power
line is
impulsive and synchronous in time with the power signal (60 Hz in North America)
. In
other words, the noise occurs at regular intervals that are fixed in time with r
espect to
zero crossings of the 60 Hz mains signal. This means that at these specific time
s the
probability of bit error is much higher than that at other times during one cycl
e of the
power line signal. All prior communication methods available for study have igno
red
this fact and have been designed to get around the noise problem by analyzing th
e
frequency characteristics of the power line noise rather than the time character
istics.
Given that the power line noise is synchronous with the 60 Hz mains frequency, a
method
can be devised to avoid these times of high noise and high bit error probability
and
communicate during low noise times. This will dramatically reduce bit error prob
ability,
and increase throughput.
2.4.1 Noise due to Office Load Devices
To investigate the communications capability and the time characteristic of nois
e on the
power line conductors, Hanson performed measurements at several outlets within t
wo
commercial buildings. The first was the Engineering building at the University o
f
Saskatchewan campus and the second was at Telecommunication Research Laboratorie
s
(TRLabs) which is located in an office building in a research park. The represen
tative
trace shown in Figure 2.7 was recorded in an office at TRLabs.
18
Figure 2.7 Measured noise in an office environment [1].
During each 60 Hz cycle, there were six noise bursts: one at each zero crossing
caused by
fluorescent lamps extinguishing and reigniting, a pair caused by power supply re
ctifiers
when they begin to conduct and another pair caused by power supply rectifiers wh
en they
stop conducting.
Hanson also developed a simple laboratory data transmission system to evaluate
transmission errors caused by noise on the power conductors. The data source was
a
32767-bit maximal length sequence at the rate of 50 kb/s constructed with a shif
t register
with taps that are exclusive-ORed together to create the sequence. To simplify c
lock
recovery at the receiver, the source data was coded into a bi-phase level (Manch
ester I)
data stream by exclusive-ORing the source data with a clock that is at twice its
data rate.
This coded data stream was used to frequency shift key (FSK) a 200 kHz carrier.
The
modulator circuit was developed around an Exar XR-2206 integrated circuit and th
e mark
and space frequencies were set at 150 kHz and 250 kHz respectively.
In the receiver, errors were detected using a self-synchronized descrambler. Thi
s is a
shift register that shifts in the received data stream and has taps at specific
locations in the
19
register. An exclusive-OR combination of these taps indicates if there is any bi
t in error
in the register. This is possible by constructing a shift register with taps lik
e that at the
source. Because a single bit error cycles through the shift register, it will go
through the
location of each register tap and hence the error indicator will indicate multip
le bit errors
(in Hanson s design there was three) for a single bit error. A Tektronix 544A digi
tal
storage oscilloscope was used to display the 60 Hz signal, the noise signal, and
the
detected error signal. By setting the oscilloscope to average over 10-minute int
ervals, the
trace voltage graphically illustrated the average error rate. Traces were transf
erred to a
PC at 10 minute intervals and averaging was done over a 9-hour period. Figure 2.
8
shows the resulting traces.

Figure 2.8 Bit error test in an office environment [1].

The traces in Figure 2.8 were obtained in a typical office environment with each
office
having one or more personal computers and two computer work areas with several
workstations present in both. The simple error detector clearly shows the strong
correlation between the stationary interference and the errors, and that certain
portions of
20
the cycle should be avoided during transmission. In this case, approximately 10%
of the
60 Hz mains cycle is unusable due to noise [1].
2.4.2 Noise in the Home Environment
The home environment frequently includes lamp dimmers and this presents an addit
ional
noise source. These devices switch off at the zero current point in the 60 Hz ma
ins cycle
and switch on again after a delay that is increased to make the lamp more dim. T
he
switch-on results in a large and rapid current transition that introduces large
high
frequency noise resulting in data errors at the switch-on time. Figure 2.9 shows
how the
control setting for lamp dimming affects the position of the shaded error bursts
within the
60 Hz mains cycle. This test was conducted using the same transmitter/receiver p
air as in
the office test. Bit errors caused by the lamp dimmer are shaded.

Figure 2.9 Bit error test in a home environment with a lamp dimmer [1].
21
Again, observe two key points: noise times and hence bit error times are synchro
nous
with the power line cycle, and the error times can change depending on the type
of load
(in this case, changing the brightness of the lamp).
2.4.3 Noise Frequency Spectrum
The frequency spectrum of the noise is also important. If noise is outside of th
e
frequency range that is being used for communications, it can be filtered and it
s effect
can be minimized or eliminated. Figure 2.10 shows an oscilloscope trace of the
frequency spectrum of noise present on a typical office power line. This trace w
as
obtained at the offices of TRLabs. The horizontal scale is 50 kHz/division and t
he
vertical scale is 20 dB/division. The horizontal axis displays frequencies from
0 to 500
kHz. The conclusion that can be drawn from this trace is that the frequency spec
trum of
the noise is approximately white meaning that it is over all frequencies, and ca
nnot
simply be filtered to eliminate its effect on communications.
Figure 2.10 Noise frequency spectrum

0 Hz
500 kHz
22
3.
Design of a Protocol to Seek and Adapt to Power
Line Noise
3.1
The Need for a Protocol
Hanson s research [1] has shown that noise on the power line is impulsive and
synchronous in time with the power signal (60 Hz in North America). The noise oc
curs
at regular intervals that are fixed in time with respect to zero crossings of th
e 60 Hz
mains signal and at these times there is higher probability of data errors. To t
ake
advantage of this information, a communications protocol must be developed.
A communications protocol, in a general sense, is a set of underlying rules that
prescribe
the nature and form of interactions between a network s interconnected devices [15
].
Many protocols exist, each with specific conditions in mind. By drawing on the d
esign
of other protocols and incorporating new information from Hanson s research, a new
protocol can be developed that is suitable for data communication on the power l
ine.
3.2
Choices in Designing a Protocol
There are several variables to consider in the design of a communications protoc
ol.
These include the type of medium that is targeted, system architecture, and flow
and error
control techniques. The following is a review of the choices that will be consid
ered in
the design of this protocol.
3.2.1 Distributed or Centralized Architecture
The first consideration is whether to design a distributed or centralized archit
ecture. The
difference lies in how control of the system is distributed.
23
A centralized architecture has some type of controller that implements the contr
ol logic
for all the I/O points connected to it. This type of system can consist of senso
rs and
actuators that are controlled by some central controller [7]. This can be viewed
as a
Master/Slave setup where there is one Master and several Slaves. The Master is i
n
charge of coordinating who can talk and when.
A distributed system allows a number of intelligent devices to communicate direc
tly with
each other. No intervening supervisory controller is required to poll devices fo
r
information and then retransmit that information to other devices. No supervisor
y device
is charged with responsibility for system-wide control algorithms. This means th
at every
device is capable of publishing information directly to other devices on the net
work [7].
3.2.2 A Multiaccess Medium
In the case of the power line medium, nodes are not joined by one-to-one communi
cation
links. Rather, the medium is one in which the received signal at one node depend
s on the
transmitted signal at one or more other nodes. Typically, such a received signal
is the
sum of the attenuated transmitted signals from a set of other nodes, corrupted b
y
distortion, delay, and noise. Such a medium is called a multiaccess medium. A me
dium
access control (MAC) method is needed to manage communication on a multi-access
medium. The purpose of the MAC is to allocate the multiaccess medium (the power
line)
among the various nodes [16].
There are two general access methods, multiple access and random access. Applica
tions
requiring continuous transmission (e.g., voice and video) are generally allocate
d
dedicated channels for the duration of communication. Sharing bandwidth through
dedicated channel allocation is called multiple access. Bandwidth sharing for us
ers with
bursty transmissions (like data) generally use some form of random channel alloc
ation
that does not guarantee channel access. Bandwidth sharing using random channel
allocation is called random access [17].
24
3.2.3 Channel Sharing
Methods of channel sharing include frequency-division (FDMA), time-division (TDM
A),
code-division (CDMA), and combinations of these methods. In FDMA, the total syst
em
bandwidth is divided into orthogonal channels that are nonoverlapping in frequen
cy and
are allocated to the different users. In TDMA, time is divided into nonoverlappi
ng
timeslots that are allocated to the different users. In CDMA, time and bandwidth
are
used simultaneously by different users, modulated by orthogonal or semi-orthogon
al
spreading codes. Using the orthogonal spreading codes the receiver can separate
out the
signal of interest from the other CDMA users with no residual interference betwe
en users
[17].
3.2.4 Messages and Packets
In an application requiring communication between two or more users, a message i
s one
unit of communication from one user to another. This message is represented as a
string
of bits. In interactive communication, user 1 might send a message to user 2, us
er 2
might reply with a message to 1, who responds with another message, and so on.
Even though a message is a unit of communication, it may not be feasible to send
an
entire message at once. The message can actually be broken down into shorter bit
strings
called packets. Packets can then be assembled at the receiver to re-form the mes
sage.
Packets contain control overhead which is necessary to facilitate communication,
ensuring reliable communication, controlling congestion, achieving synchronizati
on, and
so on [16]. The format of packets is important in order to perform this function
.
The size of packets is also an important consideration. If packets are small, th
en
reliability will be high because a small packet has a lower probability of error
. However,
the actual data throughput using small packets will be lower because each packet
requires
overhead (thus the data to overhead ratio is low). By using larger packets the d
ata to
overhead ratio is higher, but reliability may suffer because larger packets have
a higher
probability of error. The optimum size of packet depends on the error rate of th
e channel,
and the desired reliability and data throughput. This concept is shown in Figure
3.1.
25
Packet
Maximum
Throughput
Packet
Maximum
Throughput
Throughput (bps)
Optimum
Packet Size size (bits)

Figure 3.1 Data Throughput vs. Packet Size.

3.2.5 Efficient Use of the Channel
As with any communication method, efficiency is important. Efficiency in this se
nse
refers to fair and quick access to the channel s available communication capabilit
y. The
basic considerations are as follows:
-When there is only one user of the channel, that user should be able to use the

entire communication capability of the channel.

-When there is more than one user, each user should have equal access to the
channel.
-There should be low delay to gain channel access.
-Collisions among communicating devices should be minimized.
If the number of users is dynamically changing, the protocol should have the abi
lity to
detect when nodes need to send data and be able to quickly reassign access to th
e
channel. There is also the issue of priority whether a certain user is more impo
rtant or
has a more important message to send. Nodes with higher priority should have gre
ater
access privilege to the channel [18].
26
3.2.6 Error Detection
Electromagnetic waves traveling over a transmission medium may encounter noise,
causing errors. It is important to note that errors occur not only because of ch
annel
interference, but also because of collisions (more than one node trying to send
at a time).
Therefore there must be some method that quickly and properly detects bit errors
.
Single-bit errors are the most common type of data error and are the easiest to
detect and
correct. However, multiple-bit errors or burst errors are possible too. For exam
ple, the
byte 11000001 may change to 10000000. Burst errors occur when noise interferes w
ith
the transmission for a longer period of time causing a change in several consecu
tive bits.
A variety of methods are available for detecting transmission errors. Extra bits
add a
form of redundancy, and must be appended to a packet to detect any errors. The s
implest
form of error detection would be to send a copy of each bit, and if the receiver
sees that
there is a disagreement in the first and second bit, it knows there is an error.
This is
inefficient, because it requires that the entire data stream is sent twice. It i
s also
ineffective in the presence of error bursts.
Practical methods require less overhead and the probability of detecting errors
is much
higher, as well some methods are capable of correcting errors. The simplest meth
od is
parity coding. Packets are organized into blocks of bits, and a parity bit is at
tached based
on the number of 1 s in the data block. Even parity means that there is an even nu
mber
of 1 s in the encoded data, including the parity bit. Similarly, odd parity means
there are
an odd number of 1 s in the encoded data, including the parity bit. This scheme de
tects
all single bit errors and burst errors that affect an odd number of bits, but do
es not
provide error correction capability [18] [15].
An extension of parity is an arithmetic checksum. In this method, the sender div
ides the
sending data unit into equal segments of n bits. Then ones-complement arithmetic
is
used to add the segments together to get the result in n-bit form. In ones-compl
ement
arithmetic, the final carry is added to the binary sum. For example, the sum of
the 4

27
bit words 1000 + 1101 = 0101 + 1(final carry) = 0110. This sum is complemented a
nd
appended to the data as the checksum field. At the receiver, the received data (
including
the checksum field) is divided into segments of n bits and when added together s
hould
give a result of all 1s. If not, a data error has occurred. This effectively com
putes parity
vertically, where we have n columns and some number of rows. This detects all 1
bit
errors, all burst errors up to length n, and some larger burst errors. This is s
hown in
Figure 3.2.
Received Data
0011 0100 1110 1001
1001
1110
0100
0011
1000
SUM:
1100
1111
Sum of first and second chunk
Result of first sum plus third chunk
Checksum
All 1 s, it s good!
Figure 3.2 An arithmetic checksum.
The idea of parity check can also be extended to include parity check codes. The
idea is
to start with a bit string and to generate parity checks on various subsets of t
he bits. The
transformation from the string of data bits to the string of data bits and parit
y checks is
called a parity check code or linear code. The word code refers to the transform
ation
itself, and we refer to an encoded bit string (data plus parity checks) as a cod
e word [15].
Several variations of linear codes exist, one of the most popular being Hamming
codes,
which are capable of detecting multiple bit errors and correcting single bit err
ors.
28
Another method is to use a Cyclic Redundancy Check (CRC). This is an efficient
method of generating codewords at the transmitter and checking at the receiver.
These
are most often used for error detection today. Bit strings are treated as polyno
mials, and
nodes perform algebraic manipulation of these polynomials using shift registers
and flip-
flops. A modulo-2 division is implemented by means of a generator polynomial G(x
) of
degree n over the message polynomial M(x) representing the message. The n-bit ch
eck
sequence or the checksum is the remainder of the modulo-2 division of M(x) by G(
x).
This checksum is appended to and sent with the message M(x). The receiver perfor
ms
the same operation on the received data by dividing M(x) (including the CRC) by
the
same G(x) and the result of the division will give a remainder of 0. If the resu
lt is not 0,
transmitting errors occurred.
When a station finds errors, it must perform some form of error control, which i
s
discussed next.
3.2.7 Flow and Error Control
Flow and error control procedures establish the rules for exchanging data betwee
n
devices over a communication link. They ensure that all the related packets arri
ve at their
destination accurately and in order [19]. Physical limitations of the stations m
ust be
taken into consideration. Buffer space, processing capability, and transmission
line errors
are some limitations that must be considered in obtaining proper flow and error
control.
A common error control approach is to have the receiver send a message to the
transmitter indicating that an error has occurred in the preceding transmission,
or that it
received the preceding transmission correctly. The message effectively tells the
sender
whether or not it needs to resend any packets. Thus this type of error control i
s usually
called automatic repeat request (ARQ) [15].
Until the transmitter has received an acknowledgement (ACK) that a packet was re
ceived
successfully, it must store that packet in its memory for retransmission if nece
ssary.
29
There are two major strategies for storing packets until they have been acknowle
dged.
These are the stop-and-wait and sliding window protocols.
The stop-and-wait protocol is used when receiver buffer space is limited, and th
e sender
may not continue to transmit until an ACK is received. The sender sends one pack
et and
then waits for an acknowledgement from the receiver before resuming transmission
. This
method is simple, but has shortcomings. If the transmitter sends a packet that g
ets lost on
its way to the receiver, no ACK will come back. To solve this, the transmitter m
ust have
a time-out period after which time it will re-send the pending data packet. Anothe
r
problem arises if the receiver sends an ACK and it gets lost on its way back to
the
transmitter. The transmitter will time-out and resend the data packet resulting
in
duplicate copies of the packet at the receiver. However, since there is only one
packet
pending at a time, a duplicate can be detected easily by using a sequence bit th
at
alternates between 0 and 1. If two consecutive packets arrive at the receiver wi
th the
same sequence bit, acknowledgement loss or damage must have occurred and the
receiver simply discards one packet. The same concept of the stop-and-wait proto
col for
single packets applies when considering ACKs for entire messages [15].
Packet 1 ACK 1 Packet 2 Packet 2 ACK 2
Timeout Resend
Packet 2
Figure 3.3 Stop-and-wait protocol.
The alternative to the stop-and-wait protocol is the sliding window protocol. In
this
protocol, the sender keeps track of sent and correctly received packets by using
two
counters. Figure 3.4 shows two arms (as in the hands of a clock) that represent
the sent
packet counter and the correctly received packet counter. In the illustration, t
he sent
packet counter indicates that packets up to and including number 6 have been sen
t. The
correctly received counter is advanced when the receiver sends back an ACK and i
n the
illustration, the counter indicates that packets up to and including number 4 ha
ve been
30
correctly received. The difference between the sent packet count and the correct
ly
received packet count indicates the number of packets that have been sent but no
t
acknowledged. Modulo 8 counters have been shown in the illustration and these co
unters
overflow or wrap around when the sender continuously sends a long sequence of
packets. In the protocol, the number of states in the counter is known as the wi
ndow size
and in this example the window size is 8.
1
4
7
0
6
5
2
3 Trailing arm moves clockwise
as ACKS are received
Leading arm moves clockwise
as packets are sent
Figure 3.4 Sliding window protocol, sender s window [15].
The receiver s window is designed in a similar fashion. The two sliding arms indic
ate the
receive packet counter (leading arm) and the acknowledged packet counter (traili
ng arm).
As a packet is acknowledged, the two counters advance to indicate the range of p
ackets
that the receiver is expecting. If a packet is received outside of this range, i
t is taken as a
lost ACK and the packet is discarded [15].
This is an extension of the stop-and-wait protocol that allows a sequence of pac
kets to be
processed simultaneously, resulting in more efficient use of the channel. This r
equires
that packets have sequence numbers. This creates a limiting factor, because the
number
of pending packets between sender and receiver may not exceed the limit allowed
by the
sequence number. That is, if the sequence number consists of 3 bits, then packet
s 0-7
may be generated. The same sequence number must be used for the next group of
packets.
31
Notice that when using the sliding window that the packets are not always number
ed 0-7,
but rather a continuous increment. Also, to allow error-free operation of the pr
otocol, the
maximum number of pending packets may not exceed half of the window size (ie. 4
for a
window size of 8). To prove this, consider a transmission scenario allowing 5 pa
cket
transmissions. Assuming the start sequence number from 0, the transmitter may se
nd
packets 0-4 and will record these in the sending window. The receiver also recei
ves the
packets and adjusts the window accordingly to expect packets 5,6,7,0 and 1 (5 mo
re new
packets). Now suppose that the acknowledgement for packet 0 is lost. The sender
will
send this packet again. The receiver, expecting packets 5,6,7,0 and 1, will acce
pt packet
0 as part of the new set of expected packets. Since packet 0 was from the old se
t of
packets, the protocol has failed.
There are also 2 ARQ mechanisms that can be used with the sliding window protoco
l.
These are go-back-n and selective repeat. In go-back-n, when a transmission erro
r
occurs, the sender retransmits all the packets in the current window (including
ones that
were received correctly). In selective-repeat ARQ, the transmitter performs
retransmission of only the packets that were damaged.
3.3 Review of Existing Multiple Access Protocols
Systems in which multiple users share a common channel in a way that can lead to
conflicts are widely known as contention systems [20]. There are many different
contention systems, and in order to fully understand and design an appropriate p
rotocol
for timed power line communication we will now explore some contention protocols
.
The underlying principle of all the contention (random access) protocols is quit
e similar.
3.3.1 ALOHA
For transmitting data, the simplest random-access technique using Automatic Repe
at
Request (ARQ) is the ALOHA contention protocol. ALOHA is the building block for
many protocols. Whenever demand arises, each station transmits a short data pack
et on a
common channel shared with other users. Some packets will experience collision w
ith
32
others, and thus be corrupted or garbled. Collisions are detected, and the packe
t is
retransmitted, perhaps after a random delay, with the process being repeated unt
il
successful. The destination detects errors by means of built-in error-detection
coding.
The destination then arranges to send acknowledgement packets (ACKS) back to the
sender for each correctly received packet; where an ACK is not received after a
suitable
delay, the sender retransmits the relevant packet. This requires that the sender
store each
packet it sends until it receives and ACK for that packet. This is known as an A
RQ
(automatic repeat request) scheme [21].
Applicable concepts of ALOHA
Pure ALOHA is a good starting point for our protocol. Using built-in error detec
tion and
ACKs to ensure successful communication are useful concepts.
3.3.2 Slotted ALOHA
Pure ALOHA is somewhat inefficient, with a maximum channel utilization of 18.4 %
[20]. An improvement to pure ALOHA was published in 1972 by Roberts that doubles
the capacity of an ALOHA system to 36.8 % [20]. His proposal was to divide time
up
into discrete intervals, each interval corresponding to the length of one packet
. This
method became known as slotted ALOHA because it uses timeslots. In contrast to p
ure
ALOHA, a terminal is not permitted to send whenever it wants. Instead it is requ
ired to
wait for the beginning of the next timeslot [20].
Applicable concepts of Slotted ALOHA
Slotted ALOHA is even more applicable to our system because of the idea of using
timeslots to avoid noise. One of the difficulties with implementing a slotted AL
OHA
system is the need for synchronization between stations. In the case of the powe
r line
network, it is easy to achieve this by synchronizing to and creating timeslots w
ithin the
60 Hz power line cycle since every node in the network is connected to the power
line.
3.3.3 CSMA/CD and CSMA/CA
To further improve performance, many multi-access systems take advantage of the
fact
that a node can hear whether other nodes are transmitting. Instead of data being
sent
33
whenever it is ready, a transmitter must first sense the transmissions of other
stations.
This is known as carrier sensing and incorporating this into a protocol is known
as
Carrier Sense Multiple Access. Multiple access refers to the fact that more than
one node
can obtain access to the link.
This listen before transmit function can be used to implement both persistent an
d
nonpersistent CSMA protocols. In persistent CSMA if the channel is busy, the sta
tion
waits until it becomes idle. When the station detects an idle channel, it transm
its a
packet. If a collision occurs, the station waits a random amount of time and sta
rts all over
again. In nonpersistent CSMA a conscious attempt is made to be less greedy. Befo
re
sending, a station senses the channel. If no one else is sending, the station be
gins doing
so. However, if the channel is already in use, the station does not continually
sense it for
the purpose of seizing it immediately upon detecting the end of the previous tra
nsmission.
Instead, it waits a random period of time and then repeats the algorithm. Depend
ing on
the amount of channel activity, this can lead to better channel utilization, but
longer
delays than persistent CSMA [20] [19].
Ethernet systems are based on CSMA/CD, Carrier Sense Multiple Access with Collis
ion
Detect. Collision Detect describes the ability of the station to detect that ano
ther station
is transmitting at the same time and ceases transmitting immediately. It is nonp
ersistent
a node waits a random time after another transmission has completed to try resen
ding its
data [19].
Localtalk uses CSMA/CA, Carrier Sense Multiple Access with Collision Avoidance.
Collision avoidance means that the protocol attempts to minimize the occurrence
of
collisions on the link. However, it does not sense collisions. Rather it uses Re
quest to
Send/Clear to Send (RTS/CTS) handshaking. When a station has data to send, it se
nds a
request (RTS) and waits for a clear (CTS) and then begins sending. If a RTS is s
ent and
no CTS comes back, this infers that a collision occurred. The idea is that the R
TS and
CTS are short and failed transmission due to a collision is quickly detected. Al
so, it
34
employs non-persistent CSMA by waiting a random amount of time before trying aga
in
[22].
Applicable concepts of CSMA
CSMA is a great concept, but perhaps too complex it requires hardware for both c
arrier
sensing and collision detecting, and there is the possibility that the carrier s
ensing can be
fooled on a noisy medium. However, RTS/CTS handshaking is a good idea and a
variation of this will be implemented in the protocol.
3.3.4 Reservation Slotted ALOHA
The idea of reservation slotted ALOHA is to have the protocol behave like normal
ALOHA under low channel loads and move gradually over to some kind of time divis
ion
multiplexing (TDM) as the channel load grows. There are several variants of this
, one
which was proposed by Crowther et al. in 1973 [20]. His idea is simple whenever
a
transmission is successful, the station making the successful transmission is en
titled to
that slot in the next group as well. Thus as long as a station has data to send,
it can
continue doing so indefinitely. In essence it allows a dynamic mix of ALOHA and
TDM,
with the number of slots devoted to each node varying with demand. When a user i
s
finished with a slot, it lies idle for one group after which time it can be pick
ed up by
another user. In the example below user A is using the second slot, but after 2
groups, no
longer needs it. User D senses it is idle in the next group (group 3) and picks
it up in
group 4. Shaded timeslots indicate collisions where more than one station tries
to use an
idle timeslot [20].
35
A A C G B D E
A A G B D E
A G D
A D D D
Group 1
Group 2
Group 3
Group 4
A C G B D E
A A G B D E
A G D
A D D D
Group 1
Group 2
Group 3
Group 4
Figure 3.5 Reservation slotted ALOHA [20].
Another interesting addition to Reservation ALOHA proposed by Roberts [20] requi
res
stations to make advance requests before transmitting. Each group of timeslots c
ontains,
say, one special slot which is divided into a number of smaller subslots used to
make
reservations. When a station wants to send data, it broadcasts a short request p
acket
during one of the reservation subslots. If the reservation is successful (i.e.,
no collision),
then the next regular slot (or slots) is reserved. Of course, all nodes must kee
p track of
the number of slots that are reserved so to not interfere with others.
Applicable concepts of Reservation Slotted ALOHA
The idea of reserving slots is useful to the timed power line protocol. However,
using a
special reservation slot may be too difficult considering the power line archite
cture and
the fact that any single slot s transmission characteristics can change drasticall
y as the
electrical loads change. However, by using RTS/CTS as we will soon discuss, the
protocol effectively reserves slots for nodes.
3.4 Details of the Power Line Communication Protocol
The important variables discussed earlier are applicable to almost all protocol
designs.
However, because of the special medium and the synchronous nature of noise on th
e
power line [1], a protocol must be designed that is able to detect when noise is
occurring.
Once it detects when noise occurs within the 60 Hz cycle, noise in future cycles
can be
36
avoided because of its synchronous nature. It was also shown that noise times ca
n
change depending on the type of load connected to the line. Hence, once communic
ation
is established in times of low noise, the protocol must continuously or periodic
ally test
the line in order to detect when noise times change and modify communication tim
es as
necessary.
Another goal is to have the protocol as simple as possible. This power line prot
ocol will
most likely be implemented as an add-on part to various home appliances, HVAC, a
nd
other devices that require reliable, medium speed communication. Simplicity will
result
in lower cost devices and hence a more attractive solution for power line commun
ication
applications.
The review of existing protocols extracts several ideas that can be applied to t
he timed
power line communication protocol. However, there are still many things that nee
d to be
defined.
3.4.1 Designing a Centralized or Distributed System
In deciding what type of system to design, several factors are considered. Desig
ning a
centralized system has certain advantages. One master has the power to designate
which
slave is allowed to talk and when, and it allows slave nodes to be simpler. Havi
ng a
master will help take advantage of the fact that noise is synchronous to the pow
er line
cycle because it can detect this and designate communication times simply and
efficiently. Slaves can make requests to the central controller to ask for chann
el access,
and can only send data when the master sees fit and designates the channel accor
dingly.
However, there is one serious consideration when using a centralized architectur
e: not
every node will have equal channel quality when communicating with the master. I
n
fact, throughout a system of nodes connected to the power line, different pairs
of nodes
may have dramatically different communication capability than other pairs of nod
es.
This may be because of spatial location and the type of loads that are close to
each node.
This is shown in Figure 3.6. Node 2 is able to hear both nodes 1 and nodes 3. Ho
wever,
37
node 1 and node 3 have a much longer distance between them, and may not be able
to
hear each other as well. Also, the lamp connected to the line may affect node 1
but have
little effect on nodes 2 or 3. Similarly, nodes 2 and 3 may be affected by the c
omputer
power supply which does not affect node 1.
1 2 3
Figure 3.6 Nodes at different points on the line have different channel characte
ristics.
If we use a distributed architecture, each node will have equal communication lo
gic. This
has the advantage that the system will be easy to add nodes to and when a node i
s
inactive it can simply be quiet or easily disconnected from the system without aff
ecting
other nodes. The downside to this type of system is the increase in complexity.
Channel
allocation becomes a much more difficult problem with no central controller to a
llocate
it. Carrier sensing and collision detection/avoidance is necessary. Also every s
ingle
node will have to keep a record for every other node in the system that keeps tr
ack of
good timeslots for that node. This is because every pair of nodes can have much
different
channel characteristics than every other pair of nodes as shown above in Figure
3.6.
For this work, we have chosen a centralized architecture because it reduces comp
lexity
and the problem of deciding which timeslots to use becomes a much easier problem
.
Also channel allocation is simpler because there is no need for carrier sensing
and
collision detection. Therefore a typical network layout is illustrated in Figure
3.7.
38
1
2
43
5
6
7
8
9
Master
Breaker Panel
1
2
43
5
6
7
8
9
Master
Breaker Panel
Figure 3.7 Typical layout of home or office network.
The best location for the master is at the breaker panel as this position gives
the master
the best location for being able to talk to and listen to all slaves.
The above figure brings up another important issue. The breaker panel presents a
large
attenuation between lines. For example, slaves 1-4 (on the same line) may have r
eliable
communication, but none of them may be able to talk to slaves 5-9. This is becau
se the
signal power coming from any sender gets divided among all other lines connected
to the
breaker panel and also reflected back to the sender because of impedance mismatc
h. This
problem can be solved by using an electrical repeater between lines or having th
e master
relay all incoming messages out onto the other lines. However, the focus of this
thesis is
the design of a protocol, and the breaker panel problem will be left as future w
ork.
3.4.2 Synchronizing to Zero Crossings and Using Timeslots
In the chosen method, the 60 Hz power line cycle is divided into timeslots. The
power
line cycle is approximately 16.67 ms long. This conveniently divides into 16 tim
eslots
that are just over one millisecond long (1.04 ms to be exact). The remainder of
this thesis
will refer to timeslots as one millisecond. Each node must be synchronized to th
e 60 Hz
zero crossings and keep track of timeslots itself. Each node contains timing inf
ormation
and knows that every one millisecond after the start of a power line cycle means
the
beginning of a new timeslot. This results in timeslots numbered 0 through 15 in
one
39
power line cycle. Each power line cycle will bring on a new group of timeslots a
s shown
in Figure 3.8.
0 1
60 Hz power
line cycle
2
Synchronize to
positive crossing
13 14 15
Figure 3.8 60 Hz power line cycle is divided into timeslots 0 through 15.
3.4.3 Timeslot Tables
Timeslot tables are another key to the protocol. Because the power line interfer
ence is
synchronous, it will only cause certain timeslots to be unusable for data commun
ication.
Each node must keep track of this by updating an internal table. The table will
contain a
field for each timeslot that will indicate for each timeslot:
-GOOD (suitable for communication) - DEFAULT
-BAD (unsuitable for communication)
The timeslot tables will be updated based on the success/failure of received dat
a and
attempted transmissions over a period of time. When the system starts up, there
is no
knowledge of the channel, so the quality of timeslots must be checked. The maste
r will
broadcast special check packets and each slave will check the quality of received
packets over a period of time. If a node receives many errors in a particular ti
meslot it
will flag this timeslot BAD. Next the master polls each slave, asking which time
slots it
thinks are good and bad. The master then compares the tables of all the slave no
des and
puts together a master table. This table only has entries GOOD and BAD for each
40
timeslot. GOOD timeslots in the master table are the union of GOOD timeslots bet
ween
all slaves, otherwise timeslots are labeled BAD. This is shown in Figure 3.9 (wi
th only 4
timeslots for simplicity).
Slave 2
Slave 1
1 GOOD
4 GOOD
3 BAD
2 GOOD
Slave 3
1 GOOD
4 GOOD
3 BAD
2 GOOD
1 BAD
4 GOOD
3 GOOD
2 GOOD
Master
1 BAD
2 GOOD
3 BAD
4 GOOD
Only timeslots 2 and 4 are
GOOD in all slaves. Master
will broadcast its table back out
to all slaves, and their tables
will be updated accordingly
Figure 3.9 Master and slave timeslot tables.
Once the master has determined the master table, it will broadcast this to every
slave.
Since the timeslot table is extremely important information, it will broadcast i
t for one
power line cycle in every timeslot. Slaves will check to make sure they get 2 of
the same
copies before they commit the master timeslot table to memory. The slaves then a
ll have
the same timeslot table, and will only attempt communication in those timeslots.

The Master does one more thing that is essential to timeslot coordination, and t
hat is
continuous checking and polling. In timeslots labeled BAD, the master will conti
nue to
broadcast check packets that will be checked for quality by each slave. The mast
er will
periodically poll each slave to see how well it is receiving the check packets,
and if every
slave responds that a BAD timeslot is now GOOD, then that timeslot will be updat
ed to
GOOD in the master table and rebroadcast to everyone. It is important to note th
at while
one slave is talking to another in GOOD timeslots, they may determine that a GOO
D
41
timeslot is actually BAD based on the number of errors. They will give this info
rmation
to the master when they are polled again for their timeslot table.
The period of polling for timeslot tables and updating slaves with the master ta
ble is yet
another variable in this protocol. Loads on the power line can and do change. Co
nsider a
computer power supply once a computer is turned on, it usually stays on for quit
e a
while (minutes to hours). Also, a home light dimmer position may change position
causing a new noise spike but once it is in a position, it usually stays there f
or a lengthy
period. For the purposes of this thesis, the period of polling for timeslot tabl
es is chosen
to be 10 seconds. This means that if a timeslot changes from GOOD to BAD or vice
versa it may not be recognized for 10 seconds, but this is reasonable considerin
g that it
will probably not change again for a considerable period of time. However, it is
extremely important to note that 10 seconds is an estimation by the author, and
the
optimum period between polling may in fact be much different.
3.4.4 Initiating Transmission
The master node controls all data transmission on the line. When a slave has dat
a to send
to the master or any other slave, it must first wait for the master to poll it.
The master
does this every 10 seconds as described above. Each slave s response will include
information on timeslot quality (SQ) and a request to send (RTS) that indicates
the
number of 60 Hz cycles it would like channel access for. The master will then de
cide on
how to allocate the channel to each of the requesting slaves. The master s decisio
ns on
channel allocation will then depend on the number of slaves requesting channel a
ccess
and the amount of data each slave has to send. If there were too many cycles req
uested
by the slaves, the master will not be able to satisfy each slave s request, and wi
ll scale
back each slave s channel access equally.
Once it has decided on the division of channel access, it will send a Clear to S
end (CTS)
to a specific slave indicating to it that it has access to the channel for a cer
tain number of
60 Hz cycles. The designated slave will send its data in GOOD timeslots within t
hose
42
cycles after which time it will quit transmitting. The master will then send a C
TS to
another slave approving channel access for a certain number of cycles.
This process is a variation of Reservation Slotted ALOHA combined with Request t
o
Send/Clear to Send (RTS/CTS) discussed earlier. It is actually more of a reserva
tion
protocol, because the slaves are effectively making channel reservation requests
to the
master.
Also note by making the master designate all channel access, this eliminates the
need for
difficult channel access methods like carrier sensing and collision detection. R
TS/CTS is
employed, but a slave is only allowed to make a RTS when the master asks it to.
3.4.5 Flow and Error Control
Once a slave is clear to transmit its data to another node in the system, it beg
ins sending
packets in the GOOD timeslots that it has been designated. Messages will be brok
en
down into packets that are 1 timeslot long. Each message will have a sequence bi
t, which
is a bit in the header that is the same for every packet in the message. The fir
st data
packet it sends will be the Data Beginning (DB) packet (this is the beginning of
the
message). In every GOOD timeslot after that, it will send Data Middle (DM) packe
ts
until the number of GOOD timeslots passed is equal to the message length and wil
l finish
the data message with the Data End (DE) packet. In the very next GOOD timeslot t
he
receiver will send an ACK packet which acknowledges the entire message (packets
from
DB to DE). If an ACK was received, then the sequence bit is toggled and the next
message is sent (if any) beginning again with DB.
If there were any errors in the transmission of the data packets, a NACK will be
sent back
to the transmitter. The transmitter will then send the entire message over again
with the
same sequence bit. The same action is also followed by the transmitter if no ACK
or
NACK is received in the very next GOOD timeslot. If the receiver actually sent a
n ACK
and it was lost, it will receive a duplicate copy, which it will recognize becau
se of the
sequence bit, and simply discard one of the copies.
43
Notice that the ACK strategy is the stop-and-wait protocol which we discussed ea
rlier.
In this case the timeout period for receiving ACKS is simple just one timeslot.
The
sender knows what timeslot to expect an ACK in and if one isn t received, then it
times
out. Using stop-and-wait helps achieve our goal of simplicity and has sufficient
performance for our protocol.
3.4.6 Packet Format
A packet will be of a rather simple format, loosely based on an Ethernet packet
[23].
Packets are a fixed length of one millisecond, as shown in Figure 3.10.
One millisecond
8 bits 4 bits 4 bits 7 bits 1 bit
8 bits
Synch Dest. Src. Type Data Check
Seq. bit
Figure 3.10 Packet format.
The packet fields are as follows:
-Synch. Byte (8 bits) this is a simple pattern (01111110) that indicates the
start of a packet
-Destination (4 bits) the intended receiver identification number
-Source (4 bits) the sender identification number
-Type (7 bits) the packet type can consist of the following types:
o
Data packets (sent in one timeslot)
Data Beginning first data packet.
Data Middle.
Data End last data packet.
ACK Acknowledgement packet. Sent from receiver to sender
and acknowledges a data message (a group of packets with the
same sequence number). Sent after a Data End packet is received
Check packet is used strictly to check the quality of a timeslot.
o
Control Packets (NOTE: Each of these types must be sent multiple times
within one power line cycle). The data field varies depending on the type
of control packet.
44
PING Master sends this to ask a slave if it has any updates.
Slave has 1 whole power line cycle to respond, within which it
may send requests for channel access and/or timeslot table updates.
The data field is all zeros.
SQ Slot Quality (slave to master). Slave responds after PING
indicating to master which timeslots are GOOD/BAD. The data
field contains which timeslots were GOOD/BAD. A bit is binary
1 if the timeslot is GOOD and 0 if a timeslot is BAD. The first
bit is timeslot 0, and the last bit is timeslot 15.
RTS Request to send data (slave to master). Slave responds after
PING packet. The data field in this packet must contain the
number of power line cycles that the slave wants channel access
(access to all GOOD timeslots for a number of power line cycles)
CTS Clear to send data (master to slave). The data field
indicates to slave for how many timeslot groups (60 Hz) cycles it
can have full channel access
-Sequence bit (1 bit) used for determining retransmissions and duplicate
packets at the receiver
-Data length dictated by modulation technique and symbol rate. For
example, at 100 kbps 100 bits can be fit into one timeslot. 32 bits are
necessary for overhead, which means the data field is 68 bits.

-Error checking (8 bits) 8-bit CRC used for detecting errors

Note that the total number of bits in a packet will be dictated by the bit rate
selected for
transmission. The number of header and error checking bits remains the same (32
bits or
4 bytes), and the number of data bits varies. For example, 56 kb/s would allow f
or a total
of 56 bits in a packet, hence 24 bits or 3 bytes of data. 112 kb/s would allow f
or 80 bits
or 10 bytes of data.
3.4.7 Master and Slave State Diagrams
The master and slave will always have to be in a defined state in order for this
protocol to
function properly. The following state diagrams provide order and clarity to man
y of the
concepts discussed previously.
45
Startup
broadcast Check
packets
After 10 sec.
PING state poll
each slave for
information
PING all
slaves
DATA state
send CTS to
slaves as needed
Assemble and
broadcast Master
Table
CTS all
slaves who
made RTS
After 10 sec.
Startup
broadcast Check
packets
After 10 sec.
PING state poll
each slave for
information
PING all
slaves
DATA state
send CTS to
slaves as needed
Assemble and
broadcast Master
Table
CTS all
slaves who
made RTS
After 10 sec.
Figure 3.11 Master state diagram.
RECEIVE state
monitor line for
data or checks
RESPOND state
send SQ and
RTS if needed
Received
PING
After 1
power line
cycle
SEND state
send data in
GOOD timeslots
Received
CTS
Time up or out
of data
Figure 3.12 Slave state diagram.
46
3.4.8 Protocol Operation Example
Features of the protocol have been discussed up to this point, but it may be a b
it
overwhelming to put all of these facts together to determine how the protocol wo
rks. For
that reason, an example follows, step by step, of a startup procedure followed b
y a data
transmission. For this example, the master is just starting up, and no nodes in
the system
have any knowledge of the channel.
1)
The master broadcasts check packets to all slaves in every timeslot for 600 60
Hz cycles. The number of power line cycles should be sufficient to get an
accurate representation of GOOD/BAD timeslots (this will be a 10 second
test).
2)
The master will then send out a PING to the first slave (starting with slave
number 0), in every timeslot for one power line cycle and wait for a response
from the slave for the next entire power line cycle.
3) If the slave exists, it will respond throughout the next cycle with SQ (slot
quality) packets and RTS (request to send) packets. SQ packets will be sent in
the first half of the GOOD timeslots, and RTS in the second half. If it has no
data to send, the data field in the RTS packet will be 0.
4)
The master will try all 16 destination numbers, and if there is no node for a
sequence number there will simply be no response. The master will also
remember which nodes are present in the system based on whether there was a
response or not. If there was no response from a slave when it was actually
present but could not be heard, this will be taken as a slave that does not exis
t.
5)
The master will then create its master table indicating all common GOOD and
BAD timeslots for the system and broadcast it in every timeslot for one power
line cycle.
6)
The master then sends a CTS in every timeslot for one power line cycle to the
first slave indicating in the data field how many power line cycles it is allowe
d
to have access to the channel for (depending on the number of cycles the slave
requested).
a.
If a slave s RTS was not heard by the master, it will not be included in
the channel allocation.
b.
If a slave does not hear a CTS, it will miss its opportunity to transmit
and the channel will be left idle for this period. Also, if by error a
slave hears a valid CTS for two slaves (including itself) it will not
consider the CTS s valid. This will avoid collisions in the case that an
error causes a valid CTS to two different slaves. The slave will then
have to request channel access again when it is polled.
c.
If the master received too many RTS s, that is, it cannot satisfy the
channel demand from everyone, it will only grant each slave what it is
able to. It will reduce the number of power line cycles each slave has
access to, with no preference given to any. Slaves will realize this and
have to make another RTS in the next cycle. If this continues, the
47
slaves will have to reduce the amount of time they request access to
the channel.
7) The slave will use all of the GOOD timeslots for the number of power line
cycles it has been allowed to send its data.
a.
The slave s first timeslot transmission will be the Data Start packet,
and the destination node will receive this and watch for Data Middle
packets, and finally the Data End packet
b.
After the receiver verifies the Data End packet, it will send an ACK
packet to indicate if it received the entire message, or a NACK if there
was an error
c.
If the message was not received correctly (a NACK came back, or no
ACK was received), the transmitter will send it again with the same
sequence bit. If the ACK was actually sent by the receiver and it was
lost, it will recognize the duplicate packet because of the sequence bit
d.
When an ACK is received, the sender will begin with another Data
Start packet, and so on until it has no more data to send or it is out of
its allotted time for channel access
e.
When a sender is finished transmitting all its data or it runs out of the
power line cycles allocated to it, it simply quits transmitting
8) Notice that senders are only sending in GOOD timeslots. The master,
however, broadcasts check packets in BAD timeslots that the sender is
skipping so that the quality of timeslots can be monitored in case of any
change.
9) Every 10 seconds, the master will repeat its PING cycle asking for updated
timeslot tables and data requests from each slave, assembling the master table,
and rebroadcasting it to all slaves, and finally sending CTS to slaves who
requested channel access.
The entire process is illustrated in Figure 3.13.
48
Check
Master broadcasts
check packets in every
slot for 10 seconds.
PING
Master sends out
PINGs to slave 0 in
every timeslot asking
for timeslot quality and
if it has any data to
send.

Response
Slave 0 responds to
master with SQ and
RTS packets for one
timeslot. (example -
requests 2 cycles).
Master sends PING
packets to each slave
in sequence, each
slave responds with SQ
and RTS. Also, master
assembles and
broadcasts timeslot
table.

CTS Data Data

Master sends CTS in Slave 0 sends data in Same as previous
all timeslots to slave 0 all GOOD slots, and cycle, but this is now
for one full cycle master broadcasts the second and last
(example - tells slave 0 check packets in bad cycle for slave 0.
it s clear to send for 2 slots (shaded).
cycles). Receiver sends ACKS
back in GOOD slots.
Figure 3.13 Example of protocol operation.
49

Slave 0 stops, and

master sends CTS to
another slave who
made a RTS. After 10
seconds, master PINGs
each slave again
(repeats process
beginning at PING
cycle above).
4. Half Duplex Modem Design
4.1 Bandwidth Considerations
Bandwidth for an ideal transmission system is defined as the range of frequencie
s passed
by the system in an undistorted manner. Similarly, the bandwidth of a signal is
defined
as the range of frequencies contained in the signal. A proper match between sign
al and
transmission system results if the passband of the system extends over the compl
ete range
of frequencies occupied by the signal [19]. In the case of power line transmissi
on, there
are governing bodies that place restrictions on the signal bandwidth. In the Uni
ted States
this governing body is the Federal Communications Commission (FCC) and in Canada
there is Industry Canada.
The FCC states that frequencies 9 - 490 kHz are allowed for signaling on the pow
er line
[24]. It is also stated that transmitting on the power line creates an unintenti
onal radiator
and that this must not cause harmful interference. The system must also be able
to accept
other interference that may be caused by other radiators such as an authorized r
adio
station, by industrial, scientific and medical equipment, or by another intentio
nal or
unintentional radiators [24].
Industry Canada provides guidelines for transmission on the power line in the ba
ndwidth
0 to 535 kHz including the carrier voltage limits for installation in residentia
l and office
buildings as shown below [25].
50
 Below 9 kHz: No limits
9 - 95 kHz: 15.0 volts pk-pk
95 - 105 kHz: Restricted Loran C time signal frequency
105 - 185 kHz: 15.0 volts pk-pk
185 - 535 kHz: .45 (B/D)½ volts pk-pk or 15.0 volts pk-pk,
whichever is the lesser voltage. B = 6 dB
bandwidth in kHz. D = duty cycle (D = 1.0 for
continuous transmission)
This work will adhere to the bandwidth of 105 kHz to 490 kHz which will satisfy
restrictions placed by both the FCC and Industry Canada.
Available
Bandwidth

Frequency
(kHz)
0 100 200 300 400 500 600
Figure 4.1 Available spectrum for power line communication.
4.2 Modulation
Basic digital signals have a low-pass characteristic in that the frequency conte
nt of the
signals extend from 0 Hz to some maximum value. These are referred to as baseban
d
signals [19].
Transmission systems have some available bandwidth, and this seldom includes the
lower
frequency range of the baseband signal. Hence transmission systems must use some
form
of modulation to shift the frequency content of a signal from one region of the
spectrum
to another. The simplest form, amplitude modulation, involves multiplying a sign
al by a
sinusoidal carrier signal. This moves the baseband signal to a frequency range c
entered
about the frequency of the carrier and the occupied bandwidth is doubled. Demodu
lation
is performed at the receiver for shifting the received modulated signal frequenc
ies back to
baseband [19].
51
4.2.1 Choice of Modulation Scheme
There are several forms of modulation available. Some of the better known ones a
re
amplitude shift keying (ASK), frequency shift keying (FSK), phase shift keying (
PSK),
and spread spectrum as discussed earlier in this thesis. The passband modulation
scheme
chosen for this thesis is frequency shift keying (FSK).
Frequency shift keying has two different frequencies, one for mark (binary 1) an
d one for
space (binary 0). This is the same thing as modulating an FM carrier with a bina
ry digital
signal. Frequency shift keying is a popular choice for modulating data signals o
n the
power line because it is easy to generate and demodulate. However, it is somewha
t
spectrally inefficient as compared to other methods so this limits data rates. S
ince the
focus of this thesis is the communication protocol, optimizing data rate is not
considered,
and frequency shift keying (FSK) was selected because of its ease of implementat
ion.
The spectrum of an FSK signal is shown below. Its bandwidth is determined by two
factors: the mark and space frequencies chosen and the symbol rate [19].
|S(f)|
f1 and f2 = mark and
space frequencies

Figure 4.2 FSK Spectrum.

This work will use mark and space frequencies of 150 kHz and 250 kHz respectivel
y, and
a symbol rate of 60 ksymbols/sec. From Figure 4.2, it can be concluded that the
Frequency f1 f2
1/2TFrequency
spectrum
T = 1/Symbol rate
52
bandwidth occupied by this signal is from 120 kHz to 280 kHz, for a total bandwi
dth of
160 kHz.
4.3 Universal Asynchronous Receive/Transmit (UART)
Universal Asynchronous Receive Transmit (UART) is a device that uses start-stop
asynchronous format. This format is typically character based with a start bit,
an 8-bit
character, and one or 2 stop bits for a total of 10 or 11 bits. It is often used
for
applications that need a simple method of communicating low-speed data between
equipment. It is a form of serial communication, meaning that one bit is transmi
tted at a
time. The term asynchronous is used because it is not necessary to send clocking
information with the data that is sent. Typical applications of asynchronous lin
ks are
connections between terminals and computer equipment [26].
The protocol is character oriented, and transmission is carried out without cont
inuous
character synchronization between the transmit and receive devices. In this mode
each
character or chunk of data has to be identified separately, and hence the beginnin
g and
the end of each character must be marked. These are the start and stop bits
respectively.
Instead of having transmit and receive clocks connected, the receiver synchroniz
es itself
based on the start bit. The receiver oversamples the incoming data stream, usual
ly by a
factor of 16, (16x but can also be 8x or 32x) and uses some of these samples to
determine
the bit value. The oversampling clock is synchronized by the leading edge of the
start bit.
If 16x oversampling is used, every 16 samples from the oversampling clock will
represent a data bit. Traditionally the middle three samples of the 16 samples a
re used.
Two UARTs can communicate like this if parameters such as bit rate and character
length
are the same for both transmitter and receiver.
When a complete byte is received, a flag is set to indicate that a data byte is
ready to be
read. This can cause an interrupt if the device is programmed to do so. Similarl
y, when a
complete byte is transmitted this causes an event which can cause an interrupt i
ndicating
53
that another byte can be transmitted. When data bits are not transmitted in the
UART
protocol, a continuous stream of ones is transmitted, called the idle condition.
Since the
start bit is always zero, the receiver can detect when data is once again presen
t on the
line.
UART characters were chosen for testing the power line protocol because of ease
of
implementation. Communication can occur over a single wire, and clocking is take
n care
of by the transmit and receive oversampling clocks so no clock transmission or c
lock
recovery needs to be implemented. If the maximum character size and one start an
d one
stop bit is used, the overhead involved with using UART characters is 2/10 (or 2
0%), but
several characters can still be fit into one timeslot and actual operation of th
e power line
protocol can be studied which is the focus of this thesis. The UART transmission
format
is shown in Figure 4.3.
5-8 Data bitsIdle
Start bit Stop bit(s)
Idle or new start
RX clk 8X,
16X or 32X
Figure 4.3 UART character format.
4.4 Hardware Implementation
Figure 4.4 shows the half-duplex modem block diagrams, and in the following
subsections are descriptions of each system block. Each modem is half-duplex bec
ause it
has the ability to both talk and receive, but not at the same time (which would
make them
full-duplex).
54
MC68360
QUICC
Personal
Computer
FSK
Modulator
Zero Crossing
Detector
Bandpass
Filter
FSK
Demodulator
Line
Driver
Line
Coupler
MC68360
QUICC
Personal
Computer
FSK
Modulator
Zero Crossing
Detector
Bandpass
Filter
FSK
Demodulator
Line
Driver
Line
Coupler
Figure 4.4 System block diagram for both master and slave.
4.4.1 Personal Computer
The PC is needed for loading, starting and stopping execution of programs on the
MC68360 microprocessor. This computer runs Slackware Linux [27] and is loaded wi
th
libraries specific to the MC68360. Program loading is done through the computer s
parallel port.
4.4.2 Zero Crossing Detector
The zero crossing trigger is simply a power line clipper . It uses an LM311 voltage
comparator to monitor its input (from the power line) and if the voltage is posi
tive, it
outputs +5 V. If the input voltage is negative, the zero crossing trigger output
s 0 V.
Obviously when considering the 60 Hz power line cycle as an input, the zero cros
sing
trigger will output a 5 Vo-p 60 Hz square wave. This trigger as designed may cau
se
bounce at the zero crossings (due to noise). To avoid this, the microcontroller wa
s
programmed to ignore multiple edges within one millisecond of the initial edge.
55
4.4.3 MC68360 QUICC
The MC68360 is a Motorola microprocessor designed for communications application
s.
QUICC stands for QUad Integrated Communications Controller because there are fou
r
serial communication controllers on the device [26]. For this application howeve
r, only
one is needed. The controller has an operating system on it called RTEMS (Real T
ime
Executive for Multiprocessor Systems) [28]. RTEMS provides a means to send event
s
between processes and helps processes and events occur within a specific time in
terval
(hence the name real time).
The QUICC is the control center for the system. It contains the program implemen
tation
of the protocol designed in Chapter 3, and once the program is loaded into the Q
UICC by
the personal computer, it begins execution of the program immediately. The QUICC
uses the 60 Hz, 5 Vo-p square wave input from the zero crossing trigger. An edge
-
triggered interrupt is used to synchronize transmission and reception to the zer
o crossings
of the power line cycle. Once it receives the zero crossing interrupt, it uses a
n internal
timer that interrupts every one ms. This timer interrupt is used to count out ti
meslots 0
through 15.
The transmit and receive lines are connected to the first of the four QUICC s seri
al
communication controllers (SCCs). There are several modes that must be set for t
he for
SCC to operate properly and of particular importance are the transmit/receive da
ta format
and baud rate. Several communication protocols are available on the chip and, as
described earlier, the chosen method was to use the Universal Asynchronous
Receive/Transmit (UART). The UART was programmed to transmit and receive data
one byte at a time, and receive interrupts were programmed to indicate whenever
a byte
of data is received. After a byte is received and the interrupt is triggered, a
routine
executes that adds the byte to the received data and handles it depending on its
type.
4.4.4 FSK Modulator
The FSK modulator is an Agilent 33120A 15 MHz Function/Arbitrary Waveform
Generator. Using the FSK mode on the 33120A is convenient because it allows full
y
56
programmable mark and space frequencies and signal amplitude [29]. The 33120A ha
s a
50 O output impedance and does not have the current output capable of driving th
e line,
which is why a line driver is needed.
4.4.5 Line Driver
The line driver is more complicated than one might first think. Instead of just
having a
buffer that drives any signal on its input onto the power line, there has to be
some method
of disconnecting the buffer from the line when there is no data being sent. This
is
because UART characters are transmitted onto the line, and when there is no data
being
sent a simple buffer would constantly drive the 1 frequency onto the line (idle st
ate). If
some other device is trying to drive UART characters onto the line, this device
will not
be able to hear them because its own line driver is driving the idle state. The
most
obvious solution would be to used a tri-state buffer, but no part could be found
at
reasonable cost that had the output current necessary to drive a signal onto the
power line.
This problem is solved by using a resistor between the buffer output and the lin
e and a
switch which only connects the buffer to the FSK source when there is data to be
sent and
connects it to ground otherwise as shown in Figure 4.5. An input from the MC6836
0
tells the switch when data is to being sent or not (and hence whether to connect
the buffer
input to the FSK source or ground). When the buffer input is ground, it drives i
ts output
to 0 V and the resistor acts as a termination for any signal that is coming in o
n the line.
When the buffer input is connected to the FSK source, the buffer s output must dri
ve the
FSK signal onto the line through the resistor.
FSK source
GND
Buffer
Control Signal from 68360
R
To Line Coupler
To Receiver Filter
Figure 4.5 Line driver.
57
The choice of resistor is important in order to maximize power transfer onto the
line and
maintain the highest possible amplitude when terminating incoming signals. A 10
ohm
resistor was chosen for this implementation because it is a reasonable approxima
tion to
the line impedance for the frequency range that we are interested in (105 490 kH
z).
4.4.6 Bandpass Filter
A bandpass filter is needed because of the broad spectrum and high amplitude of
noise on
the line. The filter passes the frequency range of communication (determined by
FSK
mark and space frequencies and the data rate) and rejects all other frequencies.
This filter
was implemented in the same way as in Hanson s research [1].
4.4.7 Demodulator
Once the line signal is filtered and amplified, it is demodulated using an FSK
demodulator chip (XR2211). It has a programmable center frequency fo and if it d
etects a
signal above or below this frequency it outputs +5 V or 0 V respectively. The
demodulator implementation is described in the XR2211 data sheet (in the appendi
x), and
can be seen in Hanson s research [1].
4.4.8 Line Coupler
The line coupler is necessary to interface the communication electronics to the
power line
and also to isolate them from the high voltage levels found on the power line. T
he line
coupler is a simple device consisting of a resistor, capacitor and transformer.
Proper
selection of the resistor and capacitor ensures that the 60 Hz mains signal is g
reatly
attenuated so it doesn t affect the communication electronics, yet higher frequenc
ies pass
through with little attenuation.
58
1.5 µF
To transmitter
and receiver 470 kO
Figure 4.6 Line coupler.
4.5 Software Implementation
For the purposes of testing in this thesis, only the master and one slave were
programmed. The 68360 microprocessors were programmed using the UART, a timer,
and an external edge-triggered interrupt to implement the function of the protoc
ol.
Beyond programming these device-specific features, a model of the protocol for b
oth the
master and slave was programmed.
Once the 68360 is loaded, it begins execution immediately. Upon receiving an edg
e-
triggered interrupt from the zero crossing detector, it resets a timeslot number
index to 0
and also resets an internal timer. The timer counts to one millisecond and then
causes an
interrupt that is used to increment the timeslot number index. The timer does no
t stop
upon interrupting however; it resets immediately and counts to one millisecond a
gain,
repeating its interrupt. Once the timeslot number index reaches 15, it stops the
timer and
waits for the next edge trigger from the zero crossing trigger. This process rep
eats as
long as the zero crossing trigger continues.
After the master and slave have established a common timeslot table (as describe
d in
Chapter 3), the master enters a data mode where it sends variable length data mess
ages
to the slave, only in GOOD timeslots. In BAD timeslots, the master sends check
packets so quality can be continuously monitored (these are interleaved with sla
ve
transmissions). The range of message lengths that it sends to the slave is progr
ammable
59
(must be written into the actual programs, then compiled and loaded into the
microcontrollers), by specifying message_length_range_beginning and
message_length_range_end. The length of the first message will be
message_length_range_beginning, and the next message sent will be
message_length_range_beginning + 1, and so on. After each message is sent, the m
aster
expects an ACK in the next timeslot after the end of the message as described in
the
protocol section in Chapter 3. Once the message length reaches
message_length_range_end, one message length sweep has been completed and the
master starts over sending a message of length message_length_range_begin. The m
aster
sweeps through the range of message lengths for a number of times that is specif
ied by
the programmable constant num_sweeps. Once it has completed the message length
sweep num_sweeps number of times, it only sends check packets in every timeslot.
After a total of 10 seconds since the beginning of the cycle, the master sends a
nother
ping to the slave and the slave responds with the quality of timeslots. The master
then
repeats this entire cycle.
The slave checks messages and stores the number of each message length it receiv
ed
without error. The slave also keeps a count of the number of CRC errors in each
timeslot
so that it can continuously identify GOOD and BAD timeslots. This is possible be
cause
even though a message may span multiple timeslots, each timeslot has only one pa
cket
(which contains a CRC). The master also counts and stores the number of ACKS it
received for each message length in the message length range. The process includ
ing
startup is shown in Figure 4.7.
60
Startup mode Data mode Startup mode Data mode
Ping Ping Ping
10 sec. of

10 sec. of

10 sec. of var.

10 sec. of var.
Master check packets
check packets
length packets
length packets

Slave Slot quality Slot quality Slot quality

response response response

Figure 4.7 Master/Slave Communication Process.

In order to monitor the quality of reception by the slave on an oscilloscope, at
the
beginning of each timeslot the slave sets an output pin high if it correctly rec
eived a
packet in that timeslot in the last power line cycle. Also, both the master and
slave have
output pins that are set high at the beginning of a timeslot that is GOOD in the
timeslot
table and set low if the timeslot is BAD in the timeslot table. This pin s output
should be
exactly the same on the master and slave when viewed on an oscilloscope once the
master and slave timeslot tables have been coordinated.
Also for reporting purposes, the KERMIT protocol [30] was used. This is a progra
m that
facilitates communication between computers using the serial port. In this case,
it was
used to connect the 68360 to a PC. Using this interface, every time that a 10 se
cond
period is completed, both the master and slave send text reports which are print
ed on the
screens of their respective PCs. The slave reports the number of power line cycl
es that
data was received in (which is 600 for 10 seconds), the number of errors it rece
ived in
each timeslot, and the number of times it received each message length without e
rror.
The master reports the number of power line cycles it sent data in (600), and th
e number
of ACKS it received for each message length.
For the CRC-8 checkword generation and verification, the program used a shift re
gister
implementation which involves shifting and exclusive-OR operations. A generator
polynomial is necessary, which is 0x07 for CRC-8. The generator polynomial is
common to both the transmitter and receiver and is necessary for CRC generation
and
61
decoding. A 2-input exclusive-OR gate is placed in between bit positions in the
shift
register that correspond to binary 1 in the generator polynomial. The inputs to th
is
exclusive-OR gate are 1) the previous bit and 2) the output of the shift registe
r (which is
fed back). The output of the exclusive-OR is fed into the next bit position. In
CRC
generation, an 8-bit shift register is cleared and the entire bit string is shif
ted in. Eight
zeros follow the data bits and the resulting content of the shift register is th
e desired
checksum. This is appended to and transmitted with the data.
When receiving, a similar process is carried out. Each byte received is shifted
into an 8bit
register and the output of the shift register is exclusive-ORed with the bits at
the
positions in the shift register corresponding to the bit positions that are 1 in
the generator
polynomial (same as above). After the last received byte (the checksum) is shift
ed into
the register, the contents will be all 0 if there were no transmission errors. I
f any bits in
the shift register are not 0, a transmission error has occurred. Figure 4.8 illu
strates the
CRC shift register implementation.
1100101
Exclusive-OR
Figure 4.8 CRC shift register implementation (transmitter and receiver).
62
5. Protocol Performance
This chapter presents and discusses the performance of the power line protocol d
escribed
in Chapter 3 using the implementation described in Chapter 4. All tests were per
formed
at the offices of Telecommunications Research Laboratories (TRLabs) in Saskatoon
,
Saskatchewan. Two desks were used, referred to as desk 1 and desk 2 in each test
; each
desk connected to the power line and had multiple bench outlets. The distance fr
om the
bench outlets to the wall socket (which each desk plugged into) was approximatel
y 3
meters. In addition, extension cords were often used to increase distance betwee
n the
master and slave. Each test shown in this chapter was conducted over a period va
rying
from 5 to 20 minutes and with master and slave in different locations, depending
on the
type of test. These short term tests were considered sufficient to provide meani
ngful
performance measures for the timed power line communication protocol.
For all tests, the same mark and space frequencies were used (150 and 250 kHz
respectively) with a symbol rate of 60 ksymbols/sec. This signal occupies a band
width of
180 kHz. The allowed transmitting amplitude (from Chapter 4.1) is then .45(B/D)
=
.45(180/1.0)1/2 = 6.04 Vp-p. For all of the tests in this chapter, a transmittin
g amplitude
of 6.0 Vp-p was used unless otherwise noted.
5.1 Data Transmission Performance
Figure 5.1 shows the 60 Hz mains voltage and the received noise signal (after th
e line
coupler). One can notice the 60 Hz mains voltage is a sinusoid, but has peaks th
at are
somewhat flattened. This is because of power supplies loading the 60 Hz mains vo
ltage
at its peaks. Once the 60 Hz mains voltage begins to decrease, the power supply
diodes
stop conducting, and the flattening effect disappears until the next peak. When
looking at
63
the received noise trace, it is obvious that the highest level of noise is cause
d by the
switch-off of the current to the power supply.
Also, notice the information available on the oscilloscope display. Each trace i
s
numbered on the left hand side, and in this case there is trace 1 and 4. The sca
le is shown
in the lower left corner. Channel 1 has a scale of 100 V/division and channel 4
is using
500 mV/division (these are vertical divisions). The time per division (horizonta
l
divisions) is also seen in the lower middle, and is 2.00 ms/division. Other info
rmation
available on the oscilloscope is triggering information (how the display is sync
hronizing
to the signals). In the lower middle and right of the display, the oscilloscope
is showing
that its trigger source is Line at 1.10 V, and the display is shifted to 4.18 ms a
fter this
trigger point (indicated by the arrow pointing to the right just before 4.18 ms)
.

Figure 5.1 AC mains voltage and power line noise.

64
For the first data transmission test, check characters were transmitted continuo
usly and
checked at the receiver using the microprocessor setup described in Chapter 4. R
ecall
that this system was designed using UART characters for transmission, so this is
the
smallest data entity that can be checked for errors. If a character was received
without
error, a logic 0 was produced on an output pin of the microprocessor. If the chara
cter
had any errors, a logic 1 was produced on the same output pin. Also, the 60 Hz mai
ns
voltage was divided into one millisecond timeslots and checked for errors. Simil
arly
when checking timeslot errors, if any byte within a one millisecond timeslot was
in error,
a logic 1 was produced on an output pin of the microprocessor for the entire times
lot in
the next power line cycle, and if no errors occurred a logic 0 was produced.
Figure 5.2 shows the results of this test, performed with the transmitter on des
k 1 and the
receiver on desk 2 (separation of 3 meters) with a 3 meter extension which provi
ded a
total separation of approximately 6 meters. The test was conducted during busine
ss hours
on a weekday. A Tektronix oscilloscope was set up in average mode in order to ob
serve
the byte and timeslot error characteristic. The average mode on the oscilloscope
takes the
running average of 4, 8, 16, 32, 64, 128, 256 or 512 consecutive traces and disp
lays this
average. For this test, an average of 256 was used. The traces are (in order fro
m top to
bottom): 60 Hz mains voltage, received signal and noise, byte errors, and timesl
ot errors.
As expected, the byte and timeslot errors occur at the same time position as the
high level
of noise produced by the power supplies.
65
Figure 5.2 Byte and timeslot errors.
For the same test setup, the number of errors in each timeslot and timeslot erro
r
percentage for each timeslot was recorded and displayed by the microprocessor.
Timeslot error percentage was used here rather than bit error percentage because
the
program was set up to count timeslot errors, not bit errors. A single timeslot e
rror means
that at least one bit in the timeslot was incorrect. Results are shown in Table
5.1. Figure
5.3 is a graphical representation of this data. Note the relative error ratios t
imeslots 5
and 13 have many times the errors of all other timeslots.
Recall that an 8-bit CRC was used to detect errors in the packets. Even though C
RC has
excellent error detecting capability, there are still some errors that the CRC w
ill not
detect. The error detecting ability of the CRC provides detection of all burst e
rrors of 8
bits or less, and all error patterns of an odd number of bits [18]. The error pa
tterns that
are not detected are multiples of the generator polynomial in this case 10000011
1. In
66
fact, an error burst of greater than 8 bits is detected with probability 1-0.58
= 0.996 [18].
This is a small number of errors, and not necessary to detect because the only c
oncern of
the protocol is detecting an error ratio and comparing it to a threshold. The sm
all number
of errors missed will have a negligible effect on whether the error rate reaches
the
threshold or not.
Table 5.1 Microprocessor report of timeslot errors.
Total number of cycles 60712
Timeslot # Errors Error %
0 260 0.43%
1 257 0.42%
2 231 0.38%
3 482 0.79%
4 486 0.80%
5 13383 22.04%
6 130 0.21%
7 149 0.25%
8 188 0.31%
9 525 0.86%
10 423 0.70%
11 345 0.57%
12 126 0.21%
13 14156 23.32%
14 217 0.36%
15 147 0.24%
Average Slot Error Ratio
25%
20%
15%
10%
5%
0%
0 1 2 3 4 5 6 7 8 910 11 12 13 14 15
Timeslot #

Figure 5.3 Graphical representation of timeslot errors.

67
Probability of transmission error vs. the number of timeslots used (out of 16) w
as tested
for two fixed message length transmissions (length 5 and 15 timeslots). The pack
ets
were transmitted continuously so all timeslots were used equally. The duration o
f this
test was approximately 5 minutes. A successful transmission included an ACK, mea
ning
the time to complete a message transaction was 6 and 16 timeslots respectively.
The
number of timeslots used was varied from 1 to 16, using the lowest error ratio t
imeslots
first and the highest error ratio timeslots last. The first 14 timeslots had app
roximately
the same error ratio (< 1%) while the last two had error ratio > 20%. Figure 5.4
shows
the results of this test and as expected, using the high error ratio timeslots r
esults in a
much higher probability of error. Also note that the longer message (length 15)
is
affected more by the high error ratio timeslots. If a longer packet is used, the
re is higher
probability that it will use a high error ratio timeslot and thus higher average
probability
of error.
Probability of Error
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0 2 4 6 8 10 12 14 16
Number of Timeslots used (out of 16)

Length 15
Length 5
Figure 5.4 Probability of Error vs. Number of Timeslots used (out of 16).
A similar test was conducted to test efficiency vs. number of timeslots used. Ag
ain, a 5
minute test was conducted. Ideal efficiency varies linearly with the number of t
imeslots
used (ranging from 1 to 16). If the full capacity of the channel is used (all 16
timeslots)
68
and there are no data errors, then efficiency is 1.0. If half of the channel is
used (8
timeslots) and there are no data errors, then efficiency is 0.5. In the practica
l case
however, data errors cause efficiency to deviate from the ideal case. Again, two
fixed
length messages were used (length 5 and 15, with message transaction time 6 and
16
timeslots respectively) and the number of timeslots used varied using low error
ratio
timeslots first and high error ratio timeslots last. As can be seen in Figure 5.
5, as the
number of low error ratio timeslots used increases there is little deviation fro
m the ideal
efficiency curve. However, as the last two timeslots are included for data trans
mission,
not only does the curve fall below ideal efficiency, the efficiency actually dec
reases
which is an obvious indication that these timeslots should not be used for data
transmission. Also note that using the high error ratio timeslots has less effec
t on
efficiency of the shorter transmission (length 5) than the longer transmission (
length 15).
One conclusion that can be drawn from this is that if efficiency does not decrea
se by
adding a higher error ratio timeslot, then it can be used for transmission. The
threshold
error ratio that causes efficiency to decrease varies with message length. Detai
ls of this
are studied later in the chapter.
1.0 Ideal
0.9
0.8 Length 5
0.7
0.6
0.5 Length 15
0.4
0.3
0.2
0.1
0.0
0 2 4 6 8 10 12 14 16
Number of Timeslots used (out of 16)
Efficiency
Figure 5.5 Efficiency vs. Number of Timeslots used (out of 16).
69
5.2 Adapting to BAD Timeslots
Adapting to bad timeslots is the key to the timed power line transmission protoc
ol. For
this test, the transmission environment was exactly the same as in the previous
section.
The master was placed on desk 1 and the slave on desk 2 with a 3 meter extension
cord
for a total distance of approximately 10 meters. The timeslot error ratio was th
e same as
displayed in Table 5.1.
It is important to choose an appropriate timeslot error threshold for qualifying
a timeslot
as good or bad. In this case, it is obvious which timeslots are bad as timeslots
5 and 13
have a much higher error ratio than all other timeslots as illustrated in Figure
5.3.
Therefore in this case the threshold error ratio for labeling a timeslot BAD was
programmed to be 10%, as this easily labels the timeslots.
Figure 5.6 shows an oscilloscope capture of the protocol in action. The traces a
re (in
order from top to bottom): 60 Hz mains voltage, GOOD/BAD timeslot indicator, and
received signal and noise at the slave. Notice that the amplitude of the noise (
measured
in the bandwidth < 500 kHz) exceeds the signal amplitude by several multiples at
certain
times. The GOOD/BAD timeslot indicator simply produces a high output when the
current timeslot is GOOD, and a low output when the current timeslot is BAD. At
the
time of capturing this image, the master and slave had been communicating for at
least
one PING cycle (the necessary time to communicate timeslot table information). A
s
expected, the protocol has labeled two timeslots BAD and they correspond in time
to the
position of the switch-off point of the power-supply rectifiers.
70
Figure 5.6 AC mains voltage, GOOD/BAD timeslots and received signal.
5.3 Protocol Performance Tests
The above test results agree with the results of Hanson s work [1] in that data er
rors are
synchronous with the 60 Hz mains voltage. Chapter 3 described the protocol to ad
apt to
the timeslots with high error rates, and the purpose of this section is to study
the
performance of the protocol. In particular, the performance improvement in adapt
ing to
the synchronous power line noise is studied.
Performance can be measured by several factors. For this work, probability of
transmission success, packet throughput, and transmission efficiency were used a
s
performance measures. There are several variables that must be kept constant bet
ween
tests such as distance between master and slave, transmit amplitude, time of day
, and
loads connected to the line. For all of the performance tests in this section, t
he same test
71
setup was used as in Section 5.2 with master on desk 1 and slave on desk 2 and a
3 meter
extension cord for a total transmission length of approximately 10 meters. The t
ransmit
amplitude was kept constant, and all tests were conducted in early afternoon (1-
3 p.m.)
on a weekday. To verify that the test comparisons were fair, timeslot error rati
o was
measured before a performance test was conducted to ensure that it was approxima
tely
the same as in Table 5.1
The first performance measure is probability of transmission success. For this t
est, the
master and slave go through a check cycle to determine their timeslot tables bef
ore
sending test data. The test data consisted of variable length messages varying f
rom 1
timeslot to 32 timeslots (two full power line cycles) in length. The test was co
nducted for
a period of five minutes. The success probability was then calculated as the num
ber of
successful transmissions divided by the number of attempts. Recall that a succes
sful
message transaction consists of the message plus the corresponding ACK. This mea
ns
that a message of length 1 timeslot will actually require 2 timeslots to send.
Figure 5.7 shows the results of the success probability vs. message length test.
As
expected, shorter packets have a higher probability of success. The important th
ing to
note from this figure is how quickly probability of success decreases with messa
ge length
when the master and slave do not adapt to power line noise. This is because as t
he
messages become longer, there is a greater chance that they will transmit throug
h at least
one of the high noise times caused by the power-supply rectifiers. However, when
the
master and slave adapt to power line noise, the rectifier noise is avoided and t
he
probability of success vs. message length remains high.
72
Success Probability
1.0
Adapting
0.9
0.8
0.7
0.6
0.5
0.4
Non-Adapting
0.3
0.2
0.1
0.0
0 5 1015 20 2530
Message Length (timeslots)

Figure 5.7 Success Probability vs. Message Length.

The next performance measure is timeslot throughput vs. message length. In this
test, the
master and slave performed their initialization procedure to establish their tim
eslot tables,
and fixed length data messages were transmitted. The number of successful
transmissions for each message length was counted, and the throughput was calcul
ated
using the amount of time that each message length was sent (range 1 to 32).
Throughput in this sense refers to the capacity of the channel being used. It is
expressed
on a scale of 0 to 1. It takes into account ACK packets, but does not include ov
erhead
within packets (it is not the actual data throughput). For example, a message of
length 1
actually requires 2 timeslots (1 for data and 1 for ACK) the peak throughput for
message
length 1 is 0.5. Hence as messages become longer, throughput has the potential t
o
become higher, but transmission errors can cause it to become lower.
Figure 5.8 shows the throughput vs. message length for message lengths 1 through
32.
Curves for non-adapting, adapting, ideal adapting, and an ideal channel are show
n. In
this particular case, adapting to the noise means avoiding 2 timeslots meaning t
here is
73
only 14/16 or 87.5% of the channel available. This actually caused throughput to
be
slightly lower for adapting than for not adapting for short message lengths (<3)
.
However, once message length increases, adapting to the power line noise shows a
considerable performance increase over not adapting. The gap between the ideal c
hannel
curve and the ideal adapting curve is due to not using all timeslots. The gap be
tween the
ideal adapting curve and the actual adapting curve is due to the errors caused b
y the good
timeslots. Again, as mentioned earlier, if signal amplitude increased the good t
imeslots
showed almost no errors resulting in the actual adapting curve nearly matching t
he ideal
adapting curve.
It is also interesting to note the peak throughputs on the adapting and non-adap
ting
curves. While adapting, the peak throughput is approximately 0.8, while for non-
adapting it is just under 0.7. While adapting, the peak throughput is obtained a
nd
maintains relatively constant over a significant range of message lengths. When
no
adapting is performed, the peak throughput is reached at a message length of
approximately 5 but falls steadily with increasing message length. Therefore ada
pting
creates a distinct advantage in that not only does it provide higher throughput,
but also
allows a variety of message lengths to receive high throughput rates.
74
Ideal channel
(all timeslots)
1.0
0.9
Ideal Adapting
0.8
Actual Adapting
0.7
0.6
0.5
0.4
0.3
No Adapting
(all timeslots)
0.2
0.1
0.0
Throughput
0 5 1015202530
Message Length (timeslots)

Figure 5.8 Throughput vs. Message Length.

5.4 Testing in Various Environments
The testing in the previous section provided results in an office power line tra
nsmission
environment with two bad timeslots caused by power supply rectifiers. Further te
sting
was done to study other variables such as distance between nodes, transmitter am
plitude,
threshold for determining a timeslot bad, and performance with more than two bad
timeslots.
5.4.1 Creating different environments
Three new scenarios were created in order to more fully test the performance of
the timed
power line protocol. This section describes each scenario, demonstrates the adap
ting
ability of the protocol, and shows performance results in each scenario.
75
Scenario 1: A Power Macintosh connected as a noise producing load
The first new scenario had both the master and slave connected to the power line
on desk
1 along with a Power Macintosh 8500/120 computer as a noise producing load on th
e
mains supply. Figure 5.9 shows an oscilloscope trace with the computer connected
to the
line. The traces are: 60 Hz mains signal, data errors, GOOD/BAD timeslot indicat
or,
and the received signal and noise. Table 5.2 shows the timeslot error percentage
. Here
the effects of the switch-off of the power supply rectifiers is obvious, but als
o note the
effects of the switch-on point on the positive half cycle of the mains voltage.
The reason
that only the switch-on point in the positive half cycle was noticed is uncertai
n, but
possibly because rectifier positive half cycle created a larger noise spike or c
aused noise
at a frequency that interfered with the modulated signal. The protocol detects t
hese three
bad timeslots, which is seen in the GOOD/BAD trace.

Figure 5.9 Oscilloscope trace with Macintosh computer as a noise producing load.

76
Table 5.2 Timeslot errors with Macintosh computer as a noise producing load.
Total number of cycles 36901
Timeslot # Errors Error %
0 200 0.54%
1 108 0.29%
2 211 0.57%
3 245 0.66%
4 66 0.18%
5 3497 9.48%
6 93 0.25%
7 116 0.31%
8 229 0.62%
9 139 0.38%
10 3326 9.01%
11 350 0.95%
12 56 0.15%
13 4946 13.40%
14 112 0.30%
15 166 0.45%
Throughput vs. message length was also tested in this environment. The timeslot
error
percentage with the rectifiers causing error rates around 10 % for the bad times
lots is
lower than that seen in earlier tests, so the threshold for determining a timesl
ot bad was
adjusted to 5 %. Peak throughput is actually higher when not adapting than when
adapting, because now only 13 out of the 16 timeslots are used and the error rat
es of the
bad timeslots are not as high as in earlier tests (~ 20 % tested earlier). Rathe
r, peak
throughput is about the same for each case, but adapting to noise has a throughp
ut
advantage for message lengths longer than 5 or 6. Adapting presents the advantag
e once
again of a steady peak throughput with increasing message length, while non-adap
ting
throughput decreases dramatically with longer message lengths. The results of th
is test
are shown in Figure 5.10.
77
1.0
Ideal channel
(all timeslots)
0.9
0.8
Adapting
0.7
0.6
No Adapting
(all timeslots)
0.5
0.4
0.3
0.2
0.1
0.0
0 5 101520 2530
Message Length (timeslots)

Throughput
Figure 5.10 Throughput vs. Message Length with Macintosh computer as a noise
producing load.
Scenario 2: Lamp dimmer connected as a noise producing load
In this test the master was on desk 1 and slave on desk 2 and a new scenario was
created
connecting a lamp dimmer. The distance between the Master and Slave was
approximately 10 meters, which included a 3 meter extension cord used to connect
the
slave on desk 2. The lamp dimmer was of the type typically found in homes. With
no
load connected to the lamp dimmer, it creates no switching noise, so a desk lamp
with a
60 W bulb was connected as a load. Figure 5.11 shows the results of connecting t
he lamp
dimmer to the line. In this figure, the lamp dimmer was set on high. The noise s
pikes
caused by the lamp dimmer are noticeable, as seen in the lower trace. The middle
trace
shows the protocol adapting to the noise spikes, labeling the noise spike time a
s a BAD
timeslot. To demonstrate the continuous adapting ability of the protocol, the la
mp
dimmer was adjusted from the high (bright) position shown in Figure 5.11 to the
low
78
(dim) position shown in Figure 5.12. Adapting to the noise spikes and labeling t
imeslots
BAD took 10 seconds (the period of time between PINGs from master to slave).

Figure 5.11 Oscilloscope display with lamp dimmer in high position.

79
Figure 5.12 Oscilloscope display with lamp dimmer in low position.
With the lamp dimmer set on the low setting, timeslot error percentage is shown
in Table
5.3. Here there are four BAD timeslots: the two power-supply rectifier switch-of
f points
and two lamp dimmer switch-in times. In this case, the lamp dimmer spikes cause
a large
number of timeslot errors (almost 60 %), larger than the timeslot errors caused
by the
power-supply rectifiers (approx. 20 %).
Figure 5.13 shows the throughput vs. message length for the timeslot error perce
ntage
scenario in Table 5.3. Here the advantage of adapting is obvious. The gap betwee
n the
adapting curve and non-adapting curve is also large because there are four times
lots with
high error rates, resulting in a high probability of error in the non-adapting c
ase. Since
only 75 % (12/16) of the channel capacity is used in the adapting case, there is
a large
reduction when compared to the ideal case. When not adapting, peak throughput is
0.5
80
and is only attainable with a message length of 4. Even though only 12 of 16 tim
eslots
are used when adapting, throughput is much higher (almost 0.7) and is steady ove
r a wide
range of message lengths.
Table 5.3 Timeslot error percentage with lamp dimmer in low position.
Total number of cycles 29891
Timeslot # Errors Error %
0 17868 59.78%
1 85 0.28%
2 66 0.22%
3 173 0.58%
4 173 0.58%
5 6172 20.65%
6 46 0.15%
7 69 0.23%
8 17466 58.43%
9 84 0.28%
10 117 0.39%
11 107 0.36%
12 41 0.14%
13 7358 24.62%
14 50 0.17%
15 101 0.34%
Throughput
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0

Ideal channel
(all timeslots)
Adapting
No Adapting
(all timeslots)
0 5 101520 2530
Message Length (timeslots)
Figure 5.13 Throughput vs. Message Length with lamp dimmer in low position.
81
Scenario 3: Generally noisy channel
This scenario has master and slave both connected to the power line on desk 1 wi
th no
other loads. However, transmitting amplitude was set low (100 mV) so that there
was
more noise relative to the signal throughout the 60 Hz mains cycle. Table 5.4 sh
ows the
timeslot error % in this scenario. As before, the power-supply rectifiers caused
the most
errors but all other timeslots have a significant number of errors (1-3%), altho
ugh not
enough to be considered bad (5% threshold chosen). The results of the throughput
test
are shown in Figure 5.14. As before, adapting provided a more consistent through
put
with varying message length, although it dropped off more than it did in other c
ases
because of the errors caused by the used timeslots.
Table 5.4 Generally noisy channel timeslot error percentage.
Total number of cycles 52421
Timeslot # Errors Error %
0 709 1.4%
1 636 1.2%
2 606 1.2%
3 1054 2.0%
4 1664 3.2%
5 11824 22.6%
6 523 1.0%
7 663 1.3%
8 819 1.6%
9 1548 3.0%
10 1790 3.4%
11 1478 2.8%
12 1038 2.0%
13 12560 24.0%
14 635 1.2%
15 683 1.3%
82
Throughput
1.0
Ideal channel
0.9
(all timeslots)
0.8
0.7
0.6
Adapting
0.5
0.4
No Adapting
0.3
(all timeslots)
0.2
0.1
0.0
0 5 1015202530
Message Length (timeslots)

Figure 5.14 Throughput vs. Message Length for generally noisy channel.
5.5 Optimizing the GOOD/BAD Error Threshold
The cases presented above show the need to study an optimum threshold percentage
for
determining when a timeslot should not be used for transmission. To study this,
master
and slave were both placed on desk 1, and amplitude was adjusted to obtain speci
fic
timeslot error percentages. Results were then gathered for the throughput vs. me
ssage
length and efficiency vs. number of timeslots used programs. A theoretical analy
sis
follows.
In this setup, there were two bad timeslots, numbers 5 and 13. Throughput vs. me
ssage
length was tested for three different timeslot error percentages for these two t
imeslots;
each curve is shown in Figure 5.15. While adapting, the curve stayed the same fo
r each
case because timeslots 5 and 13 were always avoided and all other timeslots had
essentially no errors. In case 1 (error percentages 22-23%) adapting was obvious
ly
beneficial as throughput was higher than that for not adapting throughout the me
ssage
length range. In case 2 (error percentages 8-10%), adapting is still advantageou
s because
83
it provides a higher and more consistent throughput over the range of message le
ngths.
In case 3 (error percentages 3-4%) however, throughput is higher throughout the
message
length range when not adapting, hence adapting provides no advantage. From these
results it can be concluded that adapting is advantageous with two timeslots wit
h error
percentages > 10%, but also depends on the message length used.
Throughput
1.0 Ideal channel
0.8
0.9 4%
Adapting
0.6
0.7
9%
0.5
0.4
0.3 22%
0.2
0.1
0.0
0 5 10 15 20 25 30
Message Length (timeslots)
Two BAD timeslots
with error rate 4, 9
and 22 %
Figure 5.15 Throughput vs. Message Length to test adapting effectiveness.
The error percentages for the above tests were obtained by adjusting the amplitu
de of the
transmitter, which was difficult to do accurately. For this reason, a theoretica
l analysis
was conducted, which gives much more accurate results. The following theoretical
analysis chooses timeslot error threshold for optimizing throughput.
In the simplest theoretical case, consider a single bad timeslot and no errors i
n any other
timeslots. If the protocol avoids the timeslot, the throughput will be 15/16 or
93.75% of
the peak throughput. Hence when not adapting, the threshold for determining a ti
meslot
bad will occur when the throughput is 93.75% of the ideal throughput. The length
of the
packet has a direct effect as well, because shorter packets have less probabilit
y of hitting
bad timeslots. For a message of length 15 (occupies 16 timeslots because of the
ACK)
every timeslot will be used once in each message transmission. Assuming all time
slots
84
have no errors except the bad timeslot, the bad timeslot must have a 93.75% succ
ess rate
(or a 6.25% error rate) to give the same throughput as when avoiding the timeslo
t. Above
6.25% error rate, the timeslot can be labeled BAD and below 6.25% the timeslot c
an be
labeled GOOD. Figure 5.16 shows the threshold percentage vs. message length when
considering a single timeslot. Notice for short messages (< 5 timeslots in lengt
h) error
threshold becomes quite high, reaching 50 % for a message of length 1.
0%
10%
20%
30%
40%
50%
60%
Error Threshold to Classify BAD
0 5 1015 20 25 30
Message Length (timeslots)
Figure 5.16 Error Threshold to Classify BAD vs. Message Length for a single time
slot.
A similar argument can be followed when considering one timeslot already bad, an
d
adding a second bad timeslot. If one timeslot is already bad, adapting throughpu
t is
15/16 of the ideal channel throughput. When considering adapting to the second B
AD
timeslot, the throughput would be 14/16 or 87.5% of the peak. This means that th
e
threshold for considering the second timeslot bad is (14/16)/(15/16) or 14/15 =
93.3%.
For a message length 14 that occupies all used timeslots (15 timeslots in this c
ase) the
timeslot under consideration must have at least a 93.3% success rate or less tha
n 6.7%
error rate to be considered good.
85
As stated earlier the message length affects the optimum threshold error rate. T
he above
analysis assumes that each timeslot is used once in each message transmission. F
or a
message length 31 (occupies 32 timeslots, or 2 full power line cycles) every tim
eslot will
be used on average twice in every message transmission. That means that the succ
ess
rate for each message must still be 93.75 %, but the required success rate for t
he timeslot
is higher. If the success rate of the timeslot is SR, and for a message length o
f 31 the
timeslot is used on average twice, then SR*SR = .9375, or SR = .968 or 96.8 %.
Equation 5.1 is a general equation for the threshold for considering a timeslot
bad. If a
timeslot has error rate above this, it can be labeled BAD and with an error rate
below this
it can be labeled GOOD. Note that this formula assumes that a single timeslot is
causing
all of the errors, that is, all other timeslots being used have no errors.
numcurrentlygood
()
.
numcurrentlygood -1.
messagelength+1
optimum _ errorthreshold =
1-. .
..
..
(5.1)
.
numcurrentlygood .

For example, for a message length of 10 timeslots and all timeslots currently GO
OD, the
optimum threshold percentage is 1-(15/16)^(16/11) = .091 or 9.1 %. For a longer
message, say 20 timeslots, the optimum threshold percentage is 1-(15/16)^(16/21)
= .048
or 4.8 %. A length of 20 timeslots and only 10 currently GOOD results in 1(
9/10)^(10/21) = .467. This shows that the optimum error threshold is affected mu
ch
more by the message length than by the number of timeslots currently good. In es
sence,
for longer message lengths, the optimum error threshold is smaller.
When considering two timeslots at once with different error rates, the analysis
is similar.
For a desired success probability however, this will be the probability that bot
h timeslots
are good (assuming that they are independent events). Hence when considering the
first
two BAD timeslots, a 14/16 or 87.5% success rate or less than 12.5% failure rate
 must be
obtained for the combination of the timeslots to consider them both GOOD, hence
P(Both
GOOD) > .875 is the target, where P(Both GOOD) is the probability that both time
slots
are GOOD. P(Both GOOD) > 0.875, or P(first GOOD)*P(second GOOD) > 0.875. For
86
two timeslots with the same error rate, and using each timeslot once in every me
ssage
transmission, the success threshold for each is 93.5% (error threshold 6.5%) whi
ch is
close to the threshold when considering a single timeslot (6.25%).
If a pair of timeslots gives the desired success threshold of 93.5% but one time
slot has
higher error rate than the other (e.g. 7% and 5%) then it is better to label the
first timeslot
(7%) BAD and the second timeslot (5%) GOOD because the second timeslot is below
the
threshold for considering a second timeslot bad. Therefore formula 5.1 given abo
ve is
considered a reasonable error threshold approximation to consider a timeslot BAD
for a
given message length, one timeslot at a time from highest error rate to lowest.
5.6 Other Factors that Affect the Channel
The above analysis shows that the noise characteristics affect throughput and ef
ficiency
and how well the timed power line protocol performs. These characteristics vary
due to
the type, location and number of loads connected to the line as shown by the Mac
intosh
computer and lamp dimmer tests conducted above. Other factors which can affect
performance include time of day, distance between nodes and the transmitting amp
litude.
5.6.1 Time of Day
Change in channel characteristics due to time of day is caused by loads connecte
d to the
line. During the day there are more lights turned on, more computers turned on,
and
generally much more load on the power line than at night. This creates a noisier
channel
with higher attenuation than at night.
To test the effect of time of day, the master was connected to the power line at
desk 1 and
the slave at desk 2 with a 3 meter extension cord. One way transmission (from ma
ster to
slave) was carried out with the master simply broadcasting check packets to the
slave,
and the slave reporting the running average timeslot error percentage every 10 s
econds.
The nighttime test was conducted first. The amplitude of the master s transmitter
was set
purposely to cause a small number of errors in all timeslots except where the po
wer

87
supply rectifiers conduct (where there were a large number of errors). 10 five-m
inute
tests were conducted at different times in the evening ranging from 7 p.m. to 2
a.m. For
the daytime test, the master s transmitter was set to the same amplitude as was us
ed for
the nighttime test. This was essential in measuring the daytime performance rela
tive to
the nighttime performance. Again, 10 five-minute tests were conducted at differe
nt times
of day ranging from 10 a.m. to 4 p.m. Table 5.5 shows the timeslot error percent
age
average for night and day testing. In this case, the timeslot errors at the rect
ifier switch-
off points remained about the same. This may be because power supplies connected
to
this line are not turned off at night. Another explanation is that the maximum n
umber of
errors that can be caused in those timeslots already occurs at night because the
zener
diodes in the wall coupler are clipping the noise spikes, meaning that a further
increase in
amplitude of the noise spike has little or no effect. All other timeslots, howev
er, behaved
as expected and the error percentage was significantly higher during the day tha
n at night.
Table 5.5 Average timeslot error percentages for night and day tests.
Timeslot Day
Error %
Night
Error %
0 1.4% 0.4%
1 1.2% 0.4%
2 1.2% 0.4%
3 2.0% 0.8%
4 3.2% 0.8%
5 22.6% 22.0%
6 1.0% 0.2%
7 1.3% 0.2%
8 1.6% 0.3%
9 3.0% 0.9%
10 3.4% 0.7%
11 2.8% 0.6%
12 2.0% 0.2%
13 24.0% 23.3%
14 1.2% 0.4%
15 1.3% 0.2%
88
5.6.2 Distance between nodes
This test was conducted with both the master and slave on desk 1. Since the vari
able
under study was the distance between nodes, the transmitting amplitude remained
constant. Distance between the nodes was varied by using extension cords. Three
extension cords of length 3 meters were used, along with two cords of length 30
meters.
The first measurement was conducted with the master and slave connected to the s
ame
bank of outlets on desk 1. The actual distance through the power line was about
30
centimeters. Again the master sent check packets in each timeslot, and the slave
checked
the quality of the received data and reported it on the computer screen every 10
seconds.
Timeslot error percent for this distance was averaged over a period of approxima
tely five
minutes, then a length of extension cable was added and the test repeated. It sh
ould be
noted that extension cable is not the same cable as power conductors installed i
n homes
and offices, but is a reasonable approximation for this test. Also, this was the
only way to
know the actual wiring distance between nodes because power conductor length in
walls
is not predictable without opening the wall. The test setup is shown in Figure 5
.17.
To Breaker
Panel
Desk # 1
Master
30 cm
Computer
loads, etc.
Slave
Extension cords
(various length)
Figure 5.17 Station separation test setup
Table 5.6 shows the result of the distance test for each timeslot. As expected,
increasing
distance between nodes caused more errors because of attenuation in the cables.
Note
that timeslots 5 and 13 showed approximately a threefold increase in errors when

89
distance was changed from 3 to 6 meters. It is assumed that, at this point, the
noise from
the power supply switch-off points began to dominate over the data signal level.
It is
important to note that the highest error timeslots remained the highest for each
length of
cable, supporting the argument that these timeslots have a higher error ratio re
lative to
the other timeslots.
Figure 5.18 shows the average timeslot error rate (averaged over all timeslots)
vs. length.
Note the sharp rise at short distance is due to timeslots 5 and 13 discussed abo
ve. At long
distances, an exponential increase in errors occurs because loss over the length
of the
extension cord causes the signal to begin disappearing. At the longest length (6
9), the
error rate isquite high in all timeslots. This is due not only to the length bet
ween the
nodes, but the small signal amplitude used in order to study length effects. To
see if
communication was even possible at 69 meters, the signal amplitude was increased
and
the timeslot error percent became similar to that when the nodes are close toget
her with
small signal amplitude.
Table 5.6 Timeslot Error Ratio vs. Station Separation.
Station Separation (meters)
On Desk 3 6 9 30 39 60 69
Timeslot #
0 0.0% 0.0% 0.1% 0.2% 1.8% 5.3% 18.8% 32.7%
1 0.0% 0.0% 0.0% 0.3% 1.4% 3.9% 15.7% 25.7%
2 0.0% 0.0% 0.0% 0.3% 2.1% 5.4% 18.9% 29.7%
3 0.0% 0.0% 0.0% 0.3% 2.4% 6.2% 21.7% 37.1%
4 0.0% 0.0% 0.0% 0.5% 2.3% 7.0% 23.3% 33.6%
5 15.8% 16.2% 48.6% 53.4% 60.1% 66.3% 79.7% 85.8%
6 0.0% 0.0% 0.1% 0.2% 2.6% 4.7% 18.5% 27.4%
7 0.0% 0.0% 0.0% 0.2% 1.4% 3.5% 13.7% 24.0%
8 0.0% 0.0% 0.0% 0.6% 4.9% 10.7% 24.3% 35.5%
9 0.0% 0.0% 0.0% 0.3% 2.7% 5.3% 17.8% 33.5%
10 0.0% 0.0% 0.0% 0.2% 1.1% 2.8% 10.8% 19.1%
11 0.0% 0.0% 0.0% 0.2% 0.4% 1.4% 8.2% 20.7%
12 0.0% 0.0% 0.0% 0.1% 0.2% 0.7% 4.9% 13.6%
13 19.2% 20.0% 61.7% 62.7% 68.9% 73.4% 81.8% 86.9%
14 0.0% 0.0% 0.0% 0.2% 1.3% 3.6% 14.5% 24.2%
15 0.0% 0.0% 0.0% 0.2% 1.1% 3.5% 14.8% 24.5%
90
Average Timeslot Error Ratio
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0 10 20 30 40 50 60 70
Station Separation (meters)

BAD
timeslots
GOOD
timeslots
Figure 5.18 Average Slot Error Ratio vs. Station Separation.
5.6.3 Effects of Signal Amplitude
The results of the station separation test showed the importance of transmitting
signal
amplitude. For the signal amplitude test, the master was placed on desk 1 and sl
ave on
desk 2 (separation approx. 3 meters) with a 3 meter extension cord. To cause a h
igh
number of errors, the lamp dimmer was also used and adjusted so that its noise s
pike
occurred at the same time as the rectifier switch-off point. Signal amplitude wa
s set low
to start (100 mV), and then increased while monitoring timeslot error percentage
. Again,
the master sent check packets to the slave which monitored timeslot quality and
reported
it every 10 seconds. Timeslot error percentage was averaged over a period of
approximately 5 minutes for each signal amplitude.
Table 5.7 and Figure 5.19 show the results of the amplitude test. Timeslot error
percentage is quite high in two timeslots at low amplitude and, as expected, it
decreases
as amplitude increases. The signal amplitude as shown on the graph is relative t
o the
starting amplitude (the lowest amplitude measurement). Of particular interest wa
s to see
if the amplitude could become large enough to overcome the errors. In this parti
cular
setup, it could not; the amplitude increased to a point where it began to overwh
elm the
91
receiver (amplitude exceeded the allowed range by the demodulator), and increasi
ng the
amplitude further caused more errors.
Table 5.7 Timeslot Error Ratio vs. Amplitude.
Signal Amplitude Relative to Starting Amplitude of 100 mV
1 1.5 2 2.5 3 3.5 4 4.5
Timeslot
0 0.1% 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.2%
1 0.0% 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.8%
2 0.1% 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 1.5%
3 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.4% 9.5%
4 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.1% 2.8%
5 54.4% 19.9% 12.2% 7.4% 5.2% 4.7% 5.3% 27.5%
6 0.0% 0.1% 0.0% 0.0% 0.0% 0.0% 0.7% 12.3%
7 0.1% 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.7%
8 0.2% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.3%
9 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.5%
10 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 1.2% 18.8%
11 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 1.2%
12 0.1% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0%
13 61.0% 34.2% 24.3% 14.4% 8.9% 7.5% 7.8% 40.8%
14 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.2% 5.5%
15 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0%
Average Timeslot Error Ratio
9.0%
8.0%
7.0%
6.0%
5.0%
4.0%
3.0%
2.0%
1.0%
0.0%
Receiver
Overload
1 1.5 2 2.5 3 3.5 4 4.5
Signal Amplitude (relative to starting amplitude of 100 mV)
Figure 5.19 Average Timeslot Error Ratio vs. Signal Amplitude.
92
5.7 Protocol Drawbacks
5.7.1 Multi-phase Network
One drawback to the designed protocol is that the design has considered transmis
sion on
only a single phase. In an office environment with three phase supply, this mean
s that
approximately two thirds of power outlets would be unavailable for transmission.
Also,
since not all phases are present in one room, access to the network would be lim
ited. A
solution to this problem would be to form a separate network for each phase and
connect
them through a network bridge. A network bridge bridges data across two or more
networks (in this case the three phases). A bridge does not forward all data tha
t it
receives; rather it has built in logic that makes forwarding decisions based on
the
destination of the data. In Figure 5.20 if computer A wants to talk to computer
C, and the
network bridge recognizes that they are on different networks, it forwards the d
ata on
computer C s network. If computer B wants to talk to computer D, the bridge does n
o
forwarding of data because B and D are on the same phase or network. This approa
ch
reduces the amount of data flooding the network.
The multi-phase issue may also cause problems for the master/slave design chosen
. With
a single master coordinating all three slaves with a single timeslot table, ther
e would be a
large portion of the power line cycle labeled BAD because the power-supply recti
fier
switch-off points on one phase occur at different points relative to the other p
hases. If,
for example, each phase has two bad timeslots due to power-supply rectifiers the
n the
three-phase network will have six bad timeslots. One possible solution to this i
s to have
the master and the network bridge work together to know when to forward packets.
A
master table is still constructed for the entire network (all three phases) and
forwarded on
to all slaves, but it takes into account the phase shift of each phase. For exam
ple, if
timeslots 5 and 13 are bad in each phase due to power-supply rectifiers, then th
e master
constructs a timeslot table with 5 and 13 labeled BAD even though timeslots 5 an
d 13
occur at different times for each phase relative to the other two phases. If dat
a needs
93
forwarded from phase 1 to phase 2 and is received by the bridge in timeslot 4, t
hen it will
forward the data to phase 2 in its timeslot 4 (which occurs at a different time
than phase
1 s timeslot 4).
Network
Bridge and
Master
A
C
D
B
Figure 5.20 Three phase power line network.
5.7.2 Centralized vs. Distributed Architecture
This design has used a centralized architecture (master/slave setup). This has p
rovided
certain advantages such as timeslot table coordination, coordination of slave tr
ansmission
(eliminates the need for carrier sensing and collision detection), and a general
sense of
organization. However using this centralized architecture has certain drawbacks.

The main drawback is the master timeslot table. Each timeslot in the master tabl
e is the
union of GOOD timeslots of all slaves. If at least one slave labeled a timeslot
BAD, then
it is labeled BAD in the master table and broadcast to all slaves. If two slaves
who are
spatially close to each other have good transmission success in all timeslots, t
hey are still
limited to those timeslots labeled GOOD and BAD in the master table. One solutio
n to
this is to have each node keep track of a timeslot table for every other node. W
hen one
94
node wants to talk to another, it negotiates a timeslot table at that time and c
arries out
communication. This approach has the advantage that two nodes can communicate wi
th
each other with a timeslot table that is optimized between the two of them, and
not
affected by other nodes timeslot tables. This is a distributed architecture now,
where all
nodes have equal access to the channel. Disadvantages to this approach are each
node
must contain enough memory to store a timeslot table for every other node in the
system,
and now methods such as carrier sensing and collision detection/avoidance must b
e
employed to avoid collisions and ensure equal channel access because now every n
ode
makes its own decisions on when to transmit.
A further improvement is to have a blend of the two architectures where there ex
ists a
master but its only purpose is to coordinate who is allowed to talk and when. Ti
meslot
tables are left up to each slave to negotiate with other slaves and there is no
master table.
Now there would be no need for methods such as carrier sensing and collision
detection/avoidance, and each node pair can negotiate independent timeslot table
s which
optimizes communication.
5.7.3 Excess Overhead
One major problem with this protocol is the amount of overhead required for succ
essful
detection of BAD timeslots, communicating this information, and allocating chann
el
access. There are two basic categories of overhead in this design, packet overhe
ad and
control overhead.
Packet overhead is the overhead included in each packet. As shown in Chapter 3,
each
timeslot contains a complete packet including header and checksum. This is neces
sary in
order to be able to successfully detect where errors are occurring and to flag B
AD
timeslots. At low bit rates this becomes more of an issue because the number of
overhead bits remains the same but the number of data bits must decrease in orde
r for the
packet to fit in the one millisecond timeslot. For the purposes of this work, 60
kb/s was
used, and less than half of the bits sent were actual data. If higher bit rates
are used, the
overhead to data ratio is much lower.
95
Control overhead refers to the time dedicated to communicating timeslot table
information and controlling channel access. Every 10 seconds, the master perform
s a
polling cycle, in which each slave is polled for information for one power line
cycle and
each responds for one cycle. If all 16 slaves are present in the system, this ov
erhead
amounts to 32 cycles. One power line cycle is 16.67 ms so this causes a pause of
approximately 0.5 seconds. If each slave requests channel access in their respon
se (all
slaves have data to send, this is the worst case) then the master needs one powe
r line
cycle for each slave requesting channel access. This is a total of another 16 po
wer line
cycles over the 10 seconds. In 10 seconds there are 600 power line cycles. The t
otal
overhead in the worst case is 48 power line cycles, resulting in 48/600 or 8 % o
verhead
for timeslot table coordination and controlling channel access.
96
6. Conclusion
6.1 Summary
This thesis has reviewed published work on power line electrical characteristics
and has
proposed a method of avoiding synchronous noise present on the power line.
Hanson s research [1] showed that synchronous noise on the power line causes a hig
h
number of bit errors. This result was confirmed in this thesis with the half-dup
lex
modems and programs that tested byte and timeslot errors. As expected, a high er
ror
ratio was discovered at the same location of the synchronous noise. In the tests
conducted, the noise spikes from power supply rectifier switch-off caused the mo
st
errors. In other environments, however, it may be found that other noise spikes
can cause
additional errors, such as those caused by fluorescent lights (near the zero cro
ssings of
the 60 Hz mains signal).
A protocol was designed by combining new ideas with ideas from previously design
ed
protocols. The protocol was designed as a centralized architecture with a single
master
and up to 16 slaves. The protocol divides the 60 Hz mains signal into 16 timeslo
ts
(approx. one millisecond each). Each node in the system monitors received data f
or
errors in each timeslot and labels timeslots with too many errors as BAD. The ma
ster
controls traffic on the power line by polling slaves to see if they have data to
send or have
any information on BAD timeslots. By doing this, the master makes a union of all
GOOD timeslots in the system (assembles a timeslot table) and broadcasts this
information to all slaves. Once all of the slaves have the timeslot table, the m
aster
designates the channel to a particular slave that needs to send data for a numbe
r of 60 Hz
cycles fitting the amount of data that slave has to send. The slave will only co
mmunicate
data in GOOD timeslots, and the master will send a check pattern in BAD timeslot
s so
97
their quality can be monitored. Once this number of cycles has expired, the mast
er will
designate the channel to another slave and so on. Every 10 seconds, the master p
olls each
slave again to see if they have data to send or have any new timeslot table info
rmation
and then the process repeats. This process of polling and continuous checking of
timeslots allows the protocol to adapt to power line noise, detecting when new n
oise
sources appear or disappear.
6.2 Conclusions
This method of adapting to synchronous noise worked well. Performance was tested
with
and without adapting to noise. More specifically, packet throughput and probabil
ity of
transmission success were tested. These two factors were measured for various me
ssage
lengths (where a message length refers to the number of timeslots occupied by a
message) and for several environments.
Based on the research performed in this thesis, it is found to be advantageous t
o avoid
synchronous noise on the power line. This results in data transmission at times
of low
probability of error and increased performance. It was concluded that throughput
and
probability of success could be significantly improved by adapting to power line
noise.
The error threshold for determining that a timeslot is BAD was also investigated
. It was
found that the best threshold error ratio for determining a timeslot BAD was
approximately 6 % (a bad CRC 6 % of the time). This threshold, however, varies
depending on the number of timeslots that are already labeled BAD, and on the me
ssage
length under consideration. If there are already a few timeslots labeled BAD, th
e optimal
threshold error ratio is slightly higher. Also, for shorter message lengths, the
optimal
threshold error ratio is higher. These two variables were then used in determini
ng an
equation for calculating the error threshold for determining a timeslot BAD.
Improvements in throughput and reliability were also discovered. Throughput vari
es
depending on the number of BAD timeslots, but for a typical case of two BAD time
slots
the throughput obtained when adapting to noise was over 80 % of the peak through
put as
98
compared to approximately 60 % of the peak throughput when not adapting to noise
.
Also, when not adapting to noise, maximum throughput peaks at low message length
and
drops off rapidly for higher message lengths. When adapting however, throughput
is
much more constant with varying message length. By choosing appropriate modulati
on,
it is thought that throughputs of 100 to 500 kb/s may be possible.
The major contribution of this work is the design of a protocol to take advantag
e of the
fact that noise is synchronous with the 60 Hz power line cycle. Tests have shown
that the
protocol was able to adjust the timing of data transmission to avoid the synchro
nous
noise. Tests also showed that the protocol is robust in that it adjusts to chang
es in the
noise characteristics. The protocol, along with relatively simple hardware allow
s for a
low cost solution to medium speed power line networking.
6.3 Future Work
The results of this work have shown that data communication performance can be
increased by avoiding synchronous noise. Of significant importance is the error
ratio in
times of high noise relative to that in times of low noise. Future work suggesti
ons are
provided below to further take advantage of this fact. In some of these future w
ork
suggestions, it may not be necessary to construct hardware and test on the power
line
where simulations may suffice. Other tests require hardware and actual power lin
e
testing.
6.3.1 Modulation
The half-duplex modems designed for this research used FSK modulation. FSK,
although simple to implement, is spectrally inefficient. In the same bandwidth t
argeted in
this research (105 kHz 490 kHz) a much more spectrally efficient modulation sche
me
should be explored. If synchronous noise is avoided, some M-ary form of modulati
on
such as QAM that has multiple bits per symbol seems possible in this transmissio
n
environment. A transmit/receive pair should be designed that can select between
different levels of QAM, such as 4-QAM (QPSK) which has 2 bits per symbol to 16Q
AM
which has 4 bits per symbol. For initial tests, simplex (one-way) communication
99
can be performed to test error rates with different modulation schemes. Data
transmission performance should be measured in typical environments within an of
fice
building and within a home. Once a particular modulation scheme is considered
appropriate, half-duplex or even full-duplex modems should be designed to test p
rotocol
performance and throughput rates under the new modulation scheme. This will incr
ease
the number of bits per timeslot and reduce the overhead-to-data ratio. For examp
le, with
FSK a symbol rate of 50 kb/s means that 50 bits can be fit into a one millisecon
d
timeslot, however 32 bits are used for overhead (header and error checking). Hen
ce
32/50 or over 64 % of the bits are overhead (not considering UART start/stop bit
s), and
18/50 or 36 % of the bits are data. If QPSK is used (4 bits per symbol) at 50
ksymbols/sec, 200 bits could be fit into a one millisecond timeslot for a rate o
f 200 kb/s.
Now only 32/200 bits or 16 % of the bits are overhead, and 168 bits of data are
possible
a significant improvement. With two BAD timeslots, the effective bit rate would
be 200
kb/s * (14/16) = 175 kb/s. Note that this is the bit rate and not throughput (wh
ich would
consider overhead).
6.3.2 Selectable Bits Per Symbol
Discrete multi-tone systems (DMT) [31] are currently being developed for power l
ine
communications. DMT is similar to OFDM that is used in the HomePlug specificatio
n,
but instead of rejecting bad frequency bands, it still uses them and applies a l
ower
number of bits per symbol to them. High SNR frequency bands are assigned a high
number of bits per symbol. The HomePlug specification is exploring this method a
nd
claims that rates exceeding 100 Mbits/sec can be attained.
The idea of DMT is interesting to this work because what DMT is doing in the fre
quency
domain could also be done in the time domain. Instead of selecting a number of b
its per
symbol for a frequency channel, bits per symbol can be selected based on the SNR
(or
error ratio) in each timeslot. Low noise timeslots could be assigned a high numb
er of bits
per symbol while high noise timeslots such as the power-supply rectifier switch-
off
points may be assigned a small number of bits per symbol or completely avoided.
100
6.3.3 Length of Timeslots
The length of timeslots may be another area for improvement in this protocol. Th
e FSK
demodulator contains a phase locked loop (PLL) which loses lock when a noise spi
ke
occurs hence causing bit errors for some time after the spike because of the tim
e the PLL
takes to regain lock. If this factor is eliminated, one may find that noise spik
es cause
errors for much shorter times than measured in this work.
Timeslots of one millisecond were chosen for this research because they are long
enough
to carry sufficient data for adapting and control, yet short enough to provide s
ome
definition in selecting bad timeslots. If it is found that the time of interferi
ng noise is
much shorter than one millisecond, the period of time that needs to be avoided i
s also
shorter. By avoiding this shorter time, the amount of time the channel can be us
ed is
larger. However, as timeslots become shorter, the fraction of the timeslot used
for
overhead becomes larger. This needs to be explored in order to obtain a balance.

6.3.4 Amplitude Adapting

As shown earlier in this chapter, transmitting amplitude greatly affects the tim
eslot error
rate. However, turning the amplitude too high resulted in the transmit signal
overwhelming the receiver and timeslot error rate began to increase. Some method
of
determining an appropriate transmit amplitude must be explored. One possibility
is to
have each slave start up with some default transmit amplitude and have the maste
r listen
to transmissions from each slave. If the master finds that it cannot hear a part
icular slave
very well or if other slaves have problems hearing that slave, the master may se
nd a
message to that slave indicating that it should increase its transmitting amplit
ude.
However, if a node is far away from some other nodes in the system and it has to
transmit
at high amplitude to be heard properly, those nodes that are close to it may be
overwhelmed by this transmit signal. To solve this problem, automatic gain contr
ol
(AGC) could be used which changes the receiver filter gain depending on the ampl
itude
of the received signal (for high amplitude, filter gain decreases).
101
The idea of amplitude adapting may not be feasible or more difficult than its wo
rth for
the gain in performance it may provide, but is provided here as another possible
improvement to the timed power line communication protocol.
6.3.5 Breaker Panel Connection
In Chapter 3, the problem of transmitting through a breaker panel was mentioned.
The
problem is that the breaker panel represents high attenuation and slaves connect
ed on
different legs that branch off the breaker panel will not be able to transmit to
each other.
One solution is to have a multi-legged master that runs a distinct copy of the pro
tocol
on each leg where there are slaves. The slaves on each leg communicate with slav
es on
other legs by bridging through the master, while the slaves on one leg communica
te with
each other without bridging through the master. The master must have a table tha
t keeps
track of which slaves are on which leg. The timeslot tables are independent betw
een legs
of the system, and to communicate between legs, the master will re-route a packet
in
one timeslot to another timeslot on the other leg if necessary (if a timeslot is
GOOD on
one leg but BAD on another). The master will need to have some number of buffers
to
perform this bridging operation. If the master s buffers are filling up, it will s
top sending
CTS s on the leg that is filling up buffers. In essence, the master takes over res
ponsibility
for getting data from a slave on one leg to a slave on another leg.
6.3.6 Using Consecutive Timeslots
If a sender finds that it is using consecutive timeslots, the ability to make lo
nger packets
that stretch over those timeslots should be explored. For example, if a sender i
s using
timeslots 5 and 6 and making complete packets for each of these timeslots, it co
uld make
a single packet that is 2 timeslots long that begins in timeslot 5 and ends in t
imeslot 6.
There will be only one header and one checksum for the packet resulting in less
overhead
per packet hence increasing the amount of data that can be sent. This concept is
shown in
Figure 6.1. To do this, the packet must have some indication that it is part of
a longer
packet, perhaps by a length field or a beginning, middle, and end of packet indi
cation.
102
Header Data Checksum Header Data Checksum
Timeslot 5 Timeslot 6
Checksum
Timeslot 5 Timeslot 6
Next Group

Header Data Checksum

Timeslot 5 Timeslot 6
Figure 6.1 Concatenating timeslots.
One problem with this improvement is that if there is an error detected for the
concatenated packet, it must be thrown away without knowledge of which timeslot
the
error occurred in. If there are a lot of errors occurring with concatenated pack
ets, they
sender may decide to reduce the packet size, and concatenate fewer timeslots. On
ly when
there are no concatenated timeslots (each packet is only 1 timeslot long) can a
node
determine if there is one timeslot that is becoming bad. This process of breakin
g down a
longer, concatenated packet into smaller packets and eventually zooming in on a
single
timeslot is the only way that a node can determine if a timeslot has become bad
or not.
Once it has narrowed down the timeslot that is bad and begins avoiding it, it ma
y again
begin concatenating timeslots to make longer, more efficient packets.
6.3.7 Other Protocol Considerations
Several variables in the protocol may be explored such as the optimum message le
ngth,
the period of time between PINGs (master to slave request for information), and
error
correction.
This thesis did not select a specific message length; rather it explored the pro
tocol
performance over a range of message lengths. The message length chosen for data
103
communication may depend on the application. If only a small amount of data need
s to
be sent and it needs to be sent with low latency (highest probability of success
) then small
messages may be chosen. If high throughput is a goal then longer messages may be
chosen. In this thesis, the longest message tested was 32 timeslots (two power l
ine
cycles). The length of messages should be up to the sending node, and can change
depending on the type of data sent. Recall that the message length also has an e
ffect on
the threshold for considering a timeslot bad.
The period of time between PINGs was selected to be 10 seconds for this work, bu
t this is
another variable that was selected that may be optimized. 10 seconds was chosen
because it is short enough to effectively communicate changes in the power line
noise
characteristic and answer demand from slaves to send data, yet it is long enough
for
nodes to check enough data to construct a correct timeslot table. If there are m
any active
nodes in the system and their demand for the channel changes quickly, then a sho
rter
PING period may be more suitable. However, if there are few active nodes sending
little
data then a longer PING period may be more suitable. Perhaps the PING period cou
ld be
a variable that is tuned by the master depending on the channel activity. This i
s a small
detail compared to other issues in the power line protocol, but is provided as t
hought for
further improvement.
104
References
[1] Jack Hanson, M.Sc. thesis, University of Saskatchewan Timed Power Line Data
Transmission , December 1997.
[2] Niovi Pavlidou, A. J. Han Vinck, Javad Yazdani and Bahram Honary, Power Line
Communications: State of the Art and Future Trends , IEEE Communications Magazine,
Vol.41 No. 4 pp. 34-39, April 2003.
[3] Lars Selander, Power-Line Communications: Channel Properties and
Communication Strategies , M. Sc. , Lund University, 1999.
[4] L.H. Charles Lee, Error-Control Block Codes for Communications Engineers.
Norwood, MA: Arctech House, 2000.
[5] Glen Carty, Broadband Networking. Berkeley, CA: Osborne/McGraw-Hill,
2002.
[6] Transmission Theory for X10 Technology, http://www.x10.com/technology1.htm
[7] Introduction to the Londworks System, Version 1.0. Echelon Corporation, 1999
.
[8] Echelon Corporation, A Power Line Communication Tutorial Challenges and
Technologies.
[9] Echelon Corporation, PLT-22 Power Line Transceiver Data Sheet, 2001-2002.
[10] Electronic Industies Alliance, EIA-600.31 Physical Layer & Medium Specifica
tion,
February 1995.
[11] M. K. Lee, R. E. Newman, H. A. Latchman, S. Katar and L. Yonge, HomePlug 1.0
Powerline Communication LANs Protocol Description and Performance Results
version 5.4 , International Journal of Communication Systems, 2000; 00:1 6, [Version
:
2002/09/18 v1.01], John Wiley & Sons, Ltd. 2002.
[12] John Turnbull and Simon Garret, Broadband Applications and the Digital Home
.
London, UK: The Institution of Electrical Engineers, 2003
[13] M. K. Lee, R. E. Newman, H. A. Latchman, S. Katar and L. Yonge, Field
Performance Comparison of IEEE 802.11b and HomePlug 1.0 , Proceedings of the 27th
Annual IEEE Conference on Local Computer Networks. IEEE, 2002.
[14] J.R. Nicholson and J.A. Malack, "RF Impedance of Power Lines and Line
Impedance Stabilization Networks in Conducted Interferences Measurement",
105
IEEE Transactions On Electromagnetic Compatibility, Vol. EMC 15, No 2 pp.
84-86, May. 1973.
[15] Youlu Zheng, Shakil Akhtar, Networks for Computer Scientists and
Engineers. New York, NY: Oxford University Press, 2002.
[16] Dimitri Bertsekas, Robert Gallager, Data Networks, Second Edition. Englewoo
d
Cliffs, New Jersey: Prentice-Hall, 1992.
[17] Edgar H. Callaway Jr., Wireless Sensor Networks Architectures and Protocols
.
Boca Raton, Florida: Auerbach Publications, 2004.
[18] Jim Kurose, Keith Ross, Computer Networking: A Top-Down Approach Featuring
the Internet. Addison-Wesley Longman, 1999.
[19] Joseph L. Hammond, Peter J.P. O Reilly, Performance Analysis of Local Compute
r
Networks. Addison-Wesley Publishing Company, 1986.
[20] Andrew S. Tanenbaum, Computer Networks, Second Edition. Englewood Cliffs,
New Jersey: Prentice-Hall, 1989.
[21] B. G. Evans, Satellite Communication Systems, 3rd Edition. London, UK: The
Institution of Electrical Engineers, 1999.
[22] Gursharan S. Sidhu, Richard F. Andrews, Alan B. Oppenheimer, Inside AppleTa
lk,
Second Edition. Addison-Wesley Publishing Company, 1990.
[23] Mark Norris, Gigabit Ethernet Technology and Applications. Norwood MA:
Artech House, Inc., 2003.
[24] Federal Communications Commission, Part 15 Radio Frequency Devices, Sec.
15.113 Power Line Carrier Systems. 47CFR15.113, Title 47 Volume 1, October 2001.
[25] Industry Canada, Low Power Licence-Exempt Radiocommunication Devices (All
Frequency Bands). RSS-210, Issue 5, November 2001.
[26] Motorola, MC68360 Quad Integrated Communications Controller User s Manual.
[27] The Slackware Linux Project, http://www.slackware.com
[28] On-Line Applications Research, RTEMS user s manual,
http://www.rtems.com/onlinedocs/freesupport/manuals
[29] Hewlett Packard, HP 33120A Function Generator/Arbitrary Waveform Generator
User s Guide. August 1997.
106
[30] The Kermit Project, University of Columbia, http://www.columbia.com/kermit/
[31] Francisco Javier Canete, Jose Antonio Cortes, Luis Diez, and Jose Tomas
Entrambasaguas, Modeling and Evaluation of the Indoor Power Line Transmission
Medium , IEEE Communications Magazine, Vol. 41 No. 4 pp. 41-47, April 2003.
107
A. Hardware Pictures
Below are some pictures taken at the TRLabs technology forum. The forum was held
in
Saskatoon, SK on October 19 & 20, 2004.

Figure A.1 Complete Hardware Setup

In Figure A.1, the master is on the right, and slave on the left. They communica
te
through the power line by connecting to an extension cord that goes behind the t
able and
connects to the power line. The oscilloscope in the middle displays the signal a
nd noise
on the line. In the background is a poster describing the setup and theory.
108
Figure A.2 Close-up of hardware setup
Figure A.2 is a close-up picture of the slave hardware. As described earlier in
this
chapter it consists of a PC (the laptop), MC68360 (the box immediately to the ri
ght of the
laptop), a line coupler (small box furthest to the right) and all other electron
ics are inside
the box closest to the bottom with five plugs connected to it.
109
Figure A.3 Close-up view of project boxes
Figure A.3 shows the line coupler boxes (bottom), the line driver/filter/demodul
ator
boxes (top right) and a 60 Hz trigger box (left).
110
Figure A.4 Myself (left) and my supervisor, Prof. David Dodds (right).
111
B. Federal Communications Commission Part 15
The Federal Communications Commission part 15 is instrumental in determining
appropriate power line communication transmission bandwidth and is included here
as
reference.
[Code of Federal Regulations]
[Title 47, Volume 1]
[Revised as of October 1, 2001]
From the U.S. Government Printing Office via GPO Access
[CITE: 47CFR15.113]

[Page 691-692]

TITLE 47--TELECOMMUNICATION
CHAPTER I--FEDERAL COMMUNICATIONS COMMISSION
PART 15--RADIO FREQUENCY DEVICES--Table of Contents
Subpart B--Unintentional Radiators
Sec. 15.113 Power line carrier systems.
Power line carrier systems, as defined in Sec. 15.3(t), are subjectonly to the f
ollowing requirements:
(a) A power utility operating a power line carrier system shallsubmit the detail
s of all existing systems plus any proposed newsystemsor changes to existing sys
tems to an industry-operated entity as setforth in Sec. 90.63(g) of this chapter
. No notification to the FCC isrequired.
(b) The operating parameters of a power line carrier system(particularly the fre
quency) shall be selected to achieve the highestpractical degree of compatibilit
y with authorized or licensed users ofthe radio spectrum. The signals from this
operation shall be containedwithin the frequency band 9 kHz to 490 kHz. A power
line carrier systemshall operate on an unprotected, non-interference basis in ac
cordancewith Sec. 15.5 of this part. If harmful interference occurs, theelectric
power utility shall discontinue use or adjust its power linecarrier operation,
as required, to remedy the interference. Particularattention should be paid to t
he possibility of interference to Loran Coperations at 100 kHz.
(c) Power line carrier system apparatus shall be operated with theminimum power
possible to accomplish the desired purpose. No equipmentauthorization is require
d.
(d) The best engineering principles shall be used in the generationof radio freq
uency currents by power line carrier systems to guardagainst harmful interferenc
e to authorized radio users, particularly onthe fundamental and harmonic frequen
cies.
(e) Power line carrier system apparatus shall conform to suchengineering standar
ds as may be promulgated by the Commission. Inaddition, such systems should adhe
re to industry approved standardsdesigned to enhance the use of power line carri
er systems.
112
 (f) The provisions of this section apply only to systems operatedbya power util
ity for general supervision of
[[Page 692]]
the power system and do not permit operation on electric lines whichconnect the
distribution substation to the customer or house wiring.
Such operation can be conducted under the other provisions of thispart.
[54 FR 17714, Apr. 25, 1989; 54 FR 32339, Aug. 7, 1989]
113
C. MC68360 Code
Code listings for the protocol implementation on the Motorola MC68360 are on the
CDROM
included with this thesis. All coding was done in the c programming language.
There are two sections of code: one for the master and one for the slave. The ba
sic
structure of each is the same:
1) makefile file to make the compile and build of the code much easier.
2) uart.h header file contains important constants.
3) init.c contains initialization code. Initializes such things as the UART, any

necessary interrupts, and timers.

4) transmit.c contains code for the transmit operation. Decides what data to
send and when, and sends bytes to the UART.
5) handlers.c contains all the interrupt handlers in the system. These include
external interrupt (60 Hz trigger), the timer interrupt (for the one millisecond
timeslots), receive data interrupt (whenever a byte of data is received in the
UART). Each handler routine contains code appropriate for handling the
interrupt.
The major differences in the code between the master and slave are in the transm
it.c and
handlers.c programs. The transmit.c program in the master contains much more log
ic for
sending appropriate data and control packets, while in the slave it contains log
ic only for
sending ACK packets. The handlers.c program, on the other hand, is much more
complex in the slave than it is in the master. In addition to the timer and exte
rnal
interrupts found in both the master and slave, the slave must check the integrit
y of every
packet, what type it is, and keep track of timeslot errors. Other small differen
ces exist in
the master and slave programs uart.h and init.c but are mainly initializing diff
erent
variables.
114
D. XR2211 Data Sheet
Following is the XR2211 data sheet. This chip was instrumental in the design as
it
provided the FSK demodulation function.
115
XR-2211

...the analog plus companyTM

FSK Demodulator/
Tone Decoder
FEATURES
.
Wide Frequency Range, 0.01Hz to 300kHz
.
Wide Supply Voltage Range, 4.5V to 20V
.
HCMOS/TTL/Logic Compatibility
.
FSK Demodulation, with Carrier Detection
.
Wide Dynamic Range, 10mV to 3V rms
.
Adjustable Tracking Range, +1% to 80%
.
Excellent Temp. Stability, +50ppm/°C, max.
June 1997-3
APPLICATIONS
.
Caller Identification Delivery
.
FSK Demodulation
.
Data Synchronization
.
Tone Decoding
.
FM Detection
.
Carrier Detection
GENERAL DESCRIPTION
The XR-2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications
applications. It is particularly suited for FSK modem
applications. It operates over a wide supply voltage range
of 4.5 to 20V and a wide frequency range of 0.01Hz to
300kHz. It can accommodate analog signals between
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal within the pass band, a
quadrature phase detector which provides carrier
detection, and an FSK voltage comparator which provides
FSK demodulation. External components are used to
independently set center frequency, bandwidth, and output
delay. An internal voltage reference proportional to the
power supply is provided at an output pin.
The XR-2211 is available in 14 pin packages specified for
military and industrial temperature ranges.
ORDERING INFORMATION

Part No. Package

Operating
Temperature Range
XR-2211M 14 Pin CDIP (0.300 ) -55°C to +125°C
XR-2211N 14 Pin CDIP (0.300 ) -40°C to +85°C
XR-2211P 14 Pin PDIP (0.300 ) -40°C to +85°C
XR-2211ID 14 Lead SOIC (Jedec, 0.150 ) -40°C to +85°C
Rev. 3.01
1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000 .
FAX (510) 668-7017
1
XR-2211
BLOCK DIAGRAM
GND NC
VCC
91 4
2
3
11
6
Loop
5
14
13
12
10
8
7
Pre Amplifier
Lock
Detect
Comparator
-Det
Internal
Reference
VREF
FSK Comp
Quad
-Det
VCO
LDO
INP
LDF
TIM C1
LDOQ
TIM C2
LDOQN
TIM R
VREF

DO
COMP I
Figure 1. XR-2211 Block Diagram
Rev. 3.01
2
XR-2211
PIN CONFIGURATION
1 14
2 13
3 12
4 11
5 10
6 9
7 8
TIM C1 VCC
VCC
INP
INP
TIM C2
LDF
LDF
TIM R
GND
GND
LDO
LDOQN
LDOQN
VREF
LDOQ
LDOQ
NC
DO
DO
COMP I

1 14 TIM C1
2 13 TIM C2
3 12 TIM R
4 11 LDO
5 10 VREF
6 9 NC
7 8 COMP I
14 Lead CDIP, PDIP (0.300 ) 14 Lead SOIC (Jedec, 0.150 )
PIN DESCRIPTION

Pin # Symbol Type Description

1 VCC Positive Power Supply.
2 INP I Receive Analog Input.
3 LDF O Lock Detect Filter.
4 GND Ground Pin.
5 LDOQN O Lock Detect Output Not. This output will be low if the VCO is in the c
apture range.
6 LDOQ O Lock Detect Output. This output will be high if the VCO is in the captu
re range.
7 DO O Data Output. Decoded FSK output.
8 COMP I I FSK Comparator Input.
9 NC Not Connected.
10 VREF O Internal Voltage Reference. The value of VREF is VCC/2 - 650mV.
11 LDO O Loop Detect Output. This output provides the result of the quadrature p
hase detection.
12 TIM R I Timing Resistor Input. This pin connects to the timing resistor of th
e VCO.
13 TIM C2 I Timing Capacitor Input. The timing capacitor connects between this p
in and pin 14.
14 TIM C1 I Timing Capacitor Input. The timing capacitor connects between this p
in and pin 13.
Rev. 3.01
3
XR-2211

ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 12V, TA = +25°C, RO = 30K, CO = 0.033F, unless otherwise spec
ified.

Parameter Min. Typ. Max. Unit Conditions

General
Supply Voltage
Supply Current
4.5
4
20
7
V
mA R0 > 10K. See Figure 4.
Oscillator Section
Frequency Accuracy
Frequency Stability
Temperature
Power Supply
+1
+20
0.05
0.2
+3
+50
0.5
%
ppm/°C
%/V
%/V
Deviation from fO = 1/R0 C0
See Figure 8.
VCC = 12 +1V. See Figure 7.
VCC = + 5V. See Figure 7.
Upper Frequency Limit
Lowest Practical Operating
Frequency
Timing Resistor, R0 - See
Figure 5100 300
0.01
kHz
Hz
R0 = 8.2K, C0 = 400pF
R0 = 2M, C0 = 50F
Operating Range 5 2000 K
Recommended Range 5 K.
See Figure 7 and Figure 8.
Loop Phase Dectector Section
Peak Output Current +150 +200 +300 A Measured at Pin 11
Output Offset Current 1 A
Output Impedance 1 M.
Maximum Swing +4 + 5 V Referenced to Pin 10
Quadrature Phase Detector Measured at Pin 3
Peak Output Current
Output Impedance
Maximum Swing
100 300
1
11
A
M.
VPP
Input Preampt Section Measured at Pin 2
Input Impedance
Input Signal
Voltage Required to
20 K.
Cause Limiting 2 10 mV rms
Notes
Parameters are guaranteed over the recommended operating conditions, but are not
100% tested in production.
Bold face parameters are covered by production test and guaranteed over operatin
g temperature range.
Rev. 3.01
4
XR-2211
DC ELECTRICAL CHARACTERISTICS (CONT D)
Test Conditions: VCC = 12V, TA = +25°C, RO = 30K, CO = 0.033F, unless otherwise spec
ified.

Parameter Min. Typ. Max. Unit Conditions

Voltage Comparator Section
Input Impedance 2 M.
Measured at Pins 3 and 8
Input Bias Current 100 nA
Voltage Gain 55 70 dB RL = 5.1K.
Output Voltage Low 300 500 mV IC = 3mA
Output Leakage Current 0.01 10 A VO = 20V
Internal Reference
Voltage Level 4.9 5.3 5.7 V Measured at Pin 10
Output Impedance 100 .
AC Small Signal
Maximum Source Current 80 A
Notes
Parameters are guaranteed over the recommended operating conditions, but are not
100% tested in production.
Bold face parameters are covered by production test and guaranteed over operatin
g temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW
Package Power Dissipation Ratings
CDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 8mW/°C
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mW
Derate Above TA = 25°C . . . . . . . . . . . . . . 60mW/°C
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 5mW/°C
SYSTEM DESCRIPTION
The main PLL within the XR-2211 is constructed from an
input preamplifier, analog multiplier used as a phase
detector and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that
input signals above typically 10mV rms are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a
current controlled oscillator with its normal input current
(fO) set by a resistor (R0) to ground and its driving current
with a resistor (R1) from the phase detector.
The output of the phase detector produces sum and
difference of the input and the VCO frequencies
(internally connected). When in lock, these frequencies
are fIN+ fVCO (2 times fIN when in lock) and fIN - fVCO (0Hz
when lock). By adding a capacitor to the phase detector
output, the 2 times fIN component is reduced, leaving a
DC voltage that represents the phase difference between
the two frequencies. This closes the loop and allows the
VCO to track the input frequency.
The FSK comparator is used to determine if the VCO is
driven above or below the center frequency (FSK
comparator). This will produce both active high and
active low outputs to indicate when the main PLL is in lock
(quadrature phase detector and lock detector
comparator).
Rev. 3.01
5
XR-2211
PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this
terminal. The internal impedance at pin 2 is 20K.
Recommended input signal level is in the range of 10mV
rms to 3V rms.
Quadrature Phase Detector Output (Pin 3): This is the
high impedance output of quadrature phase detector and
is internally connected to the input of lock detect voltage
comparator. In tone detection applications, pin 3 is
connected to ground through a parallel combination of RD
and CD (see Figure 3) to eliminate the chatter at lock
detect outputs. If the tone detect section is not used, pin 3
can be left open.
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
low state when the PLL is out of lock and goes to high
state when the PLL is locked. It is an open collector type
output and requires a pull-up resistor, RL, to VCC for
proper operation. At low state, it can sink up to 5mA of
load current.
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6.
This output is also an open collector type stage which can
sink 5mA of load current at low or on state.
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, RL, to VCC for
proper operation. It can sink 5mA of load current. When
decoding FSK signals, FSK data output is at high or off
state for low input frequency, and at low or on state for
high input frequency. If no input signal is present, the logic
state at pin 7 is indeterminate.
FSK Comparator Input (Pin 8): This is the high
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase
detector output (pin 11). This data filter is formed by RF
and CF (see Figure 3.) The threshold voltage of the
comparator is set by the internal reference voltage, VREF,
available at pin 10.
Reference Voltage, VREF (Pin 10): This pin is internally
biased at the reference voltage level, VREF: VREF = VCC /2
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at pins 5, 8, 11 and 12. Pin
10 must be bypassed to ground with a 0.1F capacitor for
proper operation of the circuit.
Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 3.) With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VREF. The peak to peak voltage swing
available at the phase detector output is equal to 2 x VREF.
VCO Control Input (Pin 12): VCO free-running
frequency is determined by external timing resistor, R0,
connected from this terminal to ground. The VCO
free-running frequency, fO, is:
1
fO .
Hz
R0·C0
where C0 is the timing capacitor across pins 13 and 14.
For optimum temperature stability, R0 must be in the
range of 10K to 100K (see Figure 9.)
This terminal is a low impedance point, and is internally
biased at a DC level equal to VREF. The maximum timing
current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
VCO Timing Capacitor (Pins 13 and 14): VCO
frequency is inversely proportional to the external timing
capacitor, C0, connected across these terminals (see
Figure 6.) C0 must be non-polar, and in the range of
200pF to 10F.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with R0 at pin 12
(see Figure 10.)
VCO Free-Running Frequency, fO: XR-2211 does not
have a separate VCO output terminal. Instead, the VCO
outputs are internally connected to the phase detector
sections of the circuit. For set-up or adjustment purposes,
the VCO free-running frequency can be tuned by using
the generalized circuit in Figure 3, and applying an
alternating bit pattern of O s and 1 s at the known mark
and space frequencies. By adjusting R0, the VCO can
then be tuned to obtain a 50% duty cycle on the FSK
output (pin 7). This will ensure that the VCO fO value is
accurately referenced to the mark and space frequencies.
Rev. 3.01
6
XR-2211
Loop Data
Filter Filter
FSK
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput
FSK
Comp
Det
ÎÎÎÎLock Detect
OutputsDet
VCO
Preamp
Input
f
f
f
f
Lock Detect Lock Detect
Filter Comp
Figure 2. Functional Block Diagram of a Tone and FSK
Decoding System Using XR-2211
VCC
RB
Rl
2
Input
Signal
0.1F
LDOQN
5
Detect
Comp.
Lock
Loop
Phase
Detect C1
11
R1
RF
CF
8
FSK
Comp.
7
Internal
Reference
6
LDOQ
10
VCO
14 13
12
R0
C0
Quad
Phase
Detect 3
0.1F
+
+
RD

CD
Figure 3. Generalized Circuit Connection for
FSK and Tone Detection

Rev. 3.01
7
XR-2211
DESIGN EQUATIONS
(All resistance in , all frequency in Hz and all capacitance in farads, unless ot
herwise specified)
(See Figure 3 for definition of components)
1.
VCO Center Frequency, fO:
1
fO .

R0·C0
2.
Internal Reference Voltage, VREF (measured at pin 10):
VCC
VREF 
 650mV in volts
2
3.
Loop Low-Pass Filter Time Constant, :
.
.
C1·RPP (seconds)
where:
R1·RF
RPP .

R1 .
RF
if RF is  or CF reactance is , then RPP = R1
4.
Loop Damping, :
1250·C0
.

.

R1·C1
Note: For derivation/explanation of this equation, please see TAN-011.
5.
Loop-tracking
f
bandwidth, .

f0
f R0
f0 R1
Tracking
Bandwidth
f f
fLL f1 fO f2 fLH
Rev. 3.01
8
XR-2211
6.
FSK Data filter time constant, tF:
RB · RF
F .
·CF (seconds)
( RB .
RF)
7.
Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage acro
ss pin 10 and pin11, per unit of
phase error at phase detector input):
VREF · R1 .
volt
Kd .

10, 000·.
radian
Note: For derivation/explanation of this equation, please see TAN-011.
8.
VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit
of DC voltage change at pin 11):
radiansecond
2
K0 .


volt
VREF ·C0 · R1
9.
The filter transfer function:
1
F(s) .
at0Hz. S = J and  = 0
1 .
SR1·C1
10. Total loop gain. KT:
RF 1
KT .
KO·Kd·F(s) 
.
.

5, 000·C0·(R1 .
RF)
seconds
11.
Peak detector current IA:
VREF
IA .
(VREF in volts and IA in amps)
20, 000
Note: For derivation/explanation of this equation, please see TAN-011.
Rev. 3.01
9
XR-2211
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to
Figure 3 and Figure 10, the functions
of external components are defined as follows: R0 and C0 set the PLL center freq
uency, R1 sets the system bandwidth,
and C1 sets the loop filter time constant and the loop damping factor. CF and RF
form a one-pole post-detection filter for
the FSK data output. The resistor RB from pin 7 to pin 8 introduces positive fee
dback across the FSK comparator to
facilitate rapid transition between output logic states.
Design Instructions:
The circuit of Figure 10 can be tailored for any FSK decoding application by the
choice of five key circuit components: R0,
R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, fO and f1,
these parameters can be calculated as
follows:
(All resistance in  s, all frequency in Hz and all capacitance in farads, unless ot
herwise specified)
a)
Calculate PLL center frequency, fO:
fO .
F1·F2
b)
Choose value of timing resistor R0, to be in the range of 10K to 100K. This choice
is arbitrary. The recommended
value is R0 = 20K. The final value of R0 is normally fine-tuned with the series p
otentiometer, RX.
RX
RO .
RO .

2
c)
Calculate value of C0 from design equation (1) or from Figure 7:
1
CO .

R0· f0
d)
Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R0·f0
R1 .
·2
(f1 f2)
e)
Calculate C1 to set loop damping. (See design equation 4):
Normally,  = 0.5 is recommended.
1250·C0
C1 .

R1 ·
2
Rev. 3.01
10
XR-2211
f)
The input to the XR-2211 may sometimes be too sensitive to noise conditions on t
he input line. Figure 4 illustrates
a method of de-sensitizing the XR-2211 from such noisy line conditions by the us
e of a resistor, Rx, connected
from pin 2 to ground. The value of Rx is chosen by the equation and the desired
minimum signal threshold level.
20, 000
VREF
VIN minimum (peak) .
Va Vb .
V .
2.8mV offset .
VREF
or RX .
20, 000 1
(20, 000 .
RX)
V
VIN minimum (peak) input voltage must exceed this value to be detected (equivale
nt to adjusting V threshold)

VCC

2
Va Vb
To Phase
Detector
Input
20K
20K
Rx
VREF
ÎÎ10
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, CF:
(RF .
R1)·RB
Rsum .

(R1 .
RF .
RB)
0.25
1
CF .
Baud rate in
(Rsum·Baud Rate)
seconds
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
11
XR-2211

20
1.0
R0=5KW
R0=10KW
R0>100K
4 6 810 12 14 16 18 20 22 24

R0=5K.
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
R0=10K.
ÎÎÎÎÎÎÎÎÎÎÎ
R0=20K.
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
R0=40K.
ÎÎÎÎÎÎÎÎÎÎÎ
R0=80K.
ÎÎÎÎÎÎÎÎÎÎÎ
R0=160K
ÎÎÎÎÎÎÎÎÎÎÎ

Supply vs. Current (mA)

15
10
5
0
C0( F)
0.1
0.01
100 1000 10000
fO(HZ)
Supply Voltage, V+ (Volts)
Figure 5. Typical Supply Current vs. V+ Figure 6. VCO Frequency vs. Timing Resis
tor
(Logic Outputs Open Circuited)
1,000
CÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
0=0.001F
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
0=0.0C033F
CÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
0=0.01F
C0=0.1F
ÎÎÎÎÎÎÎÎÎÎÎÎ
C0ÎÎÎÎÎÎÎÎÎÎÎÎ
=0.0331F
C0=0.33FÎÎÎÎÎÎÎÎÎÎÎÎ

Normalized Frequency
1.02
1.01
1.00
0.99
0.98
0.97
5
fO = 1kHz
RF = 10R0
51
4 2
3
3
4
2
Curve R0
1
2
3
5K
10K
30K
1 4
5
100K
300K
R (K)
0
100
10
4 6 8 1012 14 16 18 20 2224
0 1000 10000
V+ (Volts)
fO(Hz)
Figure 7. VCO Frequency vs. Timing Capacitor Figure 8. Typical fO vs. Power Supp
ly
Characteristics
O)
Normalized Frequency Drift (% of f= 1 kHz
+1.0
+0.5
0
-0.5
-1.0
-50 -25 0 25 50 75 100 125
R0=1MW
R0=500K
R0=50K
R0=10K
1MW
500K
50K
10K
V+ = 12V
R1 = 10 R0
fO
Temperature (°C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 3.01
12
XR-2211
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.

Step 1: Calculate fO: from design instructions

(a) fO 
1200·2200 =1624
Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K. (See design instruct
ions (b))
(b) RT .
10 
10
.
15K
2
Step 3: Calculate C0 from design instructions
1
(c) CO .
39nF
15000·1624
Step 4: Calculate R1 : from design instructions
20000·1624·2
(d) R1 .
51, 000
(2200 1200)
Step 5: Calculate C1 : from design instructions
1250·39nF
(e) C1 .
3.9nF
51000·0.52
Step 6: Calculate RF : RF should be at least five times R1, RF = 51,000V5 = 255
K.
Step 7: Calculate RB : RB should be at least five times RF, RB = 255,000V5 = 1.2
M.
Step 8: Calculate RSUM :
(RF .
R1)·RB
RSUM .
240K
(RF .
R1 .
RB)
0.25
Step 9: Calculate CF :
CF .
1nF
RSUM·Baud Rate.
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
13
XR-2211
VCC
RL
5.1K
5%
Data
Output
Input
Signal
RB
1.8m 5%Loop
Phase
Detect
11
C1
2.7nF
5% R1
35.2K
1%
8
FSK
Comp.
RF 178K
5% CF1nF 10%
7
Internal
Reference0.1mF
10
VCO
14 13
12
Rx
20K
R0
20K
1%
CO
27nF 5%
2
0.1mF
Lock
Detect
Comp.
VCO
Tune
Fine
6
LDOQ
5
LDOQN
Quad
Phase
Detect
+
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals
(Bell 202 Format)

2
Input
Signal

0.1mF

Between 400K and 600K

VCC
RB
RL
5.1k
5 LDOQN
Lock
Detect
Comp.
RD
CD
LoopPhase
Detect C1
11
R1
RF
CF
8
FSK
Comp.
7
Internal
Reference0.1mF
10
VCO
14 13
12
R0
C0
Rx
6 LDOQ
3
Quad
Phase
Detect
+
Figure 11. External Connectors for FSK Demodulation with Carrier
Detect Capability
Rev. 3.01
14
XR-2211
VCC
Loop
Phase
Detect
11
C1220pF5% R1
200K
1%
8
FSK
Comp.
7
Internal
Reference0.1mF
10
VCO
14 13
12
R0
20K
1%C0
50nF 5%
Rx
5K
2
0.1mF
Input
Tone
Lock
Detect
Comp.
Tune
Fine
6 LDOQ
RL2
5.1K
RL3
5.1K
Logic Output
5 LDOQN3
CD
80nFRD
470K
Quad
Phase
Detect
VCC
VCO
+
+
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect
The lock detect section of XR-2211 can be used as a
carrier detect option for FSK decoding. The
recommended circuit connection for this application is
shown in Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at low state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
high to enable the data output.
Note: Data Output is Low When No Carrier is Present.
The minimum value of the lock detect filter capacitance
CD is inversely proportional to the capture range, +fc.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C1. For most applications, fc
> f/2. For RD = 470K, the approximate minimum value
of CD can be determined by:
16
CD .
C in F and f in Hz.
f
C in F and f in Hz.
With values of CD that are too small, chatter can be
observed on the lock detect output as an incoming signal
frequency approaches the capture bandwidth.
Excessively large values of CD will slow the response time
of the lock detect output. For Caller I.D. applications
choose CD = 0.1F.
Tone Detection
Figure 12 shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at high and low logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors RL2 and
RL3, as shown in Figure 12.
With reference to Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
follows: R0 and C0 set VCO center frequency; R1 sets the
detection bandwidth; C1 sets the low pass-loop filter time
constant and the loop damping factor.
Rev. 3.01
15
XR-2211
Design Instructions:
The circuit of Figure 12 can be optimized for any tone detection application by
the choice of the 5 key circuit components:
R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these paramete
rs are calculated as follows:
(All resistance in  s, all frequency in Hz and all capacitance in farads, unless ot
herwise specified)
a)
Choose value of timing resistor R0 to be in the range of 10K to 50K. This choice i
s dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value i
s R0 = 20K. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b)
Calculate value of C0 from design equation (1) or from Figure 7 fS = fO:
1
CO .

R0·fs
c)
Calculate R1 to set the bandwidth +f (See design equation 5):
R0·f0·2
R1 .

f
Note: The total detection bandwidth covers the frequency range of fO +f
d)
Calculate value of C1 for a given loop damping factor:
Normally,  = 0.5 is recommended.
1250·C0
C1 .

R1·2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL c
apture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic ou
tput, with RD = 470K, CD must be:
16
CD .
Cin F
f
Increasing CD slows down the logic output response time.
Design Examples:
Tone detector with a detection band of + 100Hz:
a)
Choose value of timing resistor R0 to be in the range of 10K to 50K. This choice i
s dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value i
s R0 = 20 K. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b)
Calculate value of C0 from design equation (1) or from Figure 6 fS = fO:
11
C0 .
R0·fS 20, 000·1, 000 .
50nF
Rev. 3.01
16
XR-2211
c) Calculate R1 to set the bandwidth +f (See design equation 5):
R0·fO·2 20, 000·1, 000·2
R1 .
.
400K
f 100
Note: The total detection bandwidth covers the frequency range of fO +f
d) Calculate value of C0 for a given loop damping factor:
Normally, .
= 0.5 is recommended.
1250·C0 1250·50·10 9
C1 
R1·2 400, 000·0.52
.
6.25pF
Increasing C1 improves the out-of-band signal rejection, but increases the PLL c
apture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic ou
tput, with RD = 470K, CD must be:
16 16
CD .

f 200 .
80nF
Increasing CD slows down the logic output response time.
f) Fine tune center frequency with 5K potentiometer, RX.
VCC
0.1mFRF
100K
VCC
Loop
Phase
Detect C1
11
R1
8
FSK
Comp
.
7
3
2
1
4
11 LM324
CF
Output
Demodulated
Internal
Reference
6
LDOQ
0.1mF
10
Lock
Detect
Comp.
VCO
14 13
12
R0
C0
2
0.1mF
Input
FM
Quad
Phase
Detect 5
LDOQN
+
+
+
Figure 13. Linear FM Detector Using XR-2211 and an External Op Amp.
(See Section on Design Equation for Component Values.)
Rev. 3.01
17
XR-2211
Linear FM Detection
XR-2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry
applications. The recommended circuit connection for
this application is shown in Figure 13. The demodulated
output is taken from the loop phase detector output (pin
11), through a post-detection filter made up of RF and CF,
and an external buffer amplifier. This buffer amplifier is
necessary because of the high impedance output at pin
11. Normally, a non-inverting unity gain op amp can be
used as a buffer amplifier, as shown in Figure 13.
The FM detector gain, i.e., the output voltage change per
unit of FM deviation can be given as:
R1·VREF
VOUT .

100·R0
where VR is the internal reference voltage (VREF = VCC /2
-650mV). For the choice of external components R1, R0,
CD, C1 and CF, see the section on design equations.
6
Lock Detect
5
Capacitor
Input
7
Resistor
V+
20K
20K
Internal Voltage
Reference
Input Preamplifier
and Limiter
10K 10K
Quadrature
Phase Detector
Lock
Detect
Filter
Outputs
Lock Detect
Comparator
FSK
Data
Output
FSK
Comparator
InputLoop
Detector
Output
A
From
VCO
2K
A
8K
12
R0
Timing
13
B B
C0 14
REF
Voltage
Output
10 2
B
From
VCO
B
3
2K
A
1
4
Ground
8
11
A
Timing
Voltage Controlled Loop Phase Detector FSK Comparator
Oscillator
Figure 14. Equivalent Schematic Diagram
Rev. 3.01
18
XR-2211
14 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
L
D
B
e
B1
A1
a
c
Seating
Plane
Base
Plane A
14
1 7
8
E1
E
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX
A 0.100 0.200 2.54 5.08
A1 0.015 0.060 0.38 1.52
B 0.014 0.026 0.36 0.66
B1 0.045 0.065 1.14 1.65
c 0.008 0.018 0.20 0.46
D 0.685 0.785 17.40 19.94
E1 0.250 0.310 6.35 7.87
E 0.300 BSC 7.62 BSC
e 0.100 BSC 2.54 BSC
L 0.125 0.200 3.18 5.08
a 0°
15°
0°
15°

Note: The control dimension is the inch column

Rev. 3.01
19
XR-2211
14 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
14
1
8
7
D
e B1
A1
E1
E
A
L
B
Seating
Plane
a
A2
C
eB
eA
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX
A 0.145 0.210 3.68 5.33
A1 0.015 0.070 0.38 1.78
A2 0.115 0.195 2.92 4.95
B 0.014 0.024 0.36 0.56
B1 0.030 0.070 0.76 1.78
C 0.008 0.014 0.20 0.38
D 0.725 0.795 18.42 20.19
E 0.300 0.325 7.62 8.26
E1 0.240 0.280 6.10 7.11
e 0.100 BSC 2.54 BSC
eA 0.300 BSC 7.62 BSC
eB 0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
a 0°
15°
0°
15°

Note: The control dimension is the inch column

Rev. 3.01
20
XR-2211
14 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
e
14 8
7
D
E H
B
A
L
C
A1
Seating
Plane a
1
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.007 0.010 0.19 0.25
D 0.337 0.344 8.55 8.75
E 0.150 0.157 3.80 4.00
e 0.050 BSC 1.27 BSC
H 0.228 0.244 5.80 6.20
L 0.016 0.050 0.40 1.27
a 0°
8°
0°
8°

Note: The control dimension is the millimeter column

Rev. 3.01
21
XR-2211
Notes

Rev. 3.01
22
XR-2211
Notes

Rev. 3.01
23
XR-2211
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in
this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility f
or the use of any circuits described
herein, conveys no license under any patent or other right, and makes no represe
ntation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary
depending upon a user s specific application. While the information in this public
ation has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life suppo
rt applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the li
fe support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such
applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injur
y or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adeq
uately protected under the circumstances.

Copyright 1995 EXAR Corporation

Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corpor
ation is prohibited.
Rev. 3.01
24