CMOS Integrated Circuits Lecture 10 ELEC212

ELEC212. CMOS Integrated Circuits

Lecture 10

CMOS Circuits

CMOS logic family. A CMOS logic circuit is in effect an extension, or a generalization, of the
CMOS inverter. The key logic functions are shown in Table 1.

Table 1 The key logic functions with symbols, notation and truth tables.

Name Symbol Notation Truth table

“NOT” XA A X
0 1
1 0

“OR” X  A B A B X
0 0 0
0 1 1
1 0 1
1 1 1

“AND” X  A B A B X
0 0 0
0 1 0
1 0 0
1 1 1

“NOR” X  A B A B X
0 0 1
0 1 0
1 0 0
1 1 0

“NAND” X  A B A B X
0 0 1
0 1 1
1 0 1
1 1 0

“XOR” X  A B A B X
0 0 0
0 1 1
1 0 1
1 1 0

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CMOS Integrated Circuits Lecture 10 ELEC212

All CMOS logic gates require a pMOS device and an nMOS device for each input. Each
complementary pair is connected in a manner similar to the inverter (see Lecture 6), except that
there may be additional series or parallel transistors in the drain-source circuits. A key to
understanding the principle of operation for these circuits is the logical operation of the nMOS
and pMOS transistors switches which is depicted in Fig. 1. An nMOS transistor will switch on
only when the logic 1 is on the input; the opposite is valid for the pMOST, it is hard on only
when the logic 0 is at the input, hence the ‘circle’ in the symbol for a pMOST (see right part of
Fig. 1). We will proceed now to a discussion of the NOR and NAND gate realized in CMOS
technology.

Fig. 1 Logical operation of MOSFET switches.

The NOR logic gate. The truth table for a NOR gate is shown below, where A and B are inputs
and X is the output. It can be seen that when either input is a logic 1, the output will be 0. The
only combination of inputs that results in an output of 1 is A=0 and B=0. The logic expression
that describes the NOR gate is

X  A B .
Note that it is assumed that a positive logic convention is used here, i.e. the high voltage level
corresponds to logic 1. The two-input NOR gate can be implemented in CMOS as shown in Fig.
2. The general logic symbol for the NOR gate is included in this figure. The small circle at the
output stand for an inversion following the OR gate to create the NOR gate.

Fig. 2 A two-input CMOS NOR gate with general logic symbol.

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CMOS Integrated Circuits Lecture 10 ELEC212

When both inputs are at 0V or logic 0, both nMOS devices are

off and both pMOS devices are on. This input condition leads
to 0V gate-to-source voltages for both M1 and M2 transistors,
and -5V VGS for M3 and M4. The output voltage will be very
near 5V or logic 1. Since the output voltage is so close to 5V,
the approximate equivalent circuit of Fig. 3 can be used in
many situations.

Fig. 3 A CMOS NOR gate when A=B=0.

When one or both inputs switch to logic 1 (or 5V) at least one nMOST turns on and at least one
pMOST turns off. The approximate equivalent circuits of Fig. 4 apply to this case. In either case,
a very high resistance exists between the power-supply voltage and output, and a very low
resistance exists between output and ground, which forces the output to be at 0V or logic 0.

Fig. 4 Equivalent circuits for a CMOS NOR gate when: a) A=1, B=0; b) A=B=1.
Based on this discussion, the gate circuit in Fig. 2 is seen to satisfy the conditions of the truth
table for the NOR gate. Note that the NOR gate can be extended to a higher number of inputs (N)
by adding a complementary pair of transistors (nMOS and pMOS) for each additional input to
give an N-input NOR gate.

The NAND logic gate. The logical expression for this gate is

X  A B .

For a positive logic system in which a high voltage level is defined as a logic 1, the NAND gate
output is at the high level for all but one input combination. If both inputs are high, the output
should be low. The CMOS gate in Fig. 5 satisfies this truth table. Also shown in this figure is the
logic symbol for the NAND, which is equivalent to an AND gate followed by an inversion
(hence circle in the symbol).

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CMOS Integrated Circuits Lecture 10 ELEC212

Fig. 5 A two-input CMOS NAND gate with logic symbol.

For the combination of inputs A=B=1, both M1 and M2 will be turned on and both M3 and M4
will be off. A very high impedance exists between the power supply and the output terminal,
while a low impedance exists between the output terminal and ground. An approximation to this
output condition appears in Fig. 6.

Fig. 6 Approximate equivalent circuit for CMOS NAND gate when: A=B=1.

For any other input condition, the impedance from power supply to output will be low, while the
impedance from output to ground will be high. These conditions lead to a high output voltage, as
seen in Fig. 7.

Fig. 7 Conditions leading to X=1 for CMOS NAND gate.

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CMOS Integrated Circuits Lecture 10 ELEC212

Design considerations for CMOS NOR and NAND gates. When designing either NOR or
NAND gates, it is desirable that the gates produce symmetric output with the same value of rise
and fall times and with the switching threshold close to VDD/2. Hence, the sizes of the transistors
must be chosen correctly.

As pointed out in the discussion of the CMOS inverter (see notes for Lecture 6), the surface
mobility of electrons is 2.5 times the surface mobility of holes in Si, so the pMOS transistors
need to be about 2.5 times the size of the nMOS transistors to account for this fact. In the NOR
gate, there is an added problem that the pMOSTs appear in series (M3 and M4 in Fig. 2). When
two or more devices are in series, we need to increase their sizes (i.e. W/L) to maintain the same
switching speed (t~1/(W/L)). A rough, but effective, approximation is to say that two transistors
in series appear like a transistor with twice the length; therefore, in order to keep  constant, the
width should be double as well. This approach would be exactly correct if both transistors were
in the linear region, had precisely the same gate-to-source voltages and had small source-to-drain
voltages since they would then function as resistors in series. However, the pMOSTs in Fig. 2
are not in the linear region for the entire transition time, nor do they have exactly the same V SG
nor is VSD small for both of them during the entire transition. Nevertheless, this rough
approximation is reasonably effective for determining the sizes of these series transistors. Hence,
for an N-input NOR gate, the transistors need to be sized according to

W W
( ) pMOS  2.5 N ( ) nMOS . (10.1)
L L

So, if the nMOS transistors are minimum size, the pMOSTs for the two-input NOR gate shown
in Fig. 2 will be 5x minimum size, and the overall gate will consume approximately the
equivalent of 12 minimum size transistors.

For the CMOS NAND gate shown in Fig. 5, two nMOS transistors are in series (M1 and M2) to
pull the output low, and two pMOSTs (M3 and M4) in parallel to pull the output up. The
transistors sizes are determined using the same method applied to the NOR gate. If the NAND
gate is to have the same switching speed (or propagation delays) as a minimum-size symmetric
inverter, then the two nMOSTs (in series) should have W=2Wmin. The pMOSTs can be the same
size as they would be in the minimum-size symmetric inverter, i.e. 2.5x the minimum-size
transistor. So, for an N-input NAND gate, the transistors should be sized so that

W 2.5 W
( ) pMOS  ( ) nMOS . (10.2)
L N L

Thus, in case of two-input NAND gate in Fig. 5, if the nMOSTs are made 2x the minimum size
to achieve the same speed as a minimum-size symmetric inverter, then the pMOSTs will be 2.5x
the minimum size, and the overall gate will take the area of about 9 minimum-size transistors.
Comparing to the two-input NOR gate, the two-input NAND gate uses only 75% of the area.
Therefore, if everything else is equal, the NAND gates are preferable choice in IC design.

In summary, some possible layouts for NOR and NAND gates are illustrated in Fig. 8.

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CMOS Integrated Circuits Lecture 10 ELEC212

a)

b)

Fig. 8 Possible layouts for a CMOS: a) NOR and b) NAND gates. (A, B – inputs, C – output)

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CMOS Integrated Circuits Lecture 10 ELEC212

Complex CMOS gates. Consider the general logic gate illustrated in Fig. 9. The pull-up
network is made up of pMOSTs and is derived by looking at the equation for Y, in other words,
what combination of inputs should cause the output to be high. The pull-down network, on the
other hand, is made up of nMOSTs and is derived by looking at the equation for Y, i.e. what
combination of inputs should cause the output to be low.

.
.
.

.
.
.

Fig. 9 A general CMOS logic gate. Both the pull-up and pull-down networks have the same inputs.

Notice that it is possible to derive one network from its complement by using series-parallel
transformations: for every transistor or group of transistors in series (logic operation AND) in
one network, there must be transistor or group of transistors in parallel (logic operation OR) in
the complementary networks. An example of CMOS complex gate is further illustrated in Fig.
10. As can be seen, the gate executes the logic function

Y  A( B  CD) . (10.3)

By observing Eq. (10.3), it can be seen that the

pull-down network (nMOSTs) is realized by
transistor QNA in series with parallel
connection of transistor QNB and transistors
QNC and QND being in series – thus we have
Y=A(B+CD). Complementary, the pull-up
network (pMOSTs) is realized with transistor
QPA being in parallel connection with transistor
QPB, which is in series with parallel connection
of transistors QPC and QPD, so that
Y  A( B  CD) function is valid.

Fig. 10 CMOS realization of a complex gate.