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3-Terminal 1A Positive Voltage Regulator

• Output Current up to 1A
• Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V
• Thermal Overload Protection
• Short Circuit Protection
• Output Transistor Safe Operating Area Protection

The KA78XX/KA78XXA series of three-terminal positive regulator are available in the TO-
220/D-PAK package and with several fixed output voltages, making them useful in a wide range
of applications. Each type employs internal current limiting, thermal shut down and safe
operating area protection, making it essentially indestructible. If adequate heat sinking is
provided, they can deliver over 1A output current. Although designed primarily as fixed voltage
regulators, these devices can be used with external components to obtain adjustable voltages and
Internal Block Digram
1. Load and line regulation are specified at constant junction temperature. Changes in Vo due to
heating effects must be taken
into account separately. Pulse testing with low duty is used.
Typical Applications
DC Parameters

The DV-16100-S2FBLY, dot-matrix LCD unit of a 5 x 7- dot 16-character 1-line
dot-matrix LCD panle, LCD driver, controller LSI and yellow green backlight LED
fabricated on a single PCB. Incorporating mask ROM-based character generator
and display data RAM in the controller LSI, the unit can efficiently display the
desired characters under microprocessor control.

2.1 General
• The LCD of the unit is STN (Super Twisted Nematic) Gray, Tran reflective type.
• Low power consumption with the dot-matrix LCD panel and CMOS LSI.Built-in
backlight LED with high luminance and stable radiation.
• Thin, lightweight design permits easy installation in a variety of equipment.
• Allowing for being connected at general-purpose CMOS signal level, the unit can be
easily interfaced to a microprocessor with common 4-bit and 8-bit parallel inputs and
• Multiplexing driving : 1/16duty, 1/4bias, 6 o’clock
• Built-in character generator ROM and RAM, and display data RAM:
 Character generator ROM
225 different 5 x 7 dot-matrix character patterns (Alphanumeric and symbols)
 Character generator RAM
8 different user programmed 5 x 7 dot-matrix patterns
 Display data RAM
80 x 8 bits
• Numerous instructions
Display clear, Cursor home, Display ON/OFF, Cursor ON/OFF, Blink character, Cursor
shift, Display shift.
• The unit operates from a single 5V power supply



2.2 Mechanical Characteristics

2.3 Absolute Maximum Ratings (Without LED backling)

2.4 Electrical Characteristics (Without LED backlight)

2.5 Optical Characteristics
2.6 Optical Characteristics

2.7 LED Backlight Characteristics

2.7.1 Absolute maximum ratings

2.7.2 LED Maximum Operating Range

3.1 Input signal Function

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply
EIA-232 voltage levels from a single 5-V supply. Each receiver converts EIA-232 inputs to 5-V
TTL/CMOS levels. These receivers have a typical threshold of 1.3 V and a typical hysteresis of
0.5 V, and can accept ±30-V inputs. Each driver converts TTL/CMOS input levels into EIA-232
levels. The driver, receiver, and voltage-generator functions are available as cells in the Texas
Instruments Lin ASIC library.


The eight NPN Darlington connected transistors in this family of arrays are ideally suited for
interfacing between low logic level digital circuitry (such as TTL, CMOS or PMOS/NMOS) and
the higher current/voltage requirements of lamps, relays, printer hammers or other similar loads
for a broad range of computer, industrial, and consumer applications. All devices Feature open–
collector outputs and freewheeling clamp diodes for transient suppression.
The ULN2803 is designed to be compatible with standard TTL families while the ULN2804 is
optimized for 6 to 15 volt high level CMOS or PMOS.

MAXIMUM RATINGS (TA = 25 C and rating apply to any one device in the
Package, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (TA = 25C, unless otherwise noted)
Output Characteristics

Representative Schematic Diagrams


1. General description
The P89V51RB2/RC2/RD2 is 80C51 microcontrollers with 16/32/64 kb flash and 1024 B of
data RAM.A key feature of the P89V51RB2/RC2/RD2 is its X2 mode option. The design
engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per
machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the
through put at the same clock frequency. Another way to benefit from this feature is to keep the
same performance by reducing the clock frequency by half, thus dramatically reducing the EMI.
The flash program memory supports both parallel programming and in serial ISP. Parallel
programming mode offers gang-programming at high speed, reducing programming costs and
time to market. ISP allows a device to be reprogrammed in the end product under Software
control. The capability to field/update the application firmware makes a wide range of
applications possible. The P89V51RB2/RC2/RD2 is also capable of IAP, allowing the flash
program memory to be reconfigured even while the application is running.

2. Features
• 5 V operating voltage from 0 MHz to 40 MHz
• 16/32/64 kB of on-chip flash user code memory with ISP and IAP
• Supports 12-clock (default) or 6-clock mode selection via software or ISP
• SPI and enhanced UART
• PCA with PWM and capture/compare functions
• Four 8-bit I/O ports with three high-current port 1 pins (16 mA each)
• Three 16-bit timers/counters
• Programmable watchdog timer
• Eight interrupt sources with four priority levels
• Second DPTR register
• Low EMI mode (ALE inhibit)
• TTL- and CMOS-compatible logic levels
• Brownout detection
• Low power modes
o Power-down mode with external interrupt wake-up
o Idle mode
• DIP40, PLCC44 and TQFP44 packages

Block diagram

Supply voltage.



Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance
inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during
accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also
receives the code bytes during Flash programming, and outputs the code bytes during program
verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled
low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order
address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled
low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external data
memories that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memories that use 8-bit addresses
(MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also
receives the high-order address bits and some control signals during Flash programming and

Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled
low will source current (IIL) because of the pullups. Port 3 also serves the functions of various
special features of the AT89C51 as listed below: Port 3 also receives some control signals for
Flash programming and verification.

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the

Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
Programming. In normal operation ALE is emitted at a constant rate of 1/6the oscillator
frequency, and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation
can be disabled by setting bit 0 of SFR locations 8EH. With the bit set, ALE is active only during
a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-
disable bit has no effect if the microcontroller is in external execution mode.

Program Store Enable is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to external data

External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH. Note,
however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be
strapped to VCC for internal program executions. This pin also receives the 12-volt
programming enable voltage (VPP) during Flash programming, for parts that require 12-volt

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.