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Sheet1

SODIMM
Pin Front Pin Back
1 VSS 2 VSS
3 DQ5 4 DQ4
5 VSS 6 VSS
7 DQ1 8 DQ0
9 VSS 10 VSS
11 DQS0_c 12 DM0_n/DBI0_n

13 DQS0_t 14 VSS

15 VSS 16 DQ6
17 DQ7 18 VSS
19 VSS 20 DQ2
21 DQ3 22 VSS
23 VSS 24 DQ12
25 DQ13 26 VSS
27 VSS 28 DQ8
29 DQ9 30 VSS
31 VSS 32 DQS1_c
33 DM1_n/DBI1_n 34 DQS1_t

35 VSS 36 VSS

37 DQ15 38 DQ14
39 VSS 40 VSS
41 DQ10 42 DQ11
43 VSS 44 VSS
45 DQ21 46 DQ20
47 VSS 48 VSS
49 DQ17 50 DQ16
51 VSS 52 VSS
53 DQS2_c 54 DM2_n/DBI2_n
55 DQS2_t 56 VSS

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Sheet1

57 VSS 58 DQ22

59 DQ23 60 VSS
61 VSS 62 DQ18
63 DQ19 64 VSS
65 VSS 66 DQ28
67 DQ29 68 VSS
69 VSS 70 DQ24
71 DQ25 72 VSS
73 VSS 74 DQS3_c
75 DM3_n/DBI3_n 76 DQS3_t
77 VSS 78 VSS

79 DQ30 80 DQ31

81 VSS 82 VSS
83 DQ26 84 DQ27
85 VSS 86 VSS
87 CB5/NC 88 CB4/NC
89 VSS 90 VSS
91 CB1/NC 92 CB0/NC
93 VSS 94 VSS
95 DQS8_c 96 DM8_n/DBI8_n
97 DQS8_t 98 VSS
99 VSS 100 CB6/NC

101 CB2,NC 102 VSS

103 VSS 104 CB7,NC


105 CB3/NC 106 VSS
107 VSS 108 RESET_n
109 CKE0 110 CKE1
111 VDD 112 VDD
113 BG1 114 ACT_n

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Sheet1

115 BG0 116 ALERT_n


117 VDD 118 VDD
119 A12 120 A11
121 A9 122 A7
123 VDD 124 VDD
125 A8 126 A5
127 A6 128 A4
129 VDD 130 VDD
131 A3 132 A2
133 A1 134 EVENT_n
135 VDD 136 VDD
137 CK0_t 138 CK1_t
139 CK0_c 140 CK1_c
141 VDD 142 VDD
143 Parity 144 A0
145 BA1 146 A10/AP
147 VDD 148 VDD
149 CS0_n 150 BA0
151 A14/WE_n 152 A16/RAS_n
153 VDD 154 VDD
155 ODT0 156 A15 CAS_n/
157 CS1_n 158 A13
159 VDD 160 VDD
161 ODT1 162 C0/CS2_n/NC
163 VDD 164 VREFCA
165 C1/CS3_n/NC 166 SA2
167 VSS 168 VSS
169 DQ37 170 DQ36
171 VSS 172 VSS
173 DQ33 174 DQ32
175 VSS 176 VSS
177 DQS4_c 178 DM4_n/DBI4_n
179 DQS4_t 180 VSS
181 VSS 182 DQ39
183 DQ38 184 VSS
185 VSS 186 DQ35

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Sheet1

187 DQ34 188 VSS


189 VSS 190 DQ45
191 DQ44 192 VSS
193 VSS 194 DQ41
195 DQ40 196 VSS

197 VSS 198 DQS5_c

199 DM5_n/DBI5_n 200 DQS5_t


201 VSS 202 VSS
203 DQ46 204 DQ47
205 VSS 206 VSS
207 DQ42 208 DQ43
209 VSS 210 VSS
211 DQ52 212 DQ53
213 VSS 214 VSS
215 DQ49 216 DQ48
217 VSS 218 VSS

219 DQS6_c 220 DM6_n/DBI6_n

221 DQS6_t 222 VSS


223 VSS 224 DQ54
225 DQ55 226 VSS
227 VSS 228 DQ50
229 DQ51 230 VSS
231 VSS 232 DQ60
233 DQ61 234 VSS
235 VSS 236 DQ57
237 DQ56 238 VSS
239 VSS 240 DQS7_c

241 DM7_n/DBI7_n 242 DQS7_t

243 VSS 244 VSS

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245 DQ62 246 DQ63


247 VSS 248 VSS
249 DQ58 250 DQ59
251 VSS 252 VSS
253 SCL 254 SDA
255 VDDSPD 256 SA0
257 VPP 258 Vtt
259 VPP 260 SA1

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Sheet1

DIMM
Pin Front Pin Back
1 12 V, NC 145 12 V, NC
2 VSS 146 VREFCA
3 DQ4 147 VSS
4 VSS 148 DQ5
5 DQ0 149 VSS
6 VSS 150 DQ1
DTMD0Q_Sn9,
7 _Dt,B ID0Q_nS,9 151 VSS
_Nt,C
8 TDQS9_cN, CD 152 DQS0_c
QS9_c,
9 VSS 153 DQS0_t
10 DQ6 154 VSS
11 VSS 155 DQ7
12 DQ2 156 VSS
13 VSS 157 DQ3
14 DQ12 158 VSS
15 VSS 159 DQ13
16 DQ8 160 VSS
17 VSS 161 DQ9
TDDMQ1S_1n0,
18 _Dt,B ID1Q_nS,1 162 VSS
0N_Ct ,
19 DTQDSQ1S0_1c0,_ 163 DQS1_c
cN, C
20 VSS 164 DQS1_t
21 DQ14 165 VSS
22 VSS 166 DQ15
23 DQ10 167 VSS
24 VSS 168 DQ11
25 DQ20 169 VSS
26 VSS 170 DQ21
27 DQ16 171 VSS
28 VSS 172 DQ17

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Sheet1

TDDMQ2S_1n1,
29 _Dt,B ID2Q_nS,1 173 VSS
1N_Ct ,
30 DTQDSQ1S1_1c1,_ 174 DQS2_c
cN, C
31 VSS 175 DQS2_t
32 DQ22 176 VSS
33 VSS 177 DQ23
34 DQ18 178 VSS
35 VSS 179 DQ19
36 DQ28 180 VSS
37 VSS 181 DQ29
38 DQ24 182 VSS
39 VSS 183 DQ25
TDDMQ3_Sn1,2
40 D_tB, ID3_QnS41, 184 VSS
2N_tC,
DTQDSQ12S_1c2,_
41 cN, C 185 DQS3_c
42 VSS 186 DQS3_t
43 DQ30 187 VSS
44 VSS 188 DQ31
45 DQ26 189 VSS
46 VSS 190 DQ27
47 CB4, NC 191 VSS
48 VSS 192 CB5, NC
49 CB0, NC 193 VSS
50 VSS 194 CB1, NC
TDDMQ8S_1n7,
51 _Dt,B ID8Q_nS,1 195 VSS
7N_Ct ,
DTQDSQ17S_1c7,_
52 cN, C 196 DQS8_c
53 VSS 197 DQS8_t
54 CB6, NC 198 VSS
55 VSS 199 CB7, NC
56 CB2, NC 200 VSS
57 VSS 201 CB3, NC

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Sheet1

58 RESET_n 202 VSS


59 VDD 203 CKE1, NC
60 CKE0 204 VDD
61 VDD 205 RFU
62 ACT_n 206 VDD
63 BG0 207 BG1
64 VDD 208 ALERT_n
65 A12/BC_n 209 VDD
66 A9 210 A11
67 VDD 211 A7
68 A8 212 VDD
69 A6 213 A5
70 VDD 214 A4
71 A3 215 VDD
72 A1 216 A2
73 VDD 217 VDD
74 CK0_t 218 CK1_t
75 CK0_c 219 CK1_c
76 VDD 220 VDD
77 VTT 221 VTT
78 EVENT_n 222 PARITY
79 A0 223 VDD
80 VDD 224 BA1
81 BA0 225 A10/AP
82 RAS_n/A16 226 VDD
83 VDD 227 RFU
84 CS0_n 228 WE_n/A14
85 VDD 229 VDD
86 CAS_n/A15 230 NC, SAVE_n
87 ODT0 231 VDD
88 VDD 232 A13
89 CS1_n, NC 233 VDD
90 VDD 234 NC, A17
91 ODT1, NC 235 NC, C2
92 VDD 236 VDD
93 C0, CS2_n, NC 237 NC, CS3_n, C1

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Sheet1

94 VSS 238 SA2


95 DQ36 239 VSS
96 VSS 240 DQ37
97 DQ32 241 VSS
98 VSS 242 DQ33
TDDMQ4S_1n3,
99 _Dt,B ID4Q_nS,1 243 VSS
3N_Ct ,
TDQS13_cN, CD
100 QS13_c, 244 DQS4_c
101 VSS 245 DQS4_t
102 DQ38 246 VSS
103 VSS 247 DQ39
104 DQ34 248 VSS
105 VSS 249 DQ35
106 DQ44 250 VSS
107 VSS 251 DQ45
108 DQ40 252 VSS
109 VSS 253 DQ41
TDDMQ5S_1n4,
110 _Dt,B ID5Q_nS,1 254 VSS
4N_Ct ,
TDQS14_cN, CD
111 QS14_c, 255 DQS5_c
112 VSS 256 DQS5_t
113 DQ46 257 VSS
114 VSS 258 DQ47
115 DQ42 259 VSS
116 VSS 260 DQ43
117 DQ52 261 VSS
118 VSS 262 DQ53
119 DQ48 263 VSS
120 VSS 264 DQ49
TDDMQ6S_1n5,
121 _Dt,B ID6Q_nS,1 265 VSS
5N_Ct ,
TDQS15_cN, CD
122 QS15_c, 266 DQS6_c

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Sheet1

123 VSS 267 DQS6_t


124 DQ54 268 VSS
125 VSS 269 DQ55
126 DQ50 270 VSS
127 VSS 271 DQ51
128 DQ60 272 VSS
129 VSS 273 DQ61
130 DQ56 274 VSS
131 VSS 275 DQ57
TDDMQ7S_1n6,
132 _Dt,B ID7Q_nS,1 276 VSS
6N_Ct ,
TDQS16_cN, CD
133 277 DQS7_c
QS16_c,
134 VSS 278 DQS7_t
135 DQ62 279 VSS
136 VSS 280 DQ63
137 DQ58 281 VSS
138 VSS 282 DQ59
139 SA0 283 VSS
140 SA1 284 VDDSPD
141 SCL 285 SDA
142 VPP 286 VPP
143 VPP 287 VPP
144 RFU 288 VPP

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Sheet2

Symbol Type
Ckx_t
Input
Ckx_c

CKEx Input

Csx_n Input

Cx Input

ODTx Input

ACT_n Input

RAS_n/A16
CAS_n/A15 Input
WE_n/A14

Bgx Input

Bax Input

Ax Input

A10/AP Input

A12/BC_n Input

Parity Input

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Sheet2

Sax Input

SCL Input
CMOS
RESET_n
Input

DQx, Cbx I/O

DQSx_t
I/O
DQSx_c

DM_n/DBI_n
TDQS_t
(DMU_n,
I/O
DBIU_n),
(DML_n/
DBIL_n)

SDA I/O

ALERT_n Output

EVENT_n
Output
Output

TDQS_t
TDQS_c (x8
Output
DRAM-based
RDIMM only)

VDD Supply
VPP Supply
VREFCA Supply
VSS Supply
VTT Supply
VDDSPD Supply
RFU -
NC -

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Sheet2

Function
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
device input buffers and output drivers. Taking CKE LOW provides Precharge Power- Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become
stable during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-
down. Input buffers, excluding CKE, are disabled during Self-Refresh
Chip Select: All commands are masked when CS-n is registered HIGH. CS_n provides for
external Rank selection. CS_n is considered part of the command code.
Chip ID : Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of
stacked component. Chip ID is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,
DQS_c, TDQS_t and TDQS_c signal. The ODT pin will be ignored if MR1 is programmed to
disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along
with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as
Row Address A16, A15 and A14
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
command being entered. Those pins have multi function. For example, for activation with
ACT_n Low, these are Addresses like A16, A15 and A14 but for non-activation command
with ACT_n High, these are Command pins for Read, Write and other command defined in
command truth table
Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or
Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
additional functions. See other rows. The address inputs also provide the op-code during
Mode Register Set commands. A17 is only defined for 16 Gb x4 SDRAM configurations.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether


Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst
chop (on-thefly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See
command truth table for details.
Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with
MR setting. Once it’s enabled via Register in MR5, then SDRAM calculates Parity with
ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity
should be maintained at the rising edge of the clock and at the same time with command &
address with CS_n LOW

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Sheet2

Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address
range on the I2C bus.
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to
and from the temperature sensor/SPD EEPROM on the I2C bus.
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when
RESET_n is HIGH. RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC
code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal
Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data
sheets to determine which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS_t is paired with differential signals DQS_c,
respectively, to provide differential pair signaling to the system during reads and writes.
DDR4 SDRAM supports differential data strobe only and does not support single-ended.
Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input
data is masked when DM_n is sampled LOW coincident with that input data during a write
access. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by
the mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or
TDQS is enabled by the mode register A11 setting in MR1. DBI_n is an input/output
identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data will be
stored/ output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH.
TDQS is only supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or
EEPROM/TS combo device.
Alert: It has multi functions such as CRC error flag, Command and Address Parity error flag
as Output signal. If there is error in CRC, then ALERT_n goes LOW for the period time
interval and goes back HIGH. If there is error in Command Address Parity Check, then
ALERT_n goes LOW for relatively long period until ongoing SDRAM internal recovery
transaction is complete. During Connectivity Test mode this pin functions as an input.
Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded. This pin has no function (NF) on modules
without temperature sensors.
Termination data strobe: When enabled via the mode register, the DRAM device enables
the same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and
DQS_c. When the TDQS function is disabled via the mode register, the DM/TDQS_t pin
provides the data mask (DM) function, and the TDQS_c pin is not used. The TDQS function
must be disabled in the mode register for both the x4 and x16 configurations. The DM
function is supported only in x8 and x16 configurations. DM, DBI, and TDQS are a shared
pin and are enabled/disabled by mode register settings. For more information about TDQS,
see the DDR4 DRAM component datasheet (TDQS_t and TDQS_c are not valid for
UDIMMs).
Module power supply: 1.2V (TYP).
DRAM activating power supply: 2.5V –0.125V / +0.250V.
Reference voltage for control, command, and address pins.
Ground.
Power supply for termination of address, command, and control VDD/2
Power supply used to power the I2C bus for SPD
Reserved for Future Use: No on DIMM electrical connection is present
No Connect: No on DIMM electrical connection is present

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