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7, December 2010
Abstract - Ultra low-power applications have threshold operation is applicable to wide range of
gained a lot of attention in recent years. This is due applications ranging from wireless devices,
to the increase in battery operated devices and also biomedical applications, spacecraft applications etc.
due to the scaling of CMOS devices. Various CMOS Lowering supply voltage to reduce power
circuits of low-leakage are in demand one of them is consumption is one of the choice of the designers for
the SRAM. So, at the present scenario various designing low leakage SRAM circuits. However ultra
technologies are used to design the low leakage low power design of high density SRAMs in which
SRAM. The low leakage SRAM are of prime the operating voltage is below the transistor sub-
concerned as 30% of the total chip consumption is threshold is extremely challenging. In modern SoCs
due to memory circuits. This paper deals with the where total power and total area is dominated by
various device & circuit design challenges to memory circuits reductions in Vdds for them
optimize the low leakage SRAM with various design (memory circuits) can have low leakage power [26].
methodologies and circuit topologies for optimal low Also by the system integration point of view, SRAM
power operations. This paper identifies the suitable must be compatible with sub-threshold combinational
candidates for low leakage SRAM for ultra low logic, operating at ultra low voltages. Ultra-Dynamic
power applications at device and circuit levels and Voltage Scaling (U-DVS) is another approach to
provides an effective road-map for SRAM designers reduce energy consumption by adjusting the system
to work with its ultra-low power applications. supply voltage over a large range, depending on the
performance requirement. U-DVS is suitable for
systems with time-varying throughput constraint.
Key Words – Ultra-Low Power, CMOS Scaling,
Leakage Power, Static Noise Margin. This paper is organized as follows; the scope of
the low leakage SRAM for ultra low power
application is presented in section II. Various
I. INTRODUCTION challenging issues of the current and the future
SRAM cell is reviewed in section III. Section IV
In recent years the demand for low power devices present various device level optimization
has been increases tremendously. This demand may methodologies for low leakage SRAM. Section V
be due to fast growth of battery operated portable shows the various circuit topologies for low leakage
applications such as PDAs, cell phones, laptops & SRAM cell for ultra low power applications. Finally
other handheld devices. But also at the same time conclusion is drawn in section VI.
problems arising from continuous technology scaling
have recently made power reduction an important
design issue for the digital circuits and applications. II. SCOPE OF LOW LEAKAGE SRAM FOR ULTRA
The increased importance of power is even more LOW POWER APPLICATIONS
noticeable for a new class of energy constrained
Besides the quadratic dynamic power savings,
systems. Recent interest is in operating the CMOS
very low supply voltages promise greatly reduced
circuits with power supply voltage below the
leakage power. For example, a 1-V reduction in the
transistor threshold operation [33]. As sub-threshold
supply voltage can reduce Ioff the transistor leakage
circuits can allow ultra low power designs to be
current, by over one decade due to the drain-induced
fabricated on modern process technology. Sub-
barrier-lowering (DIBL) effect. The gate oxide
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
leakage can also be reduced more than 100x with the The on-chip temperature gradients induced by
same 1-V drop in supply voltage. imbalanced switching activity are therefore typically
small across the die of a low-voltage integrated
Various low leakage applications for ultra-low power circuit. Die temperature fluctuations due to the
operations are, variations in the ambient temperature however can
cause significant fluctuations in the speed and the
A. Energy-constrained applications such as wireless power characteristics of ultra low-voltage circuits.
sensor nodes, RFID tags, medical equipments such as
hearing aids and pace-maker, wearable computing or B. Power Overhead associated with Change in
implants, Personal digital assistants, energy Supply Voltage:
scavenging applications, and Laptops, which are
dominated primarily by the need to minimize energy Power overhead associated with changing the
consumption and increase battery life time, speed is a supply voltage level should at least be compensated
secondary consideration for this class of applications, by the energy savings in the low-voltage mode. So,
understanding the energy required to change the
so sub-threshold circuits offer a good solution [13].
supply voltage level is necessary as energy overhead
is a fundamental issue and cannot be avoided.
B. Battery-powered handheld systems have been
faster than other integrated circuit applications such C. Effect of Transistor Mismatch:
as cell phones, MP3 players, and portable games. All
benefits from increased battery life, with lowering The main challenge for low-voltage operation is
integrated circuit (IC) power dissipation are provided. that relative sizing of transistors is a weak knob due
In modern system-on-chip (SoC) devices, some to the exponential dependence of drive current on
components, such as digital signal processors and threshold voltage in sub-threshold region. The basic
microprocessors, must operate at high frequencies, at and most important building block of a traditional
least intermittently. Many components do not need to SRAM, 6T bit-cell is a ratioed structure and its
run as fast, but must be integrated on the same high- correct operation depends on relative strength of its
transistors. Fig.1 shows the effect of access transistor
performance silicon die. Additionally, some
drive strength on Write Margin (WM) distribution for
applications require a small subset of the circuits to a 6T SRAM cell at different supply voltages.
operate continuously, e.g., real-time clocks and
wakeup circuitry.
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
The degradation in Ion/Ioff from 107 The reason for the diminishing sensitivity of the
approximately to 104 implies that, in sub-Vt , there is read static noise margin to the transistor sizes at
a strong interaction between the “on” and the “off” scaled supply voltages is identified. The switching
devices when it comes to setting the voltage level of current at ultra-low voltage is the sub-threshold
critical signals. This introduces a relevant failure leakage current. The sub-threshold leakage current
mechanism where SRAM density requirements call produced by a MOSFET is [7].
for the integration of many devices on shared nodes
[13].
E. SER (Soft Error Rate)
An issue for deeply voltage scaled SRAM is soft Where, Ileak, µ, Weff, COX, Leff, Vt, VT, VGS, VDS, and
error rate (SER). Soft errors occur when an alpha n are the sub-threshold leakage current, carrier
particle or cosmic ray strikes a memory node and mobility, effective transistor width, oxide capacitance
causes data loss. Since, bitcell storage capacitance per unit area, effective channel length, threshold
decreases with scaling and voltage scaling further voltage, thermal voltage, gate-to-source voltage,
reduces the stored charge, SER is a concern for sub-
drain-to-source voltage, and sub-threshold swing
threshold memory [33].
coefficient, respectively. For devices operating in the
F. Cell Stability weak inversion region, the switching current is
exponentially dependent on the voltage levels [15,
Static Noise Margin (SNM) is the maximum 16]. Alternatively, increasing the device width
amount of noise that is tolerated at the data storage produces only a linear increase in the switching
nodes of an SRAM cell. The voltage transfer current. A linear change in the sub-threshold
characteristics (VTC) of two cross-coupled inverters switching current has a relatively small impact on the
are shown in Fig.2. The resulting curve is called the voltage transfer characteristics. The sensitivity of the
‘‘butterfly curve’’. The SNM is the length of the read noise margin to the memory cell ratio is
largest square that can be embedded inside the lobes
therefore negligible in an ultra-low supply voltage,
of a butterfly curve, as illustrated in Fig.2.
i.e., sub-threshold memory circuit.
7. Device Scaling:
In this technique, the NMOS or PMOS transistors in (g). Active/Passive Clamped Transistor Scheme
the selected sub array are dynamically switched from
zero body bias to forward body bias. Forward body- (i). Passive clamped transistor scheme:
biasing (FBB) has proven to effectively improve
A passive clamped bias design uses digitally
performance, suppress short channel effects, and programmable transistors which are used to set the
reduce variations, roll-off. The drain-induced barrier virtual ground voltage during standby. This
lowering (DIBL) which limits scalability of channel programming has to set for worst case, ie, maximum
length can also be relieved by FBB during the normal SRAM leakage under process variation conditions.
operation of the device. As alone this technique does As aging can change the device on and off
not reduce the gate current but along with super high characteristics so this makes a passive clamp
Vt it is able to do so [10]. transistor scheme less effective in reducing cache
leakage power [11].
(i). Forward Body Biasing with Super High Vt
(ii). Active Clamped Transistor Scheme
Here, the device optimization is achieved using
super halo 2-D doping profile. This profile uses a non There are various actively clamped bias schemes
uniform P+ doping profile in the source body and which minimize the standby power of the memory.
drain body boundaries to reduce the source drain One of them is using replica cell bias generator to
depletion width and effectively suppresses the body derive the gate voltage of the bias device. This
punch through. The Vth roll and DIBL are also scheme tracks the process variations in Vss value.
controlled by 2D halo doping profile. The high Vt The other proposed scheme is a linear voltage
doping profile is generated by raising the halo doping regulator which is used to derive the Vss to a given
concentration of the nominal Vt device.FBB is programmable Vmin value. This results in excellent
dynamically applied to only the active portion of the PVT and aging tracking but if see the other side it
cache for fast read and write operation. The two- results in larger penalties of area and dynamic power
dimensional (2-D) halo doping profile of a super high overhead to switch between active and standby
device to achieve total leakage reduction, while voltage levels [32].
suppressing the gate leakage and junction band-to- A new scheme is proposed in which a combined
band tunneling (JBTBT) leakage. In this scheme distributed sleep and active clamp scheme is used
using a super high device and FBB is used to which incurred less than 3 % are overhead and active
dynamically reduce the active leakage in cache clamping has 14% less leakage than for passive bias
memories. and sleep transistors. It helps in reducing the leakage
The only limitation is that the technology where power of idle sub-arrays by 30-60% at 0.8-1.0 V
higher halo doping is unacceptable, a super high Vt standby. A 256kb dual Vcc SRAM has been
device can be built using a gate material with a simulated which operated between 2.3-4.2GHz with
higher flatband voltage. The simulation results shows 16-29mw total power consumption at 85oC. It has
that a 32X 32 sub-array of SRAM is designed and fixed 1.2 fixed Vlcc and 0.7-1.2 Vcore [15].
simulated at 70nm technology in which total 64%
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
Another approach is using the combination of would cause a large voltage difference between the
FBB with Vt using 2D super halo technique and CVdd and the Vdd [18].
Active clamped transistor. This approach is used so
that FBB technique is used for fast operation and In order to further improve the Vddmin, an
clamped transistors with high Vt is used to reduce the adaptive CVdd voltage regulator, which generates a
leakage [10]. desired offset with respect to Vdd, is proposed. In
this mechanism a dual rail Vdd is used to generate
logic Vdd and cell Vdd, so that logic Vdd is reduced
to 0.6V. The Vddmin is lowered and also the area
(2). High-K Metal Gate Technology required has been reduced. This technique is also
extendable to new process technologies upto 32nm.
In this proposed technology the “high-k" (Hi-k)
But it degraded the SNM as when the Vdd is scaled
material is used to replace the transistor's silicon
down ,the offset voltage is increased due to which the
dioxide gate dielectric, and new metals to replace the
SNM degrades [18].
polysilicon gate electrode of NMOS and PMOS
transistors. These new materials, along with the right
process recipe, reduce gate leakage more than 100-
fold, while delivering record transistor performance.
Along with this PMOS FBB technique is used for
lower voltages. The stronger PMOS under the FBB
can improve the minimum operating voltage up to 75
mV. This improvement is achieved without
increasing the overall SRAM leakage power, since
the Nwell is restored back to Vcc after the WL
(wordline) is turned off. The active power
consumption per access due to dynamically
discharging and charging the Nwell is less than 1% of
the total access power, where significant portion of
the active power during cache access is from signal
and clock distributions. The leakage current is Fig.9 Maximum Offset Voltage Limitation versus Different
reduced by 10x. The operating frequency of 153 Mb Process Generations [18]
SRAM using this technology at 45nm is 2.7 GHz at
0.9V and 3.8 GHz at 1.1V.The limitation is that it Fig.9 shows the maximum offset voltage
degraded the write margin [17]. limitation versus different process generations. It
shows that the maximum offset voltage is getting
(3). Dual Rail Mechanism
lower as the device shrinks from 65 nm to 32 nm
Several design solutions for Vdd minimum issues technology nodes. That is because the SNM is also
were proposed for the single rail at 65 nm and 45 nm getting lower as the device scales down. This trend
SRAM. The suppressed word-line (WL) scheme was will also make the proposed Vdd-tracking CVdd
reported to address the bit cell SNM issue caused by concept more attractive in the future technology
the ever increasing device variations in the shrinking nodes. 1 Mb SRAM is tested and the area has been
devices. This scheme can improve the SNM, but it reduced to 5%. Vdd is 0.74V-0.9V and Vddmin of
causes an unacceptable cell current degradation in the 0.6 V is achieved.
lower Vdd regime. The cell current degradation, in (4). Low Vdd Operation and Increase in the Vth
turn, becomes the limiter of Vddmin. The area is Scheme
increased to maintain an acceptable cell current. To
avoid this area penalty, dual-rail SRAM designs in 65 For high speed applications and low Vdd
nm were proposed. The dual-rail design with a operation, a new scheme is used in which the Vth of
dedicated SRAM power source, Cell-Vdd (CVdd), the has been increased. The supply voltage, ie, Vdd
can achieve a lower Vddmin, but the challenge lies in has been reduced to 0.5V and the access time is also
the large current consumption of the CVdd power reduced to 20ns when a 64 kb SRAM is simulated at
source. The large CVdd current implies large areas 90nnm technology. But at lower voltages of Vdd
which are needed to implement numerous CVdd write operation cannot be performed and also leakage
voltage regulators, and wider power lines to mitigate current of PMOS transistors results in storage
the CVdd IR-drop issue. IR drop constraints as well destructions [20].
as the area penalty results from the power routing.
However, fixing the CVdd voltage level would limit (5). Dual Boosting Scheme
the Vddmin reduction because scaling down the Vdd
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
In this scheme internally boosting of the voltage shorter BL arrays. The cascaded bit line scheme
level of the word line and cell power node is done minimizes the area penalty. It also realizes read and
which increases the driving capability of the NMOS write operation without global lines. It is useful for
access transistor during read operation and reduces low voltage operation [23].
the bit line delay because of Icell increases during
this operation. It increases the Read SNM and write (10). Uni-axial Si Strained Technology
SNM at low voltages. The operating frequency is 50
In this technique, the uni-axial Si strained
MHz but it has been observed that it results in
technology, the nitride films are deposited on Si to
overhead of area and power. It has been observed that
act as the contact etch stop layer (CESL). In this 65
during the simulation of 256kb SRAM the area
nm process, strong uniaxial tensile strain is created
overhead is 4.5% due to cell boosting and reduction
by the nitride layer in order to increase NMOS
in chip cycle by 26% at the expense of 14.6%
mobility. The amount of strain increases with the
additional power. The cell ratio is also of prime
thickness of the nitride layer that can fill between the
concern which is kept one. [23, 26].
gates and the amount of contact of the nitride film
(6). Novel Write Mechanism with the source/drain region. The 65 nm strained
silicon technology improves transistor
In this scheme a write mechanism is proposed performance/leakage tradeoff, which is essential to
which depends only on one of the 2 bit lines to achieve fast SRAM access speed at substantially low
perform the write operation. Transistor sizing is also operating voltage and standby leakage. The 1 Mb
of prime concerned in this mechanism for cell SRAM macro features a 0.667 µm2 low-leakage
stability. It also uses the sleep transistors but the memory cell and can operate over a wide range of
overall leakage power is slightly higher than supply voltages from 1.2 V to 0.5 V. It achieves
conventional SRAM and the cache are is also operating frequency of 1.1 GHz and 250 MHz at 1.2
increased by 12.25 % from the conventional SRAM. V and 0.7 V, respectively. This technology has been
A trade off is maintained between the SNM and the successful for future process technologies also [14].
leakage power. As high Vt PMOS are used which
helps in reducing the leakage but reduces the SNM The above techniques are used to reduce the
[21, 28, 32]. leakage and increase the stability of the cell. But
there are other technique which depends on the
(7). Sense Amplifier Redundancy Mechanism number of transistors in a SRAM cell to increase the
stability and reduce the leakage.
Here, a charge pump is used to resolve the zero
leakage read buffer footer. A high density 8T SRAM (11). Gate Feedback Memory Cell
is simulated with minimum operating voltage of
350mV. But speed is of concern in this technique In this scheme a gate feedback memory cell is
which decreases. Also the cell stability is decreased used for SRAM in which the decoder circuits is
[29]. separated from read circuits. The power consumption
was low, 0.83µw dynamic power consumption and
(8). Dual Vth & Dual Tox Scheme 0.197 µw static power consumption while simulating
a 512x13 bit SRAM memory cell at 130nm. The
In this scheme different combinations of limitation was that it has almost vanishing read
transistors with dual Vth and dual Tox have been stability at low voltages and also speed was the
used to design the various 6T SRAM cells. It reduces limitation [13].
both sub-threshold and gate tunneling leakage
current. This technique is useful in increasing the (12). Stacking Effect
SNM also. Various combinations have been observed
to have the best results [35]. In this scheme half stacking and full stacking
effects is used to design a conventional 6T SRAM
(9). Self Write Back Sense Amplifier Scheme cell for low leakage reduction. There is drastic
change in power consumption in full stack effect but
Self write back sense amplifier is used with the main limitations are area overhead and SNM
capacitance separator. In it a cascaded bit line scheme degraded. At 130 nm the results are fine but as the
is used as the access time of the proposed scheme is gate length is reduced power consumption also
proportional to the number of sense amplifiers. It is increases. It has been shown that the stacking of two
preferred for low SRAM macros. The proposed off transistors can significantly reduce leakage power
scheme is advantageous for smaller macro, for bit than a single off transistor [37]. Increasing the source
capacity is less than 256 kb the timing margin for voltage of NMOS transistor reduces sub-threshold
sense amplifier enable signal is unnecessary for leakage current, exponentially due to negative Vgs,
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
lowered signal rail, reduced DIBL and body effect. V2 remains large even when access MOS transistor
This effect is also called self-reverse biasing of N3 is turned on and Node V1 voltage increases.
transistor the self-reverse bias effect can be achieved
by turning off a stack of transistors. Turning off more
than one transistor in a stack raises the internal
voltage (source voltage) of the stack, which acts as
reverse biasing the source. The voltages at the
internal nodes depend on the input applied to the
stack [16].
The circuit schematic of the 7T dual-Vt SRAM Fig.14 8T SRAM Cell [36]
cell with transistors sized for a 65nm CMOS
technology is shown in Fig.13. The cross-coupled The read bitline (RBL) is conditionally
inverters formed by the transistors N1, P1, N2, and discharged based on the data stored in the SRAM
P2 store a single bit of information. The write bitline cell. The storage nodes (Node1 and Node2) are
WBL and the pass transistor N3 are used for completely isolated from the bitlines during a read
transferring new data into the cell [36]. operation. Data stability is thereby significantly
enhanced as compared to the standard 6T SRAM
Alternatively, the read bitline RBL and the cells [29].
transistor stack formed by N4 and N5 are used for
reading data from the cell. Two separate control (4). 9T SRAM Cell
signals R and W are used for controlling the read and
the write operations, respectively, with the 7T SRAM The schematic of the 9T SRAM cell, with
circuit as shown in Fig. 13. transistors sized for a 65-nm CMOS technology, is
shown in Fig. 15. The upper sub-circuit of the 9T
memory circuit is essentially a conventional 6T
SRAM cell with minimum sized devices (composed
of N1, N2, N3, N4, P1, and P2).
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
Node2, BL and BLB are charged and discharged, virtual supply voltage rail Vdd. Write access to the
respectively. A “0” is forced onto Node2 through N4. bitcell occurs through the write access transistors, M2
and M5, Transistors from the write bitlines, BL and
During a read operation, RD signal transitions high BLB. Transistors M7 through M10 implement a
while WR is maintained low. The read access buffer used for reading. Read access is single-ended
transistor N7 is activated. Provided that Node1 stores and occurs on a separate bitline, RBL, which is
“1”, BL is discharged through N5 and N7. precharged to prior to read access. The wordline for
Alternatively, provided that Node2 stores “1”, the read also is distinct from the write wordline. One key
complementary bitline (BLB) is discharged through advantage to separating the read and write wordlines
N6 and N7. Since N3 and N4 are cutoff, the storage and bitlines is that a memory using this bitcell can
nodes Node1 and Node2 are completely isolated from have distinct read and write ports.
the bitlines during a read operation [36].
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Amplifier and Cascaded Bit Line Scheme, , Solid-State Circuits,
IEEE Journal ,vol. 44 , no. 4, April.2009, pp.1192-1198.
24.Rajshekhar Keerthi,Henry Chen, “Stability and Static Noise Neeraj Kr. Shukla (IEEE, IACSIT,IAENG, IETE, IE, CSI,
margin analysis of low power SRAM”IEEE International ISTE), a Ph.D. Scholar at the UK Technical University, Dehradun
Instrumentation & Measurement Technology Conference, Victoria (Uttarakhand) India.He is an Asst. Professor in the Department of
Canada, May 2008,pp-1541-1544. Electrical, Electronics & Communication Engineering, ITM
25. Farshad Moradi etal. “65nm Sub threshold 11 T SRAM for University, Gurgaon, (Haryana) India. He has received his
ultra low voltage Application, IEEE xplore, 2008, pp-113-117. M.Tech. (Electronics Engineering) and B.Tech. (Electronics &
26. Yeonbae Chung ,Seung-Ho Song , “Implementation of low- Telecommunication Engineering) Degrees from the J.K. Institute
voltage static RAM with enhanced data stability and circuit speed”, of Applied Physics & Technology, University of Allahabad,
Microelectronics Journal vol. 40, Issue 6, June 2009, pp. 944-951. Allahabad (Uttar Pradesh) India in the year of 1998 and 2000,
27. Peter Geens ,WIm Dehaene, “A dual port dual width 90nm respectively. His main research interests are in Low-Power Digital
SRAM with guaranteed data retention at minimal standby supply VLSI Design and its Multimedia Applications, Open Source EDA,
voltage”, 34th European Solid-State Circuits Conference, 2008. and RTL Design.
ESSCIRC 2008.pp-290-293.
28. Naveen verma, Anantha P. Chandrakasan ,”A reconfigurable R.K. Singh (IAENG, ACEEE, IE, ISTE), Professor in the
65nm SRAM achieving voltage scalability from 0.25 v-1.2V & Department of Electronics & Communication Engineering, VCT-
performance scalability from 20Khz-200Mhz, 34th European Kumaon Engineering College, Dwarahat, Almora (UK) India. He
Solid-State Circuits Conference, 2008. ESSCIRC 2008, pp-282- is being honored with the Ph.D. in Electronics Engineering in the
285. Year 2003 from the University of Allahabad, Allahabad (Uttar
29. Naveen verma, Anantha P. Chandrakasan, “A 256kb 65nm 8T Pradesh), India. He has received his M.E. (Electronics & Control
Sub-threshold SRAM Employing Sense-Amplifier Redundancy”, Engineering) in 1992 from BITS, Pilani and B.E. (Electronics &
Solid-State Circuits, IEEE Journal, vol. 43, no. 1, Jan 2008, Communication Engineering) in 1990 from Marathawada
pp.141-150. University, India. He has authored several text-books in the field of
30. Chang, L. Montoye, R.K. Nakamura, Y.Batson, VLSI Design, Basic Electronics, and Opto-Electronics. He has
K.A.Eickemeyer, R.J.Dennard, R.H. Haensch, W.Jamsek, D, “An worked at various capacities as, the Principle, Kumaon
8T-SRAM for Variability Tolerance and Low-Voltage Operation Engineering College, Dwarahat in the year 2003-04, Director (O),
in High-Performance Caches”, Solid-State Circuits, IEEE Journal Directorate of Technical Education, Uttaranchal in the year 2005,
vol. 43, April 2008, Issue 4, pp-956-963. and Joint Director, State Project Facilitation Unit, Dehradun for the
31. Jawar Singh,Dhiraj K.Pradhan et al, ” A single ended 6T World Bank TEQIP Project. He is also the recipient of couple of
SRAM cell design for ultra low voltage applications”,IEICE prestigious awards, e.g., Rastriya Samman Puruskar, Jewel of India
Electronic Express,2008,pp-750-755. Award, Rastriya Ekta Award, Life Time Achievement Award, and
32.Sinangil M., Naveen Verma, A.P.Chandrakasan , “A Arch of Excellence Award. His current areas of interest are VLSI
Reconfigurable 8T Ultra –Dynamic Voltage Scalable( U-DVS ) Design, Opto-Electronics and its applications.
SRAM in 65nm CMOS” , Solid-State Circuits, IEEE Journal ,vol.
44 , no. 11, Nov.2009, pp.3163-3173. Manisha Pattanaik (WSEAS, IE, ISTE) has been honored the
33.Benton H. Calhoun Anantha P. Chandrakasan “A 256-kb 65- Ph.D. from Indian Institute of Technology (IIT) Kharagpur, (West
nm Sub-threshold SRAM Design for Ultra-Low-Voltage Bengal) India in the field of VLSI Design from the Department of
Operation”, Solid-State Circuits, IEEE Journal vol. 42, March Electronics and Electrical Communication Engineering in the year
2007, Issue 3 , pp.680-688. 2004. Currently she is an Assistant Professor (VLSI Group) at
34. Sherif A.Tawfik, Volkan Kursun, “Stability Enhancement ABV-India Institute of Information Technology & Management
Techniques for Nanoscale SRAM ciruits, International SOC design (ABV-IIITM), Gwalior, (Madhya Pradesh), India. She has been
Conefrence, 2008, pp 113-116. awarded various scholarships, e.g., National Scholarships, Merit
35. Behnam Amelifard et al. “Reducing the Sub threshold and gate Scholarships and MHRD Fellowships. She shared the
tunneling leakage of SRAM cells using dual Vt and Dual Tox responsibility in the capacity of referee for IEEE International
assignment”, Fujitsu labs of America,2008. Conferences on VLSI Design for two consecutive years, 2003-04.
36.Zhiyu Liu, Volkan Kursun, “ Characterization of a novel Nine Her areas of interest are Leakage Power Reduction of Nano-Scale
Transistor SRAM cell,IEEE Transactions on Very Large Scale CMOS Circuits, Characterization of Logic Circuit Techniques for
Integration Systems,vol.46, Issue 4,April 2008.pp-488-492. Low-Power/Low-Voltage and High performance analog & digital
37. Narendra, S.Borkar, V. De, D.Antoniadis and VLSI applications and CAD of VLSI Design.
A.Chandrakasan,“Scaling of Stack Effect and its Application for
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