Analogue Control Loop

Chapter 44
44.1 Input Interface
44.2 Input Scaling
44.3 Filtering
44.4 PID Control
44.5 Output Scaling
44.6 Output Interface
44.7 Nomenclature

This chapter explains how a typical analogue con-
trol loop is realised by means of computer control.
A simple level control loop with a tag no LRC 47
is considered. The signal is followed from the level
transmitter,through the system and back out to the
control valve. Both hardware and software aspects
are covered. An explanation of the structure of the
database is deferred to Chapter 45.
Consider again the level control loop depicted
in Figure 3.1, the block diagram for which is shown
in Figure 3.2, and whose implementation by com-
puter control is depicted in Figure 44.1.
This may be considered to consist of four sub
systems:
1. Process and load (F/H), and instrumentation
comprising current to pressure (I/P) converter,
valve (P/F) and dp cell (H/I).
2. Input interface consisting of current to voltage
(I/V) converter,sampler and analogue to digital
converter (A/D).

4-20 mA F1
0-25510 0-5V 0-5V 0.2-1.0 bar
F/H

u F0 h
D/A ZOH V/I I/P P/F F/H

AOT card
AIN card H/I

AOT PID FIL AIN A/D I/V

0-100% 0-5V 4-20 mA

0-102310
Fig. 44.1 Block diagram for realisation of analogue control loop
 322 44 Analogue Control Loop
3. Function blocks for input scaling (AIN), fil-
tering (FIL), control (PID) and output scaling
(AOT).
4. Output interface consisting of sampler, digital
to analogue converter (D/A), zero order hold
(ZOH) and transmitter (V/I).
44.1 Input Interface
The three elements of I/V, sampler and A/D are all
realised by the circuits of an AIN card.Assume that
the dp cell’s output is one of a number of 4–20 mA
channels handled by the card, the circuit for which
is as depicted in Figure 44.2.
The I/V conversion essentially consists of con-
verting the 4–20 mA signal into a 0–5 V signal
compatible with the input range of the A/D con-
verter. The mA signal is dropped to earth across a
250 § resistor and converted into a 1–5 V signal.
This is subsequently scaled into a 0–5 V signal by
an op-amp circuit, as described in Chapter 6. Note
the RC network for filtering high frequency noise,
such as mains frequency and harmonics thereof,
as described in Chapter 69. Also note the barrier
for electrical protection which is described fully
in Chapter 52. The barrier depicted is external but
on some systems is realised by circuits on the AIN
card.
24V
Barrier
4-20mA
AIN card
1–5V 250Ω
0V
Fig. 44.2 Analogue input channel
The sampling process, sometimes referred to as
scanning, is necessary because the A/D converter
is usually shared between all the input channels
on the card. The sampler is often referred to as a
multiplexer and sampled signals are said to be mul-
tiplexed. In operation, under control of the RTOS,
the 0–5 V signal is switched through to the input
of the A/D converter, and held there long enough
for the A/D conversion to take place. The analogue
signal must be sampled frequently enough for the
samples to be a meaningful representation, but not
so often as to cause unnecessary loading on the
system. At the same time the sampling frequency
must not be too low as to cause aliasing effects.
The various input channels would be sampled at
different frequencies, as appropriate.
The A/D converter is an integrated circuit chip.
It converts the sampled 0–5 V signal into a bit pat-
tern. Given that the original level measurement is
from a dp cell, whose accuracy is ±1% at best,
one would expect a 10-bit word with a range of
0–102310 and a resolution of approximately ±0.1%
to be adequate. However, this is insufficient resolu-
tion for some routines.For example,in PID control,
the derivative action operates on the difference be-
tween successive input samples and, to avoid nu-
merical instability, higher resolution is required.
Therefore, it is not uncommon for A/D conversion
to use at least 14 bit words with a range of 0–1638310
and a resolution of approximately ±0.006%.
 44.2 Input Scaling 323

44.2 Input Scaling d0  1,j − 0,j
0,j+1 = 0,j +  .t = 0,j + .t
dt j T
The AIN function block of Figure 44.1 represents

an analogue input scaling routine. It operates on = 0,j + k. 1,j − 0,j

the output of the A/D converter. The following
equation is used universally for linear scaling. For
brevity, a 10-bit A/D converter is assumed:
1
0 = bias + .span
1023
where 1 is the decimal value of the binary output
of the A/D converter.
A typical algorithm, written in structured text,
for implementing it would be:
OP: = BI + SN∗ IP/1023 (44.1)
For example, a bit pattern of 10000110012 corre-
sponds to 1 = 53710 which, given a bias of −0.1
and a span of 2.1, yields a value for 0 of approxi-
mately 1.0 with a resolution of approximately 0.1%.
The resultant value of 1.0012 is stored in slot 18 of
Table 43.1 which obviously corresponds to the tank
being half full.
44.3 Filtering
The FIL function block of Figure 44.1 represents a
filter routine. It operates on the output of the AIN
function block. Strictly speaking, given the high
frequency filtering of the AIN card, this is only
necessary if there is lower frequency noise, which
is unlikely on the level in a buffer storage tank. The
filter is nevertheless included as a typical example
of signal processing.
The most common type of filter is the simple
first order lag, as explained in Chapter 69, which is
of the form:
d0
T + 0 = 1
dt
which may be rearranged:
d0 1 − 0
= mately ±0.25% to be adequate. However, in prac-
dt T tice, most D/A converters use at least 10-bit words
Using Euler’s first order explicit method of numer-
ical integration:
A typical algorithm for implementing the filter
would be
OP: = OP + FC∗ (IP − OP) (44.2)
44.4 PID Control
The PID function block of Figure 44.1 represents
the routine for a 3-term controller. It operates on
the output of the FIL function block. The func-
tioning of PID control was discussed in detail in
Chapter 23. In particular, a discretised version of
the absolute form of the classical PID controller
with derivative feedback was developed in Equa-
tion 23.8. Typical algorithms, written in structured
text, for implementing this controller would be
E = SP − IP
if (OP = 0 or OP = 100) then goto L
IA = IA + KI∗ E
L OP = BI + (KC∗ E + IA − KD∗ (IP − PIP))
if OP < 0 then OP = 0
if OP > 100 then OP = 100 (44.3)
44.5 Output Scaling
The AOT function block of Figure 44.1 represents
an analogue output scaling routine. It operates on
the output of the PID function block.The output of
the AOT function block is a decimal number whose
binary equivalent is consistent with the input range
of the D/A converter.
Given that the output signal is eventually used
to position a valve, which can be done to within
±1% at best, one would expect an 8-bit word with
a range of 0–25510 and a resolution of approxi-
with a range of 0–102310 and a resolution of ap-
proximately ±0.1%.
 324 44 Analogue Control Loop

The following equation is used extensively for This effectively converts the pulse output from the
output scaling. The range of the controller output D/A converter into a quasi,or piecewise linear,ana-
is normally 0–100% and, for brevity, an 8-bit A/D logue signal that can be output to the I/P converter
converter is assumed: and thence to the control valve. Figure 44.4 depicts
(1 − bias) the construction of the quasi analogue signal.
0 = 255.
span
The output 0 is stored in the database as a bit pat- D/A output
tern. The algorithm used for the output scaling is
typically
t
OP: = 255∗ (IP − BI)/SN (44.4)

44.6 Output Interface
The four elements of sampler, D/A, ZOH and V/I
are all realised by the circuits of an AOT card. As-
sume that the output is one of a number of 4–20 mA
channels handled by the card, the circuit for which
is as depicted in Figure 44.3.Again note the barrier
for electrical protection.
The sampler is virtual.On a regular basis,under
control of the RTOS, values of the AOT output are
extracted from the database and routed through to
the D/A converter. The sampler is held open long
enough for the conversion to take place.
The D/A converter is an integrated circuit chip.
It converts the sampled bit pattern into a 0–5 V
signal. Since D/A converters are relatively cheap, it
is normal practice for each output channel to have
its own dedicated D/A converter.
The ZOH holds, or latches onto, the output of
the D/A converter in between sampling periods.
ZOH output
t
Analogue
equivalent
t
Fig. 44.4 Construction of quasi analogue output signal
The transmitterV/I provides the scaling and power
for signal transmission. The 0–5 V latched signal
from the D/A is a very low power,TTL or otherwise,
signal. After scaling into a 1–5 V signal it is con-
verted into a 4–20 mA signal. The op-amp circuit
shown in Figure 6.13 is typical of the type used for
such power amplification.

AOT card I/P converter

Barrier
4-20mA
0-5V

0V
Fig. 44.3 Analogue output channel
 44.7 Nomenclature 325

44.7 Nomenclature
Symbols
 some variable
T filter time constant
t step length which is, in effect,
the sampling period
k filter constant, t/T

Subscripts
0 output
1 input
j current value

Pseudocode
BI bias
E error
FC filter constant
IA integral action
IP input
KC proportional gain
KD derivative gain
KI integral gain
OP output
PIP previous input
P set point
SN span