POWER designer

Expert tips, tricks, and techniques for powerful designs

No. 119
121
Power Supply Design Considerations for
Feature Article ............... 1-7 Modern FPGAs
— By Dennis Hudgins, Low Voltage Applications Manager, Tucson Design Center
Full-Featured Synchronous
Buck Regulators ................2 Introduction
Today’s FPGAs tend to operate at lower voltages and higher currents than
Multiple-Rail Power their predecessors. Consequently, power supply requirements may be more
Sequencing .........................4 demanding, requiring special attention to features deemed less important in
past generations. Failure to consider the output voltage, sequencing, power
on, and soft-start requirements, can result in unreliable power up or potential
damage to the FPGA.
Output Voltage Requirements
The first criteria to consider when designing a power supplies for FPGAs are the
voltage requirements for the different supply rails. Most FPGAs have specifica-
tions for the CORE and IO voltage rails, and many require additional auxiliary
rails that may power internal clocks, phase lock loops or transceivers. Table 1
provides the voltage levels and tolerances for several popular FPGAs.
Table 1. Voltage Requirements for Common Modern FPGAs
IO CORE AUX
FPGA Voltages Tolerance Voltages Tolerance Voltages Tolerance
Cyclone II 1.5V - 3.3V 5% 1.2V 50mV — —
Cyclone III 1.5V - 3.3V 5% 1.2V 50mV 2.5V 5%
Stratix III 1.5V - 3.3V 5% 1.1V or 0.9V 50mV 2.5V 5%
Virtex V 1.2V - 3.3V 5% 1.0V 5% 2.5V 5%
Spartan III 1.2V - 3.3V Varies 1.2V 5% 2.5V 5%

Since FPGAs generally specify several permissible voltage levels for the IO,
the voltage selected is dictated by the external digital circuitry. To provide
flexibility, the FPGA will generally provide multiple IO banks that can
be powered separately allowing the FPGA to interface with various logic
families. For simplicity, the solutions illustrated in this article will assume all
IO banks are powered off of a single power supply rail.
The core voltage supplies the internal logic configuration blocks of the FPGA
and is where many of the internal digital path processes occur. As such, the
current demanded by the core will vary greatly depending on the percent
utilization of the FPGA. Most FPGA vendors provide design tools that
estimate core current requirements based on the internal blocks utilized.

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Integrated Features for Optimized Power Supply Designs

LM20xxx Family Features Highest Power Density 5A Regulators

• External soft-start
• Tracking VIN VIN SW VOUT
• Precision enable EN
FB
LM20145
• Power good AVIN
PGOOD
• Pre-biased start-up COMP VCC

RT
• Enhanced system reliability SS/TRK

- High accuracy current limit

eTSSOP-16
- Over-voltage protection, under voltage 32mm2
lockout, and over-current protection
Efficiency vs Output Current
• Available in eTSSOP-16 packaging (VIN = 5.0V, VOUT = 3.3V, fSW = 500 kHz)
100

Feature Options
95
• Fixed and adjustable switching frequency
Efficiency

90
• Clock synchronization in
• Clock synchronization out 85

Applications 80
LM20145
Powering FPGAs, DSPs, and microprocessors in servers, Competitor
networking equipment, optical networks, and industrial 75
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
power supplies

Product Number VIN (V) IOUT SYNC IN Frequency Adjust SYNC OUT Frequency
LM20123 2.95 to 5.5 3 1.5 MHz
LM20133 2.95 to 5.5 3 ✔ Sync
LM20143 2.95 to 5.5 3 ✔ 500 kHz - 1.5 MHz
LM20124 2.95 to 5.5 4 1 MHz
LM20134 2.95 to 5.5 4 ✔ Sync
LM20144 2.95 to 5.5 4 ✔ 500 kHz - 1.5 MHz
LM20154 2.95 to 5.5 4 ✔ 1 MHz
LM20125 2.95 to 5.5 5 500 kHz
LM20145 2.95 to 5.5 5 ✔ 250 kHz - 750 kHz
LM20242 4.5 to 36 2 ✔ 250 kHz - 750 kHz

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2
POWER designer
Power Supply Design Considerations for Modern FPGAs
Over time the voltages used to power the core have
been steadily dropping. Modern cores like the
Stratix III can operate off of voltages as low as 0.9V.
Lower core voltages are enabled by finer geometry
silicon processes, and are valuable in keeping the
power dissipated in the FPGA to a reasonable level.
With process technologies designed to operate at
lower voltage levels, keeping within the core voltage
tolerance requirements has become more challeng-
ing for the power supply designer.
Output Capacitance and Transient Considerations
A good power supply design will keep the core
voltage within tolerance at all times. Most of the
power supply transient concerns can be managed
by properly selecting the bypass and bulk capaci-
tances for the power supply. In general, every core
ball or pin connection should be bypassed directly
under the FPGA with high-quality X5R or X7R
ceramic capacitors. The values recommended
for each of these capacitors range from 1 μF to
10 μF and will generally be specified by the FPGA
manufacturer. These capacitors provide a charge
when the FPGA needs to rapidly draw large spikes
of current during high speed operations. Likewise,
the bulk capacitance should be selected to provide
charge during large steps of current which tend
to occur during power on, application start, or a
change in application state. Before increasing the
amount of output capacitance to solve transient
droop issues, changes to the power supply should
be made that do not involve an increase in PCB
area or component count. The response to a load
transient is dictated by the large signal response
time that consists of ramping the inductor current
to the correct operating level and the small signal
response of the control loop.
Transient Response Optimizations
To optimize the transient response, ensure
the supply is switching at the highest possible
frequency. This will allow use of a small inductor
and reduce the large signal response time. Typical
high performance power supply solutions can be
designed to have crossover frequencies as high as
one-tenth to one-fifth the switching frequency.
Pushing the crossover frequency too high may result
in ringing at the output during a load transient
indicating poor phase margin. Any ringing in
the output should be avoided; this may result in
instability with external component variation or
when operating at temperature extremes.
AUX Voltage Considerations
Many FPGAs require a third power supply
commonly referred to as the auxiliary rail or AUX.
Since the AUX rail may power internal clocks, phase
lock loops, or transceivers, the amount of output
voltage ripple on this rail should be minimized. In
some cases, additional ferrite beads and capacitors
filtering may be needed to meet the application or
FPGA noise requirement. In applications where
noise is extremely important, a low noise, high
PSRR LDO, like the LP3878, should be consid-
ered instead of a switching converter.
Sequencing Requirements
The sequencing requirements can vary depending on
the particular FPGA being used, and many newer
FPGAs specify no sequencing is required. While this
is technically true for the FPGA, it is not the optimal
way to design a power solution.
National offers several devices to address sequencing
requirements. The LM3880 is designed to address
sequential sequencing of multiple supply rails. This
device is available in a small SOT-23 package and
can sequence up to three supply rails.
LM3880
FLAG1
VIN VIN
FLAG2
EN
FLAG3
Power Power Power
GND Supply 1 Supply 2 Supply 3
EN EN EN
Figure 1. Simplified Buck Converter Schematic
Many options are available to control the up-and-
down, three-flag outputs sequencing timing. National
also provides devices to support customized flag order
and timing. Figure 1 illustrates a typical application
circuit for the LM3880.
power.national.com
3
Industry’s Easiest and Smallest Solution for
Multiple-Rail Power Sequencing
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LM3880 Power Sequencer in a Tiny SOT23-6 Package Controls Up to 3 Supplies

Application Diagram

5V
Memory
VIN
HG 1.8V @ 4A
Time Sequence of Flag Outputs
EN LG
LM1771
FB
Input supply
5V
5V
VCC
I/O
VIN
FLAG 1 3.3V @ 1A
LM3880
EN
EN FLAG 2 SNS
LP38692
FLAG 3

5V Core
VIN 1.2V @ 2A
SW
EN
LM2832
FB

LM3880 Features Applications

• Easiest method to sequence rails • Sequencing power rails of digital logic devices
• Input voltage range of 2.7V to 5.5V (ASICs, FPGAs, DSPs, microcontrollers) to
• Standard timing options: 10 ms, 30 ms, 60 ms, avoid latch-up conditions
120 ms • Systems with multiple rails
• 1-2-3 power up and reverse-power down
3-2-1 control
• Customization of timing and sequence available
through factory programming
• Available in tiny SOT23-6 package

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4
POWER designer
Power Supply Design Considerations for Modern FPGAs
Voltage tracking is another method of sequencing
power supplies applicable to FPGAs and many
processors. The most common, and generally rec-
ommended, method to power up FPGAs and other
processors is to have the CORE voltage track the
I/O voltage during startup as shown in Figure 2.
VCORE
VIO
Voltage
VENABLE 1
Time
Figure 2. Startup voltage tracking
This power up technique is known as simultaneous
startup, and its primary advantage is that it avoids
turning on any parasitic conduction paths that
may exist between the CORE and IO supply rails.
Turning on a parasitic conduction path may lead
to unreliable startup or even damage to the FPGA
or DSP.
Master Supply
V CORE
Tracking Supply
EN
R1
V IO
SS/TRK
R2
Figure 3. Typical voltage tracking configuration
Some of National’s devices that feature voltage
tracking include the LM20k family of high perfor-
mance synchronous DC/DC converters, as well as
the LM3743 controller. Figure 3 illustrates a typical
voltage tracking configuration for these devices.
Start-up / Power On Requirements
When sequential sequencing is used in systems
with multiple voltage rails, as is the case with many
FPGA solutions, it is likely that an output of one
of the power supplies could be pre-biased through
various parasitic conduction paths. In this situation,
how the power supply handles this pre-biased state
can have an impact on long-term system reliability,
or even the ability of the power supply or FPGA
to successfully start. To avoid the pitfalls associated
with a pre-biased startup, the power supply should
not pull the output low if a pre-biased condition
exists. Figure 4 illustrates how a pre-biased condition
should be handled when the output is pre-biased to
three different voltage levels.
VOUT3
VOUT2
500 mV/DIV
VOUT2
2 ms/DIV
Figure 4. Pre-biased startup of the LM3743
All power solutions featured in this publication are
capable of properly handling a pre-biased start up.
Power supplies used to power both the CORE and IO
must be monotonic during power on to avoid FPGA
startup problems. A monotonic startup continuously
increases until the output reaches the final value. The
critical area for monitonicity for most modern core
voltage rails occurs between 0.5V to 0.9V. This is
when the FPGA initializes the internal logic blocks to
valid operating states.
Soft-Start Requirements
Using soft-start for both the core and IO voltage
rails is highly recommended, even if not specified by
the FPGA manufacturer. Slowly ramping the input
voltage reduces the inrush currents seen in some
FPGAs. Using soft-start also reduces the current
needed to charge the output capacitance of the
power supply and will decrease the voltage droop on
the input bus during start-up.
power.national.com
5
 POWER designer
Power Supply Design Considerations for Modern FPGAs

The start-up or soft-start requirements for several startup sequence will be the CORE followed by
FPGAs are summarized in Table 2. the IO, and then by the AUX rails. The LM3880
Table 2. Required Start-Up/Soft-Start Times features an integrated precision enable circuit that
VCCIO CORE AUX
allows the user to set the turn on voltage with two
external resistors. An additional N-FET device is
FPGA Min Max Min Max Min Max
used to drop the 12V supply rail down to the oper-
Cyclone II N/A 100 ms N/A 100 ms N/A N/A
ating voltage range of the LM3880. The LP3878 is
Cyclone III 50 μs 50 ms 50 μs 50 ms 50 μs 50 ms
used to power the 2.5V AUX rail. This device was
Stratix III 100 μs 100 ms 100 μs 100 ms 100 μs 100 ms
selected based on the excellent noise performance
Virtex V 0.2 ms 50 ms 0.2 ms 50 ms 0.2 ms 50 ms (18 mV RMS) and high PSRR.
Spartan III 0.6 - N/A 0.6 - N/A 0.6 - N/A
LM20242
2.0 ms 2.0 ms 2.0 ms SS/
TRACK BOOT
V IO
A startup time of 10 ms generally limits the capacitive 12V VIN SW 3.3V/2A
EN
inrush currents to an acceptable level while meeting COMP
FB

PGOOD VCC
the requirements for most FPGAs and DSPs. GND

Application Examples
The application examples shown below implement SS/
LM20242

BOOT
requirements previously discussed for powering TRACK
VIN SW
V AUX
2.5V/2A
FPGAs. These solutions are meant to be guidelines for EN
FB
COMP
selecting the correct devices and circuit topologies to PGOOD VCC

meet the FPGA power requirements. GND

12V

LM20242
LM26400
SS/
VIN BOOT
BST1 BST2 CORE TRACK
IO V CORE
3.3V/2A SW1 SW2 1.2V/2A VIN SW 1.2V/2A
FB1 FB2
SS1 SS2 EN
EN1 EN2 FB
GND COMP
PGOOD VCC

LM3880 GND
FLAG2
VIN
FLAG3
EN FLAG1

GND

LP3878
Figure 6. 2A CORE and I/O solution with voltage tracking
INPUT OUTPUT
AUX
2.5V/300mA from a 12V bus
SHUTDOWN
BYPASS ADJ Figure 6 uses the synchronous LM20242 device
GND

capable of supplying 2A of output current. This

solution is also ideal for lower output current FP-
Figure 5. 2A Core and I/O Solution from a 12V Bus GAs and features a monotonic startup with voltage
tracking. The LM20242 also utilizes current mode
Figure 5 features the dual output LM26400 to control that offers reduced component count and
provide the CORE and IO voltages with current easy compensation. The LM20242 is a full-featured
capability up to 2A from a 12V input bus. This device with many fault protection features such as
solution is optimal for use in the Cyclone and Spartan over-voltage protection (OVP), under-voltage pro-
families of FPGAs; it may also be used in Stratix tection (UVP), thermal shutdown, and an accurate
and Virtex designs where the FPGA utilization is current limit. The synchronous operation of the
low. This solution provides a monotonic startup LM20242 offers improved efficiency over non-syn-
with soft-start to limit inrush startup currents. chronous devices resulting in cooler operation and
Sequencing is performed with the LM3880. The increased reliability.

6
POWER designer
Power Supply Design Considerations for Modern FPGAs

Figure 7 illustrates the LM20125 being used to 5V

LM3743
BOOT

power both the CORE and I/O for load currents VCC HGATE
+ +

SW
up to 5A. Since the LM201xx family of devices ILIM
V IO
3.3V/20A
SS/
shares the same pin-out, higher or lower currents TRACK

COMP/EN
LGATE
GND
+

can be obtained by interchanging the devices. These FB

full featured devices offer voltage tracking, pro-

grammable soft-start, and 1.5% voltage accuracy LM20125
V AUX
at the feedback pin. The LM20125 leads the
L
VCC PVIN SW 2.5V/5A
EN
industry in both power density and efficiency for SS/
AVIN
FB

PGOOD
TRACK
a 5A integrated FET device. Efficiencies as high as COMP VCC
SS/TRK
GND
97% are achievable due to 35 mΩ integrated FETs.
The LM20125 is offered in a small TSSOP-16 LM3743
package and is fully protected with a high accuracy BOOT
+ +
VCC HGATE
current limit, over-voltage protection, and thermal SW
V CORE
ILIM 1.0V/20A
shutdown. SS/
TRACK
LGATE +

GND
COMP/EN

Figure 7. 5A Core and I/O solution with voltage tracking FB

from a 5V bus
LM20125
SS/TRK V IO
SW 3.3V/5A

5V PVIN FB
Figure 8. High current LM3743 based power supply solution.
EN
AVIN PGOOD

COMP VCC The LM20125 is used to power the auxiliary voltage

PGND AGND
rail and has a compatible SS/TRK pin.
National offers a wide range of products that
LM20123
V AUX
support the power requirements of the latest gener-
2.5V/3A
SS/TRK SW
ation of FPGAs. These power solutions can support
PVIN FB
EN
PGOOD
the sequencing, soft-start, and voltage tolerance
AVIN

COMP VCC
requirements for the newest families of FPGAs, as
PGND AGND
well as handle challenges such as pre-biased outputs
and demanding transient response needs. For your
complete FPGA power supply needs, please visit
LM20125

SS/TRK SW
V CORE
1.1V/5A
www.national.com. ■
PVIN FB References
EN
1. LM3880 Product Datasheet -
AVIN PGOOD
http://cache.national.com/ds/LM/LM3880.pdf
COMP VCC 2. LM26400 Product Datasheet -
PGND AGND http://cache.national.com/ds/LM/LM26400Y.pdf
3. LM20242 Product Datasheet -
http://cache.national.com/ds/LM/LM20242.pdf
The circuit shown in Figure 8 utilizes the LM3743 4. LM20125 Product Datasheet -
http://cache.national.com/ds/LM/LM20125.pdf
for powering both the CORE and IO. This 5. LM3743 Product Datasheet -
controller is capable of supporting designs up to http://cache.national.com/ds/LM/LM3743.pdf
6. Cyclone II Device Handbook -
20A and features a SS/TRACK pin to provide a http://www.altera.com/literature/lit-cyc2.jsp
monotonic simultaneous start-up. The LM3743 7. Cyclone III Device Handbook -
http://www.altera.com/literature/lit-cyc3.jsp
provides increased system reliability by offering 8. Stratix III Device Handbook -
http://www.altera.com/literature/lit-stx3.jsp
both high- and low-side current limit as well as 9. Virtex V Product Datasheet -
output under voltage protection. The device also http://direct.xilinx.com/bvdocs/publications/ds003.pdf
10. Spartan III Product Datasheet -
features a hiccup mode protection that eliminates http://direct.xilinx.com/bvdocs/publications/ds099.pdf
thermal runaway during fault conditions. power.national.com
7
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