A B C D E

COMPAL CONFIDENTIAL
1
MODEL NAME : BDW00 1

COMPAL P/N : DA8DW00L110/DA8DW00L410

PCB NO : LA-1452
Revision : 1C
DATE :

2 2

Abacus/TangII Schematics Document

uFCBGA/uFCPGA Northwood

2003-02-24
3 3

REV: 1C

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 1 of 47
A B C D E
 A B C D E

Compal confidential Block Diagram

Model Name : ABACUS/TangII
File Name : LA-1452

DT & Mobile Northwood

1 Fan Control CPU Bypass uFCBGA/uFCPGA CPU Thermal Sensor Clock Generator 1

+1.2VP ADM1032
& CPUVID ICS950810
page 7 page 7, 8 +CPU_CORE page 5,6 +3VS page 6 +3VS page 15

HA#( 3..31) HD#(0..63)

System Bus
400/533 MHz
DT/BD-PE/ICH4/EXT VGA
DT/BD-GL/ICH4/INT VGA
CRT Connector INTEL Memory DDR-DIMM X2
BANK 0, 1, 2, 3
page 17
BROOKDALE-GL/PE BUS(DDR) +2.5V 200/266MHz
(PIRQE#,G_GNT#,G_REQ#) FOR EXT. INT. CRT
+1.5VS +2.5V
EXT. CRT 760 BGA
+2.5V +1.25VS page 12,13,14
AGP4X(1.5V) +1.25VS
AGP GRAPHIC/CHRONTEL
AGP Conn +CPU_CORE page 9,10,11
page 16

2 LVDS Connector TV OUT page 17

HUB LINK
2

+1.5VS
66MHz

+3VS
+3VS 33MHz PCI BUS INTEL 48MHz 2 USB Ports
+3VALW +3VALW
+5VALW page 32
IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 +1.5VS
(PIRQC#D#,GNT#1,REQ#1) (PIRQB#,GNT#0,REQ#0) (PIRQA#,GNT#2,REQ#2) ICH4
+1.5VALW 24.576MHz AC-LINK
+CPU_CORE 421 BGA
Minipci CONN LAN CardBus VCC5REF
ATA100

WIRELESS BCM-4401L & 1394 VCC5REFSUS page 18,19,20

+3VALW PCI4510/PCI1510 MDC
+3V page 26 +3VS
+3VS +3VALW page 22 +3VALW
+3V page 23,24,25 +3V page 29
LPC BUS
+3VS Cable
RJ45 Card Bus IDE HDD IDE AC97 Codec
3
1394 33MHz
CD-ROM
3

page 22 SLOT CONN +5VALW STAC9750 RJ11

page 24 page 23 page 21 +5VS page 21
+5VDDA
NS EC87591L page 27
SIDE IRQ15 PIDE IRQ14
Embedded
845PE / PCI4510 Controller
845GL / PCI1510 +3VS
+3VALW page 30

AMP & INT. HeadPhone

Speaker & MIC Jack
+5VDDA
+5VALW page 28 page 28
Touch Pad Int.KBD
LED Status page 31
LID Switch
+5VS
+5VALW
+3VALW page 29 BIOS
+3VALW page 31
Power Circuit DC/DC Interface Power On/Off
4
DC/DC Suspend Reset & RTC
4

page EC I/O Buffer EC DEBUG

34,35,36,37,38,39,40 page 33 page 32 +5VALW page 31 +3VALW page 30 Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 2 of 47
A B C D E
 5 4 3 2 1

Power Managment table

Revision List

+3VS
Schematics Rev PCB Rev CHIPS Rev Signal
+5VS
+3VALW +3V
SST-Build 0.1 0.1 +1.5VS
+5VALW +5V
+1.2VP
D 845PE Rev B0 State +12VALW +2.5V D
PT-Build 0.2 0.2 845GL Rev B1 +CPU_CORE
ICH4 Rev B0
+1.25VS
ST-Build
S0 ON ON ON

QT-Build
S1 ON ON ON

S3 ON ON OFF

S5 S4/AC ON OFF OFF

S5 S4/AC don't exist OFF OFF OFF

Ceramic Capacitor Spec Guide:

C C
Temperature Characteristics:
Symbol 0 1 2 3 4 5 6 7

CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R

8 9 A B C D E F G

NP0 C0G BJ CH CJ CK SH SJ

H I J

UJ UK SL

Tolerance:
Symbol A B C D F G H J
B B
CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%

K M N P Q V X Z

+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20%

SMBUS Control Table

THERMAL THERMAL NOTE1:
SOURCE INVERTER BATT SERIAL SENSOR SENSOR SODIMM CLK CHIP MINI PCI
EEPROM (CPU)
(U57) (U25/U23) @XX : Depop component
SMB_EC_CK1 NS 87591 1@XX : Pop for INT, Depop for EXT
SMB_EC_DA1
(1010)

SMB_EC_CK2 NS 87591 2@XX : Pop for EXT, Depop for INT

SMB_EC_DA2
A A

SMB_CLK ICH4
SMB_DATA
Dell-Compal Confidential
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 3 of 47
5 4 3 2 1
 5 4 3 2 1

PQ26
SUSP#
+1.5VALW +1.5VS
D
page 35 page 35 D

SUSP# +5VS
+5VALW page 31

SHDN# SIDEPWR
page 21
+5VSHDD
SUSP#
MAX1632 page 25
+5VDDA
page 36

SYSON
+3VALW +3V
page 31
C C

page 34 VR_ON#
SUSP#
AC page 31
+3VS

B+ CM2843 +1.2V
+12VALW page 38

Battery VR_ON#
page 34

+5VS
Mobile +3VS
B B

ISL6215 +CPU_CORE +1.5VS VGA Conn.

180 pin
DT page 38 +2.5V
+3V
ISL6219
+5VALW
(Either one by CPU)
+12VALW
SUSP# B+ page 16
+1.25VS
A
SYSON ISL6225 A

page 36 +2.5V
Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 4 of 47
5 4 3 2 1
 A B C D E F G H I J

1 1

+CPU_CORE

AC10
AC12
AC14
AC16
AC18

AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18

AB11
AB13
AB15
AB17
AB19

AE10
AE12
AE14
AE16
AE18
AE20

AF11
AF13
AF15
AF17
AF19

AF21
AC8

AD7
AD9
AA8

AB7
AB9

AE6
AE8

AF2

AF5
AF7
AF9

C10
C12
C14
C16
C18
C20

D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20

B11
B13
B15
B17
B19

E10
2 2

C8

D7
D9
A8

B7
B9
H A#[3..31] U19A HD#[0..63]
<9> HA#[3..31] HD#[0..63] <9>

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#3 K2 B21 HD#0
HA#4 A#3 D#0 HD#1
K4 A#4 D#1 B22
HA#5 L6 A23 HD#2
HA#6 A#5 D#2 HD#3
K1 A#6 D#3 A25
HA#7 L3 C21 HD#4
HA#8 A#7 D#4 HD#5
M6 A#8 CPU CORE D#5 D22
HA#9 L2 B24 HD#6
HA#10 A#9 D#6 HD#7
M3 A#10 D#7 C23
HA#11 M4 C24 HD#8
HA#12 A#11 D#8 HD#9
N1 A#12 D#9 B25
HA#13 M1 G22 HD#10
3 HA#14 A#13 D#10 HD#11 3
N2 A#14 D#11 H21
HA#15 N4 C26 HD#12
HA#16 A#15 D#12 HD#13
N5 A#16 D#13 D23
HA#17 T1 J21 HD#14
A#17 D#14

HOST ADDRESS
HA#18 R2 D25 HD#15
HA#19 A#18 D#15 HD#16
P3 A#19 D#16 H22
HA#20 P4 E24 HD#17
HA#21 A#20 D#17 HD#18
R3 A#21 D#18 G23
HA#22 T2 F23 HD#19
HA#23 A#22 D#19 HD#20
U1 A#23 D#20 F24
HA#24 P6 E25 HD#21
HA#25 A#24 D#21 HD#22
U3 A#25 D#22 F26
HA#26 T4 D26 HD#23
HA#27 A#26 D#23 HD#24
V2 A#27 D#24 L21
HA#28 R6 G26 HD#25
HA#29 A#28 D#25 HD#26
W1 H24
4 HA#30
HA#31
T5
U4
V3
A#29
A#30
A#31
DT/Mobile D#26
D#27
D#28
M21
L22
J24
HD#27
HD#28
HD#29
4

A#32 D#29 HD#30

W2 K23

HOST DATA
A#33 D#30 HD#31
Y1 H25
A#34 D#31 HD#32
AB1 M23
<9> H_REQ#[0..4]
H _REQ#[0..4]

H_REQ#0 J1
A#35
NorthWood D#32
D#33
D#34
N22
P21
M24
HD#33
HD#34
HD#35
H_REQ#1 REQ#0 D#35 HD#36
K5 N23
H_REQ#2 REQ#1 D#36 HD#37
J4 M26
H_REQ#3 REQ#2 D#37 HD#38
J3 N26
REQ#3 D#38
CONTROL SIGNAL

H_REQ#4 H3 N25 HD#39

REQ#4 D#39 HD#40
<9> H_ADS# G1 R21
ADS# D#40 HD#41
P24
D#41 HD#42
5 R25 5
D#42 HD#43
+CPU_CORE
For Mobile AC1
AP#0 D#43
R24
V5 T26 HD#44
R284 @4.7K_0402_5% AP#1 D#44 HD#45
AA3 T25
BINIT# D#45 HD#46
1 2 AC3 T22
IERR# D#46 HD#47
T23
D#47 HD#48
2 1 U26
R301 200_0402_5% D#48 HD#49
<9> H_BREQ0# H6 U24
BR0# D#49 HD#50
<9> H_BPRI# D2 U23
BPRI# D#50 HD#51
<9> H_BNR# G2 V25
BNR# D#51 HD#52
<9> H_LOCK# G4 U21
LOCK# D#52 HD#53
V22
D#53 HD#54
V24
CLK_CPU_BCLK D#54 HD#55
<15> CLK_CPU_BCLK AF22 W26
CLK_CPU_BCLK# BCLK0 D#55 HD#56
<15> CLK_CPU_BCLK# AF23 Y26
BCLK1 D#56 HD#57
W25
D#57 HD#58
6 Y23 6
D#58 HD#59
GND D#59
Y24
F3 CPU CORE Y21 HD#60
<9> H_HIT# HIT# D#60 HD#61
<9> H_HITM# E3 AA25
HITM# D#61 HD#62
<9> H_DEFER# E2 AA22
DEFER# D#62 HD#63
AA24
D#63

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
NorthWood

7 7
+CPU_CORE

Dell-Compal Confidential
8
Title
Compal Electronics, Inc. 8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Custom
Date: 星期五, 四月 25, 2003 Sheet 5 of 47
A B C D E F G H I J
 A B C D E F G H I J
2 1 H_SKTOCC#
R267 @33_0402_5%
1 2 +CPU_CORE
R318 56_0402_5%

AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26

AF10
AF12
AF14
AF16
AF18
AF20
AF26
AE7
AE9
AF1

AF6
AF8

C11
C13
C15
C17
C19

C22
C25

D10
D12
D14
D16
D18
D20
D21
D24
B10
B12
B14
B16
B18
B20
B23
B26

E11
E13
E15
E17
E19
E23
E26

F10
F12
F14
F16
F18

F22
F25
H _GHI# 2 PM_CPUPERF#

C2

C5
C7
C9

D3
D6
D8
B4
B8

E1

E4
E7
E9

F2

F5
1 PM_CPUPERF# <19>
U19B R317 @0_0402_5%

SKTOCC#
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73

VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
1 For Mobile 1

<9> H_RS#0 F1 J26

RS#0 DP#0
<9> H_RS#1 G5 K25
RS#1 DP#1
<9> H_RS#2 F4 K26
RS#2 DP#2
AB2
RSP# GND DP#3
L25 +H_GTLREF1
+3VS J6
<9> H_TRDY# TRDY#
AA21
H_BSEL0 H_A20M# GTLREF0
1 2 <18> H_A20M# C6
A20M# GTLREF1
AA6
R19 1.5K_0402_5% For H_FERR# B6 F20
<18> H_FERR# FERR# GTLREF2
H_IGNNE# B2 F6
Mobile <18> H_IGNNE# H_SMI# B5
IGNNE# GTLREF3
A22
<18> H_SMI# H_PWRGD AB23 SMI# NC1
A7 +CPU_CORE
2 <18> H_PWRGD H_STPCLK# PWRGOOD NC2 2
R269 @0_0402_5% Y4
<18> H_STPCLK# STPCLK#
2 1 H_DPSLPR# AD25
<18> H_DPSLP# DPSLP#
H_INTR D1 AD24 TESTTHI0_1 1 2
<18> H_INTR H_NMI LINT0 TESTHI0
E5 AA2 R285 56_0402_5%
<18> H_NMI H_INIT# LINT1 TESTHI1 TESTTHI2_7
+CPU_CORE W5 AC21 1 2
<18> H_INIT# H_RESET# AB25 INIT# TESTHI2
AC20 R275 56_0402_5%
<8,9> H_RESET# RESET# TESTHI3
TESTHI4 AC24
2 1 H_DPSLPR# AC23
R271 200_0402_5% TESTHI5 ITPCLKOUT0 R293 1
<9> H_DBSY# H5 DBSY# ITPCLKOUT0 AA20 2 56_0402_5%
H2 AB22 ITPCLKOUT1 R276 1 2 56_0402_5%
H_PWRGD <9> H_DRDY# DRDY# ITPCLKOUT1 TESTTHI8_10
2 1 AD6 U6 R294 1 2 56_0402_5%
<15> H_BSEL0 BSEL0 TESTHI8
R288 300_0402_5% AD5 W4
BSEL1 TESTHI9
Y3

+CPU_CORE
H_THERMDA
H_THERMDC
B3
C4
THERMDA
DT/Mobile TESTHI10
GHI# A6 H _GHI#
H_DSTBN#[0..3]
H_DSTBN#[0..3] <9>
3 H_RESET# THERMDC H_DSTBN#0 3
2 1 DSTBN#0 E22
R279 51.1_0603_1% 1 2 H_THERMTRIP# A2 K22 H_DSTBN#1
R315 62_0402_5% THERMTRIP# DSTBN#1 H_DSTBN#2
R22
Place resistor <100mils from
CPU pin
<19> H_THERMTRIP#
<8> ITP_BPM0
ITP_BPM0 AC6
ITP_BPM1 AB5 BPM#0
NorthWood DSTBN#2
DSTBN#3 W22 H_DSTBN#3
H_DSTBP#[0..3]
H_DSTBP#[0..3] <9>
<8> ITP_BPM1 ITP_BPM2 AC4 BPM#1 H_DSTBP#0
BPM#2 DSTBP#0 F21
ITP_BPM3 Y6 J23 H_DSTBP#1
+1.2VP +CPU_CORE ITP_PRDY# AA5 BPM#3 DSTBP#1 H_DSTBP#2
<8> ITP_PRDY# BPM#4 DSTBP#2 P23
ITP_PREQ# AB4 W23 H_DSTBP#3
<8> ITP_PREQ# BPM#5 DSTBP#3
1

ITP_TCK D4 L5
<8> ITP_TCK ITP_TDI TCK ADSTB#0 H_ADSTB#0 <9>
R206 R207 C1 R5
<8> ITP_TDI ITP_TDO TDI ADSTB#1 H_ADSTB#1 <9>
0_0603_5% D5
<8> ITP_TDO ITP_TMS TDO H_D BI#[0..3]
@0_0603_5% F7
4 <8> ITP_TMS ITP_TRST# TMS H_DBI#0 H_DBI#[0..3] <9> 4
E6 E21
2

<8> ITP_TRST# TRST# DBI#0 H_DBI#1

G25
DBI#1 H_DBI#2
For L24 LQG21F4R7N00_0805
DBI#2
P26 R266
1 2 H_VCCA AD20 V21 H_DBI#3 2 1
Mobile L25 LQG21F4R7N00_0805 1 A5
VCCA DBI#3 @0_0402_5%
SYSRST# <19>
H_VCCIOPLL VCCSENSE H_DBR#
1 2 AE23 AE25 H_ITP_DBR# <8>
TP2 VCCIOPLL DBR#
1 1 1
Murata LQG21F4R7N00 AF25
C321 C305 C320 NC7 H_PROCHOT# 1 +CPU_CORE
AF3 C3 2
22U_1206_10V4Z 1U_0603_10V4Z NC8 PROCHOT# R311 62_0402_5%
V6
2 2 2 MCERR# H_SLP#
AB26 H_SLP# <18>
H_VSSA 22U_1206_10V4Z SLP#
RP61 AC26
CLK_CPU_ITTP ITP_CLK0 H_VSSA
<15> CLK_CPU_ITP 1 4 AD26
ITP_CLK1 GND VSSA
AD22
2 3 CLK_CPU_ITTP# A4 1
<15> CLK_CPU_ITP# VSSSENSE
5 L24 5
@0_4P2R_0402_5% COMP0 TP1
P1
COMP1
AD2
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
NC3
2

VCCVID
RP62 AD3
R302 NC4
1 4

VID0
VID1
VID2
VID3
VID4

NC5
NC6
<8> CLK_ITP#
<8> CLK_ITP 2 3
51.1_0603_1% R300
+CPU_CORE 0_4P2R_0402_5% 51.1_0603_1%
1

F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5

AE5
AE4
AE3
AE2
AE1

AE21
AF24

AF4
NorthWood
R278 2 1 51_0402_5% ITP_PREQ# +3VS
R291 2 1 51_0402_5% ITP_PRDY# +1.2VP +CPU_CORE

R262 2 1 51_0402_5% ITP_BPM0

2
R272 2 1 51_0402_5% ITP_BPM1 1 C317
0.1U_0402_16V4Z

2
R268 2 1 51_0402_5% ITP_BPM2 R303
CPU_VID4 <8,40>
R296 2 1 51_0402_5% ITP_BPM3 1K_0402_5% R307
6 CPU_VID3 <8,40> 2 6
CPU_VID2 <8,40> 470_0402_5%

1
CPU_VID1 <8,40> <19,31> PROCHOT#
1 2 ITP_TDI CPU_VID0 <8,40>

1
1
R313 @1.5K_0402_5%
1 2 ITP_TMS 2
R305 @1.5K_0402_5% Q26
1 2 ITP_TRST# MMBT3904_SOT23
GTL Reference Voltage

3
R314 680_0402_5% VL
+5VS +5VS +CPU_CORE <10,16,18,22,23,25,26,30,33> PCIRST#
Layout note :
If used ITP port must depop
8.2K_0402_5% 1. Place R_A and R_B near CPU (Within 1.5"). H_PROCHOT#
H_PROCHOT# <37>
2. Place decoupling cap 220PF near CPU.(Within
1

2
1 50 0mils)

2
R265 R316

G
1

R334 C174 R_A

7 H_THERMDA R333 0.1U_0402_16V4Z R337 49.9_0603_1% 1 3 47K_0402_5% 7
2 <34,36> SHDN_1632#
@10K_0402_5%

S
2

1
1
Width 10mil , Spacing 10mil 8.2K_0402_5% Trace width>=7mil
1
Q62 2 R320
2

+H_GTLREF1
C470 U57 2N7002_SOT23 470_0402_5%
1

1
2200P_0603_50V7K 2 1 1 1 Q64

3
2 D+ VDD1 R261 C319 C318 MMBT3904_SOT23 H_THERMTRIP#
2 1 2
H_THERMDC 3 6 R_B
D- ALERT# 100_0603_1% 1U_0603_10V4Z 220P_0603_50V8J Q59

3
SMB_EC_CK2 8 4 2 2 MMBT3904_SOT23
2

<8,30> SMB_EC_CK2 SCLK THERM#

SMB_EC_DA2 7 5
<8,30> SMB_EC_DA2 SDATA GND

ADM1032ARM_RM8 Dell-Compal Confidential

8
Title
Compal Electronics, Inc. 8
CPU Temperature Sensor THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Custom
Date: 星期五, 四月 25, 2003 Sheet 6 of 47
A B C D E F G H I J
 A B C D E F G H I J

Layout note : +CPU_CORE

Layout note : For DT
Place close t o CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side. Place close to CPU power and
Place 10uF caps on the peripheral near balls. gr ound pin as possible 1 1 1 1 1
Use 2~3 vias per PAD. (<1inch)
1 + C390 + C371 + C261 + C147 + C263 1
470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM

2 2 2 2 2

For Desktop's CPU: +CPU_CORE

Please place these cap in the socket cavity area ESR total=0.75m ohm
C total=6350uF
+CPU_CORE 1 1 1 1 1
For Mobile's CPU: + C352 + C259 + C148 + C149 + C150
ESR total=1.875m ohm 470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM
1 1 1 1 1 C total=2590uF 2 2 2 2 2
C407 C391 C63 C65 C294
2 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 2
2 2 2 2 2 +CPU_CORE

+CPU_CORE
1 1 1 1 1
+ C151 + C152 + C265 + C262 + C266
1 1 1 1 1 330U_D_2.5VM @330U_D2E_2.5VM 330U_D_2.5VM 330U_D_2.5VM 330U_D_2.5VM

C412 C376 C290 C282 C406 2 2 2 2 2

10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K
2 2 2 2 2

+CPU_CORE PLACE ON CPU SIDE

Please place these cap on the socket north side 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
3 1 1 1 1 1 1 1 1 1 1
3
+CPU_CORE C104 C111 C113 C117 C119 C120 C110 C112 C116 C118
2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K

C388 C408 C400 C258 C293

10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K
2 2 2 2 2 +12VALW

3
+CPU_CORE 2
<17,33> SUSP
Q29
SI2303DS_SOT23
Fan1 Control circuit
4 4
1 1 1 1 1 +5VS
+12VS Q10

1
C411 C410 C257 C402 C401 FMMT619_SOT23 C
10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 2 1 2 D14
2 2 2 2 2 R376 3.48K_0603_1% B 1SS355_SOD323
1

2
E

3
C574 2

2
0.1U_0402_16V4Z D22 C578 +5VFAN_1
+CPU_CORE 2 +5VS 1N4148_SOT23 0.1U_0402_16V4Z
1 JP12

3 1
5

1
1 C566
@1000P_0402_50V7K 1
1 1 1 1 1

P
<30> EN_FAN1 + 2
4 2 Q12 D21
C403 C405 C291 C99 O 2SA1036K_SOT23 2 3
2 1 3
-

G
10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K U10 ACES_85205-0300

2
2 2 2 2 R385 LMV321M7_SC70-5
5 5

2
13K_0603_1% 1N4148_SOT23
1 2 +3VS
2 1 R340 10K_0402_5%
Please place these cap on the socket south side
R381
FAN1_TACH <30>
7.32K_0603_1%
+CPU_CORE

1 1 1 1 1
C122 C121 C356 C62 C404
Fan2 Control circuit
10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K
2 2 2 2 2
Q8
@2SC2411K_SOT23 +5VS
6 6

1
C
+CPU_CORE 2 1 2 D11
+12VS
R11 @3.48K_0603_1% B @1SS355_SOD323

2
E

3
1 1 1 1 1 2

2
D20 +5VFAN_2
C351 C292 C368 C100 C296 +5VS @1N4148_SOT23 C234
10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K @0.1U_0402_16V4Z 1 JP19

3 1
5

1
2 2 2 2 2 1 C235
@1000P_0402_50V7K 1
1

P
<30> EN_FAN2 + 2
4 2 D6
O Q1 2 3
2 1 3
-
G
+CPU_CORE U1 @2SA1036K_SOT23 @ACES_85205-0300

2
R10 @LMV321M7_SC70-5
2

@13K_0603_1% @1N4148_SOT23
7 1 1 1 1 1 2 +3VS 7

1
2 1 R200 10K_0402_5%
C409 C64 C68 C66
10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K R6 Q63
2 2 2 2 @SM05_SOT23 FAN2_TACH <30>
@7.32K_0603_1%

3
Dell-Compal Confidential
8
Title
Compal Electronics, Inc. 8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Custom
Date: 星期五, 四月 25, 2003 Sheet 7 of 47
A B C D E F G H I J
 10 9 8 7 6 5 4 3 2 1

Mobile CPU Desktop CPU

MO/DT_CPU
H
1 0 H
+3VS
VID 4 3 2 1 0 4 3 2 1 0
CPU_VID0 2 1
VCC
<6,40> CPU_VID0
R260 1K_0402_5%
1.750V 0 0 0 0 0 0 0 1 0 0
CPU_VID1
<6,40> CPU_VID1 2
R259
1
1K_0402_5%
1.700V 0 0 0 0 1 0 0 1 1 0
CPU_VID2 2 1
1.650V 0 0 0 1 0 0 1 0 0 0
<6,40> CPU_VID2
R258 1K_0402_5%
1.600V 0 0 0 1 1 0 1 0 1 0
CPU_VID3
<6,40> CPU_VID3 2
R257
1
1K_0402_5%
1.550V 0 0 1 0 0 0 1 1 0 0
G CPU_VID4 2 1
1.500V 0 0 1 0 1 0 1 1 1 0 G
<6,40> CPU_VID4
R256 1K_0402_5%
1.450V 0 0 1 1 0 1 0 0 0 0
1.400V 0 0 1 1 1 1 0 0 1 0
1.350V 0 1 0 0 0 1 0 1 0 0
1.300V 0 1 0 0 1 1 0 1 1 0
1.250V 0 1 0 1 0 1 1 0 0 0
+CPU_CORE
1.200V 0 1 0 1 1 1 1 0 1 0
1.150V 0 1 1 0 0 1 1 1 0 0
+CPU_CORE
F 1.100V 0 1 1 0 1 1 1 1 1 0 F
1 1 1
C200 C199 C560
1
R184
2
1.5K_0603_1%
1.050V 0 1 1 1 0 X X X X X
@10U_1206_6.3V7K @0.1U_0402_16V4Z @0.1U_0402_16V4Z
2 2 2
1
R183
2
75_0603_1%
1.000V 0 1 1 1 1 X X X X X
1
R372
2
39_0603_1%
0.975V 1 0 0 0 0 X X X X X
JP15
1
R310
2
150_0603_1%
0.950V 1 0 0 0 1 X X X X X
1
3
1 2 2
4 2 1
0.925V 1 0 0 1 0 X X X X X
3 4 AGP_BUSY# <16,19>
R373 @33_0402_5%
5
7
5 6 6
8
H_ITP_DBR# <6> 0.900V 1 0 0 1 1 X X X X X
<6> ITP_BPM0 7 8
<6> ITP_BPM1 9
11
9 10 10
12
ITP_TDI <6> 0.875V 1 0 1 0 0 X X X X X
<6> ITP_PRDY# 11 12 ITP_TMS <6>
E <6> ITP_PREQ# 13
15
13 14
14
16
ITP_TRST# <6> 0.850V 1 0 1 0 1 X X X X X E
<6,9> H_RESET# 15 16 ITP_TCK <6>
<6> ITP_TCK 17
19
17 18
18
20
0.825V 1 0 1 1 0 X X X X X
<6> CLK_ITP 19 20
<6> CLK_ITP# 21
23
21 22
22
24
0.800V 1 0 1 1 1 X X X X X
23 24 ITP_TDO <6>
1 25
25 K
26 0.775V 1 1 0 0 0 X X X X X
1

1
C201 @2MM SMT KEY26
@2.2P_0402_16VCJ C198 R304
0.750V 1 1 0 0 1 X X X X X
2 @2.2P_0402_16VCJ 27.4_0603_1%
2 0.725V 1 1 0 1 0 X X X X X
0.700V 1 1 0 1 1 X X X X X

2
0.675V 1 1 1 0 0 X X X X X
D
ITP Debug Connector 0.650V 1 1 1 0 1 X X X X X D
0.625V 1 1 1 1 0 X X X X X
0.600V 1 1 1 1 1 X X X X X
VRM output off 1 1 1 1 1

C C

+5VS

1
C394
C482 @0.1U_0402_16V4Z
@0.1U_0402_16V4Z
2 1 2
U25 U23
<6,30> SMB_EC_DA2 1 8 <6,30> SMB_EC_DA2 1 8 +5VS
SDA VCC SDA VCC
<6,30> SMB_EC_CK2 2 7 <6,30> SMB_EC_CK2 2 7 1 2
SCL A0 SCL A0 R308 @10K_0402_5%
3 6 3 6
OS# A1 OS# A1
B 4 5 1 2 4 5 B
GND A2 R351 @1K_0402_5% GND A2
@LM75CIMMX-5_MSOP8 @LM75CIMMX-5_MSOP8

1
R306
@1K_0402_5%

Address:1001_000X Address:1001_000X

2
Dell-Compal Confidential
A
Title
Compal Electronics, Inc. A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Custom
Date: 星期五, 四月 25, 2003 Sheet 8 of 47
10 9 8 7 6 5 4 3 2 1
 5 4 3 2 1

DD R_SDQ[0..63]
<12> DDR_SDQ[0..63]
DD R_SDQS[0..7]
HD#[0..63] <12> DDR_SDQS[0..7]
HD#[0..63] <5> DDR_SDM[0..7]
H A#[3..31] <12> DDR_SDM[0..7]
HA#[3..31] <5> DDR_SMA[0..12]
<12,13> DDR_SMA[0..12]

U12A
<12> DDR_CLK2# DDR_CLK3 <13>
<12> DDR_CLK2 DDR_CLK3# <13>
HD#0 T30
BROOKDALE-GL/PE W31 HA#3
<12> DDR_CLK1# DDR_CLK4 <13>
HD#0 HA#3 <12> DDR_CLK1 DDR_CLK4# <13>
HD#1 R33 HOST,HUB AA33 HA#4
D HD#1 HA#4 <12> DDR_CLK0# DDR_CLK5 <13> D
HD#2 R34 AB30 HA#5
HD#3 HD#2 HA#5 HA#6 <12> DDR_CLK0 DDR_CLK5# <13>
N34 V34
HD#4 HD#3 HA#6 HA#7
R31 Y36
HD#5 HD#4 HA#7 HA#8
L33 AC33
HD#6 HD#5 HA#8 HA#9
L36 Y35
HD#6 HA#9

AM34
AN11

AN21

AN34
AK22

AP11

AP21

AP33
HD#7 HA#10

AL21

AL33
P35 AA36

AN9
AP9
HD#8 HD#7 HA#10 HA#11 U12B
J36 AC34
HD#9 HD#8 HA#11 HA#12
K34 AB34
HD#10 HD#9 HA#12 HA#13 DDR_SDQ0 AN4 DDR_SMA12
K36 Y34 AN15

SCMD_CLK0
SCMD_CLK0#
SCMD_CLK1
SCMD_CLK1#
SCMD_CLK2
SCMD_CLK2#
SCMD_CLK3
SCMD_CLK3#
SCMD_CLK4
SCMD_CLK4#
SCMD_CLK5
SCMD_CLK5#
HD#11 HD#10 HA#13 HA#14 DDR_SDQ1 AP2 SDQ_0 SMAA12/BS0 DDR_SMA11
M30 AB36 AL15
HD#12 HD#11 HA#14 HA#15 DDR_SDQ2 AT3 SDQ_1 SMAA11/DQS8 DDR_SMA10
M35 AC36 AK26
HD#13 HD#12 HA#15 HA#16 DDR_SDQ3 AP5 SDQ_2 SMAA10/DQ31 DDR_SMA9
L34 HD#13 HA#16 AC31 SDQ_3 SMAA9/SMA3 AK16
HD#14 K35 AF35 HA#17 DDR_SDQ4 AN2 AN17 DDR_SMA8
HD#15 HD#14 HA#17 HA#18 DDR_SDQ5 AP3 SDQ_4 SMAA8/SMA4 DDR_SMA7
H36 HD#15 HA#18 AD36 SDQ_5 SMAA7/SMA6 AP17
HD#16 G34 AD35 HA#19 DDR_SDQ6 AR4 AP19 DDR_SMA6
HD#17 HD#16 HA#19 HA#20 DDR_SDQ7 AT4 SDQ_6 SMAA6/SDQ29 DDR_SMA5
G36 HD#17 HA#20 AE34 SDQ_7 SMAA5/SMA8 AL17
HD#18 J33 AD34 HA#21 DDR_SDQ8 AT5 AL19 DDR_SMA4
HD#19 HD#18 HA#21 HA#22 DDR_SDQ9 AR6 SDQ_8 SMAA4/SMA11 DDR_SMA3
D35 HD#19 HA#22 AE36 SDQ_9 SMAA3/SMA7 AK20
HD#20 F36 AF36 HA#23 DDR_SDQ10 AT9 AP23 DDR_SMA2
HD#21 HD#20 HA#23 HA#24 DDR_SDQ11 AR10 SDQ_10 SMAA2/SMA9 DDR_SMA1
F34 HD#21 HA#24 AE33 SDQ_11 SMAA1/SDQ19 AN25
HD#22 E36 AF34 HA#25 DDR_SDQ12 AT6 AL25 DDR_SMA0
HD#23 HD#22 HA#25 HA#26 DDR_SDQ13 AP6 SDQ_12 SMAA0/SMA12 DDR_SMAB5
H34 HD#23 HA#26 AG34 SDQ_13 SMAB5 AK18 DDR_SMAB5 <13>
HD#24 F35 AG36 HA#27 DDR_SDQ14 AT8 AN19 DDR_SMAB4
HD#25 HD#24 HA#27 HA#28 DDR_SDQ15 AP8 SDQ_14 SMAB4 DDR_SMAB2 DDR_SMAB4 <13>
D36 HD#25 HA#28 AE31 SDQ_15 SMAB2 AN23 DDR_SMAB2 <13>
HD#26 H35 AH35 HA#29 DDR_SDQ16 AP10 AP25 DDR_SMAB1
HD#27 HD#26 HA#29 HA#30 DDR_SDQ17 AT11 SDQ_16 SMAB1 DDR_SMAB1 <13>
E33 HD#27 HA#30 AG33 SDQ_17
HD#28 E34 AG31 HA#31 DDR_SDQ18 AT13 AP27 DDR_SBS1
HD#29 HD#28 HA#31 DDR_SDQ19 AT14 SDQ_18 SBA1 DDR_SBS0 DDR_SBS1 <12,13>
B35 HD#29 SDQ_19 SBA0 AN27 DDR_SBS0 <12,13>
HD#30 G31 AB35 DDR_SDQ20 AT10
HD#30 HADSTB0# H_ADSTB#0 <6> SDQ_20
HD#31 C36 AF30 DDR_SDQ21 AR12 AR2 DDR_SDQS0
HD#32 D33
HD#31 HADSTB1# H_ADSTB#1 <6> DDR_SDQ22 AR14 SDQ_21 BROOKDALE-GL/PE SDQS0
AT7 DDR_SDQS1
HD#33 HD#32 DDR_SDQ23 AP14 SDQ_22 SDQS1 DDR_SDQS2
C HD#34
D30
D29
HD#33 HIT# P36
M36
H_HIT# <5> DDR_SDQ24 AT15 SDQ_23 DDR SDQS2 AT12
AT17 DDR_SDQS3 C
HD#35 HD#34 HITM# H_HITM# <5> DDR_SDQ25 AP16 SDQ_24 SDQS3 DDR_SDQS4
E31 HD#35 ADS# T36 H_ADS# <5> SDQ_25 SDQS4 AR24
HD#36 D32 T34 DDR_SDQ26 AT18 AT29 DDR_SDQS5
HD#37 HD#36 BNR# H_BNR# <5> DDR_SDQ27 AT19 SDQ_26 SDQS5 DDR_SDQS6
C34 HD#37 BPRI# M34 H_BPRI# <5> SDQ_27 SDQS6 AT34
HD#38 B34 U33 DDR_SDQ28 AR16 AL36 DDR_SDQS7
HD#39 HD#38 BREQ0# H_BREQ0# <5> DDR_SDQ29 AT16 SDQ_28 SDQS7
D31 HD#39 DBSY# U31 H_DBSY# <6> SDQ_29
HD#40 G29 N36 DDR_SDQ30 AP18 AP4 DDR_SDM0
HD#40 DEFER# H_DEFER# <5> SDQ_30 SDM0
HD#41 C32 U36 DDR_SDQ31 AR20 AR8 DDR_SDM1
HD#42 HD#41 DRDY# H_DRDY# <6> DDR_SDQ32 AR22 SDQ_31 SDM1 DDR_SDM2
B31 V30 H_TRDY# <6> AP12
HD#43 HD#42 HTRDY# DDR_SDQ33 AP22 SDQ_32 SDM2 DDR_SDM3
B32 T35 H_LOCK# <5> AR18
HD#44 HD#43 HLOCK# DDR_SDQ34 AP24 SDQ_33 SDM3 DDR_SDM4
B30 AT24
HD#45 HD#44 DDR_SDQ35 AT26 SDQ_34 SDM4 DDR_SDM5
B29 C26 H_DBI#3 <6> AP28
HD#46 HD#45 DINV3 DDR_SDQ36 AT22 SDQ_35 SDM5 DDR_SDM6
E27 B33 H_DBI#2 <6> AR34
HD#47 HD#46 DINV2 DDR_SDQ37 AT23 SDQ_36 SDM6 DDR_SDM7
C28 C35 H_DBI#1 <6> AL34
HD#48 HD#47 DINV1 DDR_SDQ38 AT25 SDQ_37 SDM7
B27 N33 H_DBI#0 <6>
HD#49 HD#48 DINV0 DDR_SDQ39 AR26 SDQ_38 DDR_CKE3
D26 AL13 DDR_CKE3 <13>
HD#50 HD#49 DDR_SDQ40 AP26 SDQ_39 SCKE3/SCK#5 DDR_CKE2
D28 V36 H_REQ#0 <5> AK14 DDR_CKE2 <13>
HD#51 HD#50 HREQ0# DDR_SDQ41 AT28 SDQ_40 SCKE2/RSVD DDR_CKE1
B26 AA31 H_REQ#1 <5> AN13 DDR_CKE1 <12>
HD#52 HD#51 HREQ1# DDR_SDQ42 AR30 SDQ_41 SCKE1/SDQ58 DDR_CKE0
G27 W33 H_REQ#2 <5> AP13 DDR_CKE0 <12>
HD#53 HD#52 HREQ2# DDR_SDQ43 AP30 SDQ_42 SCKE0/RSVD
H26 AA34 H_REQ#3 <5>
HD#54 HD#53 HREQ3# DDR_SDQ44 AT27 SDQ_43
B25 W35 H_REQ#4 <5>
HD#55 HD#54 HREQ4# DDR_SDQ45 AR28 SDQ_44 DDR_SCS#0
C24 HI[0..10] <18> AL29 DDR_SCS#0 <12>
HD#56 HD#55 H I10 DDR_SDQ46 AT30 SDQ_45 SCS#0/SCKE2 DDR_SCS#1
B23 AF2 AP31 DDR_SCS#1 <12>
HD#57 HD#56 HI10 HI9 DDR_SDQ47 AT31 SDQ_46 SCS#1/RSVD DDR_SCS#2
B24 AE2 AK30 DDR_SCS#2 <13>
HD#58 HD#57 HI9 HI8 DDR_SDQ48 AR32 SDQ_47 SCS#2/SCK#2 DDR_SCS#3
E23 AF3 AN31 DDR_SCS#3 <13>
HD#59 HD#58 HI8 HI7 DDR_SDQ49 AT32 SDQ_48 SCS#3/SCAS#
C22 AE5
HD#60 HD#59 HI7 HI6 DDR_SDQ50 AR36 SDQ_49 DDR_SRAS#
G25 AE4 AK28 DDR_SRAS# <12,13>
HD#61 HD#60 HI6 HI5 DDR_SDQ51 AP35 SDQ_50 SRAS#/SCKE0 DDR_SCAS#
B22 AF4 AN29 DDR_SCAS# <12,13>
HD#62 HD#61 HI5 HI4 DDR_SDQ52 AP32 SDQ_51 SCAS#/RSVD DDR_SWE#
D24 AD8 AP29 DDR_SWE# <12,13>
HD#63 HD#62 HI4 HI3 DDR_SDQ53 AT33 SDQ_52 SWE#/SDQ5
G23 AC5
HD#63 HI3 HI2 DDR_SDQ54 AP34 SDQ_53 RDCLKO
HI2
AC7
SDQ_54 SRCVEN_OUT#
AK24 RDCLKI & RDCLKO 100mils
L31 AB8 HI1 DDR_SDQ55 AT35 AL23 R DCLKI 2 1
B <6> H_DSTBP#0 HDSTBP0# HI1 HI0 DDR_SDQ56 AN36 SDQ_55 SRCVEN_IN# LENGTH 5mils WIDTH B
J34 AA7 R297 @0_0603_5%
<6> H_DSTBP#1 HDSTBP1# HI0 SDQ_56
E29 DDR_SDQ57 AM36 AJ34 2 1
<6> H_DSTBP#2 HDSTBP2# DDR_SDQ58 AK36 SDQ_57 SMY_RCOMP +2.5V
<6> H_DSTBP#3 E25 AD4 HUB_PSTRB <18>
HDSTBP3# HI_STBS DDR_SDQ59 AJ36 SDQ_58 R298
<6> H_DSTBN#0 N31 AC4 HUB_PSTRB# <18> AM2 1 2 SDREF
HDSTBN0# HI_STBF DDR_SDQ60 AP36 SDQ_59 SM_VREF 60.4_0603_1%
<6> H_DSTBN#1 G33
HDSTBN1# DDR_SDQ61 AM35 SDQ_60 R299
<6> H_DSTBN#2 C30 P34 H_RS#2 <6> 1
HDSTBN2# RS2# SDQ_61

1
D25 U34 DDR_SDQ62 AK35 0_0603_5% 1
<6> H_DSTBN#3 HDSTBN3# RS1# H_RS#1 <6> DDR_SDQ63 AK34 SDQ_62
R36 C364 R292 C357
RS0# H_RS#0 <6> SDQ_63 0.1U_0402_10V6K 0.1U_0402_10V6K
D22 60.4_0603_1%
<6,8> H_RESET# CPURST# 2
1 R18 2 BROOKDALE-GL/PE_760P
K30 24.9_0603_1% 2

2
<15> CLK_MCH_BCLK HCLK
J31 B28 HX_RCOMP 10 mil 1 R263 2
<15> CLK_MCH_BCLK# HCLK# HX_RCOMP HY_RCOMP 10 mil
D27 V35 24.9_0603_1%
HD_VREF2 HY_RCOMP
H24 H28 H_XY_SWING <11>
HD_VREF1 HX_SWING
<11> MCH_GTLREF H30 Y30
HD_VREF0 HY_SWING
AD30 AD3 HUB_VREF <11,18>
HA_VREF HI_VREF
P30 AC2 1 2 +1.5VS
HCC_VREF HI_RCOMP R295 68_0603_1%
1 1 1 AD2 HUB_VSWING <11,18>
HI_SWING
C335 C304 C274 BROOKDALE-GL/PE_760P
0.1U_0402_10V6K 1 1
2 2 2 0.1U_0402_10V6K
82845GL-INT VGA C302 C327
0.1U_0402_10V6K 0.1U_0402_10V6K
2 2
82845PE-EXT VGA
0.1U_0402_10V6K

Close to H28 Close to Y30

A A

Layout note :
1. HX_RCOMP, HY_RCOMP Trace width 10 mil. Dell-Compal Confidential
2. Terminator Max 500 mil.
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 9 of 47
5 4 3 2 1
 A B C D E

AGP_AD[0..31] +1.5VS
<16> AGP_AD[0..31]
AGP_SBA[0..7] Place close to pin D14
<16> AGP_SBA[0..7]
CLK_MCH_DISPLAY +2.5V

AB10
P10
V10
1

W9
G1
C1
D4
D6

R1
R9
U12C U12D

A3
A7

K6

P6

V6
L1
L9
R234
AGP_PIPE# H8 AGP/DVO V4 AGP_AD0 10_0402_5%

VCCAGP0
VCCAGP1
VCCAGP2
VCCAGP3
VCCAGP4
VCCAGP5
VCCAGP6
VCCAGP7
VCCAGP8
VCCAGP9
VCCAGP10
VCCAGP11
VCCAGP12
VCCAGP13
VCCAGP14
VCCAGP15
VCCAGP16
<16> AGP_PIPE# AGP_SBA0 GPIPE# GAD0/DVOBHSYNC AGP_AD1
C3 GSBA0/ADDIN0 GAD1/DVOBVSYNC V2
AGP_SBA1 C2 W4 AGP_AD2 Y19 AH8 100U_D2_6.3VM

2
AGP_SBA2 GSBA1/ADDIN1 GAD2/DVOBD1 AGP_AD3 VCC1 VCCSM0
D3 W5 1 AA19 AK8 1 1 1
AGP_SBA3 GSBA2/ADDIN2 GAD3/DVOBD0 AGP_AD4 C249 VCC2 VCCSM1
D2 U5 W20 AG9
AGP_SBA4 GSBA3/ADDIN3 GAD4/DVOBD3 AGP_AD5 5P_0402_50V8C VCC3 VCCSM2 + + +
E4 U4 U21 AJ9
A AGP_SBA5 GSBA4/ADDIN4 GAD5/DVOBD2 AGP_AD6 VCC4 VCCSM3 C340 C399 C159 A
E2 U2 W21 AL9
AGP_SBA6 GSBA5/ADDIN5 GAD6/DVOBD5 AGP_AD7 2 VCC5 VCCSM4 100U_D2_6.3VM
F3 V3 AA21 AM22
AGP_SBA7 GSBA6/ADDIN6 GAD7/DVOBD4 AGP_AD8 VCC6 VCCSM5 2 2 2
F2 T2 A9 AJ23
GSBA7/ADDIN7 GAD8/DVOBD6 AGP_AD9 VCC7 VCCSM6
T3 B9 AL37
GAD9/DVOBD9 AGP_AD10 VCC8 VCCSM7 100U_D2_6.3VM
<16> AGP_WBF# G5 T4 C9 AU9
GWBF# GAD10/DVOBD8 AGP_AD11 VCC9 VCCSM8
<16> AGP_RBF# G7 R2 D9 AK10
GRBF# GAD11/DVOBD11 AGP_AD12 VCC10 VCCSM9
BROOKDALE-GL/PE GAD12/DVOBD10 R5 E9
VCC11 VCCSM10
AJ11
AGP_ST0 C4 R7 AGP_AD13 Place close to pin AE7 B10 AL11
<16> AGP_ST0 AGP_ST1 GST0 GAD13/DVOBCCLKINT# AGP_AD14 VCC12 VCCSM11
<16> AGP_ST1 B4 T8 C10 AU25
AGP_ST2 GST1 GAD14/DVOBFLDSTL AGP_AD15 CLK_MCH_66M VCC13 VCCSM12
<16> AGP_ST2 B3 P3 D10 AM26
GST2 GAD15/MDDC CLK AGP_AD16 VCC14 VCCSM13
P8 F10 AU13
GAD16/DVOCVSYNC VCC15 VCCSM14

1
V8 K4 AGP_AD17 H10 AM14
<16> AGP_ADSTB0 GAD_STB0/DVOBCLK GAD17/DVOCHSYNC AGP_AD18 VCC16 VCCSM15
U7 K2 R286 A11 AJ27
<16> AGP_ADSTB0# GAD_STB0#/DVOBCLK# GAD18/DVOCBLANK# VCC17 VCCSM16
M8 J2 AGP_AD19 22_0402_5% B11 AJ1
<16> AGP_ADSTB1 GAD_STB1/DVOCCLK GAD19/DVOCD0 AGP_AD20 VCC18 VCCSM17
<16> AGP_ADSTB1# L7 GAD_STB1#/DVOCCLK# GAD20/DVOCD1 M3 C11 VCC19 VCCSM18 AL1
F4 L5 AGP_AD21 D11 AJ15

2
<16> AGP_SBSTB GSBSTB GAD21/DVOCD2 AGP_AD22 VCC20 VCCSM19
<16> AGP_SBSTB# E5 GSBSTB# GAD22/DVOCD3 L4 1 E11 VCC21 VCCSM20 AP15
H4 AGP_AD23 C333 G11 AU29
GAD23/DVOCD4 AGP_AD24 10P_0402_50V8K VCC22 VCCSM21
<16> AGP_FRAME# M4 G_FRAME#/MDVI DATA GAD24/DVOCD7 G2 J11 VCC23 VCCSM22 AH2
N7 K3 AGP_AD25 B12 AJ2
<16> AGP_IRDY# G_IRDY#/MI2C CLK GAD25/DVOCD6 2 VCC24 VCCSM23
N5 J4 AGP_AD26 C12 AK2
<16> AGP_TRDY# G_TRDY#/MDVI CLK GAD26/DVOCD9 AGP_AD27 VCC25 VCCSM24
P2 J5 D12 AL2
<16> AGP_STOP#
N2
G_STOP#/MDDC DATA GAD27/DVOCD8
J7 AGP_AD28 F12
VCC26 BROOKDALE-GL/PE VCCSM25
AM30
<16> AGP_DEVSEL# G_DEVSEL#/MI2C DATA GAD28/DVOCD11 AGP_AD29 VCC27 VCCSM26
<16> AGP_REQ# D5 G_REQ# GAD29/DVOCD10 H3 H12 VCC28 POWER VCCSM27 AH3
P4 K8 AGP_AD30 G13 AJ3
<16> AGP_PAR G_PAR/ADD_DETECT GAD30/DVOBCINTR# AGP_AD31 VCC29 VCCSM28
<16> AGP_GNT# B5 G_GNT# GAD31/DVOCFLDSTL G4 J13 VCC30 VCCSM29 AK3
AGP_C/BE#3 H2 H14 AL3
<16> AGP_C/BE#3 GCBE3#/DVOCD5 VCC31 VCCSM30

1
AGP_C/BE#2 M2 J15 AH4
<16> AGP_C/BE#2 AGP_C/BE#1 GCBE2# VCC32 VCCSM31
N4 AE7 AA17 AJ4 L27
<16> AGP_C/BE#1 GCBE1#/DVOBBLANK# GCLKIN CLK_MCH_66M <15> VCC33 VCCSM32
AGP_C/BE#0 R4 AJ31 RSTIN# W17 AK4 KC FBM-L11-201209-221LMAT_0805
<16> AGP_C/BE#0 GCBE0#/DVOBD7 RSTIN# VCC34 VCCSM33
DREFCLK D14 CLK_MCH_DISPLAY <15> U17 VCC35 VCCSM34 AL4
L2 E7 R270 W18 AU17
B AGP RCOMP/DVOBCRCOMP PWROK PM_PWROK <19,30,32> VCC36 VCCSM35 B
W2 Y3 1 2 V19 AJ5

2
+AGPREF AGP_VREF PSBSEL H_SEL0 <15> VCC37 VCCSM36
47.5_0603_1% 8.2K_0402_5% U19 AL5
R215 1 INTCRT_B VCC38 VCCSM37
<16> INT_HSYNC 2 B7 HSYNC BLUE G15 INTCRT_B <16> K10 VCC39 VCCSM38 AU5
1 2 C6 ANALOG DISPLAY H16 INTCRT_B# K12 AM18 +1.5VS
<16> INT_VSYNC VSYNC BLUE# INTCRT_G +CPU_CORE VCC40 VCCSM39
R214 D7 E15 K14 AJ19
<16> INTDDCCK DDCA_CLK GREEN INTCRT_G# INTCRT_G <16> VCC41 VCCSM40
47.5_0603_1% C7 F16 K16 AK32
<16> INTDDCDA DDCA_DATA GREEN# VCC42 VCCSM41
B16 C15 INTCRT_R W19 AU33 1
REFSET RED INTCRT_R <16> VCC43 VCCSM42
D16 INTCRT_R# AH6 C334
RED# VCCSM43
1

KC FBM-L11-201209-221LMAT_0805
0.1U_0402_10V6K
B18 AK6 4.7U_0805_10V4Z
VTTFSB0 VCCSM44
1

1
R17 1 BROOKDALE-GL/PE_760P C18 AP20
VTTFSB1 VCCSM45

1
137_0603_1% R241 R273 D18 AG7 2
VTTFSB2 VCCSM46 1

C385
36.5_0603_1% C324 8.2K_0402_5% H18 AJ7
VTTFSB3 VCCSM47

L28
0.1U_0402_10V6K B19 AL7
2

VTTFSB4 VCCSM48

1
2 C19 AP7
2

2 VTTFSB5 VCCSM49
D19 AH10 2 R281 VCCA_DAC
VTTFSB6 VCCSM50 1_0402_5%
E19 AH12

2
VTTFSB7 VCCSM51

0.01U_0402_25V4Z
0.1U_0402_10V6K
G19 AH14 1 1
VTTFSB8 VCCSM52

C268

C267
J19 AH18

2
VTTFSB9 VCCSM53
B20 AH22
VTTFSB10 VCCSM54
PSBSEL FSB FREQUENCY C20
VTTFSB11 VCCSM55
AH26
2 2
D20
VTTFSB12 VCCA_SM 0.1U_0402_10V6K
F20 AG1
VTTFSB13 VCCA_SM0
* 0 400 MHZ H20
VTTFSB14 VCCA_SM1
AG2 1 1 1
F18
VTTFSB15 C640 C353 + C336
K18 AT20
VTTFSB16 VCCQSM0
1 533 MHZ K20
VTTFSB17 VCCQSM1
AT21
2 2
100U_D2_6.3VM
K22 AU21
VTTFSB18 VCCQSM2 2
K26
VTTFSB19 0.1U_0402_10V6K
M28 A31
VTTFSB20 VTTDECAP0 0.1U_0402_10V6K
T28 AC37
VTTFSB21 VTTDECAP1
Y28 R37
VTTFSB22 VTTDECAP2 0.1U_0402_10V6K
AD28 L37
C R277 VTTFSB23 VTTDECAP3 C
G37
L3 VTTDECAP4
+1.5VS 2 1 AB2
TESTIN#
KC FBM-L11-201209-221LMAT_0805 Y2 A17 VCCA_FSB 1 1 1 1 1
VCCA_DPLL 1.5K_0402_5% MEM_SEL VCCA_FSB
+1.5VS 1 2
1 A37 AD10 C277 C297 C316 C332 C32
RSVD0 VCCA_HI
1 1 AB3 AD6
+ RSVD1 VCCHI0 2 2 2 2 2
AA2 AC9
C29 C22 C251 RSVD2 VCCHI1
AA3 AC1 +1.5VS
22U_1206_10V4Z 150U_D2_6.3VM 0.1U_0402_10V6K RSVD3 VCCHI2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AA4 AE3
R43 2 2 2 RSVD4 VCCHI3
AA5
0_0402_5% RSVD5 VCCA_DPLL
Y4 A13
RSTIN# RSVD6 VCCA_DPLL
2 1 PCIRST# <6,16,18,22,23,25,26,30,33> Y8 B6 +3VS
RSVD7 VCCGPIO
W7 B14
L4 RSVD8 VCCA_DAC0 VCCA_DAC
A15 1
KC FBM-L11-201209-221LMAT_0805 VCCA_DAC1
1 2 AU37
NC
1 2 VCCA_FSB AU36 AF10 2 1 C270
+1.5VS NC SMX_RCOMP +2.5V 0.1U_0402_10V6K
C69 AT37
@15P_0402_50V8J NC R287 2
AU2 A2
NC NC 60.4_0603_1%
1 1 1 AU1 A36 1
NC NC

1
AT1 B37
C27 C28 C33 NC NC R283 C344
AJ35 B1
0.1U_0402_10V6K 22U_1206_10V4Z 0.1U_0402_10V6K NC NC 60.4_0603_1% 0.1U_0402_10V6K
AH34
2 2 2 NC 2
BROOKDALE-GL/PE_760P

2
INTCRT_B#

INTCRT_G# +1.5VS

INTCRT_R# 1 1
C343 C341
D 0.1U_0402_10V6K 0.1U_0402_10V6K D
2 2

NEAR AA1
NEAR AE1
Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 10 of 47
A B C D E
 5 4 3 2 1

HUB_VSWING <9,18>
R264 R312 10 mil Trace,
226_0603_1% 100_0603_1% 7 mil Space
1 2 0.01U_0402_25V4Z 1 2 0.01U_0402_25V4Z
HUB_VREF <9,18>
+1.5VS

1
1 1 1 1 1 1
C126 PLACE NOTE: R309 C392
C337 C393 CAP PLACE C339 C125
0.01U_0402_25V4Z 0.1U_0402_10V6K 0.01U_0402_25V4Z
2 2 2 AT MIDPOINT 2 2 2

AR17

AH30
AJ17

AM3
AG4

AG3
AR9

AU3
AR3
AN3

AC3
AB4

G17
C31
Y17

V17

E17

2
J17
OF THE BUS. 100_0603_1%
U12E
AM10 C17

VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS0 VSS129 0.1U_0402_10V6K
AR23
VSS1 VSS130
B17 NEAR MCH NEAR ICH NEAR MCH NEAR ICH
D D
AU23 AM16
VSS2 VSS131
F24
VSS3 VSS132
W3 Within 250mil Within 250mil
AM24 U3
VSS4 VSS133
A25 R3
VSS5 VSS134
C16 D17
VSS6 VSS135
N37 N3
VSS7 VSS136
U18
VSS8 VSS137
L3 10 mil Trace,
V18 J3 7 mil Space
VSS9 VSS138
Y18 G3 +CPU_CORE 1 2 MCH_GTLREF <9>
VSS10 VSS139 R245 49.9_0603_1%
AA18 E3
VSS11 VSS140

1
AL31 AT2 1
VSS12 VSS141
AR31 VSS13 VSS142 F30
AU31 AR29 R244 C299
VSS14 VSS143 100_0603_1% 0.1U_0402_10V6K
F32 VSS15 VSS144 AJ29
2
H32 AG29

2
VSS16 VSS145
K32 VSS17 VSS146 AE29
M32 VSS18 VSS147 AC29 FSB DECOUPLING
P32 AA29 +CPU_CORE
VSS19 VSS148
T32 VSS20 VSS149 W29 NEAR MCH
V32 VSS21 VSS150 R29
Y32 U29 10U_1206_6.3V7K 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS22 VSS151
AB32 VSS23 VSS152 N29
AD32 VSS24 BROOKDALE-GL/PE VSS153 L29 1 1 1 1 1 1 1
AF32 VSS25 VSS154 J29
AH32 VSS26 VSS VSS155 C29 C245 C246 C253 C255 C254 C252 C250
AM4 A29 0.1U_0402_10V6K
VSS27 VSS156 2 2 2 2 2 2 2
A5 VSS28 VSS157 AU15
C5 VSS29 VSS158 AR15 10 mil Trace,
AG5 D15 10U_1206_6.3V7K 0.1U_0402_10V6K 0.1U_0402_10V6K 7 mil Space
VSS30 VSS159 R246
AN5 VSS31 VSS160 B2
AR5 VSS32 VSS161 AR1 +CPU_CORE 2 1 H_XY_SWING <9>
AR19 VSS33 VSS162 AN1

2
C 301_0603_1% C
AM32 VSS34 VSS163 AE1 1
A33 AA1 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS35 VSS164 R247 C309
C33 VSS36 VSS165 U1
AJ33 N1 1 1 1 1 1 150_0603_1% 0.01U_0402_25V4Z
VSS37 VSS166 2
AN33 J1

1
VSS38 VSS167 C288 C281 C279 C284 C289
AR33 VSS39 VSS168 E1
F6 AM28 0.1U_0402_10V6K
VSS40 VSS169 2 2 2 2 2
H6 F28
VSS41 VSS170
M6 AU27
VSS42 VSS171 0.1U_0402_10V6K 0.1U_0402_10V6K
T6 AR27
VSS43 VSS172
Y6 AL27
VSS44 VSS173
AB6 F14
VSS45 VSS174
AF6 AR13
VSS46 VSS175
AM6 AJ13
VSS47 VSS176
U20 J27
VSS48 VSS177
V20
VSS49 VSS178
C27 SYSTEM MEMORY DECOUPLING
Y20 A27
VSS50 VSS179 +2.5V
AA20 E13
VSS51 VSS180 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AM20 D13
VSS52 VSS181
A21 C13
VSS53 VSS182
B21 B13 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VSS54 VSS183
C21 AM12
VSS55 VSS184 C345 C346 C348 C349 C350 C370 C359 C347 C363 C362 C373 C374 C361 C358
D21 AK12
VSS56 VSS185
E21 F26
VSS57 VSS186 2 2 2 2 2 2 2 2 2 2 2 2 2 2
G21 AR25
VSS58 VSS187
J21 AJ25
VSS59 VSS188 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
D34 J25
VSS60 VSS189
W34 AU11
VSS61 VSS190
A35 AR11
VSS62 VSS191 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
E35 AR37
VSS63 VSS192
G35 AN37
VSS64 VSS193
J35 C25 1 1 1 1 1 1 1 1 1 1 1 1 1
B VSS65 VSS194 B
L35 AJ37
VSS66 VSS195 C360 C367 C378 C380 C379 C383 C384 C381 C382 C366 C338 C354 C365
AN7 AG37
VSS67 VSS196 0.1U_0402_10V6K
AR7 AE37
VSS68 VSS197 2 2 2 2 2 2 2 2 2 2 2 2 2
AU7 AA37
VSS69 VSS198
B8 U37
VSS70 VSS199 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C8 AH28
VSS71 VSS200
D8 AF28
VSS72 VSS201
F8 AB28
VSS73 VSS202
V21 V28
VSS74 VSS203
Y21 P28
VSS75 VSS204
AJ21
VSS76 VSS205
K28 GMCH DECOUPLING
AR21 K24
VSS77 VSS206 +1.5VS
F22 J37
VSS78 VSS207 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
H22 E37
VSS79 VSS208
M10 C37
VSS80 VSS209
T10 AT36 1 1 1 1 1 1 1 1 1 1 1 1 1
VSS81 VSS210
Y10 AH36
VSS82 VSS211 C326 C329 C322 C331 C308 C330 C328 C271 C278 C298 C256 C342 C280
AH16
VSS83
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110

AH20 B15
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

VSS84 VSSA_DAC0 2 2 2 2 2 2 2 2 2 2 2 2 2
AH24 C14
VSS85 VSSA_DAC1
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
BROOKDALE-GL/PE_760P
N35
R35
U35
AA35
AC35
AE35
AG35
AL35
AN35
AR35
AU35
B36
W36
AF8
AM8
G9
J9
N9
U9
AA9
AE9
A23
C23
D23
J23

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

1 1 1 1 1 1 1 1 1 1 1 1 1
C301 C300 C285 C269 C276 C275 C260 C307 C295 C287 C311 C286 C283
2 2 2 2 2 2 2 2 2 2 2 2 2
A A
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 11 of 47
5 4 3 2 1
 A B C D E F G H

+2.5V
SDREF_DIMM
RP32 10_4P2R_0402_5% RP46 10_4P2R_0402_5% +2.5V
DDR_SDQ4 1 4 DDR_DQ4 DDR_SDQ30 1 4 DDR_DQ30 JP22 R322
DDR_SDQ0 2 3 DDR_DQ0 DDR_SDQ26 2 3 DDR_DQ26 1 2 20mil 2 1
VREF VREF SDREF
3 VSS VSS 4 1
DDR_DQ5 5 6 DDR_DQ0 0_0402_5%
RP42 10_4P2R_0402_5% RP37 10_4P2R_0402_5% DDR_DQ1 DQ0 DQ4 DDR_DQ4 C413 DDR _DQ[0..63]
7 DQ1 DQ5 8 DDR_DQ[0..63] <13>
DDR_SDQ1 1 4 DDR_DQ1 DDR_SDQ31 1 4 DDR_DQ31 9 10 0.1U_0402_16V4Z
DDR_SDQ5 DDR_DQ5 DDR_SDQ27 DDR_DQ27 DDR_DQS0 VDD VDD DDR_DM0 2 DDR _DQS[0..7]
2 3 2 3 11 DQS0 DM0 12 DDR_DQS[0..7] <13>
DDR_DQ2 13 14 DDR_DQ7
DQ2 DQ6 D DR_DM[0..7]
15 VSS VSS 16 DDR_DM[0..7] <13>
RP33 10_4P2R_0402_5% R124 10_0402_5% DDR_DQ6 17 18 DDR_DQ3
DDR_SDQ6 DDR_DQ6 DDR_SDM0 DDR_DM0 DDR_DQ8 DQ3 DQ7 DDR_DQ12 DDR_SMAA[0..12]
1 4 2 1 19
DQ8 DQ12
20 DDR_SMAA[0..12]
DDR_SDQ2 2 3 DDR_DQ2 DDR_SDM1 2 1 DDR_DM1 21 22
1 R117 10_0402_5% DDR_DQ9 VDD VDD DDR_DQ13 1
23 24
DDR_DQS1 DQ9 DQ13 DDR_DM1
25 26
RP43 10_4P2R_0402_5% R126 10_0402_5% DQS1 DM1
27 28
DDR_SDQ3 DDR_DQ3 DDR_SDM2 DDR_DM2 DDR_DQ14 VSS VSS DDR_DQ10 DDR_SMA0 DDR_SMAA0
1 4 2 1 29 30 2 1
DDR_SDQ7 DDR_DQ7 DDR_SDM3 DDR_DM3 DDR_DQ15 DQ10 DQ14 DDR_DQ11 R167 10_0402_5%
2 3 2 1 31 32
R121 10_0402_5% DQ11 DQ15 DDR_SMA1 DDR_SMAA1
33 34 2 1
VDD VDD R134 10_0402_5%
<9> DDR_CLK1 35 36
RP20 10_4P2R_0402_5% R108 10_0402_5% CK0 VDD DDR_SMA2 DDR_SMAA2
<9> DDR_CLK1# 37 38 2 1
DDR_SDQ9 DDR_DQ9 DDR_SDM4 DDR_DM4 CK0# VSS R132 10_0402_5%
1 4 2 1 39
VSS VSS
40
DDR_SDQ8 2 3 DDR_DQ8 DDR_SDM5 2 1 DDR_DM5 DDR_SMA3 2 1 DDR_SMAA3
R113 10_0402_5% R149 10_0402_5%
DDR_DQ20 41 42 DDR_DQ17 DDR_SMA4 2 1 DDR_SMAA4
RP31 10_4P2R_0402_5% R115 10_0402_5% DDR_DQ16 DQ16 DQ20 DDR_DQ21 R135 10_0402_5%
43 DQ17 DQ21 44
DDR_SDQ13 1 4 DDR_DQ13 DDR_SDM6 2 1 DDR_DM6 45 46 DDR_SMA5 2 1 DDR_SMAA5
DDR_SDQ12 DDR_DQ12 DDR_SDM7 DDR_DM7 DDR_DQS2 VDD VDD DDR_DM2 R140 10_0402_5%
2 3 2 1 47 DQS2 DM2 48
R118 10_0402_5% DDR_DQ18 49 50 DDR_DQ19 DDR_SMA6 2 1 DDR_SMAA6
DQ18 DQ22 R152 10_0402_5%
51 VSS VSS 52
DDR_DQ22 53 54 DDR_DQ23 DDR_SMA7 2 1 DDR_SMAA7
DDR_DQ24 DQ19 DQ23 DDR_DQ29 R116 10_0402_5%
55 DQ24 DQ28 56
57 58 DDR_SMA8 2 1 DDR_SMAA8
DDR_DQ28 VDD VDD DDR_DQ25 R137 10_0402_5%
59 DQ25 DQ29 60
DDR_DQS3 61 62 DDR_DM3 DDR_SMA9 2 1 DDR_SMAA9
RP21 10_4P2R_0402_5% RP16 10_4P2R_0402_5% DQS3 DM3 R148 10_0402_5%
63 VSS VSS 64
DDR_SDQ15 1 4 DDR_DQ15 DDR_SDQ37 1 4 DDR_DQ37 DDR_DQ26 65 66 DDR_DQ27 DDR_SMA10 2 1 DDR_SMAA10
DDR_SDQ14 DDR_DQ14 DDR_SDQ32 DDR_DQ32 DDR_DQ30 DQ26 DQ30 DDR_DQ31 R146 10_0402_5%
2 3 2 3 67 68
DQ27 DQ31 DDR_SMA11 2 DDR_SMAA11
69 VDD VDD 70 1
71 72 R151 10_0402_5%
RP40 10_4P2R_0402_5% RP28 10_4P2R_0402_5% CB0 CB4 DDR_SMA12 2 DDR_SMAA12
73 CB1 CB5 74 1
DDR_SDQ11 1 4 DDR_DQ11 DDR_SDQ36 1 4 DDR_DQ36 75 76 R136 10_0402_5%
DDR_SDQ10 DDR_DQ10 DDR_SDQ33 DDR_DQ33 VSS VSS
2 3 2 3 77 DQS8 DM8 78
79 CB2 CB6 80
81 VDD VDD 82
2 RP41 10_4P2R_0402_5% RP26 10_4P2R_0402_5% 2
83 CB3 CB7 84 Note:
DDR_SDQ16 1 4 DDR_DQ16 DDR_SDQ38 1 4 DDR_DQ38 85 86
DDR_SDQ20 DDR_DQ20 DDR_SDQ34 DDR_DQ34 DU DU/RESET#
2 3 2 3 87 VSS VSS 88 Place Close to DIMM0
<9> DDR_CLK0 89 CK2 VSS 90
<9> DDR_CLK0# 91 CK2# VDD 92
RP35 10_4P2R_0402_5% RP15 10_4P2R_0402_5% 93 94
DDR_SDQ21 DDR_DQ21 DDR_SDQ35 DDR_DQ35 DDR_CKE1 VDD VDD DDR_CKE0
1 4 1 4 <9> DDR_CKE1 95 CKE1 CKE0 96 DDR_CKE0 <9>
DDR_SDQ17 2 3 DDR_DQ17 DDR_SDQ39 2 3 DDR_DQ39 97 98
DDR_SMAA12 DU/A13 DU/BA2 DDR_SMAA11
99 100
DDR_SMAA9 A12 A11 DDR_SMAA8
101 102
RP44 10_4P2R_0402_5% RP27 10_4P2R_0402_5% A9 A8
103
VSS VSS
104 Layout note
DDR_SDQ22 1 4 DDR_DQ22 DDR_SDQ44 1 4 DDR_DQ44 DDR_SMAA7 105 106 DDR_SMAA6
DDR_SDQ18 DDR_DQ18 DDR_SDQ40 DDR_DQ40 DDR_SMAA5 A7 A6 DDR_SMAA4
2 3 2 3 107
A5 A4
108 Place these resistor
DDR_SMAA3 109 110 DDR_SMAA2
DDR_SMAA1 111
A3 A2
112 DDR_SMAA0 close by DIMM0,
RP34 10_4P2R_0402_5% RP17 10_4P2R_0402_5% A1 A0 all trace length
113 114
DDR_SDQ23 DDR_DQ23 DDR_SDQ41 DDR_DQ41 DDR_SMAA10 VDD VDD DDR_BS1
1 4 1 4 115 116 Max=1.4"
DDR_SDQ19 DDR_DQ19 DDR_SDQ45 DDR_DQ45 DDR_BS0 A10/AP BA1 DDR_RAS#
2 3 2 3 117
BA0 RAS#
118
DDR_WE# 119 120 DDR_CAS#
DDR_SCS#0 WE# CAS# DDR_SCS#1
<9> DDR_SCS#0 121 122 DDR_SCS#1 <9>
RP45 10_4P2R_0402_5% RP29 10_4P2R_0402_5% S0# S1#
123 124
DDR_SDQ28 DDR_DQ28 DDR_SDQ46 DDR_DQ46 DU DU +1.25VS
1 4 1 4 125 126
DDR_SDQ24 DDR_DQ24 DDR_SDQ42 DDR_DQ42 DDR_DQ33 VSS VSS DDR_DQ32
2 3 2 3 127 128
DDR_DQ36 DQ32 DQ36 DDR_DQ37
129 130
DQ33 DQ37
131 132
RP38 10_4P2R_0402_5% RP22 10_4P2R_0402_5% DDR_DQS4 VDD VDD DDR_DM4
133 134 RP47
DDR_SDQ25 DDR_DQ25 DDR_SDQ47 DDR_DQ47 DDR_DQ34 DQS4 DM4 DDR_DQ39 DDR_CKE0 1
1 4 1 4 135
DQ34 DQ38
136 4
DDR_SDQ29 2 3 DDR_DQ29 DDR_SDQ43 2 3 DDR_DQ43 137 138 DDR_CKE1 2 3
DDR_DQ38 VSS VSS DDR_DQ35
139 140
DDR_DQ40 DQ35 DQ39 DDR_DQ45 56_4P2R_0402_5%
141 142
DQ40 DQ44
143 144
DDR_DQ44 VDD VDD DDR_DQ41
145 146
3 DDR_DQS5 DQ41 DQ45 DDR_DM5 3
147 148 RP49
DQS5 DM5 DDR_SCS#0 1
149 150 4
DDR_DQ42 VSS VSS DDR_DQ43 DDR_SCS#1 2
151 152 3
DD R_SDQ[0..63] RP30 10_4P2R_0402_5% DDR_DQ46 DQ42 DQ46 DDR_DQ47
<9> DDR_SDQ[0..63] 153 154
DDR_SDQ49 DDR_DQ49 DQ43 DQ47 56_4P2R_0402_5%
1 4 155 156
DD R_SDQS[0..7] DDR_SDQ48 DDR_DQ48 VDD VDD
<9> DDR_SDQS[0..7] 2 3 157 158 DDR_CLK2# <9>
VDD CK1#
159 160 DDR_CLK2 <9>
DDR_SMA[0..12] VSS CK1
<9,13> DDR_SMA[0..12] 161 162
RP18 10_4P2R_0402_5% DDR_DQ48 VSS VSS DDR_DQ52
163 164
DDR_SDM[0..7] DDR_SDQ53 DDR_DQ53 DDR_DQ49 DQ48 DQ52 DDR_DQ53
<9> DDR_SDM[0..7] 1 4 165
DQ49 DQ53
166
DDR_SDQ52 2 3 DDR_DQ52 167 168
DDR_DQS6 VDD VDD DDR_DM6
169 170
DDR_DQ54 DQS6 DM6 DDR_DQ51
171 172
RP51 10_4P2R_0402_5% RP25 10_4P2R_0402_5% DQ50 DQ54
173 174
DDR_SDQ57 DDR_DQ57 DDR_SDQ55 DDR_DQ55 DDR_DQ55 VSS VSS DDR_DQ50
1 4 1 4 175
DQ51 DQ55
176
DDR_SDQ61 2 3 DDR_DQ61 DDR_SDQ54 2 3 DDR_DQ54 DDR_DQ60 177 178 DDR_DQ61
DQ56 DQ60
179 180
DDR_DQ56 VDD VDD DDR_DQ57
181
DQ57 DQ61
182 Note:
RP50 10_4P2R_0402_5% RP23 10_4P2R_0402_5% DDR_DQS7 183 184 DDR_DM7
DDR_SDQ56 DDR_DQ56 DDR_SDQ50 DDR_DQ50 DQS7 DM7
1 4 1 4 185
VSS VSS
186 Place Close to DIMM0
DDR_SDQ60 2 3 DDR_DQ60 DDR_SDQ51 2 3 DDR_DQ51 DDR_DQ63 187 188 DDR_DQ62
DDR_DQ58 DQ58 DQ62 DDR_DQ59
189 190
DQ59 DQ63 DDR_BS0
191 192 <9,13> DDR_SBS0 2 1
RP36 10_4P2R_0402_5% RP39 10_4P2R_0402_5% VDD VDD R139 10_0402_5%
<13,15,18,26> DIMM_SMDATA 193 194
DDR_SDQ58 DDR_DQ58 DDR_SDQ59 DDR_DQ59 SDA SA0 DDR_BS1
1 4 1 4 <13,15,18,26> DIMM_SMCLK 195 196 <9,13> DDR_SBS1 2 1
DDR_SDQ63 DDR_DQ63 DDR_SDQ62 DDR_DQ62 SCL SA1 R133 10_0402_5%
2 3 2 3 197 198
+3VS VDD_SPD SA2 DDR_RAS#
199 200 <9,13> DDR_SRAS# 2 1
VDD_ID DU R141 10_0402_5%
2 1 DDR_CAS#
<9,13> DDR_SCAS#
JAE MM50-200B1-1R_200P_Reverse R131 10_0402_5%
2 1 DDR_WE#
<9,13> DDR_SWE#
Layout note R138 10_0402_5%
4 DDR_SDQS0 DDR_DQS0 DDR_SDQS4 DDR_DQS4 4
2 1 2 1 Place these resistors
R119 10_0402_5% R114 10_0402_5%
close to DIMM0,
DIMM0
DDR_SDQS1 2 1 DDR_DQS1 DDR_SDQS5 2 1 DDR_DQS5
R109 10_0402_5% R106 10_0402_5% all trace length<500 mil
DDR_SDQS2 2 1 DDR_DQS2 DDR_SDQS6 2 1 DDR_DQS6
R120 10_0402_5% R107 10_0402_5%
DDR_SDQS3 2 1 DDR_DQS3 DDR_SDQS7 2 1 DDR_DQS7 Dell-Compal Confidential
R127 10_0402_5% R129 10_0402_5%
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 12 of 47
A B C D E F G H
 A B C D E

+2.5V +2.5V
+1.25VS +1.25VS SDREF_DIMM
JP23
1 VREF VREF 2
RP89 RP103 RP96 3 4 1
DDR_DQ4 DDR_DQ26 DDR_DQ48 DDR_DQ5 VSS VSS DDR_DQ0
1 4 4 1 4 1 5 DQ0 DQ4 6
DDR_DQ0 2 3 3 2 DDR_DQ30 3 2 DDR_DQ49 DDR_DQ1 7 8 DDR_DQ4 C488
DQ1 DQ5 0.1U_0402_16V4Z
9 VDD VDD 10
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQS0 11 12 DDR_DM0 2
RP109 DDR_DQ2 DQS0 DM0 DDR_DQ7
RP82 RP70 13 14
DDR_DQ5 DQ2 DQ6
1 4 4 1 DDR_DQ27 4 1 DDR_DQ53 15 VSS VSS 16
DDR_DQ1 2 3 3 2 DDR_DQ31 3 2 DDR_DQ52 DDR_DQ6 17 18 DDR_DQ3
DDR_DQ8 DQ3 DQ7 DDR_DQ12 +1.25VS
19 20
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% DQ8 DQ12
21 22
RP88 DDR_DQ9 VDD VDD DDR_DQ13
RP69 RP95 23 24
1 DDR_DQS0 1 DQ9 DQ13 1
4 4 1 DDR_DQ56 4 1 DDR_DQ54 DDR_DQS1 25 26 DDR_DM1
DDR_DQ6 2 DQS1 DM1
3 3 2 DDR_DQ51 3 2 DDR_DQS6 27
VSS VSS
28 1 2 DDR_SMA12
DDR_DQ14 29 30 DDR_DQ10 R128 56_0402_5%
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQ15 DQ10 DQ14 DDR_DQ11
31 32
DQ11 DQ15 RP48 56_4P2R_0402_5%
RP94 RP53 33 34
DDR_DQ3 VDD VDD
1 RP67 4 4 1 DDR_DQ60 4 1 DDR_DQ50 <9> DDR_CLK4 35
CK0 VDD
36 4 1 DDR_SMA11
DDR_DQ2 2 3 3 2 DDR_DQ57 3 2 DDR_DQ55 37 38 3 2 DDR_SMA9
<9> DDR_CLK4# CK0# VSS
39 40
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% VSS VSS
RP108 RP68 R174 56_0402_5% RP81 56_4P2R_0402_5%
DDR_DQ7 1 4 4 1 DDR_DQ61 1 2 DDR_DM0 DDR_DQ20 41 42 DDR_DQ17 4 1 DDR_SMA7
DDR_DQ8 DQ16 DQ20
2 3 3 2 DDR_DQS7 1 2 DDR_DM1 DDR_DQ16 43 DQ17 DQ21 44 DDR_DQ21 3 2 DDR_SMA8
R168 56_0402_5% 45 46
56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQS2 VDD VDD DDR_DM2
47 DQS2 DM2 48
RP87 RP93 R173 56_0402_5% DDR_DQ18 49 50 DDR_DQ19 RP78 56_4P2R_0402_5%
DDR_DQ9 1 DQ18 DQ22
4 4 1 DDR_DQ62 1 2 DDR_DM2 51 52 4 1 DDR_SMA6
DDR_DQ12 2 VSS VSS
3 3 2 DDR_DQ58 1 2 DDR_DM3 DDR_DQ22 53 DQ19 DQ23 54 DDR_DQ23 3 2 DDR_SMA3
R175 56_0402_5% DDR_DQ24 55 56 DDR_DQ29
56_4P2R_0402_5% 56_4P2R_0402_5% DQ24 DQ28
57 VDD VDD 58
RP92 RP66 R179 56_0402_5% DDR_DQ28 59 60 DDR_DQ25 RP77 56_4P2R_0402_5%
DDR_DQS1 1 DQ25 DQ29
4 4 1 DDR_DQ63 1 2 DDR_DM4 DDR_DQS3 61 DQS3 DM3 62 DDR_DM3 4 1 DDR_SMA10
DDR_DQ13 2 3 3 2 DDR_DQ59 1 2 DDR_DM5 63 64 3 2 DDR_SMA0
R180 56_0402_5% DDR_DQ26 VSS VSS DDR_DQ27
65 DQ26 DQ30 66
56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQ30 67 68 DDR_DQ31
R177 56_0402_5% DQ27 DQ31
RP107 RP100 69 70
DDR_DQ14 1 VDD VDD
4 4 1 DDR_DQ36 1 2 DDR_DM6 71 CB0 CB4 72
DDR_DQ10 2 3 3 2 DDR_DQ32 1 2 DDR_DM7 73 74 1 2 DDR_SMA1
R181 56_0402_5% CB1 CB5 R323 33_0402_5%
75 VSS VSS 76
56_4P2R_0402_5% 56_4P2R_0402_5% 77 DQS8 DM8 78 1 2 DDR_SMA2
RP86 RP75 79 80 R182 33_0402_5%
DDR_DQ11 1 CB2 CB6
4 4 1 DDR_DQ33 81 VDD VDD 82
DDR_DQ15 2 3 3 2 DDR_DQ37 83 84
2 CB3 CB7 RP102 33_4P2R_0402_5% 2
85 DU DU/RESET# 86
56_4P2R_0402_5% 56_4P2R_0402_5% 87 88 4 1 DDR_SMAB1
VSS VSS
RP106 RP99 <9> DDR_CLK3 89 CK2 VSS 90 3 2 DDR_SMAB2
DDR_DQ20 1 4 4 1 DDR_DQS4 91 92
DDR_DQ16 2 <9> DDR_CLK3# CK2# VDD
3 3 2 DDR_DQ38 93 VDD VDD 94
DDR_CKE3 95 96 DDR_CKE2 RP55 33_4P2R_0402_5%
<9> DDR_CKE3 CKE1 CKE0 DDR_CKE2 <9>
56_4P2R_0402_5% 56_4P2R_0402_5% 97 DU/A13 DU/BA2 98 4 1 DDR_SMA4
RP85 RP74 DDR_SMA12 99 100 DDR_SMA11 3 2 DDR_SMA5
DDR_DQ17 1 A12 A11
4 4 1 DDR_DQ34 DDR_SMA9 101
A9 A8
102 DDR_SMA8
DDR_DQ21 2 3 3 2 DDR_DQ39 103 104
DDR_SMA7 VSS VSS DDR_SMA6 RP54 33_4P2R_0402_5%
105 106
DDR _DQS[0..7] DDR_SMMAB5 A7 A6 DDR_SMMAB4
56_4P2R_0402_5% 56_4P2R_0402_5%
DDR_DQS[0..7] <12> 107 108 4 1 DDR_SMAB4
DDR_SMA3 A5 A4 DDR_SMMAB2
RP105 RP98 109
A3 A2
110 3 2 DDR_SMAB5
DDR_DQ18 1 4 4 1 DDR_DQ35 DDR _DQ[0..63] DDR_SMMAB1 111 112 DDR_SMA0
DDR_DQS2 2 DDR_DQ[0..63] <12> A1 A0
3 3 2 DDR_DQ44 113
VDD VDD
114
DDR_SMA[0..12] DDR_SMA10 115 116 DDR_SBS1 RP80 56_4P2R_0402_5%
DDR_SMA[0..12] <9,12> A10/AP BA1 DDR_SBS1 <9,12>
56_4P2R_0402_5% 56_4P2R_0402_5% <9,12> DDR_SBS0 DDR_SBS0 117 118 DDR_SRAS# 4 1 DDR_SWE#
D DR_DM[0..7] BA0 RAS# DDR_SRAS# <9,12>
RP84 RP73 DDR_SWE# 119 120 DDR_SCAS# 3 2 DDR_SBS0
DDR_DM[0..7] <12> <9,12> DDR_SWE# WE# CAS# DDR_SCAS# <9,12>
DDR_DQ19 1 4 4 1 DDR_DQ40 DDR_SCS#2 121 122 DDR_SCS#3
DDR_DQ22 2 <9> DDR_SCS#2 S0# S1# DDR_SCS#3 <9>
3 3 2 DDR_DQ45 123
DU DU
124
125 126 RP76 56_4P2R_0402_5%
DDR_DQ33 VSS VSS DDR_DQ32
56_4P2R_0402_5% 56_4P2R_0402_5% 127 128 4 1 DDR_SRAS#
DDR_DQ36 DQ32 DQ36 DDR_DQ37
RP104 RP72 129 130 3 2 DDR_SCAS#
DDR_DQ23 1 DQ33 DQ37
4 4 1 DDR_DQ41 131 132
DDR_DQ24 2 VDD VDD
3 3 2 DDR_DQS5 DDR_DQS4 133 134 DDR_DM4
DDR_DQ34 DQS4 DM4 DDR_DQ39
135 136
DQ34 DQ38
56_4P2R_0402_5% 56_4P2R_0402_5% 137
VSS VSS
138 1 2 DDR_SBS1
RP91 RP97 DDR_DQ38 139 140 DDR_DQ35 R358 56_0402_5%
DDR_DQ28 1 DQ35 DQ39
4 4 1 DDR_DQ43 <9> DDR_SMAB1
DDR_SMAB1 2 1 DDR_SMMAB1 DDR_DQ40 141 142 DDR_DQ45
DDR_DQ25 2 DQ40 DQ44
3 3 2 DDR_DQ42 R178 10_0402_5% 143 144
DDR_DQ44 VDD VDD DDR_DQ41
145 146
56_4P2R_0402_5% 56_4P2R_0402_5% DDR_SMAB2 DDR_SMMAB2 DDR_DQS5 DQ41 DQ45 DDR_DM5
<9> DDR_SMAB2 2 1 147 148
3 R171 10_0402_5% DQS5 DM5 3
RP83 RP71 149 150
DDR_DQ29 1 VSS VSS
4 4 1 DDR_DQ47 DDR_DQ42 151
DQ42 DQ46
152 DDR_DQ43
DDR_DQS3 2 3 3 2 DDR_DQ46 DDR_SMAB4 2 1 DDR_SMMAB4 DDR_DQ46 153 154 DDR_DQ47
<9> DDR_SMAB4 DQ43 DQ47
R176 10_0402_5% 155 156
56_4P2R_0402_5% 56_4P2R_0402_5% VDD VDD
157 158 DDR_CLK5# <9>
DDR_SMAB5 DDR_SMMAB5 VDD CK1#
<9> DDR_SMAB5 2 1 159 160 DDR_CLK5 <9>
R170 10_0402_5% VSS CK1
Layout note 161
VSS VSS
162
DDR_DQ48 163 164 DDR_DQ52 +1.25VS
DDR_DQ49 DQ48 DQ52 DDR_DQ53
Place these resistor 165
DQ49 DQ53
166
closely DIMM1, 167 168
DDR_DQS6 VDD VDD DDR_DM6
169 170
all trace DDR_DQ54 DQS6 DM6 DDR_DQ50
171 172 RP79
DQ50 DQ54 DDR_CKE3 1
length<=800mil 173 174 4
DDR_DQ55 VSS VSS DDR_DQ51 DDR_CKE2 2
175 176 3
DDR_DQ60 DQ51 DQ55 DDR_DQ61
177 178
DQ56 DQ60 56_4P2R_0402_5%
179 180
DDR_DQ56 VDD VDD DDR_DQ57
181 182
DDR_DQS7 DQ57 DQ61 DDR_DM7
183 184 RP101
DQS7 DM7 DDR_SCS#2 1
185 186 4
DDR_DQ63 VSS VSS DDR_DQ62 DDR_SCS#3 2
187 188 3
DDR_DQ58 DQ58 DQ62 DDR_DQ59
189 190
PAD1 PAD2 PAD3 PAD4 DQ59 DQ63 56_4P2R_0402_5%
191 192
VDD VDD
<12,15,18,26> DIMM_SMDATA 193 194
SDA SA0 +3VS
1 1 1 1 <12,15,18,26> DIMM_SMCLK 195
SCL SA1
196 Layout note
197 198
EMI Clip PAD for Memory Door +3VS
199
VDD_SPD SA2
200 Place these resistor
PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 VDD_ID DU
close by DIMM1,
JAE MM50-200B1-1 200P_Normal all trace length
Max=0.8"
PAD12 PAD13 PAD14
PAD16 PAD17
4
1 1 1 DIMM1 4
1 1

PAD-2.5X3 PAD-2.5X3 PAD-2.5X3

PAD-2.5X3 PAD-2.5X3
Dell-Compal Confidential
PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11
Compal Electronics, Inc.
1 1 1 1 1 1 1 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 13 of 47
A B C D E
 A B C D E

Layout note : Layout note :

Di stribute as close as possible Di stribute as close as possible
to DDR-SODIMM0. to DDR-SODIMM1.

+2.5V +2.5V

1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
+ C170 C194 C185 C183 C189 C184 C182 C186 C190
1 + C135 C418 C419 C415 C420 C423 C422 C421 C414 150U_D2_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 1
150U_D2_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C164 C167 C166 C162 C160 C157 C158 C168 C169 C177 C172 C173 C179 C175 C176 C181 C180 C187
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Layout note :
Place one cap close to every 2 pull up resistors termination to
2 +1.25VS 2
+1.25VS

1 1 1 1 1 1 1 1 1 1
C527 C528 C529 C530 C518 C531 C532 C533 C515 C534
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1 1 1 1 1
C535 C536 C512 C537 C538 C539 C522 C511 C521 C513
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1
C520 C514 C516 C517 C503 C519
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
3 2 2 2 2 2 2 3

+1.25VS

1 1 1 1 1 1 1 1 1 1
C509 C510 C508 C507 C504 C502 C501 C497 C495 C496
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1 1 1 1 1
C494 C540 C526 C525 C524 C543 C141 C188 C192 C506
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

4 4
1 1 1 1 1 1
C137 C178 C191 C139 C138 C505
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 14 of 47
A B C D E
 A B C D E F G H

Clock Generator
+3VS L26 +3V_CLK
KC FBM-L11-201209-221LMAT_0805
1 2 Width=40 mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1
L21 +3V_48M 1 2
BLM21A601SPT_0805 L22 C325 C264 C42 C43 C44 C59 C58 C61 C306
+3VS 1 2 @KC FBM-L11-201209-221LMAT_0805 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2
1 1 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 C243 C244 1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2

14
19
32
37
46
50
1
8
U75
BLM21A601SPT_0805

VDD_PCI_0
VDD_PCI_1
VDD_REF

VDD_3V66_0
VDD_3V66_1

VDD_CPU_0
VDD_CPU_1
VDD_48MHZ
L23 +3VS
C310 @10P_0402_50V8K
1 2 XTALIN 2 26 +3V_VDD 1 2
+3VS XTAL_IN VDDA

1
1 1
X2 C303

1
C312
R24 14.31818MHZ_20P 0.1U_0402_16V4Z 10U_1206_10V4Z

2
1K_0402_5% 2 2
1 2 XTALOUT 3 27
C272 @10P_0402_50V8K XTAL_OUT VSSA
2

45 CPU_BCLK 1 2
CPUCLKT2 CLK_CPU_BCLK <5>
R463 54 R225 27.4_0603_1%
SEL0 R218 49.9_0603_1%
<6> H_BSEL0 2 1 55 SEL1
2@0_0402_5% 1 2 40 1 2
R213 1K_0402_5% SEL2
<10> H_SEL0 1 2
1 2 R219 49.9_0603_1%
<19,30> PM_SLP_S3#
R356 0_0402_5%
1 2 25 44 CPU_BCLK# 1 2
<19,30> PM_SLP_S1# PWR_DWN# CPU_CLKC2 CLK_CPU_BCLK# <5>
R355 @0_0402_5% 34 R226 27.4_0603_1%
<19> PM_STPPCI# PCI_STOP# MCH_BCLK
<19,40> PM_STPCPU# 53 CPU_STOP# CPUCLKT1 49 1 2 CLK_MCH_BCLK <9>
R223 27.4_0603_1%
R242 R216 49.9_0603_1%
1 2 1 2
+3VS 10K_0402_5% 28 VTT_PWRGD# 1 2
R217 49.9_0603_1%
1

C
2 Q25 R232 MCH_BCLK# 2
1 2 2 CPUCLKC1 48 1 2 CLK_MCH_BCLK# <9>
+CPU_CORE B R224 27.4_0603_1%
2SC2411K_SOT23 1 2 43
R238 E +3VS 10K_0402_5% MULT0 CPU_ITP
52 1 2
3

CPUCLKT0 CLK_CPU_ITP <6>

220_0402_5% 2 1 R228 27.4_0603_1%
R221 @1K_0603_1% R227 49.9_0603_1%
<12,13,18,26> DIMM_SMDATA 29 SDATA 1 2
<12,13,18,26> DIMM_SMCLK 30 SCLK 1 2
R220 49.9_0603_1%

51 CPU_ITP# 1 2
CPUCLKC0 CLK_CPU_ITP# <6>
33 R222 27.4_0603_1%
3V66_0
35 24
3V66_1/VCH_CLK 3V66_5

23 AGP_66M R255 1 2 33_0402_5%

3V66_4 CLK_AGP_66M <16>
R20 1 2 475_0603_1% 42 22 MCH_66M R254 1 2 33_0402_5%
IREF 3V66_3 CLK_MCH_66M <10>
21 ICH_66M R253 1 2 33_0402_5%
3V66_2 CLK_ICH_66M <18>

R230 1 2 33_0402_5% ICH_48M 39 7 PCI_ICH R248 1 2 33_0402_5%

<19> CLK_ICH_48M 48MHZ_USB PCICLK_F2 CLK_PCI_ICH <18>
6
PCICLK_F1
5
PCICLK_F0
R231 1 2 33_0402_5% MCH_DISPLAY 38
<10> CLK_MCH_DISPLAY 48MHZ_DOT
18
PCICLK6 PCI_DEBUG R457 1@33_0402_5%
17 1 2 CLK_PCI_DEBUG <33>
PCICLK5 PCI_LAN R252 33_0402_5%
16 1 2 CLK_PCI_LAN <22>
R236 1 ICH_14M PCICLK4 PCI_PCM
<19> CLK_ICH_14M 2 33_0402_5% 56 13 R251 1 2 33_0402_5%
CLK_PCI_PCM <23,25>
REF PCICLK3 PCI_MINI R250 33_0402_5%
12 1 2 CLK_PCI_MINI <26>
PCICLK2
GND_3V66_0
GND_3V66_1
GND_48MHZ

R235 1 2 33_0402_5% 11 PCI_LPC R249 1 2 33_0402_5%

GND_PCI_0
GND_PCI_1

<27> CLK_CODEC_14M PCICLK1 CLK_PCI_LPC <30>

GND_IREF
GND_CPU
GND_REF

10
PCICLK0
3 3
1 1 1 1 1
C247 C248 C313 C315
@10P_0402_50V8K @10P_0402_50V8K ICS950810CG_TSSOP56 @10P_0402_50V8K @10P_0402_50V8K
4
9
15
20
31
36
41
47

2 2 2 2 2

C314
@10P_0402_50V8K

CPU Frequency Select Table

SEL[2:0] CK-408 Speed

001 100 MHZ

* 011 133 MHZ

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 15 of 47
A B C D E F G H
 A B C D E

AGP_ST[0..2]
<10> AGP_ST[0..2] +1.5VS B+ +12VALW +5VS +5VALW +2.5V +2.5V +3VS
AGP_SBA[0..7]
<10> AGP_SBA[0..7]
1 1 1 1 1 1 1 1
AGP_AD[0..31]
<10> AGP_AD[0..31] +
C127 C241 C240 C369 C242 C372 C355 C239
AGP_C/BE#[0..3] 0.1U_0402_16V4Z 0.1U_0603_50V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 150U_D2_6.3VM 0.1U_0402_16V4Z
<10> AGP_C/BE#[0..3] 2 2 2 2 2 2 2
2

JP8
1 1
1 2
GND GND +1.5VS
+2.5V 3 4 +5VS
3 4
5 6
5 6
7 8
7 8
9 10
9 10

1
11
11 12
12 Place this cap near AGP
AGP BUS Pullup 13
13 14
14
+AGPREF AGP_NBREF
R240
15 16 +3VALW 1K_0603_1%
AGP_RST# 15 16
on VGA BD 17
17 18
18 AGP_ADSTB0 <10>
AGP_C/BE#0 19 20 R243

2
19 20 AGP_ADSTB0# <10>
21 22 1 2
AGP_AD1 GND GND AGP_AD0 EXTVGA_IN# 2 1@0_0402_5%
23 23 24 24 1

1
AGP_AD3 25 26 AGP_AD2 R229 100K_0402_5% 1
AGP_AD5 25 26 AGP_AD4 R239
27 27 28 28
AGP_AD7 29 30 AGP_AD6 1K_0603_1% C273
29 30 POP for INT VGA 0.1U_0402_16V4Z
31 31 32 32
AGP_AD9 33 34 AGP_AD8 2

2
AGP_AD11 33 34 AGP_AD10 DEPOP for EXT VGA
35 35 36 36
AGP_AD13 37 38 AGP_AD12
AGP_AD15 37 38 AGP_AD14
39 39 40 40
41 GND GND 42
43 44 AGP_C/BE#1
<10> AGP_FRAME# 43 44 +3VS
<10> AGP_PAR 45 45 46 46 AGP_IRDY# <10>
<10> AGP_TRDY# 47 47 48 48 AGP_DEVSEL# <10>
49 50 R166
<10> AGP_STOP# AGP_AD17 49 50 AGP_PIPE# <10>
51 51 52 52 2 1
AGP_AD19 53 54 AGP_AD16
AGP_AD21 53 54 AGP_AD18 @0_0402_5%
55 55 56 56
AGP_AD23 57 58 AGP_AD20
57 58

5
AGP_C/BE#2 59 60 AGP_AD22
59 60
61 62 1

P
GND GND AGP_AD24 STP_AGP# IN1 SUS_STAT# <19,30>
<10> AGP_ADSTB1 63 63 64 64 4 O
2 AGP_AD26 2
<10> AGP_ADSTB1# 65 65 66 66 IN2 2

G
67 68 AGP_AD28 U36
AGP_AD25 67 68 AGP_AD30 SN74AHC1G08HDCK_TSSOP5
69 70

3
AGP_AD27 69 70
71 71 72 72 PM_C3_STAT# <19>
AGP_AD29 73 74
AGP_AD31 73 74 PIRQE# <18>
75 75 76 76
AGP_C/BE#3 77 78
77 78 AGP_SBSTB <10>
EXTVGA_IN# 79 80
<30> EXTVGA_IN# 79 80 AGP_SBSTB# <10>
81 82
AGP_SBA7 GND GND AGP_SBA6 AGP_RST#
83 84 1 2 V_PRST# <23,24,25>
AGP_SBA5 83 84 AGP_SBA4 R290 @0_0402_5%
85 86
AGP_SBA3 85 86 AGP_SBA2
87 88
AGP_SBA1 87 88 AGP_SBA0
89 90
89 90
91 92
91 92 AGP_ST0
<10> AGP_RBF# 93 94 1 2 PCIRST# <6,10,18,22,23,25,26,30,33>
93 94 AGP_ST1 R282 0_0402_5%
<10> AGP_WBF# 95 96
INTVGA_IN# 95 96 AGP_ST2
<31> INTVGA_IN# 97 98
97 98
99 100
GND GND
<10> AGP_REQ# 101 102 BKOFF# <30>
101 102
<10> AGP_GNT# 103 104 ENABKL <31>
103 104
<19> PID3 105 106 PID0 <19>
STP_AGP# 105 106
107 108 PID1 <19>
107 108
<27,30,33,38> SUSP# 109 110 SMB_EC_DA1 <30,31,34>
109 110
111 112 SMB_EC_CK1 <30,31,34>
111 112
<15> CLK_AGP_66M 113 114 PID2 <19>
113 114
115 116 AGP_NBREF
C /R 115 116
<17> C /R 117 118 1 2 +AGPREF
117 118 R237 2@0_0402_5% POP for EXT VGA +3VALW
119 120
Y/ G GND GND INTCRT_B
<17> Y/G 121 122 INTCRT_B <10>
121 122 CRT_B DEPOP for INT VGA
123 124 CRT_B <17>
COMP/B 123 124

14
<17> COMP/B 125 126
125 126 INTCRT_G
127 128 INTCRT_G <10>
3 127 128 CRT_G 3
129 130 1

P
<8,19> AGP_BUSY# 129 130 CRT_G <17> <30> G_RST# A
M_SEN# 131 132 3 V_PRST#
<17,31> M_SEN# 131 132 INTCRT_R O
133 134 INTCRT_R <10> 2
133 134 <6,10,18,22,23,25,26,30,33> PCIRST# B

G
INT_VSYNC 135 136 CRT_R
<10> INT_VSYNC 135 136 CRT_R <17>
CRT_VSYNC 137 138 U33A

7
<17> CRT_VSYNC 137 138
139 140 SN74LVC32APWLE_TSSOP14
INT_HSYNC GND GND
<10> INT_HSYNC 141 142
CR T_HSYNC 141 142
<17> CRT_HSYNC 143 144 +3V
143 144
145 146
INTDDCDA 145 146
<10> INTDDCDA 147 148 +3VS
3VDDCDA 147 148
<17> 3VDDCDA 149 150
149 150
151 152
INTDDCCK 151 152
<10> INTDDCCK 153 154
3VDDCCK 153 154
<17> 3VDDCCK 155 156
155 156
157 158
157 158
159 160
GND GND
+5VALW 161 162
161 162
163 164 B+
163 164
165 166
165 166
167 168
167 168
+1.5VS 169
169 170
170 Daughter Card Present Table
171 172
171 172
173 174 +12VALW
173 174
175
175 176
176 DOCKED NON DOCKED
177 178
177 178
179 180
GND GND
EXTVGA_IN#
LOW HIGH
(Ext. Graphy)
FOXCONN_QT00180A-5120C
INTVGA_IN#
4
CLK_AGP_66M LOW HIGH 4
(Int. Graphy)
Terminator on VGA BD

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 16 of 47
A B C D E
 5 4 3 2 1

C236
33P_0402_50V8J
1 2

C /R 1 2
<16> C /R
L18
FLM1608081R8K_0603 2

1
D
1 D
R203 C221
75_0603_1% C227 270P_0603_50V8J
100P_0402_50V8J 1
2

2
C233
33P_0402_50V8J
1 2 JP3
3
SVIDEO_C 6
7
COMP/B 1 2 SVIDEO_CVBS 5
<16> COMP/B
L19 2
FLM1608081R8K_0603 4
2 1

1
1 SVIDEO_Y 8
R204 C222 9
75_0603_1% C225 270P_0603_50V8J
100P_0402_50V8J 1
2 SUYIN_35138S-07T1-01

2
D19 D4 D5
C228 @DAN217_SOT23 @DAN217_SOT23 @DAN217_SOT23

1
33P_0402_50V8J
1 2

Y/ G 1 2

3
<16> Y/G +3VS
L20

1
1 FLM1608081R8K_0603 2
R205
75_0603_1% C226 C220
C 100P_0402_50V8J 270P_0603_50V8J C
2 1
2

CRTVCC

CRTVCC
+3VS +3VS
1

1
2.7K_0402_5%
C14 R5 R201

1
0.1U_0402_16V4Z 2K_0402_5% 2K_0402_5%
2 R4 R202
0_0402_5% R3 2.7K_0402_5%

2
CRTVCC

2
2
G
DAN217_SOT23 DAN217_SOT23 DAN217_SOT23 1
D1 D18 D3 1 3 3VDDCDA
3VDDCDA <16>

1
M_SEN# C15

S
<16,31> M_SEN#
0.1U_0402_16V4Z

2
@3.3P_0603_50V8J 2 Q14

G
2N7002_SOT23
1 1 1 1 3 3VDDCCK
3VDDCCK <16>
Q23

S
2

3
C3 C219 C4 +3VS 2N7002_SOT23
@3.3P_0603_50V8J @3.3P_0603_50V8J JP1
2 2 2
6
B B
DDC_MONID0 11
CRT_R 1 2 CRTR 1
<16> CRT_R
L2 7
FBM-10-201209-260-T_0805 12
CRT_G 1 2 CRTG 2
<16> CRT_G
L15 8
FBM-10-201209-260-T_0805 13
CRT_B 75_0603_1% 1 2 CRTB 3
CRT Connector
+5VS <16> CRT_B
R7 L1 9
1

1K_0402_5% FBM-10-201209-260-T_0805
1 1 1 14
CRTVCC 1 2 4
R1 R195 R2 C2 C214 C1 10
75_0603_1% 75_0603_1% 3.3P_0603_50V8J 3.3P_0603_50V8J 3.3P_0603_50V8J 15
1

2 2 2 5
2

2
5

Q24
SI2303DS_SOT23 FOX_DZ11A91-L8
OE#
P

2 CR T_HSYNC 2 4 1 2 1 2
<7,33> SUSP <16> CRT_HSYNC A Y L16
G

R459 FBM-11-160808-121-T_0603
3

U13 33_0402_5%
3

1 2
SN74AHCT1G125GW_SOT353-5 CRTVCC L17 1 1 1 1 1 1
FBM-11-160808-121-T_0603
1 C217 C218 C8 C7 C5 C224
27P_0402_50V8J 27P_0402_50V8J 100P_0402_50V8J
C6 2 2 2 2 2 2
0.1U_0402_16V4Z
5

2
R460 100P_0402_50V8J
OE#
P

CRT_VSYNC 2 4 1 2 100P_0402_50V8J
<16> CRT_VSYNC A Y 100P_0402_50V8J
G

33_0402_5%
A U4 A
3

SN74AHCT1G125GW_SOT353-5

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 17 of 47
5 4 3 2 1
 A B C D

U55A
AD [0..31]
<22,23,24,25,26,33> AD[0..31]
AD0 H5
AD0
ICH4 INTRUDER#
W6 SM_INTRUDER#
SM_INTRUDER# <32>
AD1 J3 AC3 SMLINK0 R164 1 2 @0_0402_5%
AD2 AD1 SMLINK0 SMLINK1 R172 1
H3
AD2 SMLINK1
AB1 2 @0_0402_5%
1 AD3 SMB_CLK 1
AD4
K1
G5
AD3 SM I/F SMB_CLK
AC4
AB4 SMB_DATA
AD5 AD4 SMB_DATA AC IN
J4 AA5 ACIN <30,34,36>
AD6 AD5 SMB_ALERT#/GPI11
H4
R319 AD7 AD6
J5
H_FERR# AD8 AD7
+CPU_CORE 2 1 K2
AD8
AD9 G2 Y22 GATEA20
AD10 AD9 A20GATE GATEA20 <30>
62_0402_5% L1 AB23 R104 2 1 68_0402_5%
AD11 AD10 A20M# H_A20M# <6>
G4 U23 H_DPSLP# <6>
AD12 AD11 DPSLP#
L2 AA21 H_FERR# <6>
AD13 AD12 FERR# R110 2
H2
AD13 IGNNE#
W21 1 68_0402_5% H_IGNNE# <6>
AD14 L3 V22
AD15 AD14 INIT# H_INIT# <6>
Place closely pin P5 F5 CPU I/F AB22 R105 2 1 68_0402_5%
AD15 INTR H_INTR <6>
AD16 F4 V21 R91 2 1 68_0402_5%
AD17 AD16 NMI H_NMI <6>
N1 Y23 R103 2 1 68_0402_5%
AD17 CPU_PWRGOOD H_PWRGD <6>
CLK_PCI_ICH AD18 E5 U22 +3VS
AD19 AD18 RCIN# KBRST# <30>
N2 U21 R112 2 1 68_0402_5%
AD19 SLP# H_SLP# <6>
1

AD20 E3 W23 R102 2 1 68_0402_5%

AD21 AD20 SMI# H_SMI# <6> DIMM_SMCLK
R348 N3 V23 R101 2 1 68_0402_5% 1 2
AD22 AD21 STPCLK# H_STPCLK# <6>
22_0402_5% E4 R163 8.2K_0402_5%
AD23 AD22 DIMM_SMDATA
M5 AD23 1 2
AD24 E2 HI[0..10] R162 8.2K_0402_5%
2

AD25 AD24 HI0 HI[0..10] <9>

1 P1 AD25 HI0 L19
AD26 E1 L20 HI1
C480 AD27 AD26 HI1 HI2
P2 AD27 HI2 M19
10P_0402_50V8K AD28 D3 M21 HI3 +3VALW
2 AD29 AD28 HI3 HI4
R1 AD29 HI4 P19
AD30 D2 R19 HI5
AD31 AD30 HI5 HI6 SMB_CLK
P4 T20 1 2

PCI I/F
AD31 HI6 HI7 R353 8.2K_0402_5%
HI7 R20
P23 HI8 SMB_DATA 1 2
C/BE#0 HI8 HI9 R352 8.2K_0402_5%
Place closely pin T21 <22,23,25,26,33> C/BE#0 J2 C/BE#0 HI9 L22
2 C/BE#1 H I10 2
CLK_ICH_66M <22,23,25,26,33> C/BE#1 C/BE#2
K4
M4
C/BE#1 HUB I/F HI10 N22
K21 1 2
<22,23,25,26,33> C/BE#2 C/BE#3 C/BE#2 HI11
N4 R99 62_0402_5% +3VS
<22,23,25,26,33> C/BE#3 C/BE#3
1

T21 CLK_ICH_66M
REQ#0 CLK66 CLK_ICH_66M <15>
R321 B1
<22> REQ#0 REQ#1 REQ#0
22_0402_5% A2 P21
<26> REQ#1 REQ#1 HI_STB HUB_PSTRB <9>
REQ#2 B3 N20 IRQ14 1 2
<23,25> REQ#2 REQ#2 HI_STB# HUB_PSTRB# <9>
REQ#3 C7 R143 8.2K_0402_5%
2

REQ#4 REQ#3 HUB_RCOMP_ICH 1 IRQ15

1 B6 R23 2 +1.5VS 1 2
REQ#4 HICOMP HUB_VREF R87 68_0603_1% R123 8.2K_0402_5%
M23
C395 HUB_VREF HUB_VSWING
<22> GNT#0 C1 R22
15P_0402_50V8J GNT#0 HUB_VSWING GATEA20
<26> GNT#1 E6 HUB_VREF <9,11> 1 2
2 GNT#1 R95 10K_0402_5%
<23,25> GNT#2 A7 HUB_VSWING <9,11>
GNT#2 APICCLK KBRST#
B7 J19 1 2
GNT#3 APICCLK APICD0 R94 10K_0402_5%
D6 H19
GNT#4 APICD0 APICD1
K20
APICD1

Interrupt I/F
CLK_PCI_ICH P5 D5 PIRQA#
<15> CLK_PCI_ICH PCICLK PIRQA# PIRQA# <23,25>
C2 PIRQB#
PIRQB# PIRQB# <22>
F1 B4 PIRQC#
<22,23,25,26,33> PCI_FRAME# FRAME# PIRQC# PIRQD# PIRQC# <26>
<22,23,25,26> PCI_DEVSEL# M3 A3 PIRQD# <26>
DEVSEL# PIRQD# PIRQE# RP4
L5 C8
PCI Pullups <22,23,25,26> PCI_IRDY#
G1
IRDY# PIRQE#/GPI2
D7 GPI3
PIRQE# <16>
GPI4 1 8
<22,23,25,26> PCI_PAR PAR PIRQF#/GPI3 GPI4 GPI3
<22,23,25,26> PCI_PERR# L4 C3 2 7
RP5 PCI_PLOCK# PERR# PIRQG#/GPI4 GPI5 PIRQE#
M2 C4 3 6
PCI_PERR# LOCK# PIRQH#/GPI5 IRQ14 GPI5
1 10 +3VS <30> EC_WAKEUP# W2 AC13 IRQ14 <21> 4 5
REQA# PIRQA# ICH_PCIRST# PME# IRQ14 IRQ15
2 9 U5 AA19 IRQ15 <21>
PCI_STOP# PIRQB# PCIRST# IRQ15 SIRQ 8.2K_8P4R_1206_5%
3 8 <22,23,25,26> PCI_SERR# K5
SERR# SERIRQ
J22 SIRQ <23,25,30>
PCI_SERR# 4 7 REQ#4 F3
<22,23,25,26> PCI_STOP# STOP#
+3VS 5 6 <22,23,25,26,33> PCI_TRDY# F2
TRDY#
D10
REQA# EE_CS
8.2K_10P8R_1206_5% B5
REQA#/GPI0 EEPROM I/F EE_IN
D11 R156
REQB# A6 A8 1 2
3 PIDERST# REQB#/GPI1/REQ5# EE_OUT +3VALW 3
<21> PIDERST# E8 C12
SIDERST# GNTA#/GPO16 EE_SHCLK @1K_0402_5%
<21> SIDERST# C5
RP3 GNTB#/GPO17/GNT5# SMLINK0 1 2
PCI_IR DY# 1 10 A10 R165
+3VS LAN_RXD0
PC I_TRDY# 2 9 PIRQC# A9 8.2K_0402_5%
PCI_DEVSEL# PIRQD# LAN_RXD1 SMLINK1
3 8 A11 1 2
PCI_FRAME# SIRQ LAN_RXD2 R169
4 7 B10
PCI_PLOCK# LAN_TXD0 8.2K_0402_5%
+3VS 5 6 C10
LAN I/F LAN_TXD1
LAN_TXD2
A12 AC IN 1 2
8.2K_10P8R_1206_5% C11 R161
LAN_CLK R159 @10K_0402_5%
B11
LAN_RSTSYNC
Y5 1 2
+3VS LAN_RST#
RP2 10K_0402_5%
1 8 REQ#0 APICCLK
2 7 REQ#1 APICD0
ICH4
3 6 REQ#2 APICD1
4 5 REQ#3

2
8.2K_8P4R_1206_5% R89 R88
1 2 REQB# 10K_0402_5% 0_0402_5%
R158 8.2K_0402_5%
+3VS

1
1 2 PIDERST# (Strap)
R153 @8.2K_0402_5% R97
10K_0402_5%
2
G

DIMM_SMCLK 3 1 SMB_CLK
<12,13,15,26> DIMM_SMCLK
2
S

+3VS
4 Q28 SMB_DATA 1 DIMM_SMDATA 4
3 DIMM_SMDATA <12,13,15,26>
2N7002_SOT23
D

S
5

Q27
1 2N7002_SOT23
P

ICH_PCIRST# IN1
4
2
O PCIRST# <6,10,16,22,23,25,26,30,33> Dell-Compal Confidential
IN2
G

U9 Compal Electronics, Inc.

3

SN74AHC1G08HDCK_TSSOP5 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 18 of 47
A B C D
 A B C D

Place close to pin B8

+3VALW
IAC_BITCLK

1
R79
10K_0402_5% R336
@10_0402_5%
+3VS
U55B

2
1 1

1 2 ICH_SPKR
<8,16> AGP_BUSY#
AGP_BUSY# R2
AGPBUSY#/GPI6
ICH4 GPI7
R3
1
C460
R98 @1K_0402_5% SYSRST# Y3 V4 EC_SMI# @10P_0402_50V8K
<6> SYSRST# VLBA# SYSRST# GPI8 SCI# EC_SMI# <30> 2
<30> VLBA# AB2 V5 SCI# <30>
ICH_AC_SDOUT BATLOW# GPI12 LID_OUT#
1 2 <16> PM_C3_STAT# T3
C3_STAT#/GPO21 GPO13
W3 LID_OUT# <30>
R150 @8.2K_0402_5% ICLKRUN# AC2
V20
CLKRUN#/GPIO24 GPIO GPIO25
V2
W1
EC_FLASH# <30>
<40> PM_DPRSLPVR DPRSLPVR GPIO27
1 2 PM_STPCPU# AA1 W4
<30> PWRBTN# PWRBTN# GPIO28
R90 1K_0402_5% AB6
<10,30,32> PM_PWROK EC_SWI# PWROK
<30> EC_SWI# Y1
RI# Place close to pin J23
PM_STPPCI#
1
R78
2
1K_0402_5%
<30> RSMRST# AA6
W18
RSMRST# PM AA13 PDA0 CLK_ICH_14M
<15,30> PM_SLP_S1# SLP_S1#/GPO19 PDA0 PDA0 <21>
Y4 AB13 PDA1
<15,30> PM_SLP_S3# SLP_S3# PDA1 PDA1 <21>

1
Y2 W13 PDA2
<30> PM_SLP_S4# SLP_S4# PDA2 PDA2 <21>
AA2 Y13 PDCS1# R93
<30> PM_SLP_S5# SLP_S5# PDCS1# PDCS3# PDCS1# <21>
2 1 W19 AB14 @10_0402_5%
<15,40> PM_STPCPU# STP_CPU#/GPO20 PDCS3# PDCS3# <21>
R84 2 1 @0_0402_5% Y21
<15> PM_STPPCI# RTCCLK STP_PCI#/GPO18 PDDREQ
R81 @0_0402_5% AA4 AA11

2
SUS_CLK PDDREQ PDDACK# PDDREQ <21>
AB3 SUS_STAT#/LPCPD# PDDACK# Y12 PDDACK# <21> 1
<16,30> SUS_STAT# ICH_THRM# PDIOR#
V1 THRM# PDIOR# AC12 PDIOR# <21>
W12 PDIOW# C124
PDIOW# PDIORDY PDIOW# <21> @10P_0402_50V8K
PIORDY AB12 PDIORDY <21> 2
J21 AB11 PDD0
PM_CPUPERF# SSMUXSEL/GPO23 PDD0 PDD1
<6> PM_CPUPERF#
2 1 V_GATE
Y20
V19
CPUPERF#/GPO22 IST PDD1 AC11
Y10 PDD2
<30,40> VGATE VGATE/VRMPWRGD PDD2 PDD3
R96 33_0402_5% AA10
PDD3 PDD4
R391 IAC_BITCLK 2 1 B8
AC97 I/F PDD4 AA7
AB8 PDD5 Place close to pin F19
@0_0402_5% <27,29> IAC_BITCLK R160 33_0402_5% C13 AC_BITCLK PDD5 PDD6
<27,29> IAC_RST# AC_RST# PDD6 Y8
IAC_SDATA_IN0 PDD7 CLK_ICH_48M
2 <6,31> PROCHOT# 2 1 <27> IAC_SDATA_IN0 IAC_SDATA_IN1
D13
A13
AC_SDATAIN0 IDE I/F PDD7 AA8
AB9 PDD8 2
<29> IAC_SDATA_IN1 AC_SDATAIN1 PDD8

1
B13 Y9 PDD9
R392 ICH_AC_SDOUT AC_SDATAIN2 PDD9 PDD10 R92
D9 AC_SDATAOUT PDD10 AC9
2 1 ICH_THRM# ICH_AC_SYNC C9 W9 PDD11 @10_0402_5%
<30> EC_THRM# AC_SYNC PDD11 PDD12
PDD12 AB10
0_0402_5% W10 PDD13

2
LPC_AD0 PDD13 PDD14
T2 LPC_AD0 PDD14 W11 1
<30> LAD0 LPC_AD1 PDD15
<30> LAD1 R4 Y11
LPC_AD2 LPC_AD1 PDD15 C123
T4
<30> LAD2 LPC_AD3 LPC_AD2 SDA0 @10P_0402_50V8K
1 2 RTCCLK
<30> LAD3
U2
U3
LPC_AD3 LPC I/F SDA0
AA20
AC20 SDA1 SDA0 <21> 2
LPC_DRQ#0 SDA1 SDA1 <21> PDD [0..15]
R347 @100K_0402_5% U4 AC21 SDA2
LPC_DRQ#1 SDA2 SDA2 <21> PDD[0..15] <21>
LFRAME# T5 AB21 SDCS1#
<30> LFRAME# LPC_FRAME# SDCS1# SDCS3# SDCS1# <21>
AC22 SDCS3# <21>
SDCS3# SDD [0..15]
SDDREQ SDD[0..15] <21>
AB18 SDDREQ <21>
SDDREQ SDDACK#
<32> USBP0+ C20 AB19 SDDACK# <21>
USBP0+ SDDACK# SDIOR#
<32> USBP0- D20 Y18 SDIOR# <21>
USBP0- SDIOR# SDIOW#
A21 AA18 SDIOW# <21>
USBP1+ SDIOW# SDIORDY
B21 AC19 SDIORDY <21>
USBP1- SIORDY
<32> USBP2+ C18
USBP2+ SDD0
<32> USBP2- D18 W17
USBP2- SDD0 SDD1
A19 AB17
USBP3+ SDD1 SDD2
B19 W16
USBP3- SDD2 SDD3
C16 AC16
USBP4+ SDD3 SDD4
D16 W15
USBP4- SDD4 SDD5
A17 AB15
+3VS USBP5+ SDD5 SDD6
B17
USBP5- USB I/F SDD6
W14
AA14 SDD7
SDD7 SDD8
Y14
SDD8
R82 1 2 100K_0402_5% PID0 <32> OVCUR#0
OVCUR#0 B15 AC15 SDD9
OVCUR#1 OC#0 SDD9 SDD10
C14 AA15
3 OC#1 SDD10 3
R83 1 2 100K_0402_5% PID1 <32> OVCUR#2
OVCUR#2 A15
OC#2 SDD11
Y15 SDD11
OVCUR#3 B14 AB16 SDD12
OC#3 SDD12
R80 1 2 100K_0402_5% PID2 OVCUR#4 A14
OC#4 SDD13
Y16 SDD13 +RTCVCC
OVCUR#5 D14 AA17 SDD14
OC#5 SDD14
R77 1 2 100K_0402_5% PID3 Y17 SDD15 R145
USB_RBIAS SDD15 15K_0402_5%
A23
USB_RBIAS
B23 2 1
USB_RBIAS#
1
2

J23 CLK_ICH_14M <15>

R86 CLK14 C156
F19 CLK_ICH_48M <15> 2 1 2 1
+3VALW 22.6_0603_1% CLK48 1U_0603_10V4Z
J20
GPIO32 RTC_RST# J1 R326 2
G22 W7
GPIO33 RTCRST# JOPEN 1K_0402_5%
F20
1

R144 1 OVCUR#1 GPIO34 VBIAS R_VBIAS1

2 8.2K_0402_5% G20 CLOCK Y6 1 2 2
GPIO35 VBIAS
F21
R142 1 OVCUR#3 GPIO36 RTCX1
2 8.2K_0402_5% H20 AC7 C163 R154
GPIO37 RTCX1 R329 0.047U_0402_16V4Z 1K_0402_5%
F23
R130 1 OVCUR#4 <21> SIDEPWR GPIO38 RTCX2
2 8.2K_0402_5% H22 GPIO AC6 2 1
GPIO39 RTCX2 10M_0603_5%
<16> PID0 G23
R147 1 OVCUR#5 GPIO40
2 8.2K_0402_5% <16> PID1 H21
GPIO41
X3
F22 H23 32.768KHZ_12.5P
<16> PID2 GPIO42 SPKR ICH_SPKR <28>
<16> PID3 E23 1 2 2 1
GPIO43
MISC THRMTRIP# W20 H_THERMTRIP# H_THERMTRIP# <6>
R331 R324 @22M_0603_5%

2
1 1 10M_0603_5%
R330
R346 C450 C448 @2.4M_0603_1%
10K_0402_5% ICH4 12P_0402_50V8J 12P_0402_50V8J
1 2 2 2
+3VS

1
D46
@RB751V_SOD323
CLKRUN# 2 1 ICLKRUN#
<22,25,26,30> CLKRUN#
4 4

1 2 ICH_AC_SYNC
<27,29> IAC_SYNC
R335 33_0402_5%
1 2 ICH_AC_SDOUT
<27,29> IAC_SDATAO
R325 33_0402_5%
1 1 Dell-Compal Confidential
C457 C452
@22P_0402_50V8J @22P_0402_50V8J Compal Electronics, Inc.
2 2 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 19 of 47
A B C D
 A B C D E F G H

U55C

D22 VSS0
ICH4 VCC3.3_0 A5 +3VS
+3VS

E10 VSS1 VCC3.3_1 AC17

E14 VSS2 VCC3.3_2 AC8 1 1 1 1 1 1 1 1
E16 VSS3 VCC3.3_3 B2
E17 H18 C146 C140 C428 C441 C9 C416 C466 C424
VSS4 VCC3.3_4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
E18 VSS5 VCC3.3_5 H6
E19 J1 2 2 2 2 2 2 2 2
VSS6 VCC3.3_6 4.7U_0805_10V4Z
E21 J18
VSS7 VCC3.3_7
E22 K6
VSS8 VCC3.3_8
F8 M10
1 VSS9 VCC3.3_9 1
G19 P12
VSS10 VCC3.3_10
G21 P6 1 1 1 1 1 1 1 1
VSS11 VCC3.3_11
G3 U1
VSS12 VCC3.3_12 C463 C449 C430 C397 C469 C473 C472 C443
G6 V10
VSS13 VCC3.3_13 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
H1 V16
VSS14 VCC3.3_14 2 2 2 2 2 2 2 2
J6 V18
VSS15 VCC3.3_15
K11
VSS16
K13
VSS17
K19 E11 +3VALW
VSS18 VCCSUS3.3_0
K23 F10
VSS19 VCCSUS3.3_1 +3VALW
K3 F15
VSS20 VCCSUS3.3_2
L10 VSS21 VCCSUS3.3_3 F16
L11 VSS22 VCCSUS3.3_4 F17
L12 VSS23 VCCSUS3.3_5 F18 1 1 1 1 1 1 1
L13 VSS24 VCCSUS3.3_6 K14
L14 V7 C433 C434 C431 C451 C464 C454 C442
VSS25 VCCSUS3.3_7 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L21 VSS26 VCCSUS3.3_8 V8
M1 V9 2 2 2 2 2 2 2
VSS27 VCCSUS3.3_9
M11 VSS28
M12 VSS29
M13
M20
VSS30 GND POWER K10
VSS31 VCC1.5_0 +1.5VS
M22 VSS32 VCC1.5_1 K12 1 1 1 1
N10 VSS33 VCC1.5_2 K18
N11 K22 C447 C436 C396 C426
VSS34 VCC1.5_3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
N12 VSS35 VCC1.5_4 P10
N13 T18 2 2 2 2
VSS36 VCC1.5_5
N14 VSS37 VCC1.5_6 U19
N19 VSS38 VCC1.5_7 V14
N21 VSS39
N23 VSS40
N5 VSS41 VCCSUS1.5_0 E12 +1.5VALW
2 +1.5VS 2
P11 VSS42 VCCSUS1.5_1 E13
P13 VSS43 VCCSUS1.5_2 E20
P20 VSS44 VCCSUS1.5_3 F14
P22 VSS45 VCCSUS1.5_4 G18 1 1 1 1 1 1 1 1 1
P3 VSS46 VCCSUS1.5_5 R6
R18 T6 C425 C427 C437 C467 C465 C446 C440 C445 C398
VSS47 VCCSUS1.5_6 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R21 VSS48 VCCSUS1.5_7 U6
R5 2 2 2 2 2 2 2 2 2
VSS49
T1
VSS50 VCC5REF
T19 E7
VSS51 VCC5REF1
T23
VSS52 VCC5REF2
V6 VCC DECOUPLING
U20
VSS53 VCC5REFSUS
V15 E15
VSS54 VCC5REFSUS1
V17
VSS55
V3
VSS56
W22 L23 +1.5VS
VSS57 VCCHI_0 +1.5VS +1.5VALW
W5 M14
VSS58 VCCHI_1
W8 P18
VSS59 VCCHI_2
Y19 T22
VSS60 VCCHI_3
Y7 1 1 1 1 1 1 1
VSS61
A16
VSS62 C417 C453 C459 C444 C429 C435 C439
A18 AA23 +CPU_CORE
VSS63 VCC_CPU_IO_0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
A20 P14
VSS64 VCC_CPU_IO_1 2 2 2 2 2 2 2
A22 U18
VSS65 VCC_CPU_IO_2 +1.5VS_PLL
A4
VSS66
AA12
VSS67
AA16
VSS68 VCCPLL
C22 1 2 +1.5VS VCCHI DECOUPLING
AA22 R85 0_0805_5%
VSS69
AA3
VSS70
AA9 AB5 +RTCVCC
VSS71 VCCRTC
AB20
VSS72 +3VS_ICHLAN
AB7
3 VSS73 +CPU_CORE +1.5VS_ICHLAN +3VS_ICHLAN 3
AC1
VSS74
AC10 E9 1 2 +3VS
VSS75 VCCLAN3.3_0 R338 0_0805_5%
AC14 F9
VSS76 VCCLAN3.3_1 +1.5VS_ICHLAN
AC18 1 1 1 1 1 1 1 1
VSS77
AC23
VSS78 C130 C438 C432 C468 C462 C455 C456 C461
AC5 F6 1 2 +1.5VS
VSS79 VCCLAN1.5_0 R332 0_0805_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
B12 F7
VSS80 VCCLAN1.5_1 2 2 2 2 2 2 2 2
B16
VSS81
B18
VSS82
B20
VSS83
B22
VSS84
B9
VSS85
C15
VSS86
C17
VSS87 +3VALW +5VALW +3VS +5VS
C19
VSS88
C21
VSS89
C23
VSS90

1
C6
VSS91 +RTCVCC +1.5VS_PLL D23 R111 D13 R349
D1
VSS92 1SS355_SOD323 1K_0603_1% 1SS355_SOD323 1K_0603_1%
D12
VSS93
D15
VSS94
D17 2 1 1

2
VSS95 VCC5REFSUS VCC5REF
D19
VSS96 C153 C129 C128
D21
VSS97 0.1U_0402_10V6K 0.1U_0402_16V4Z 0.01U_0402_25V4Z
D23 1 1 1 1
VSS98 1 2 2 C143
D4
VSS99 C136 0.1U_0402_16V4Z C475 C474
D8
VSS100 1U_0603_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z
A1
VSS101 2 2 2 2

ICH4
4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 20 of 47
A B C D E F G H
 A B C D E

SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
Placea caps. near HDD VGS: -2.5V, RDS: 190mOHM
HDD Connector CONN. Layout Note: +5VSHDD trace Id(MAX): 2.3A
+5VSHDD
width 60 mil VGS(MAX): +-8V
SDD [0..15] 0.1U_0402_16V4Z 1U_0603_10V4Z 1 D
<19> SDD[0..15]
1 1 1 1 1 1
Correct HDD pin define ,pls update layout C386 C389 C387 C375 C377
1 C643 1
JP6 1000P_0402_50V7K @22U_1206_10V4Z
2 2 2 2 2 2
<18> SIDERST# SDD7 1 2 SDD8 G S
SDD6 3 4 SDD9 22U_1206_10V4Z 0.1U_0402_16V4Z 2 3
SDD5 5 6 SDD10
SDD4 7 8 SDD11
SDD3 9 10 SDD12
SDD2 11 12 SDD13
SDD1 13 14 SDD14
SDD0 15 16 SDD15 +5VS +5VSHDD
17 18 +12VALW
SDDREQ 19 20
<19> SDDREQ 21 22 R274 3 1
<19> SDIOW# 23 24

1
470_0402_5% 1 2 SDIORDY
<19> SDIOR# 25 26 +3VS
SDIORDY SEC_CSEL1 2 R280 4.7K_0402_5% R55 Q6
<19> SDIORDY RSDDACK# 27 28 100K_0402_5% SI2301DS_SOT23

2
IRQ15 29 30
<18> IRQ15 31 32

2
<19> SDA1 33 34
<19> SDA0 35 36 SDA2 <19>
1 2 RSDDACK#
<19> SDCS1# SHDD_LED# 37 38 SDCS3# <19> <19> SDDACK#
R289 22_0402_5%
39 40
+5VSHDD 41 42 +5VSHDD
43 44

1
1

1
D R54
FOX_HH99227-S1-TR 2 150K_0603_5% C86
<19> SIDEPWR 0.1U_0402_16V4Z
G
SDDREQ 1 2 Q18 S 2

2
2N7002_SOT23
C323
33P_0402_50V8J
2 2

1 2 PDIORDY
+3VS
R370 4.7K_0402_5%
CD-ROM Connector
PDD [0..15] 1 2 RPDDACK# +5VS
<19> PDD[0..15] <19> PDDACK#
R371 22_0402_5%

1 2
1 2
C197 47P_0402_50V8J C105

14
0.1U_0402_16V4Z
1 2 C195 1

P
47P_0402_50V8J CD_AGND <27> PDDREQ I0
C196 1 2 1 2 3
JP14 O
2
I1

G
<27> INT_CD_L 47P_0402_50V8J C559 U18A
1 2 INT_CD_R <27>
33P_0402_50V8J 74HCT08PW_TSSOP14

7
3 3 4 PDD8 3
<18> PIDERST# 5 6
PDD7 PDD9
PDD6 7 8 PDD10
PDD5 9 10 PDD11
PDD4 11 12 PDD12
PDD3 13 14 PDD13
15 16 Placea caps. near CDROM
PDD2 PDD14
PDD1 17 18 PDD15 CONN.
PDD0 19 20 PDDREQ
21 22 PDDREQ <19>
+5VS
23 24 PDIOR# <19>
+5VS
<19> PDIOW# 25 26
PDIORDY RPDDACK# R374
<19> PDIORDY IRQ14 27 28 100K_0402_5%
<18> IRQ14 29 30 PDIAG#
<19> PDA1 1 2 1 1 1 1
31 32 +5VS

2
C567 C565 C204 C202
<19> PDA0 33 34 PDA2 <19>
R67 R74
<19> PDCS1# 35 36 PDCS3# <19>
PHDD_LED# W=80mils 1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_1206_10V4Z 100K_0402_5% 100K_0402_5%
37 38 2 2 2 2
39 40

1
+5VS 41 42 +5VS
43 44 1 2

PRI_CSEL 45 46 C563 +5VS PHDD_LED# 4

47 48 0.1U_0402_16V4Z I0 ACT_LED#
6 ACT_LED# <29>
49 50 O
2

SHDD_LED# 5
I1 U18B
R185 1 1 1 1 74HCT08PW_TSSOP14
470_0402_5% SUYIN_800185MB050S106ZU C206 C561 C205 C203
1

1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_1206_10V4Z

2 2 2 2

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 21 of 47
A B C D E
 5 4 3 2 1

+1.8VLAN
+3VWOL WLAN LOM LED (JP28)
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1
1 1 1 1 1 1 1 1 WLAN_LINK_80211A LINK_LED100# ORANGE (100M)
C96 C41 C72 C95 C82 C70
C97 C94 C77 C74 C88 C87 C80 4.7U_0805_10V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2 2 2 2 WLAN_LINK_10_LDE LINK_LED10# GREEN (10M)
2 2 2 2 2 2 2 2 0.1U_0402_16V4Z Place close
to pin 57
10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z WLAN_ACT_LED ACTLED# YELLOW

L7 WLAN_LINK_80211A
D
@BLM11A121SPT_0603 NC ORANGE/GREEN D
2 1 15 mil WLAN_LINK_10_LDE
+3VALW +3VAUXLAN +3VAUXLAN
R461 0_0603_5%
1 2 +1.8VLAN +3VAUXLAN
+3VAUXLAN +3VWOL +3VWOL
+3V 2 1
L39 1 1 1 1 1 1
1 2 +3VAUXLAN +3VWOL BLM11A121SPT_0603 Place close
+3VS
C46 C55 C48 C45 C47 C38
R462 @0_0603_5%
to pin 69 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 2 2 2 2 2
+1.8VLAN
C67 +3VAUXLAN
1000P_0402_50V7K 1000P_0402_50V7K
AD [0..31] 2
<18,23,24,25,26,33> AD[0..31] +3VAUXLAN

1
LINK_LED10# 1 2 (LAN_10LINK)

3
R33 R31 D8

112

115
125

106

114
10K_0402_5% 10K_0402_5% RB751V_SOD323

17
44

19
30
40
52

79
94

96
97

91
92

25
56

65
68
U11

1
D E
47K
2 Q16 B
VDDCORE1
VDDCORE2
VDDCORE3

VDDBUS1
VDDBUS2
VDDBUS3
VDDBUS4
VDDBUS5
VDDBUS6
VDDBUS7

NC10
VDDIO1
VDDIO2

REG_AVDD1
REG_AVDD2

REG_VOUT1
REG_VOUT2

VESD1
VESD2
VESD3

XTAL_AVSS
XTAL_AVDD

2
<26> WLAN_LINK_10_LED
R32 G 2N7002_SOT23 2
10K_0402_5% D9 S 10K

3
1 2 C Q4
AD31 122 75 LINK_LED10# RB751V_SOD323 +3VAUXLAN DTA114YKA_SOT23
AD30 PCI_AD31 LED0_L LINK_LED100#
123 76

1
AD29 PCI_AD30 LED1_L ACTLED# LINK_LED100# (LAN_100LINK) R14
124 PCI_AD29 LED2_L 77 1 2

3
AD28 126 78 2 1
AD27 PCI_AD28 LED3_L D2 200_0603_5%
127 PCI_AD27

1
AD26 RB751V_SOD323 D E
128 PCI_AD26 47K
AD25 1 58 2 Q15 B
PCI_AD25 EPHY_AGND <26> WLAN_LINK_80211A
AD24 3 57 RB751V_SOD323G 2N7002_SOT23 2
AD23 PCI_AD24 EPHY_AVDD +1.8VLAN
6 D7 S 10K Q3

3
AD22 PCI_AD23 C DTA114YKA_SOT23
8 PCI_AD22 EPHY_BIAS_AVDD 69 +3VAUXLAN 1 2
C AD21 9 70 +3VAUXLAN C
AD20 PCI_AD21 EPHY_BIAS_AVSS L8
10

1
AD19 PCI_AD20 EPHY_PLLVDD ACTLED# (LAN_ACTIVE) R13
11 PCI_AD19 EPHY_PLLVDD 64 1 2 +1.8VLAN 1 2

3
AD18 14 63 LCN0603T-R22J-S_5%_0603 2 1
AD17 PCI_AD18 EPHY_PLLGND D10 200_0603_5%
15 PCI_AD17

1
AD16 R34 1 D E
16 71 2 @10K_0402_5% RB751V_SOD323
AD15
AD14
AD13
33
34
36
PCI_AD16
PCI_AD15
PCI_AD14
Broadcom EPHY_VREF
EPHY_RDAC
EPHY_TESTMODE
72
88
R28 1 2 1.27K_0603_1% <26> WLAN_ACT_LED 2
G
S Q17
2
B
47K

Q5
10K

3
AD12 PCI_AD13 LAN_TX+ 2N7002_SOT23 C DTA114YKA_SOT23
37 62
AD11
AD10
38
39
PCI_AD12
PCI_AD11
BCM 4401L EPHY_TDP
EPHY_TDN
61
59
LAN_TX-
LAN_RX+

1
AD9 PCI_AD10 EPHY_RDP LAN_RX- +3VAUXLAN
41 60
AD8 PCI_AD9 EPHY_RDN
42
AD7 PCI_AD8 +3VAUXLAN
45 104
AD6 PCI_AD7 NC0 +3VAUXLAN
48 105
AD5 PCI_AD6 NC1
49 103
PCI_AD5 NC2

1
AD4 50 108
AD3 PCI_AD4 NC3 R35 R30 R25
51 102
PCI_AD3 NC4

1
AD2 53 109 1K_0402_5% @10K_0402_5% @10K_0402_5% 1
AD1 PCI_AD2 NC5
54 110
AD0 PCI_AD1 NC6 C20
55 107 U8

2
PCI_AD0 NC7 0.1U_0402_16V4Z
1 8
CS VCC R452 2
4 87 2 7

2
<18,23,25,26,33> C/BE#3 PCI_CBE3_L VAUX_AVAIL SK NC
18 86 3 6 @100K_0402_5% R15
<18,23,25,26,33> C/BE#2 PCI_CBE2_L NC8 DI ORG
<18,23,25,26,33> C/BE#1 32 85 4 5 1 2
PCI_CBE1_L NC9 DO GND
<18,23,25,26,33> C/BE#0 43
PCI_CBE0_L 200_0603_5%
<18,23,25,26,33> PCI_FRAME# 20 90 AT93C46_SO8
PCI_FRAME_L BOOTROM_SCL
<18,23,25,26> PCI_IRDY# 21 93
PCI_IRDY_L BOOTROM_SDA
<18,23,25,26,33> PCI_TRDY# 23
PCI_TRDY_L SPROM_CS
<18,23,25,26> PCI_DEVSEL# 26 98
PCI_DEVSEL_L SPROM_CS SPROM_CLK
<18,23,25,26> PCI_STOP# 27 95
B PCI_STOP_L SPROM_CLK SPROM_DOUT B

10

11

12

13
<18,23,25,26> PCI_PERR# 28 101
PCI_PERR_L SPROM_DOUT

9
29 99 SPROM_DI +3VAUXLAN JP7
<18,23,25,26> PCI_SERR# PCI_SERR_L SPROM_DIN LAN_RJ45T+
31 1

G_O_LED-

LED_YELLOW-
LDE_ORANGE+

LDE_GREEN+

LED_YELLOW+
<18,23,25,26> PCI_PAR PCI_PAR PR1+
116 U2
<18> PIRQB# PCI_INT_L
89 LAN_RJ45T- 2
PCIRST# EXT_POR_L LAN_DISABLE# <30> LAN_TX+ PR1-
0,16,18,23,25,26,30,33> PCIRST# 117 1 12
PCI_RST_L LAN_TX- TD+ TX+ LAN_RJ45R+
<15> CLK_PCI_LAN 118 83 2 11 3
PCI_CLK JTAG_TDO TD- TX- PR2+
<18> GNT#0 119 80
PCI_GNT_L JTAG_TCK
<18> REQ#0 121
PCI_REQ_L JTAG_TDI
82 SPROM_DOUT SPROM_CLK 3
TDC TCT
10 4
PR3+
<31> LAN_PME# 113 73 4 9
LAN_AD17 PCI_PME_L JTAG_TRST_L RDC RCT
5 81 5
PCI_IDSEL JTAG_TMS LAN_RX+ PR3-
1Kb None None 5
RD+ RX+
8
22 LAN_RX- 6 7 LAN_RJ45R- 6
<19,25,26,30> CLKRUN# PCI_CLKRUN_L RD- RX- PR2-
67 4Kb 10K Pullup None 1 1 7

SHLD1

SHLD2
XTAL_IN Pulse_H1112 PR4+
66
XTAL_OUT C213 8
PR4-
1

16Kb None 10K Pullup 0.01U_0402_25V4Z

VSS10
VSS11

1
2 2
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

FOX_JM66113-L1B1-TR

14

15
1

1
Y1 R29 R193 R190
25MHZ_20P 200_0603_5% EPHY_PLLVDD 75_0603_1% R192 R191
BCM4401_LQFP128 C215 75_0603_1%
2

12
46
111
100
84
2
24
74
13
47
120
35

XI 1 2 XO 0.01U_0402_25V4Z 75_0603_1%

2
1 2 Close to RJ45 under inch

2
1 1
C54 C52 2 75_0603_1% 2
C40 4.7U_0805_10V4Z 1000P_0402_50V7K
C39 27P_0402_50V8J 2 1 C211 C212
2 27P_0402_50V8J 2 1000P_1808_2KV7K 1000P_1808_2KV7K
Place closely pin 118 1 1
CLK_PCI_LAN
1

A +3VAUXLAN A
R52
33_0402_5% LAN_RX+ R53 2 1 49.9_0805_1% Chassis GND & Digital GND Short Together
LAN_RX- R51 2 1 49.9_0805_1% 1 1
LAN_TX+ R42 2 1 49.9_0805_1%
Dell-Compal Confidential
2

1 LAN_TX- R46 2 1 49.9_0805_1% C56 C84

AD17 1 2 LAN_AD17 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R64 100_0402_5% C79 2 2
22P_0402_50V8J Place close to U11 Compal Electronics, Inc.
2 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 22 of 47
5 4 3 2 1
 A B C D E

This page POP with 845PE for EXT.

AD [0..31]
<18,22,24,25,26,33> AD[0..31]
2 1 <18,22,24,25,26,33> AD[0..31] CBS_CAD[0..31] <24,25>
R73 +3V_CBSA U35A
@402K_0603_1% +3V_CBSD AD31 J5 E8 CBS_CAD31
+3V_CBSD AD30 AD31 CAD31/D10 CBS_CAD30
J6 C8
R70 AD29 AD30 CAD30/D9 CBS_CAD29
K2 B8
2@1K_0402_5% U35B AD28 AD29 CAD29/D1 CBS_CAD28
K3 E9
+3V_CBSA AD27 AD28 CAD28/D8 CBS_CAD27
G1 K5 F9
P HY_CPS VCC_G01 AD26 AD27 CAD27/D0 CBS_CAD26
2 1 P10 M1 K6 F11
CPS VCC_M01 AD26 CAD26/A0
2

2
R59 R1 L11 AD25 L2 E11 CBS_CAD25
1 R69 @0_0402_5% VCC_R01 VDPLL AD24 AD25 CAD25/A1 CBS_CAD24 1
W8 1 2 L3 C11
@0_0402_5% PHY_CNA VCC_W08 2@BLM21A05 _0805 AD23 AD24 CAD24/A2 CBS_CAD23
1 2 P17 L19 M2 A12
CNA VCC_L19 AD22 AD23 CAD23/A3 CBS_CAD22
H19 1 1 M3 C12
R68 R50 VCC_H19 AD21 AD22 CAD22/A4 CBS_CAD21
E19 M6 E12
1

1 VCC_E19 AD21 CAD21/A5

@0_0402_5% 2@43K_0402_5% A13 C115 C103 AD20 M5 C13 CBS_CAD20
CBS_PC0
CBS_PC1
V10
W10
PC0
VCC_A13
VCC_A08
A8
A5
2@10U_1206_10V4Z
2 2
2@0.01U_0402_25V4Z AD19
AD18
N2
N3
AD20
AD19 PCI4510 CAD20/A6
CAD19/A25
A14
E13
CBS_CAD19
CBS_CAD18
CBS_PC2 PC1 VCC_A05 AD17 AD18 CAD18/A7 CBS_CAD17
P9 N6 B14

PCI4510_R0 W13
PC2
PCI4510 G14
CBS_VCC AD16
AD15
P1
R6
AD17
AD16
CAD17/A24
CAD16/A17
F18
G17
CBS_CAD16
CBS_CAD15
R0 VCCCB_G14 AD15 CAD15/IOWR#
2

R63 A11 AD14 P7 F19 CBS_CAD14

R72 R58 PCI4510_R1 VCCCB_A11 +3V_CBSD AD13 AD14 CAD14/A9 CBS_CAD13
1 2 V13 V5 G18
2@0_0402_5% R71 2@0_0402_5% R1 AD12 AD13 CAD13/IORD# CBS_CAD12
L1 U6 H15
2@6.34K_0603_1% VCCP_L01 AD11 AD12 CAD12/A11 CBS_CAD11
W5 V6 H14
VCCP_W05 AD10 AD11 CAD11/OE# CBS_CAD10
R7 H17
1

C53 1 AD9 AD10 CAD10/CE2# CBS_CAD9

G2 2 2@0.1U_0402_16V4Z P8 H18
IEEE1394_TPA0+ 1.8V_G02 AD8 AD9 CAD9/A10 CBS_CAD8
V12 L18 U7 J14
2@0_0402_5% TPA0+ 1.8V_L18 AD7 AD8 CAD8/D15 CBS_CAD7
1 2 Place close to pin H1 W7
AD7 CAD7/D7
J17
IEEE1394_TPA0- W12 C73 2@0.1U_0402_16V4Z AD6 R8 K14 CBS_CAD6
TPA0- CLK_PCI_PCM AD5 AD6 CAD6/D13 CBS_CAD5
E6 VCCD0# <24,25> U8 J19
VCCD0# AD4 AD5 CAD5/D6 CBS_CAD4
B5 VCCD1# <24,25> V8 K17

1
VCCD1# AD3 AD4 CAD4/D12 CBS_CAD3
V15 W9 K15
TPA1+ R47 AD2 AD3 CAD3/D5 CBS_CAD2
V9 L14
@33_0402_5% AD1 AD2 CAD2/D11 CBS_CAD1
W15 A4 VPPD0 <24,25> U9 K18
TPA1- VPPD0# AD0 AD1 CAD1/D4 CBS_CAD0
C5 VPPD1 <24,25> R9 L15
VPPD1# AD0 CAD0/D3

2
IEEE1394_TPB0+ V11 1
TPB0+
IEEE1394_TPB0- W11 E1 C75 B11 CBS_CC/BE3#
TPB0- GND_E01 @22P_0402_50V8J CC/BE3#/REG# CBS_CC/BE3# <24,25>
K1 L6 C14 CBS_CC/BE2#
GND_K01 2 <18,22,25,26,33> C/BE#3 C/BE3# CC/BE2#/A12 CBS_CC/BE2# <24,25>
2 1 2 1 IEEE1394_TPB1+ V14 N1 P2 G15 CBS_CC/BE1#
2@0.1U_0402_16V4Z TPB1+ GND_N01 <18,22,25,26,33> C/BE#2 C/BE2# CC/BE1#/A8 CBS_CC/BE0# CBS_CC/BE1# <24,25>
R65 2@1K_0402_5% C89 W6 U5 J15
2 IEEE1394_TPB1- GND_W06 <18,22,25,26,33> C/BE#1 C/BE1# CC/BE0#/CE1# CBS_CC/BE0# <24,25> 2
2 1 W14 P19 <18,22,25,26,33> C/BE#0 V7
R56 2@1K_0402_5% TPB1- GND_P19 C/BE0# CBS_CRST#
K19 B13 CBS_CRST# <24,25>
IEEE1394_TPBIAS0 GND_K19 CRESET CBS_CFRAME#
U12 G19 B15 CBS_CFRAME# <24,25>
TPBIAS0 GND_G19 CFRAME#/A23 CBS_CIRDY#
A15 F13 CBS_CIRDY# <24,25>
IEEE1394_TPBIAS1 GND_A15 CIRDY#/A15 CBS_CTRDY#
2 1 U15 A10 E14 CBS_CTRDY# <24,25>
C98 2@1U_0603_10V4Z TPBIAS1 GND_A10 CTRDY#/A22 CBS_CDEVSEL#
A7 <18,22,25,26> PCI_PAR W4 A16 CBS_CDEVSEL# <24,25>
GND_A7 PCI_PAR CDEVSEL#/A21 CBS_CSTOP#
E17 CBS_CSTOP# <24,25>
R22 CSTOP#/A20 CBS_CPERR#
F15 CBS_CPERR# <24,25>
1V8_VR_EN# CPERR#/A14 CBS_CSERR#
H5 2 1 E10 CBS_CSERR# <24,25>
VR_EN# 2@0_0402_5% CSERR#/WAIT# CBS_CPAR
F14 CBS_CPAR <24,25>
CPAR/A13 CBS_CREQ#
R11 <18,22,25,26> PCI_DEVSEL# R2 B12 CBS_CREQ# <24,25>
+3V_CBSA AVD2 DEVSEL# CREQ#/INPACK# CBS_CGNT#
U13 G3 PCM_SUSP# <24,25,30> <18,22,25,26,33> PCI_FRAME# N5 D19 CBS_CGNT# <24,25>
AVD3 SUSPEND# FRAME# CGNT#/WE# CBS_CCLK_INTERNAL
U14 <18,25> GNT#2 J1 C15 CBS_CCLK_INTERNAL <24,25>
AVD4 GNT# CCLK/A16
U11 R57 P3 A9 CBS_CSTSCHNG
AGND2 <18,22,25,26> PCI_IRDY# IRDY# CSTSCHG/BVD1 CBS_CCLKRUN# CBS_CSTSCHNG <24,25>
R12 J3 2 1 PCM_PME# <25,31> <18,22,25,26> PCI_PERR# R3 B9 CBS_CCLKRUN# <24,25>
AGND3 RI_OUT#/PME# 2@0_0402_5% PERR# CCLKRUN#/WP
R13 <18,25> REQ#2 J2
AGND4 PCM_SPK# REQ#
E2 PCM_SPK# <25,28> <18,22,25,26> PCI_SERR# T1 E18 CBS_CBLOCK# CBS_CBLOCK# <24,25>
VDPLL SPKROUT SERR# CBLOCK#/A19
P15 <18,22,25,26> PCI_STOP# P5 C10 CBS_CINT# CBS_CINT# <24,25>
VDPLL PIRQA# STOP# CINT#/READY
F5 PIRQA# <18,25> <18,22,25,26,33> PCI_TRDY# P6
INTA#/MFUNC0 CBS_MFUNC1 TRDY# CBS_CAUDIO
G6 <6,10,16,18,22,25,26,30,33> PCIRST# H3 F10 CBS_CAUDIO <24,25>
INTB#/MFUNC1 CBS_MFUNC2 PCI_RESET# CAUDIO/BVD2 CBS_CCD2#
F3 C9 CBS_CCD2# <24,25>
MFUNC2 CCD2/CD2# CBS_CCD1#
F2 SIRQ <18,25,30> <16,24,25> V_PRST# H2 L17 CBS_CCD1# <24,25>
MFUNC3 CBS_MFUNC4 G_RST# CCD1/CD1#
N14 G5
VSPLL MFUNC4 CBS_MFUNC5 CBS_CVS2
F1 F12 CBS_CVS2 <24,25>
FILTER0 LEDSKT/MFUNC5 CBS_MFUNC6 PCM_ID L5 CVS2/VS2# CBS_CVS1
T19 H6 <24,25> PCM_ID B10 CBS_CVS1 <24,25>
FILTER1 FILTER0 MFUNC6 IDSEL CVS1/VS1#
1 2 R17
C78 2@0.1U_0402_10V6K FILTER1 CBS_RSVD/D2
F8 CBS_RSVD/D2 <24,25>
+3V_CBSD CRSVD/D2 CBS_RSVD/A18
N15 <15,25> CLK_PCI_PCM H1 F17 CBS_RSVD/A18 <24,25>
MC_RSVD1 CBS_SCL PCICLK CRSVD/A18 CBS_RSVD/D14
E3 J18 CBS_RSVD/D14 <24,25>
SCL CBS_SDA CRSVD/D14
M14 D1
MC_RSVD3 SDA
N17
3 MC_RSVD4 PHY_TEST_MA 2@PCI4510GHK_PBGA209 3
N18 P18 2 1
MC_RSVD5 PHY_TEST_MA R44 2@4.7K_0402_5%
N19
MC_RSVD6 CBS_TEST0
M15 U10 2 1
MC_RSVD7 TEST0 R61 2@200_0402_5%
M17
MC_RSVD8 CBS_TEST1
M18 R10 2 1
MC_RSVD9 TEST1 R60 2@200_0402_5%
M19
+3V_CBSD MC_RSVD10 IEEE1394_TPBIAS0
F6
CLK48_RSVD
B7
SC_CD#

1
C7 1
SC_RST

1
CBS_MFUNC1 1 2 F7 R18 PCI4510XI R198
R23 2@10K_0402_5% SC_CLK XI C223 2@ 56.2_0603_1%
A6 U3
CBS_MFUNC2 SC_DATA 2@ 1U_0603_10V4Z
1 2 B6
R38 2@10K_0402_5% SC_PWR 2 TPB0- JP2
E7

2
CBS_MFUNC4 SC_MODE PCI4510XO 8 1
1 2 C6 R19

2
R36 2@10K_0402_5% SC_FCB XO R199 7 2
1
CBS_MFUNC5 2@PCI4510GHK_PBGA209 2@24.576MHz_16P 2@ 56.2_0603_1% 6 3 TPB0+ 1
1 2 2
R39 2@10K_0402_5% X1 IEEE1394_TPB0- 5 4 TPA0- 2
3
CBS_MFUNC6 IEEE1394_TPB0+ 3
1 2 1 2 4
R26 2@10K_0402_5% IEEE1394_TPA0- @BTS0402-01_8P 4
1 1 IEEE1394_TPA0+ TPA0+ 5
C83 C106 GND1
6
POP for 845PE GND2

1
7

1
2@22P_0402_50V8J 2@22P_0402_50V8J R196 GND3
8
2 2 R197 GND4
2@ 56.2_0603_1% 2@ 56.2_0603_1% RP1
1 8 2@AMP_440168-2_4P

2
+3V +3V_CBSA 2 7

2
2@BLM21A601SPT_0805 3 6
L10 4 5
1 2 2@0.1U_0402_16V4Z
2 1 CBS_SCL 2@0_8P4R_1206_5%

1
1 1 1 1 1 R21 2@ 220_0402_5% 1
4 CBS_SDA R194 4
2 1
C114 C108 C101 C102 C109 R37 2@ 220_0402_5% C216 2@5.1K_0603_1%
2@10U_1206_10V4Z 2@0.1U_0402_16V4Z 2@ 270P_0603_50V8J
2 2 2 2 2 2

2
Dell-Compal Confidential
2@0.1U_0402_16V4Z 2@0.1U_0402_16V4Z
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 23 of 47
A B C D E
 A B C D E

PCMCIA Power Controller

+12VALW CBS_VCC

1 1
C31 U7
0.1U_0603_50V4Z 13 C18
VCC 4.7U_0805_10V4Z
12
2 VCC 2
9 11
12V VCC CBS_VPP
1 L9 +3V_CBSD 1
+5VALW BLM21A601SPT_0805 C85 C57 C81 C90
1 1 2 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3V
10
VPP C23 1 1 1 1 1 1 1 1 1 1
1 5 0.1U_0402_16V4Z
5V 2 C71 C49
6
C25 5V 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z VCCD0# 2 2 2 2 2 2 2 2 2 2
1 VCCD0# <23,25>
2 VCCD0 VCCD1#
2 VCCD1# <23,25>
+3VALW VCCD1 VPPD0 C36 C51 C34 C92
15 VPPD0 <23,25>
VPPD0 VPPD1 0.1U_0402_16V4Z 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
14 VPPD1 <23,25>
VPPD1
3
3.3V
1 4 8
3.3V SHDN OC
GND

C21
2 0.1U_0402_16V4Z TPS2211AIDBR_SSOP16
7

16

V_PRST#
V_PRST# <16,23,25>

CBS_VCCL
+3VALW +5VALW CBS_VCC
1 1
2 2
1 1
1 1 C60 C50
0.01U_0402_25V4Z 4.7U_0805_10V4Z C37 C35
C17 C30 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U_0603_10V4Z 1U_0603_10V4Z 2 2
2 2

Near U35 Pin G14 Near U35 Pin A11

CBS_VPP
1 1
C24 C26 1 2 CBS_VCCL
0.01U_0402_25V4Z 1U_0603_10V4Z CBS_VCC L6
2 2 KC FBM-L11-201209-221LMAT_0805

1 2 +3V_CBSD
L5
@KC FBM-L11-201209-221LMAT_0805 2 1
C76 C93
CardBus Socket C19 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1000P_0402_50V7K 1 2
2 1

JP18 Near U35 Pin W5

Near U35 Pin L1
1 35
CBS_CAD0 1 35 CBS_CCD1#
<23,25> CBS_CAD0 2 36 CBS_CCD1# <23,25>
CBS_CAD1 2 36 CBS_CAD2
<23,25> CBS_CAD1 3 37 CBS_CAD2 <23,25>
CBS_CAD3 3 37 CBS_CAD4
<23,25> CBS_CAD3 4 38 CBS_CAD4 <23,25>
CBS_CAD5 4 38 CBS_CAD6
<23,25> CBS_CAD5 5 39 CBS_CAD6 <23,25>
3 CBS_CAD7 5 39 CBS_RSVD/D14 3
<23,25> CBS_CAD7 6 40 CBS_RSVD/D14 <23,25>
CBS_CC/BE0# 6 40 CBS_CAD8
<23,25> CBS_CC/BE0# 7 41 CBS_CAD8 <23,25>
CBS_CAD9 7 41 CBS_CAD10
<23,25> CBS_CAD9 8 42 CBS_CAD10 <23,25>
CBS_CAD11 8 42 CBS_CVS1
<23,25> CBS_CAD11 9 43 CBS_CVS1 <23,25>
CBS_CAD12 9 43 CBS_CAD13
<23,25> CBS_CAD12 10 44 CBS_CAD13 <23,25>
CBS_CAD14 10 44 CBS_CAD15
<23,25> CBS_CAD14 11 45 CBS_CAD15 <23,25>
CBS_CC/BE1# 11 45 CBS_CAD16
<23,25> CBS_CC/BE1# 12 46 CBS_CAD16 <23,25>
CBS_CPAR 12 46 CBS_RSVD/A18
<23,25> CBS_CPAR 13 47 CBS_RSVD/A18 <23,25>
CBS_CPERR# 13 47 CBS_CBLOCK#
<23,25> CBS_CPERR# 14 48 CBS_CBLOCK# <23,25>
CBS_CGNT# 14 48 CBS_CSTOP# CBS_CCLK
<23,25> CBS_CGNT# 15 49 CBS_CSTOP# <23,25> 1 2 CBS_CCLK_INTERNAL <23,25>
CBS_CINT# 15 49 CBS_CDEVSEL# R27 47_0402_5%
<23,25> CBS_CINT# 16 50 CBS_CDEVSEL# <23,25>
16 50
CBS_VCCL 17 51 CBS_VCCL
17 51
CBS_VPP 18 52 CBS_VPP
CBS_CCLK 18 52 CBS_CTRDY#
19 53 CBS_CTRDY# <23,25>
CBS_CIRDY# 19 53 CBS_CFRAME#
<23,25> CBS_CIRDY# 20 54 CBS_CFRAME# <23,25>
CBS_CC/BE2# 20 54 CBS_CAD17
<23,25> CBS_CC/BE2# 21 55 CBS_CAD17 <23,25>
CBS_CAD18 21 55 CBS_CAD19 AD20 PCM_ID
<23,25> CBS_CAD18 22 56 CBS_CAD19 <23,25> <18,22,23,25,26> AD20 1 2 PCM_ID <23,25>
CBS_CAD20 22 56 CBS_CVS2 R41 100_0402_5%
<23,25> CBS_CAD20 23 57 CBS_CVS2 <23,25>
CBS_CAD21 23 57 CBS_CRST#
<23,25> CBS_CAD21 24 58 CBS_CRST# <23,25>
CBS_CAD22 24 58 CBS_CSERR#
<23,25> CBS_CAD22 25 59 CBS_CSERR# <23,25>
CBS_CAD23 25 59 CBS_CREQ#
<23,25> CBS_CAD23 26 60 CBS_CREQ# <23,25>
CBS_CAD24 26 60 CBS_CC/BE3#
<23,25> CBS_CAD24 27 61 CBS_CC/BE3# <23,25>
CBS_CAD25 27 61 CBS_CAUDIO
<23,25> CBS_CAD25 28 62 CBS_CAUDIO <23,25>
CBS_CAD26 28 62 CBS_CSTSCHNG
<23,25> CBS_CAD26 29 63 CBS_CSTSCHNG <23,25> <23,25,30> PCM_SUSP# 2 1 +3V_CBSD
CBS_CAD27 29 63 CBS_CAD28 R40 10K_0402_5%
<23,25> CBS_CAD27 30 64 CBS_CAD28 <23,25>
CBS_CAD29 30 64 CBS_CAD30
<23,25> CBS_CAD29 31 65 CBS_CAD30 <23,25>
CBS_RSVD/D2 31 65 CBS_CAD31
<23,25> CBS_RSVD/D2 32 66 CBS_CAD31 <23,25>
CBS_CCLKRUN# 32 66 CBS_CCD2#
<23,25> CBS_CCLKRUN# 33 67 CBS_CCD2# <23,25>
33 67
34 68
34 68
69 70 1
GND GND
71 72
GND GND C107
73 74
4 GND GND 1000P_0402_50V7K 4
75 76
GND GND 2
77 78
GND GND
79 80
GND GND
81 82
GND GND
Dell-Compal Confidential
JAE JC21-BRB-E500
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 24 of 47
A B C D E
 A B C D E

This page POP with 845GL for INT.

CBS_CAD[0..31]
CBS_CAD[0..31] <23,24>

U34B
76 CBS_CAD0
A_D3/CAD0 CBS_CAD1
78
A_D4/CAD1 CBS_CAD2
1
PCI1510 A_D11/CAD2
77
1
81 CBS_CAD3
A_D5/CAD3 CBS_CAD4
79
A_D12/CAD4 CBS_CAD5
83
A_D6/CAD5 CBS_CAD6
82
A_D13/CAD6 CBS_CAD7
86
A_D7/CAD7 CBS_CAD8
87
A_D15/CAD8 CBS_CAD9
89
A_A10/CAD9 CBS_CAD10
90
A_CE2#/CAD10 CBS_CAD11
91
U34A A_OE#/CAD11 CBS_CAD12
<18,22,23,24,26,33> AD[0..31] 92
Multifunction& A_A11/CAD12 CBS_CAD13
94
Miscellaneous A_IORD#/CAD13 CBS_CAD14
PCI1510 A_A9/CAD14
96
AD0 56 58 95 CBS_CAD15
AD0 MF0/INTA# PIRQA# <18,23> A_IOWR#/CAD15
AD1 55 59 CBS_1510MF1 97 CBS_CAD16
AD2 AD1 MF1 CBS_1510MF2 A_A17/CAD16 CBS_CAD17
53 63 114

PC CARD / CARD BUS INTERFACE

AD3 AD2 MF2/DMAREQ# A_A24/CAD17 CBS_CAD18
52 64 SIRQ <18,23,30> 115
AD4 AD3 MF3/IRQSER CBS_1510MF4 A_A7/CAD18 CBS_CAD19
51 67 116
AD5 AD4 MF4/RI_OUT# CBS_1510MF5 A_A25/CAD19 CBS_CAD20
50 68 118
AD6 AD5 MF5/DMAGNT# A_A6/CAD20 CBS_CAD21
49 69 CLKRUN# <19,22,26,30> 120
AD7 AD6 MF6/CLKRUN# A_A5/CAD21 CBS_CAD22
48 121
AD8 AD7 A_A4/CAD22 CBS_CAD23
46 57 PCM_PME# <23,31> 123
AD9 AD8 RI_OUT#/PME# A_A3/CAD23 CBS_CAD24
45 61 PCM_SPK# <23,28> 127
AD10 AD9 SPKROUT A_A2/CAD24 CBS_CAD25
44 65 PCM_SUSP# <23,24,30> 128
AD11 AD10 SUSPEND# A_A1/CAD25 CBS_CAD26
43 85 129
AD12 AD11 CLK_48M_RSVD A_A0/CAD26 CBS_CAD27
42 139
AD13 AD12 A_D0/CAD27 CBS_CAD28
41 125 140
AD14 AD13 VR_EN# A_D8/CAD28 CBS_CAD29
39 62 141
AD15 AD14 VR_PORT A_D1/CAD29 CBS_CAD30
38 1 142
AD16 AD15 A_D9/CAD30 CBS_CAD31
25 144
AD17 AD16 C91 A_D10/CAD31
24
AD18 AD17 1@0.1U_0402_16V4Z CBS_RSVD/A18
23 99 CBS_RSVD/A18 <23,24>
AD19 AD18 2 A_A18/RSVD CBS_RSVD/D14
22 84 CBS_RSVD/D14 <23,24>
2 AD20 AD19 A_D14/RSVD CBS_RSVD/D2 2
18
AD20
PCI A_D2/RSVD
143 CBS_RSVD/D2 <23,24>
AD21 17 36 +3V_CBSD
AD21 PWR VCCP
AD22 16 88 CBS_CC/BE0#
AD22 A_CE1#/CC/BE0# CBS_CC/BE0# <23,24>
AD23 CBS_CC/BE1#
PCI BUS

15 98 CBS_CC/BE1# <23,24>
AD24 AD23 CBS_1510MF1 A_A8/CC/BE1# CBS_CC/BE2#
11 54 1 2 113 CBS_CC/BE2# <23,24>
AD24 VCC1 +3V_CBSD A_A12/CC/BE2#
CORE LOGIC

AD25 10 70 R75 1@10K_0402_5% 124 CBS_CC/BE3#

AD25 VCC2 A_REG#/CC/BE3# CBS_CC/BE3# <23,24>
AD26 9 104 CBS_1510MF2 1 2 100 CBS_CPAR
AD26 VCC3 A_A13/CPAR CBS_CPAR <23,24>
AD27 7 126 R76 1@10K_0402_5% 102 CBS_CPERR#
PWR

AD27 VCC4 A_A14/CPERR# CBS_CPERR# <23,24>

AD28 6 137 CBS_1510MF4 1 2 110 CBS_CIRDY#
AD29 AD28 VCC5 A_A15/CIRDY# CBS_CCLK_INTERNAL CBS_CIRDY# <23,24>
5 12 R66 1@10K_0402_5% 107
AD30 AD29 VCC6 CBS_1510MF5 A_A16/CCLK CBS_CCLK_INTERNAL <23,24>
4 32 1 2
AD31 AD30 VCC7 R62 1@10K_0402_5% CBS_CBLOCK#
3 101 CBS_CBLOCK# <23,24>
AD31 A_A19/CBLOCK# CBS_CSTOP#
8 103 CBS_CSTOP# <23,24>
GND A_A20/CSTOP# CBS_CDEVSEL#
<18,22,23,26,33> C/BE#0 47 21 106 CBS_CDEVSEL# <23,24>
C/BE0# GND A_A21/CDEVSEL# CBS_CTRDY#
<18,22,23,26,33> C/BE#1 37 40 108 CBS_CTRDY# <23,24>
C/BE1# GND A_A22/CTRDY# CBS_CFRAME#
<18,22,23,26,33> C/BE#2 26
C/BE2#
GND GND
60
A_A23/CFRAME#
111 CBS_CFRAME# <23,24>
13 80 135 CBS_CSTSCHNG
<18,22,23,26,33> C/BE#3 C/BE3# GND A_BVD1/CSTSCHG CBS_CSTSCHNG <23,24>
93 134 CBS_CAUDIO
GND A_BVD2/CAUDIO CBS_CAUDIO <23,24>
PCM_ID 14 112 131 CBS_CINT#
<23,24> PCM_ID IDSEL GND A_READY/CINT# CBS_CSERR# CBS_CINT# <23,24>
132 133 CBS_CSERR# <23,24>
GND A_WAIT#/CSERR# CBS_CCLKRUN#
<15,23> CLK_PCI_PCM 20 136 CBS_CCLKRUN# <23,24>
PCLK A_WP/CCLKRUN#
35 73 75 CBS_CCD1#
<18,22,23,26> PCI_PAR PAR VCCD0# VCCD0# <23,24> A_CD1#/CCD1# CBS_CCD1# <23,24>
CBS_CCD2#
Card PWR

<18,22,23,26> PCI_SERR# 34 74 VCCD1# <23,24> 138 CBS_CCD2# <23,24>

SERR# VCCD1# A_CD2#/CCD2#
<18,22,23,26> PCI_PERR# 33 71 VPPD0 <23,24>
PERR# VPPD0 CBS_CREQ#
31 72 122
S/W

<18,22,23,26> PCI_STOP# STOP# VPPD1 VPPD1 <23,24> A_INPACK/CREQ# CBS_CREQ# <23,24>

28 105 CBS_CGNT#
<18,22,23,26> PCI_IRDY# IRDY# A_WE#/CGNT# CBS_CGNT# <23,24>
<18,22,23,26,33> PCI_TRDY# 29
TRDY# CBS_CVS1
<6,10,16,18,22,23,26,30,33> PCIRST# 19 130 CBS_CVS1 <23,24>
PRST# A_VS1#/CVS1 CBS_CVS2
<18,22,23,26> PCI_DEVSEL# 30 117 CBS_CVS2 <23,24>
DEVSEL# A_VS2#/CVS2
<18,22,23,26,33> PCI_FRAME# 27 66 V_PRST# <16,23,24>
FRAME# GRST# CBS_CRST#
<18,23> GNT#2 2 119 CBS_CRST# <23,24>
3 GNT# A_RESET/CRST# 3
<18,23> REQ#2 1 109 CBS_VCC
REQ# VCC_CARD
1@ PCI1510PGE_PQFP144

1@ PCI1510PGE_PQFP144

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 25 of 47
A B C D E
 5 4 3 2 1

Place close to pin 25 AD[0..31]

<18,22,23,24,25,33> AD[0..31]

MINI PCI TYPE III CLK_PC I_MINI

<18,22,23,25,33> C/BE#[0..3]
C/BE#[0..3]

2
R428
D JP24 +3VMINI 33_0402_5% D
+3VMINI

1
+3VAUXMINI
2
1 TIP RING 2 +3VAUXMINI 1 2 +3VALW
C614 R400 @0_0603_5%
3 4 22P_0402_50V8J
8PMJ-3 8PMJ-1 1
5 8PMJ-6 8PMJ-2 6
7 8PMJ-7 8PMJ-4 8
9 8PMJ-8 8PMJ-5 10 1 2 +3V
11 12 R399 2@ 0_0603_5%
<22> W LAN_ACT_LED LED1_GRNP LED2_YELP W LAN_LINK_10_LED <22>
<30> RADIO_DISABLE# 13 LED1_GRNN LED2_YELN 14 W LAN_LINK_80211A <22>
15 CHSGND REVERVED 16
<18> PIRQD# 17 INTB# 5V 18 +5VMINI
19 3.3V INTA# 20 PIRQC# <18>
21 RESERVED RESERVED 22
23 GROUND 3.3VAUX 24
<15> CLK_PCI_MINI 25 CLK RST# 26 PCIRST# <6,10,16,18,22,23,25,30,33>
27 GROUND 3.3V 28
<18> REQ#1 29 REQ# GNT# 30 GNT#1 <18>
31 3.3V GROUND 32
AD31 33 34
AD31 PME# MINI_PME# <31>
AD29 35 36
AD29 RESERVED AD30 W LAN_LINK_80211A
37 GROUND AD30 38 2 1
AD27 39 40 R398 100K_0402_5%
AD25 AD27 3.3V AD28
41 AD25 AD28 42
43 44 AD26 W LAN_LINK_10_LED 2 1
C/BE#3 RESERVED AD26 AD24 R397 100K_0402_5%
45 C/BE#3 AD24 46
AD23 47 48 1 2 AD18 IDSEL AD18
C AD23 IDSEL R403 2@ 100_0402_5% W LAN_ACT_LED C
49 GROUND GROUND 50 2 1
AD21 51 52 AD22 R429 100K_0402_5%
AD19 AD21 AD22 AD20
53 AD19 AD20 54
55 56 M66EN 2 1
GROUND PAR PCI_PAR <18,22,23,25>
AD17 57 58 AD18 R401 2@ 1K_0402_5%
C/BE#2 AD17 AD18 AD16
59 C/BE#2 AD16 60
<18,22,23,25> P C I_ IRDY# 61 IRDY# GROUND 62
63 3.3V FRAME# 64 PCI_FRAME# <18,22,23,25,33>
<19,22,25,30> CLKRUN# 65 CLKRUN# TRDY# 66 PCI_TRDY# <18,22,23,25,33>
<18,22,23,25> PCI_SERR# 67 SERR# STOP# 68 PCI_STOP# <18,22,23,25>
69 GROUND 3.3V 70
71 72 MPCIACT# 2 1 +3VAUXMINI
<18,22,23,25> PCI_PERR# PERR# DEVSEL# PCI_DEVSEL# <18,22,23,25>
C/BE#1 73 74 R405 2@ 100K_0402_5%
AD14 C/BE#1 GROUND AD15
75 AD14 AD15 76
77 78 AD13
AD12 GROUND AD13 AD11
79 AD12 AD11 80
AD10 81 82
AD10 GROUND A D9
83 GROUND AD09 84
A D8 85 86 C/BE#0
A D7 AD8 C/BE#0
87 AD7 3.3V 88
89 90 A D6
A D5 3.3V AD6 A D4
91 AD5 AD4 92
93 94 A D2
A D3 RESERVED AD2 A D0
95 AD3 AD0 96
+5VMINI 97 5V RESERVED_WIP 98 DIMM_SMCLK <12,13,15,18>
A D1 99 100
AD1 RESERVED_WIP DIMM_SMDATA <12,13,15,18>
101 GROUND GROUND 102
103 104 M66EN +3VAUXMINI +5VMINI +5VS
AC_SYNC M66EN L36
105 AC_SDATA_IN AC_SDATA_OUT 106
B 30mil B
107 AC_BIT_CLK AC_CODEC_ID0# 108 1 2
109 110 2@ BLM21A05 _0805
AC_CODEC_ID1# AC_RESET#
111 MOD_AUDIO_MON RESERVED 112 1 1 1 1
113 114 C600
AUDIO_GND GROUND C596 C616 C610
115 SYS_AUDIO_OUT SYS_AUDIO_IN 116
117 118 2@ 0.1U_0402_16V4Z 2@ 0.1U_0402_16V4Z 2@ 1000P_0402_50V7K
AUDIO_OUTGND AUDIO_INGND 2 2 2 2
119 AUDIO_GND AUDIO_GND 120
121 122 MPCIACT#
RESEVED MPCIACT# 2@ 0.1U_0402_16V4Z
+5VMINI 123 VCC5VA 3.3VAUX 124

127 127 128 128

2@AMP 1318914
+3VMINI +3VS
2@0.1U_0402_16V4Z 2@ 0.1U_0402_16V4Z
30mil 1 2
L35
1 1 1 1 1 2@ BLM21A05 _0805

C613 C612 C599 C598 C609

2@ 10U_1206_10V4Z 2@ 1000P_0402_50V7K
WIRELESS SUPPORT ONLY 2 2 2 2 2

A A
2@ 0.1U_0402_16V4Z

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 26 of 47
5 4 3 2 1
 A B C D E F G H

+5VALW +5VDDA
+5VDDA
U26
5 C134
1 W=40Mil VOUT 1000P_0402_50V7K 1
1
VIN HP_OUT_R
1 1 1 2
1 1 4 C556 1 1
BYPASS C555
3 1
C564 C562 EN 0.1U_0402_16V4Z C481 C554 HP_OUT_L 1 2
@4.7U_0805_10V4Z 0.1U_0402_16V4Z C558 2 2 4.7U_0805_10V4Z
2
2 2 GND 2 2 C165
TPS793475DBV_SOT23-5 2 1000P_0402_50V7K
4.7U_0805_10V4Z
0.1U_0603_50V4Z 0.1U_0402_16V4Z

<16,30,33,38> SUSP#

+5VDDA 1 2
L30
BLM21A05 _0805
+3VCC Place close to pin 2
R345 C486
AVDD_AC97 0.1U_0402_16V4Z 1 2 1000P_0402_50V7K CLK_CODEC_14M
+3VS
0_0805_5% 2 1

1
1 1 1 1 1 1
1 2 R341
C541 C551 C484 C491 C478 @10_0402_5%
0.1U_0402_16V4Z 4.7U_0805_10V4Z MAX 80mA 4.7U_0805_10V4Z C487
2 2 2 2 2 2 1000P_0402_50V7K

2
2 2
LEFT <28> 1
0.1U_0402_16V4Z

25

38

9
C477 U24 C479
RIGHT <28> @10P_0402_50V8K
0.1U_0402_16V4Z

AVCC

AVCC

VCC

VCC
2

14 35 LEFT 1 2
AUX_L LINE_OUT_L C476 @1000P_0402_50V7K R350
15 36 RIGHT 1 2
AUX_R LINE_OUT_R @100K_0402_5%
16 37 MDMIC 1 2
VIDEO_L MONO_OUT MD_MIC <29>
2 1 C483 1U_0603_10V4Z
C544 0.1U_0402_16V4Z 17 39
VIDEO_R HP_OUT_L HP_OUT_L <28>
23 41 HP_OUT_R <28>
LIN_IN_L HP_OUT_R
24 1 2 C500
LIN_IN_R
6 1 2 IAC_BITCLK <19,29>
CD_L_R BIT_CLK R359 22_0402_5% @27P_0402_50V8J
<21> INT_CD_L 2 1 1 2 18 1 2 CLK_CODEC_14M <15>
R360 0_0603_5% C549 1U_0603_10V4Z CD_L R342 @0_0402_5%
8 1 2 IAC_SDATA_IN0 <19>
C D_R_R SDATA_IN R357 47_0402_5%
<21> INT_CD_R 2 1 1 2 20 1 2
R363 0_0603_5% C547 1U_0603_10V4Z CD_R C485
2
XTL_IN

2
2 1 CD_GNA 1 2 19 22P_0402_50V8J
R362 @6.8K_0603_1% C546 1U_0603_10V4Z CD_GNA X4
2 1 21 24.576MHz_16P
<28> MICIN MIC1
R361 @6.8K_0603_1%

1
2 1 1 2 22 3 1 2
R369 @51K_0402_5% C545 0.1U_0402_16V4Z MIC2 XTL_OUT
2 1 MDSPK 1 2 13 29 1 2 C542
<29> MD_SPK 0.033U_0402_16V4ZPHONE AFLT1
R368 0_0402_5% C550 C499 820P_0603_50V7K 22P_0402_50V8J
MONO_IN 1 2 1 2 12 30 1 2
3 <28> MONO_IN 1U_0603_10V4Z PC_BEEP AFLT2 3
R364 C553 C493 820P_0603_50V7K
2

47K_0402_5% 1 28
VREFOUT
<19,29> IAC_RST# 11
R365 C552 RESET#
27
4.7K_0402_5% 2700P_0603_50V7K REFFLT
<19,29> IAC_SYNC 10
2 SYNC
32 1 2 C490
1

FLT3D @1U_0603_10V4Z
<19,29> IAC_SDATAO 5 1 1
SDATA_OUT 0.1U_0402_16V4Z
1
2 1 45 31 C523 C498
C557 R344 2 ID0# BPCFG_00/NC_50 1U_0603_10V4Z
1@1K_0402_5% 46 33
0.033U_0402_16V4Z R343 @1K_0402_5% ID1# FLTI_00/NC_50 2 2
34
FLTO_00/NC_50

2
2 EAPD SPK_SHUTDOWN#
<28> EAPD 47 43 SPK_SHUTDOWN# <28> 1 1
EAPD NC_00/GPIO0_50 R354 short the digital ground and analong ground
44
NC_00/GPIO1_50 C489 @100K_0402_5%
+3VCC 2 1 48
R339 10K_0402_5% S/PDIF_OUT @4.7U_0805_10V4Z
40
NC_00/HP_COMM_50 2 2
4 26

1
GND AGND
7 42
GND AGND
C492
1 @1U_0603_10V4Z
STAC9750_TQFP48
C471
1U_0603_10V4Z
2 1 CD_GNA 2
<21> CD_AGND
R367
0_0402_5%
ID0# ID1#
1

1 1 14.318 OPEN
R366
@6.8K_0603_1% 1 0 27MHZ
0 1 48MHZ
2

4 4

* 0 0 24.576MHZ

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 27 of 47
A B C D E F G H
 A B C D E

+5VDDA Gain Setting GAIN0 GAIN1 AV(inv) INPUT

IMPEDANCE

0 0 6dB 90K ohm

1
1 2 +5VALW R379 R380
L31 10K_0402_5% @10K_0402_5% 0 1 10dB 70K ohm
+5VAMP BLM21A05 _0805
1 2 +5VDDA

2
L32 GAIN0 1 0 15.6dB 45K ohm
1
@BLM21A05_0805 * 1
W=40mils GAIN1
1 1 21.6dB 25K ohm

1
1 1 1 1
R383 R384
C571 C582 C570 C583 @10K_0402_5% 10K_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_10V4Z 0.1U_0402_16V4Z

16
15
U28

6
2 2 2 2

2
PVDD1
PVDD2
VDD
Speaker Connector
1 2 C579 7 2 GAIN0 JP16
0.47U_0603_16V4Z RIN+ GAIN0 INTSPK_R+ 1
GAIN1 INTSPK_R- 1
3 2
GAIN1 INTSPK_L+ 2
3
RIGHT INTSPK_L- 3
1 2 C584 17 4
<27> RIGHT 0.1U_0402_16V4Z RIN- INTSPK_R+ 4
18
ROUT+
15 mils trace ACES_85205-0400

14 INTSPK_R-
ROUT-
1 2 C581 9
0.47U_0603_16V4Z LIN+
4 INTSPK_L+ @DAN217_SOT23
LOUT+ D45 D43

1
LEFT 1 2 C576 5 @DAN217_SOT23
<27> LEFT 0.1U_0402_16V4Z LIN- INTSPK_L-
8
LOUT-
+3VS
2

+3VS

3
R389 12
100K_0402_5% NC
2 BYPASS 2
10
BYPASS D44 D42
19
1

SHUTDOWN @DAN217_SOT23 @DAN217_SOT23

<27> SPK_SHUTDOWN#
1 1

GND1
GND2
GND3
GND4
+5VDDA
C588 C580
Q30 0.47U_0805_16V7K @0.1U_0402_16V4Z 1 2
1

D 2N7002_SOT23 D D TI6017A2_TSSOP20 2 2
20
13
11
1
2 2 HP_PLUG 2 R327
<27> EAPD
G G G 1K_0402_5%
S S Q31 S Q32 1
3

1
2N7002_SOT23 2N7002_SOT23
R328 R157 C161
@2K_0402_5% 2K_0402_5% 4.7U_0805_10V4Z
2 EXT. MIC
<30> MUTE JP11

2
5

L14 4
BLM11A121SPT_0603
1 2 3
6
<27> MICIN 2 1 1 2 EXTMIC 2
L29 1
C548 BLM11A121SPT_0603
0.22U_0603_10V7K 1 7
8
C458
47P_0402_50V8J JA6333L-6S0-TR
+3VS 2
1

3 3
R431 +3VS
100K_0402_5% C621
+3VS 0.1U_0402_16V4Z +5VDDA +5VDDA
1 2
2

U15
5

U14 R430 1
10K_0402_5% NC R436 R437 +3VS
1 5
P

<30> BEEP IN1 VCC

4 1 2 2 100K_0402_5% 100K_0402_5%
O A
2 4
IN2 Y
G

2
1 3 C619 R125
2

SN74AHC1G08HDCK_TSSOP5 GND 100K_0402_5%

1 2 1 2 1 2
3

TC7SH14FU_SSOP5
C617 R434 C624 @0.1U_0402_16V4Z HP OUT
0.1U_0402_16V4Z 2 2K_0402_5% 1U_0603_10V4Z JP9

1
HP_PLUG 5
+3V POWER <31> HP_PLUG
C620
1 2 MONO_IN R122 @220U_D_6.3M_R40 L12 4
MONO_IN <27>
0_0402_5% C142 BLM11A121SPT_0603
1

C 1U_0603_10V4Z 2 PR_RIGHT PR

+
<27> HP_OUT_R 1 2 1 1 2 3
1 2 1 2 2 6
<23,25> PCM_SPK# B PR_LEFT PL

+
R433 Q13 1 2 1 2 1 2 2
E <27> HP_OUT_L
2K_0402_5% C623 2SC2411K_SOT23 R155 L13 1
3

1U_0603_10V4Z 0_0402_5% C154 BLM11A121SPT_0603

1 1
@220U_D_6.3M_R40 7
8
C155 C144
1 2 1 2 47P_0402_50V8J 2 2
<19> ICH_SPKR
R432 C636 JA6333L-6S0-TR
2K_0402_5% C622

+
1 2
1U_0603_10V4Z 47P_0402_50V8J
1

220U_10V_M
4 4
D15

+
1 2
1SS355_SOD323
C635
2

220U_10V_M
Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 28 of 47
A B C D E
 5 4 3 2 1

+3V

1 +5VMDC 1 2
+3VMDC +5VALW
1 1 1 C626 R435
1 2 @1000P_0402_50V7K @1000P_0402_50V7K @0.1U_0402_16V4Z @0_0805_5%
+3V R443 0_0805_5% C627 C628 C625 2
1 2 @0.1U_0402_16V4Z
+3VALW R444 @0_0805_5% 2 2 2
1 2 JP25

C630 C629 1 2
0.1U_0402_16V4Z <27> MD_MIC MONO_OUT/PC_BEEP AUDIO_PWDN
4.7U_0805_10V4Z 3 4
D 2 1 AGND MONO_PHONE MD_SPK <27> D
5 6
AUXA_RIGHT RESERVED
7 8
AUXA_LEFT GND
9 10
CD_GND +5V
11 12
CD_RIGHT RESERVED
13 14
CD_LEFT RESERVED
15 16 1 2
GND PRIMARY_DN 1: Have primary CODEC on mother board
As close to P17 +3VMDC
17
3.3Vaux RESERVED
18 R438 10K_0402_5%
+3V
19 20
GND RESERVED
21 22 IAC_SYNC <19,27>
3.3Vmain AC97_SYNC R439 1
<19,27> IAC_SDATAO 23 24 2 IAC_SDATA_IN1 <19>
AC97_SDATA_OUT AC97_SDATA_IN1 @22_0402_5%
<19,27> IAC_RST# 25 26
AC97_RESET# AC97_SDATA_IN0
27 28 2 1
GND GND R441 10_0402_5%
29 30
AC97_MSTRCLK AC97_BITCLK
1 2 IAC_BITCLK <19,27>
R442 22_0402_5%
FOX_QT8A0301-3011

MDC Conn.

MDC Note
Touch Pad & Status LED Conn. Pin 1 is NC for Pctel and connexant MDC modem
C C
Pin 2 is NC for Pctel and connexant MDC modem
JP13
TP_CLK TP_DATA
<30> TP_CLK 1 2 TP_DATA <30>
3 4 +5VS
+5VS 5 6
7 8 PWR_LED# +5VALW
9 10 PWR_LED# <31>
ACT_LED# BATT_LED#
<21> ACT_LED# CHARGE_LED# 11 12 BATT_LED# <31>
<31> CHARGE_LED# 13 14 Screw Hole
15 16
+3VALW 17 18 LID_SW# <30>
H7 H8 H13 H12 H3 H19 H11 H5 H4 H2 H10 H16
19 20 @C315D126 @C315D126 @C315D126 @C315D126 @C394D118 @C394D118 @C394D118 @C315D118 @C394D118 @C394D118 @C394D118 @C394D118
ACES 87216-2012_20P

1
1 2 TP_CLK
C193 @220P_0603_50V8J H14 H17 H20 H21 H28 H27 H26 H18 H29 H6 H34 H37
@C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C138D138N @O197x138D197x138N @C315D177 @C177D87 @C177D79

1 2 TP_DATA
C171 @220P_0603_50V8J

1
CP1
5 4 CHARGE_LED#
6 3 ACT_LED#
7 2 PWR_LED# H33 H30 H32 H15 H25 H9 H23 H22 H1
8 1 BATT_LED# @O335x79D315x59@O335x79D315x59@O335x79D315x59@O335x79D315x59@H_O177x99D157x79 @O335x79D315x59 C197B256D157 C197B256D157 C256D87
B B
@220P_1206_8P4C_50V8K
1

1
Fiduial Mark
FD1 FD2 FD3 FD4 FD5 FD6 FD7
1 1 1 1 1 1 1

@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK

FD8 FD9 FD10 FD11 FD12 FD13 FD14

1 1 1 1 1 1 1

@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK
A A

FD15 FD16 FD17 FD18

1 1 1 1
Dell-Compal Confidential
@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 29 of 47
5 4 3 2 1
 A B C D E

EC_AVCC
+3VALW EC_3VDD +RTCVCC
0.1U_0402_10V6K 1 2 2
+3VALW +3VS
1 1 1 1 R411 0_0402_5%
1 C608 BD_ID 0V 0.5V 1.0V 1.5V

123
136
157
166

161
C611 C607 C595 C589 1U_0603_10V4Z

16

34
45

95
4.7U_0805_10V4Z 1000P_0402_50V7K C602 U32 1
2 2 2 2 0.1U_0402_16V4Z REV 0.1 0.2 0.3 1.0

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

VBAT
VDD

AVCC
2
0.1U_0402_16V4Z /10K 100K/10K 100K/25K 100K/43K
+5VALW
7 81 BATT_TEMP
<18,23,25> SIRQ SERIRQ AD0 BATT_TEMP <34>
8
LDRQ# AD1
82 I/O Address

1
BLM18PG600SN1_0603 9 83 VBATT BADDR1-0 Index Data
<19> LFRAME# LFRAME# AD2
L33
<19> LAD0 15 84 BATT-OVP <35> ALI/MH#
R393 0 0 2E 2F
LAD0 Host interface AD3
1 +3VALW 1 2 EC_AVCC <19> LAD1 14
13
LAD1 IOPE0AD4
87
88
100K_0603_1% 4E
* 01 10 (HCFGBAH, 4F
HCFGBAL) (HCFGBAH, HCFGBAL)+1 1
2 1 <19> LAD2 LAD2 IOPE1/AD5
10 89 BATT_CHGI 1 1 Reserved

2
<19> LAD3 CLK_PCI_LPC LAD3 AD Input IOPE2/AD6
C594 C593 18 90
1000P_0402_50V7K <15> CLK_PCI_LPC LCLK IOPE3/AD7 ADP_I <35,37>
0.1U_0402_16V4Z 1 2 EC_RST 19 93 B D_ID
1 2 +3VALW RESET1# DP/AD8
R402 10K_0402_5% 22 94
SMI# DN/AD9

1
1 2 ECAGND 23 2
L34 PWUREQ# R394
99 EN_FAN2 <7>
BLM18PG600SN1_0603 DA0 43K_0603_1% C592
100 EN_FAN1 <7>
DA output DA1 0.1U_0402_10V6K
<19> SCI# 31 101 IREF <35>
IOPD3/ECSCI# DA2 1
102

2
DA3 IREF2 <35>
5 32 ECAGND
AD B[0..7] <18> GATEA20 GA20/IOPB5 IOPA0/PWM0
ADB[0..7] <31> <18> KBRST# 6 33 BEEP <28>
KBRST/IOPB6 IOPA1/PWM1
36
KBA[0..19] KSI[0..7] PWM IOPA2/PWM2
KBA[0..19] <31> <31,32> KSI[0..7] 37 ACOFF <35>
KSI0 or PORTA IOPA3/PWM3
71 38 VLBA# <19>
KSO[0..15] KSI1 KBSIN0 IOPA4/PWM4
<31> KSO[0..15] 72 39 EC_ON <32>
KSI2 KBSIN1 IOPA5/PWM5
73 40 LID_OUT# <19>
KSI3 KBSIN2 IOPA6/PWM6
74 43 PCM_SUSP# <23,24,25>
KSI4 KBSIN3 IOPA7/PWM7
77
KSI5 KBSIN4 KSO16
78 153 KSO16 <32>
KSI6 KBSIN5 IOPB0/URXD KSO17
Place closely pin 18 79
KBSIN6 IOPB1/UTXD
154
1 2 TP_DATA KSI7 80 Key matrix scan 162 EC_DEBUG
+5VS R407 10K_0402_5% CLK_PCI_LPC KBSIN7 IOPB2/USCLK SMB_EC_CK1
163 SMB_EC_CK1 <16,31,34>
KSO0 PORTB IOPB3/SCL1 SMB_EC_DA1
49 164 SMB_EC_DA1 <16,31,34>
KBSOUT0 IOPB4/SDA1

1
1 2 TP_CLK KSO1 50 165
KSO2 KBSOUT1 IOPB7/RING/PFAIL/RESET2 PCIRST# <6,10,16,18,22,23,25,26,33>
R404 10K_0402_5% R406 51
10_0402_5% KSO3 KBSOUT2
52 168 PWRBTN# <19>
KSO4 KBSOUT3 IOPC0 SMB_EC_CK2
53 169 SMB_EC_CK2 <6,8>
LID_SW# KSO5 KBSOUT4 IOPC1/SCL2 SMB_EC_DA2
2 1 56 170
2

+3VALW KBSOUT5 IOPC2/SDA2 SMB_EC_DA2 <6,8>

R410 100K_0402_5% 1 KSO6 57 171
KSO7 KBSOUT6 PORTC IOPC3/TA1 FAN1_TACH <7>
58 172 EC_WAKEUP# <18>
2 C597 KSO8 KBSOUT7 IOPC4/TB1/EXWINT22 2
59 175 EC_THRM# <19>
15P_0402_50V8J KSO9 KBSOUT8 IOPC5/TA2
60 176 FAN2_TACH <7>
2 KSO10 KBSOUT9 IOPC6/TB2/EXWINT23
61 1 PM_PWROK <10,19,32>
KSO11 KBSOUT10 IOPC7/CLKOUT
64 ENV0 ENV1 TRIS
+5VS KSO12 KBSOUT11
65 26 ACIN <18,34,36>
KSO13 KBSOUT12 IOPD0/RI1/EXWINT20
RP7 66 29 PM_SLP_S4# <19>
IRE 0 0 0
PS2_CLK KSO14 KBSOUT13 PORTD-1 IOPD1/RI2/EXWINT21
1 8 67 30 PM_SLP_S3# <15,19>
PS2_DATA KSO15 KBSOUT14 IOPD2/EXWINT24/RESET2
2 7 68 * OBD 0 1 0
KBD_DATA KBSOUT15
3 6 2 ON/OFF <32>
KBD_CLK EC_TINIT# IOPE4/SWIN
4 5 105
TINT# IOPE5/EXWINT40
44 PM_SLP_S5# <19>
DEV 1 0 0
EC_TCK 106 PORTE 24
TCK IOPE6/LPCPD/EXWIN45 EXTVGA_IN# <16>
8.2K_8P4R_1206_5% EC_TDO 107 25 PROG 1 1 0
TDO IOPE7/CLKRUN/EXWINT46 CLKRUN# <19,22,25,26>
EC_TDI 108 JTAG debug port
EC_TMS TDI KBA0
109 124
TMS IOPH0/A0/ENV0 KBA1
IOPH1/A1/ENV1
125 SHBM=1: Enable shared memory with host BIOS
+3VALW KBD_CLK 110 126 KBA2 TRIS=1: While in IRE and OBD, float all the
RP6 KBD_DATA PSCLK1/IOPF0 IOPH2/A2/BADDR0 KBA3
111 127 signals for clip-on ISE use
FSEL# PS2_CLK PSDAT1/IOPF1 IOPH3/A3/BADDR1 KBA4
1 8 114 128
SELIO# PS2_DATA PSCLK2/IOPF2 PORTH IOPH4/A4/TRIS KBA5
2 7 115 131
FR D# TP_CLK PSDAT2/IOPF3 PS2 interface IOPH5/A5/SHBM KBA6
3 6 <29> TP_CLK 116 132
EC_SMI# TP_DATA PSCLK3/IOPF4 IOPH6/A6 KBA7
4 5 <29> TP_DATA 117 133
LID_SW# PSDAT3/IOPF5 IOPH7/A7
<29> LID_SW# 118
8.2K_8P4R_1206_5% PSCLK4/IOPF6 ADB0
<39> AC_LOW_PRES# 119 138
PSDAT4/IOPF7 IOPI0/D0 ADB1
139
IOPI1/D1 ADB2
140
IOPI2/D2 ADB3
141
C R Y1 PORTI IOPI3/D3 ADB4 +3VALW
158 144
R423 20M_0603_5% 32KX1/32KCLKIN IOPI4/D4 ADB5
145
C R Y2 IOPI5/D5 ADB6
1 2 160 146
32KX2 IOPI6/D6 ADB7
147
IOPI7/D7 KBA1
32.768KHZ_12.5P R424 (ENV1) 2 1
2 1 150 FR D# R412 10K_0402_5%
3 IOPJ0/RD FRD# <31> 3
1 1 120K_0402_5% PORTJ-1 151 FWR#
IOPJ1/WR0 KBA2
X5 (BADDR0) 2 1
C615 C618 152 SELIO# R414 10K_0402_5%
12P_0402_50V8J SELIO# SELIO# <31>
10P_0402_50V8K
2 2 EC_SMI# KBA3
<19> EC_SMI# 62
IOPJ2/BST0 IOPD4
41 SCRLED# <32> (BADDR1) 2 1
LAN_DISABLE# 63 42 R416 @10K_0402_5%
<22> LAN_DISABLE# IOPJ3/BST1 PORTD-2 IOPD5 NUMLED# <32>
<16> G_RST# 2 1 69 54 CAPSLED# <32>
IOPJ4/BST2 PORTJ-2 IOPD6 KBA5
R390 0_0402_5%
<19> EC_SWI# 70
IOPJ5/PFS IOPD7
55 (SHBM) 2 1
75 R418 10K_0402_5%
<26> RADIO_DISABLE# IOPJ6/PLI
76 143 KBA8
<15,19> PM_SLP_S1# IOPJ7/BRKL_RSTO IOPK0/A8
142 KBA9
IOPK1/A9 KBA10
<33,38> SYSON 148 135
IOPM0/D8 PORTK IOPK2/A10 KBA11
<16,27,33,38> SUSP# 149 134
+3VALW IOPM1/D9 IOPK3/A11 KBA12
<33,40> VR_ON 155 130
R415 IOPM2/D10 PORTM IOPK4/A12 KBA13
<19,40> VGATE 156 129
IOPM3/D11 IOPK5/A13_BE0 KBA14 +3VALW
<19> RSMRST# 2 1 3 121
IOPM4/D12 IOPK6/A14_BE1
1

0_0402_5% 4 120 KBA15

<28> MUTE CPU_DT/MO# IOPM5/D13 IOPK7/A15_CBRD
R395 27 JP17
100K_0402_5% IOPM6/D14 KBA16
1 2 <16> BKOFF# 28 113 1
IOPM7/D15 IOPL0/A16 KBA17 EC_TINIT# 1 For EC debug C591 0.01U_0402_25V4Z
112 2
R417 FSEL# PORTL IOPL1/A17 KBA18 EC_TCK 2 BATT_CHGI ECAGND
173 104 3 1 2
2

<31> FSEL# SEL0# IOPL2/A18 3

CPU_DT/MO# 100K_0402_5% 174 103 KBA19 EC_TDO 4
SEL1# IOPL3/A19 EC_TDI 4
47 48 FSTCHG <35> 5
CLK IOPL4/WR1# 5
1

EC_TMS 6 BATT_TEMP 1 2
R396 6 C587 0.01U_0402_25V4Z
7
7
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7

NC10

@100K_0402_5% KSO16 8
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

KSO17 8
9
EC_DEBUG 9 C585 0.01U_0402_25V4Z
10
2

10 BATT-OVP ECAGND
1 2
17
35
46
122
159
167
137

96

11
12
20
21
85
86
91
92
97
98

+3VALW @96212-1011S
+3VALW
VBATT 1 2
2

4 SUS_STAT# <16,19> ECAGND C586 0.01U_0402_25V4Z 4

2

R422
CPU_DT/MO# CPU 3.3K_0402_5% +3VALW R421 PC87591L-VPCN01 A2_LQFP176
100K_0402_5%
2
G
14
1

HIGH DT Dell-Compal Confidential

1

4 1 3
P

FWE# A EC_FLASH# <19>

6
Compal Electronics, Inc.
D

<31> FWE# O
LOW MOBILE 5 FWR# Q35
B
G

2N7002_SOT23 Title
U33B
SCHEMATIC, M/B LA-1452
7

SN74LVC32APWLE_TSSOP14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS Custom 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 30 of 47
A B C D E
 A B C D E

AD B[0..7]
<30> ADB[0..7]
KBA[0..19]
<30> KBA[0..19]

Output Port
Input Port

+5VALW

1 2 +3VALW 1 2
+3VS
R386 100K_0402_5%
+3VALW 1 2 C575
1 R233 100K_0402_5% 0.1U_0402_16V4Z 1

20
1 2
1 2 C577 0.1U_0402_16V4Z U27
R382 100K_0402_5% +3VALW ADB0 3 2

VCC
D0 Q0 PWR_LED# <29>
ADB1

20
4 5 CHARGE_LED# <29>
U30 ADB2 D1 Q1
7 6 BATT_LED# <29>
ADB0 ADB3 D2 Q2
2 18 1 2 8 9

VCC
<16,17> M_SEN# 1A1 1Y1 ADB1 0.1U_0402_16V4Z ADB4 D3 Q3 VCHG <35>
4 16 C605 13 12
<6,19> PROCHOT# 1A2 1Y2 ADB2 ADB5 D4 Q4
<16> INTVGA_IN# 6 14 14 15
PME# 1A3 1Y3 ADB3 ADB6 D5 Q5

14
8 12 17 16
1A4 1Y4 ADB4 U33C ADB7 D6 Q6
<28> HP_PLUG 11 9 18 19
2A1 2Y1 ADB5 KBA2 D7 Q7
13 7 9

P
<16> ENABKL 2A2 2Y2 ADB6 A AA
15 5 8 11

GND
<39> AC_LOW_PRES2# 2A3 2Y3 ADB7 SELIO# O LARST# CP
<34> 9C/12C#/8C# 17 3 10 1
2A4 2Y4 B MR

G
1 SN74LVC32APWLE_TSSOP14 SN74HCT273PW_TSSOP20

GND

10
+3VALW 1G
19
2G
SN74LVC244APWR_TSSOP20

10
14
+5VALW 1 2 1 2
U33D R377 20K_0402_5%
KBA1 12 C569

P
A
11 C C 1U_0603_10V4Z
SELIO# O
13
<30> SELIO# B G
SN74LVC32APWLE_TSSOP14 NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
7

+5VALW

+5VALW

1
1 2 R375
2 100K_0402_5% 2
+3VALW C590
+3VALW 0.1U_0402_16V4Z U29

2
8 1
1

+5VALW VCC A0
7 2
R387 AA WP A1
1 2 <16,30,34> SMB_EC_CK1 6 3
10K_0402_5% R419 100K_0402_5% SCL A2
<16,30,34> SMB_EC_DA1 5 4
SDA GND
1 2 SMB_EC_DA1
CC 1 2 R453 8.2K_0402_5% AT24C16_SO8
2

R420 100K_0402_5% 1 2 SMB_EC_CK1

LAN_PME# 1 2 R454 8.2K_0402_5% EC I2C Bus Address:
<22> LAN_PME#
R49 0_0402_5%
MINI_PME# 1 2 24C164: 1011xxx R/W#
<26> MINI_PME#
R48 0_0402_5% 24C16: 1010xxx R/W#
PCM_PME# 1 2 PME#
<23,25> PCM_PME#
R45 0_0402_5%

CP2
KSI1 4 5
KSI7 3 6
KSI6 2 7
KSO9 1 8

@100P_1206_8P4C_50V8K
CP3
KSI4 4 5 +3VALW
KSI5 3 6 U16
<30> KBA[0..19]
KSO0 2 7
3 INT_KBD CONN. KSI2 1 8 KBA0 21
A0 VCC0
31 3
KBA1 20 30 1 1
@100P_1206_8P4C_50V8K KBA2 A1 VCC1
19
CP4 KBA3 A2 C632 C631
18
KSI3 KBA4 A3 ADB0 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4 5 17 25
KSO5 3 KBA5 A4 D0 ADB1 2 2
6 16 26
KSO1 2 KBA6 A5 D1 ADB2
7 15 27
KSI0 KBA7 A6 D2 ADB3
1 8 14 28
KBA8 A7 D3 ADB4
KSO10

KSO14

KSO12

KSO6

KSO7

KSO2

KSO1
KSI3

KSO0

KSI4

KSI6

KSI1

8 32
@100P_1206_8P4C_50V8K KBA9 A8 D4 ADB5
7 33
CP5 KBA10 A9 D5 ADB6
36 34
KSO2 4 KBA11 A10 D6 ADB7
5 6 35
KSO4 3 KBA12 A11 D7
25

23

21

19

17

15

13

11

6 5 ADB[0..7] <30>
A12
9

JP10 KSO7 2 7 KBA13 4

KSO8 1 KBA14 A13
8 3 10 1 2
Dummy

23

21

19

17

15

13

11

A14 RP# +3VALW

KBA15 2 11 R440 100K_0402_5%
@100P_1206_8P4C_50V8K KBA16 A15 NC
1 12
24

22

20

18

16

14

12

10

A16 READY/BUSY#
8

CP6 KBA17 40 29
KSO6 4 KBA18 A17 NC0
5 13 38
24

22

20

18

16

14

12

10

KSO3 3 KBA19 A18 NC1

6 37
KSO12 2 A19
7
KSO15

KSO11

KSO13

KSO13 1
KSO3

KSO8

KSO4

KSI0

KSO5
KSI2

KSI5

KSO9

KSI7

8 <30> FSEL# 22
CE#
<30> FRD# 24 23
@100P_1206_8P4C_50V8K OE# GND0
<30> FWE# 9 39
CP7 WE# GND1
KSO14 4 5
KSO11 3 6 SST39VF080-70_TSOP40
KSO10 2 7
FOX_GS22250-0001 KSO15 1 8

@100P_1206_8P4C_50V8K
4 4

KSO[0..15]
<30> KSO[0..15]

<30,32> KSI[0..7]
KSI[0..7] Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 31 of 47
A B C D E
 A B C D E

+3VALW

1
R186
RTC Battery 100K_0402_5% Power BTN
D12

2
PM_PWROK <10,19,30>
BATT1 1 ON/OFF
ON/OFF <30>

1 C638
- 2 +
1 RTCPWR
ON/OFFBTN# 3
2 EC_ON# <37>
@1000P_0402_50V7K @1000P_0402_50V7K +3VALW DAN202U_SC70

VL ML1220T13RE

1
1 2 D41 1
1 1000P_0402_50V7K

1
VL R188 C209
1
C639 4.7K_0402_5% D16

1
D17 1SS355_SOD323 RLZ20A_LL34
+RTCVCC 2
2 1

2
1

2
R449 2 EC_ON 22K
1 2 2

2
<30> EC_ON

100K
R447 470K_0402_5% 1 2 R189 22K
+RTCVCC

100K
100K_0402_5% R448 470K_0402_5% BAS40-04_SOT23 CHGRTC 22K_0402_5%

2
Q21
3 1 1 2 DTC124EK_SOT23
2

3
SM_INTRUDER# <18>

1
D C633
2 Q41 0.1U_0402_16V4Z
G 2N7002_SOT23 Q22
S DTC115EKA_SOT23 WHEN R=0,Vbe=1.35V
3 WHEN R=33K,Vbe=0.8V
1

D
SHDN_1632 <36>
2 Q40
<36> SHDN#
G 2N7002_SOT23
S
3

2 2

+5VALW USB_AS USB_BS +3VALW

USB Over Current USB PORT
1

R212
R12 100K_0402_5%
W=40mils USB_AS USB_BS
USB_A USB_B
2

U6
1 8 1 2 OVCUR#0 1 2 2 1
GND OC1# OVCUR#0 <19>
2 7 100K_0402_5% R210 47K_0402_5% L38 1 1 L40
IN OUT1

1
1 3 6 FBM-11-451616-800T 1 1 FBM-11-451616-800T
EN1# OUT2 OVCUR#2 + + + +
4 5 1 2 OVCUR#2 <19>
C16 EN2# OC2# R211 47K_0402_5% 1 C641 C10 C12 C231 C229 C642
1
0.1U_0402_16V4Z TPS2042ADR_SO8 @100U_4A_10V 0.1U_0402_16V4Z @100U_4A_10V

2
2 C238 C237 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 150U_D3_10VM 150U_D3_10VM
N ote: 0.1U_0402_16V4Z
JP4
USB_AS=USB_BS=Trace width=40mils 1
VCC VCC
5
<33> SYSON# USB0D- 2 6 USB2D-
USB0D+ D0- D1- USB2D+
3 7
D0+ D1+
4 8
VSS VSS
3 3
1 1 10 9 1 1
G2 G1
12 11
C232 C11 G4 G3 C13 C230
@15P_0402_50V8J FOX_UB11123-8Z4-HT @15P_0402_50V8J
2 2 2 2

@15P_0402_50V8J
@15P_0402_50V8J

JP5
<30> KSO16 1 2 KSI0 <30,31>
1 2
<30> CAPSLED# 3 4 SCRLED# <30> 2 1 2 1
3 4 R209 0_0402_5% R9 0_0402_5%
5 6 NUMLED# <30>
5 6 ON/OFFBTN#
7 8
7 8 U21 U17
+3VS 9 10 +3VALW
9 10 USBP0- USB0D- USB2D- USBP2-
<19> USBP0- 1 4 4 1 USBP2- <19>
SUYIN_12750AR-10G2T-9
USBP0+ USB0D+ USB2D+ USBP2+
<19> USBP0+ 2 3 3 2 USBP2+ <19>
@JTS0402-02_4P @JTS0402-02_4P

2 1 2 1
R208 0_0402_5% U22 R8 0_0402_5%
1
1 4
Power SW Function Button 3
3 6

5
@CM1210_6P

5
4 4
+3VS

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 32 of 47
A B C D E
 A B C D E

+12VALW
+1.5VALW to +1.5VS Transfer

1
+12VALW
R445
68K_0402_5%

1
+1.5VALW +1.5VS R451

2
100K_0402_5%
U66
8 1 0.1U_0402_16V4Z

2
D S

1
7 2 SUSON SYSON#
D S <32> SYSON#

1
1 6 3 1 1 R446
D S

1
1 R378 D 47K_0402_5% 1
5 4 1

1
C568 D G C573 C572 470_0805_5% D Q2
<30,38> SYSON 2
10U_1206_10V4Z SI4800DY_SO8 10U_1206_10V4Z SYSON# 2 C634 G 2N7002_SOT23

2
2 2 2 G 0.01U_0402_25V4Z S

1 2

3
Q39 S 2

1
D 2N7002_SOT23
2 SUSP Q61
G R450 @SM05_SOT23
S 1M_0402_5%

3
Q60
RU NON 2N7002_SOT23

3
+12VALW

1
+CPU_CORE
+3VALW R426
10K_0402_5%

1
R427

2
2
@330_0603_5%
+3VALW to +3V Transfer R425
<7,17> SUSP
@100K_0402_5%

1
+3VALW +3V D

1
D Q36
<16,27,30,38> SUSP# 2
U70 2 Q38 G 2N7002_SOT23
8 1 0.1U_0402_16V4Z G @2N7002_SOT23 S

3
1
D S
7 2 S

3
D S
1
2 2
6 3 1 1
D S R187 R456
5 4
D G

1
C208 C210 470_0402_5% D 100K_0402_5%
1
SI4800DY_SO8 VR_ON 2 Q37

2
2 2 <30,40> VR_ON
C207 G @2N7002_SOT23
2

22U_1206_10V4Z S

3
2
1

22U_1206_10V4Z D
2 SYSON#
SUSON G
S Q20
3

2N7002_SOT23

+5VALW to +5VS Transfer

+12VALW +5VS
1

+5VALW +5VS JP27

R408 <18,22,23,25,26> AD9 1 2 PCI_TRDY# <18,22,23,25,26>
100K_0402_5% U31 22U_1206_10V4Z
<18,22,23,25,26> PCI_FRAME# 3 4 PCIRST# <6,10,16,18,22,23,25,26,30>
8 1 CLK_PCI_DEBUG <15>
D S 5 6
7 2
2

D S 7 8 C/BE#3 <18,22,23,25,26>
1

1M_0402_5% 6 3
D S <18,22,23,25,26> C/BE#2 9 10 C/BE#1 <18,22,23,25,26>
5 4 1 1 R413 <18,22,23,25,26> AD8
D G 11 12 AD7 <18,22,23,25,26>
1

3 470_0805_5% 3
1 <18,22,23,25,26> AD5 13 14 AD3 <18,22,23,25,26>
1

D R409 SI4800DY_SO8 C603 C604 <18,22,23,25,26> AD1 15 16 AD0 <18,22,23,25,26>

SUSP 2 C601 RU NON
<18,22,23,25,26> AD2
2

0.01U_0402_25V4Z 2 2 17 18 C/BE#0 AD4 <18,22,23,25,26>

G <18,22,23,25,26> AD6
2 19 20 C/BE#0 <18,22,23,25,26>
S
3

Q33 1@AMP 5-175638-0

2N7002_SOT23
1

0.1U_0402_16V4Z D
2 SUSP
+5VALW G
S Q34
3

1 2N7002_SOT23
CLK_PCI_DEBUG
+ C606 Debug PORT

2
150U_D3_10VM
R458
2 33_0402_5%

1
1
C637
10P_0402_50V8K
2
+3VALW +3VS
+3VALW to +3VS Transfer
U20 C131
8 1 0.1U_0402_16V4Z
D S
7 2 1 1
D S
1

6 3
D S R100
1 5 4
D G C133 470_0402_5%
1 2 22U_1206_10V4Z2
4 + C145 SI4800DY_SO8 4
150U_D2_6.3VM C132
2

10U_1206_10V4Z
2 2
1

D
RU NON 2 SUSP
G Dell-Compal Confidential
Q19
S
Compal Electronics, Inc.
3

2N7002_SOT23
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 33 of 47
A B C D E
 A B C D E

Detector

+3VALWP

BATT+
PL4
PR161
BATT++

BATT+
1 2 LOW_PWR <39>
1 100K_0402_5% 1
MBH2012102YZT_0805
PL5

1 2 BATT++
FBM-L18-453215-900-LMA90T_1812 9C/12C#/8C# <31>
PR162

1
VIN
PCN1 PR163 1K_0402_5%
RP34-8RD-3PDL2J PL6 PC44 @1K_0402_5%

2
PC43 0.1U_0805_25V7K
3 A DPIN 1 2 0.1U_0805_25V7K
VIN

1
1 GND 12P_0603_50V8J MCK4532800YAT_1812
PR44
560P_0603_50V7K

AIR_ADP 2 10_1206_5%
1

12P_0603_50V8J

560P_0603_50V7K
PC46

PR45

1
1K_0402_5%
4
5
6
7

1 2
PC48

PC47
1 2 BATT_TEMP
2

BATT_TEMP <30>

1
PZD1 PCN2
PC45

PL7 RLZ24B 1 PD6

BATT+
2

2
BATT+ @BAS40-04

2200P_0603_50V7K
ADPGND 1 2 3
ID

1
PC219
4
MCK4532800YAT_1812 B/I
5

2
TS
6

2
SMD
7
SMC
10 8
GND GND-

2
11 9 PR47
GND GND-
1 2
2 PR46 +3VALWP 2
1K_0402_5% 25.5K_0402_1%
SUYIN-200275MR009G516ZL 9P

1
PR48
100_0402_5%
1 2 SMB_EC_DA1 <16,30,31>

1
PR49 100_0402_5%
PCN2 battery connector pin assignment <16,30,31> SMB_EC_CK1
2 1
PD7
S M ART Battery: @BAS40-04

1 . B ATT+

2
2 . B ATT+
3 .9C/12C#/8C# PD8
4 .B/I
@BAS40-04 +5VALWP

5. TS

3
PR51
6 . S M B _EC_DA1 +5VALWP 2.2M_0603_5%
7 . SMB_EC_CK1 VL 1 2 2 1
VS
B+

8 . G ND PR50
9 . G ND 100K_0603_5%

1
1
PC52 PR52
0.01U_0603_50V7K 499K_0603_1%

2
PU5A

2
PD9

8
3 3
RB751V
+ 3
2 1 1
<6,36> SHDN_1632#
Vin Detector - 2

1
0.1U_0603_16V
PD10

1
1000P_0603_50V8J
LM393A PR53
17.90V/17.24V

4
RB751V

1
PC50

PC51
499K_0603_1% PC49
2 1 PR55 1000P_0603_50V8J

2
<35> ACON 191K_0603_1%

2
PR56
1M_0603_1%

2
1 2
VIN PR54
VIN
VL 1 2
1

1
84.5K_0603_1%

PR59
VS 34K_0603_1%
PR58

10K_0603_5% PR60

2
10K_0603_5%
PR57

1 2 47K_0603_5% PACIN <35>

ACIN <18,30,36> PR32 2 2 1 P ACIN
PR61 PQ12
PU5B
Precharge detector
2

2
8

22K_0603_5% 66.5K_0603_1% 2N7002

3
1 2 5 + 15.97V/14.84V FOR

1
7

1
PACIN <35>
6 - ADAPTOR
20K_0603_1%1
1

1
1000P_0603_50V8J

LM393A
4
PC53

PR62

PC54 PZD2 PR63

100K
0.1U_0603_16V RLZ4.3B 10K_0603_5% 2
2

PQ13 +5VALWP
2

DTC115EUA
2

100K
4 4

3
2 1 RTCVREF
PR64
10K_0603_5%
Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 34 of 47
A B C D E
 A B C D E

Iadp=0~4.10A(90W) Charger
Iadp=0~3.20A(70W)
B+++
Iair=0~2.25A(Air)
P3 B+
P2
PQ14 PQ15 PR65 PL8 PQ16
SI4825DY_SO-8 SI4825DY_SO-8 0.02_2512_1% SI4825DY_SO-8
VIN 8 1 1 8 2 1 1 2 1 8

@15U_D_25V

10U_1210_25V

10U_1210_25V

0.1U_0805_25V7K
7 2 2 7 FBM-L18-453215-900-LMA90T_1812 2 7

1
PC226

PC55
6 3 3 6 + 3 6

2200P_0603_50V7K
PC56
5 5 5

PC57

PC58
1 1

2
PR66

4
200K_0402_5% PR67
47K_0603_5%
1 2

3
2
1
VIN

2
PD11
PR69 4 PR70
1SS355
PR68 PU6 0_0603_5%
ACOFF# 150K_0402_5% MB3887 PQ17 10K_0603_5%
1 2
1 24 SI4835DY_SO-8

1
-INC2 +INC2 ACOFF#
<30,37> ADP_I

1
PR72 2 1 2 23 PC59

5
6
7
8
22K_0402_5%
1 D OUTC2 GND
PR71 2200P_0603_50V7K
<34> PACIN 1 2 2
G 100K_0603_5% 3 22 CS 1 2
+INE2 CS 100K

0.01U_0402_16V
S PQ19 2
3

ACOFF <30>

@28.7K_0603_1%
2N7002

1
PC61
ACON 4 21 1 2
<34> ACON

1
-INE2 VCC(o)

21K_0603_1%

PR74
100K PQ18
PR73 PR76 PC60 DTC115EUA

PR75

3
1 2 1 2 5 20 0.1U_0805_25V7K
16.9K_0603_1% 10K_0603_5% FB2 OUT PC63
1

@30.1K_0603_1%
PC62 0.1U_0603_16V

2
4700P_0603_50V 6 19 1 2 LXCHRG
VREF VH PC66

0.1U_0603_16V
PC64
0.1U_0805_25V7K

1
1 2 1 2 7 18 1 2
FB1 VCC

PR80
PL9 PR82

2
<30> IREF2 PC65 PR79 15U_SPC-1204P-150 0.02_2512_1% BATT+
2 2200P_0603_50V7K 1K_0603_5% 8 ACON <34> BATT+ 2
17 1 2 1 2 1 2
-INE1 RT

2
PR81

4.7U_1210_25V

4.7U_1210_25V
1 2 9 16 47K_0603_1%

1
<30> IREF +INE1 -INE3

47U_EC_25V
PD13

1
0.01U_0402_16V

PC68

PC70

PC71
PR83 PR85 PC69 EA60QC04 +
1

21K_0603_1% 2 1 10 15 1 2 1 2
OUTC1 FB3
1
IREF=0.82*Icharge

2
PC72
PR86 PR84 330K_0603_5% 1500P_0603_5%
20K_0603_1% 10K_0603_5%
IREF=0~3.3V 11 14
2

3
OUTD CTL
2

1
1 2
12 13 PR87
-INC1 +INC1 @10K_0603_5%
PC73
+3VALWP 10P_0603_50V

2
CS
1

PR231
1

47K_0603_5%
2

100K
2 PR164 104K_0603_0.1%
PQ63 2 1 2 1
DTC115EUA
1

100K PR89
PR36 2.2M_0603_5% 312K_0603_0.1%
3

BATT++
3 1 2 1
3 100K 3
2 PQ40 1 2
<30> FSTCHG PQ64 2N7002
Charge voltage
2
845K_0603_1%

DTC115EUA
1

100K PC74
4S CC-CV MODE : 16.8V
PR90

PR37 100K_0603_5% 22P_0603_50V

3

VS
2 1
+5VP
VCHG is H
4S PULSE MODE : 17.4V
1
2

PQ41 VCHG is L
0.1U_0603_16V
300K_0603_0.5%
0.01U_0603_50V7K

PC154

DTC115EK
100K
1

1
PC119

2
PR91

VCHG <31>
2

100K
2

PU7A
8

+ 3
1
<30> BATT-OVP - 2

LM358
4
1

143K_0603_0.5%

0.01U_0603_50V7K
1
PR92

PC76
@0.1U_0603_16V
1

@2.2K_0603_5%
PC75

PR93
2

4 4

OVP voltage :
LI-4S :18.0V----BATT-OVP=2.00V Dell-Compal Confidential
Compal Electronics, Inc.
Title
LI-3S :13.5V----BATT-OVP=1.50V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
BATT-OVP=0.2206*BATT++ R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 35 of 47
A B C D E
 A B C D E

+3.3V/+5V/+12V
B+

1 1
PL10
FBM-L11-322513-151LMAT
1

PC77 4.7U_1210_25V
1 2

470P_0805_100V

1
2
PC79

PC78
DAP202U PD14
0.1U_0805_25V7K PD15 PR94 EC11FS2

1
1 2 BST31 BST51 22_1206_5%

2
B++++

3
SNB 2 1 FLYBACK

2
2200P_0603_50V7K

4.7U_1210_25V
0.1U_0805_25V7K

4.7U_1210_25V

8
7
6
5
@15U_D_25V

VL
PC84

1
1

PC227

+ PQ21 VS 0.1U_0805_25V7K
PC82

PC83
PC80

PC81

SI4800DY_SO-8 PR95 1 2

3
0_0402_5% PT1
2

4.7U_1206_10V

0.1U_0603_16V
4 DH31 1 2 B++++ PQ22 9U_SDT-1204P-100-120

PR96 1

1
0_0402_5%
SI4800DY_SO-8

2
PC85
PR97

PC86
10_1206_5% +12VALWP

4.7U_1210_25V

5
6
7
8
2200P_0603_50V7K

0.1U_0805_25V7K
1
2
3

4.7U_1210_25V
@15U_D_25V
LX3

1
PC228

PC90
+

PC89
8
7
6
5

PC88
0.1U_0805_25V7K

PC87
0.1U_0805_25V7K
4.7U_1210_25V
+3.3V Ipeak = 6.66A ~ 10A

2
1
2 PQ23 PR98 2
4

1
PC91
47P_0402_50V

SI4810DY_SO-8 0_0402_5%

PC92
1

PC93
2

1
1

PC94

DL3

D H3
4

2
2

3
2
1
PL11
10U_SPC-1204P-100 1 2 DH51

5
6
7
8
1
2
3

PR99
2

1
0_0402_5% PQ24 PC96

22

21
SI4810DY_SO-8 47P_0402_50V
25 4

V+

VL

2
BST3 12OUT
2

5 DL5 4
VDD CSH5
27 18
1

DH3 BST5
1M_0402_5%

PU8 16
DH5
PR100

26 17
LX3 LX5

1
+3VALWP PR101 24 19
1

3
2
1
DL3 DL5

1
0.012_2512_1% 20
PGND PR102 PR103
14
2

CSH3 CSH5 2M_0402_5% 0.012_2512_1%

1 13
CSH3 CSL5
2 12

2
CSL3 FB5
150U_D_6.3V_FP

150U_D_6.3V_FP

3 MAX1632 15

2
FB3 SEQ
3.57K_0603_1%

<18,30,34> ACIN 1 2 10 9 2.5VREF

SKIP# REF
1

23 6
1

SHDN# SYNC
PC98

PR105
PC99

+ + PR104 11
RST#

1
10K_0402_5% 7
PC102 TIME/ON5 PC103 CSL5
+5VALWP
2

100P_0402_50V PR106 28 4.7U_1206_10V

GND
2

2
@300K_0402_5% RUN/ON3
2

150U_D_6.3V_FP
+3VALWP
1

1
150U_D_6.3V_FP
8

PC106
PD16 PC109 PC104 1 2 1 2 PR109 PD17 +
VL
2

+5VP

PC105
3 EP10QY03 @1000P_0402_50V7K 10.2K_0402_1% PC108 EP10QY03 + 3
2
10K_0402_5%
2

680P_0402_50V PR107 PR108 100P_0402_50V

2
1
PR111

PR110 @0_0402_5% 0_0402_5%

2
1

@0_0603_5% PR112
2

PR113 @100K_0402_5%
1

1
0_0402_5%
1

PR114 PC110

1
2

SHDN_1632# <6,34> VL POK PR115 @100P_0402_50V8K

1 2
NC_TEST2 10K_0402_1%

2
PR177 @0_0603_5%
1

VL PC111 20K_0603_1% PD18

2
VL @RB751V
@0.047U_0603_16V
2

PR178 +5V Ipeak = 6.66A ~ 10A

1
1.96K_0603_1%

PR118 PQ42
47K_0603_1% PR116 2N7002 NC_TEST1
1
PR117

47K_0402_1%
0.47U_0603_16V

VL 200K_0603_1% 2
1
PC158

PR119 PU9A SHDN_1632 <32>

2

19.1K_0603_1%
3
8

LM393A
2

3 +
1
SHDN# <32>
2 -
0.047U_0603_16V
1
PC112
4

2
10K_0603_1%
1000P_0603_50V8J

4 PR120 4
1
PC113

1U_0805_25V

100K_0603_1% VL
PH1
2

PC114

CPU thermal protection at 90 degree C Dell-Compal Confidential

PR121
100K_0603_1%
Recovery at 45 degree C Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 36 of 47
A B C D E
 A B C D E

+1.5VALW+-5%
+1.5VALWP
PQ26
+5VALW SI3445DV PL12
4.7U_SPC-1205P-4R7A +3VALW

D
LX18

S
6
4 5

150U_D_6.3V_KO
H_PROCHOT# PR304

0.1U_0603_16V
2

1
VL

PC147
1 2M_0402_5%

1
G
1 2 2 1

RB051L-40
VL VS

PC116
+

PD20
3

2
1

470P_0603_50V
10K_0603_5%

PC148
PD19 PR303

10K_0603_5%

PR122
PC118 RB751V PQ27 PR308 47K_0402_1%

2
1

1
2PR125
1 4.7U_1206_25V 1K_0603_5% 1
47K_0402_1%
2

2
1

1
1M_0603_5%
1 2 2 2SC2411K PC236 PR305

1
PR126 D 0.01U_0603_50V7K 226K_0402_1%

2
PR127
2

2
1
VL G PU21A

2
8
PC121 S

1
2200P_0603_50V7K PQ83 D
+ 3
2

2N7002

0.1U_0603_16V
2 1

PC122
G - 2 1 2

1
0.022U_0402_16V
S

0.01U_0603_50V7K
PQ84 LM393A PR307

4
1

1
PC238

PC239
PU9B 2N7002 PR306 137K_0402_1%

8
LM393A
3

+ 5 PR131 100K_0402_1%

2
PQ28 2 7 200K_0603_1%
2SA1036K - 6 2 1 2.5VREF
1

301K_0603_1%
0.01U_0603_50V7K
4

1
1
PC125

PR133
PD36
2 1 ADP_I <30,35>

2
<6> H_PROCHOT#

2
@RB751V

PU21B
2 2

+ 5
Adaptor Current Detector 7
- 6
ADP_I : 2.01V.... clock throttle(Iin=5.025A) LM393A
ADP_I : 1.81V....No clock throttle(Iin=4.525A)
PR134
200_1206_5%
1 2

PD21
PR135
RLS4148 VS1
200_1206_5% PD22
2 1 1 2 RLS4148
VIN
2 1

PD23 VS
RLS4148
PJP2

1.5K_1206_5%

1.5K_1206_5%

1.5K_1206_5%

1.5K_1206_5%
1

PR33 1
BATT+ 2 1 4MM

PR136

PR137

PR138
1 2
PQ31 +2.5VP +2.5V
TP0610T
PR140

2
PJP3
10K_0603_5%
+5VP 2MM
2 1 2 1 3 1 1 2
+1.5VALWP 1 2
PR139 PZD3 B+ +1.5VALW
200_0805_5% RLZ4.3B
2

3 3
PJP4
1

0.22U_1206_25V

0.1U_0805_25V7K

PR142 1

3MM
100K_0603_5%

150K_0603_5%
1

0.1U_0603_16V
PC126

PC127

PZD4 1 2
+5VALWP +5VALW
PR141

PC128

RLZ5.1B
2

2
2

PJP5
3MM
1 2
+3VALWP +3VALW
1 2
<32> EC_ON#
LM358 PJP6
PR143
22K_0603_5% + 5 2MM
7 1 2
2
+12VALWP +12VALW
- 6
PR123 2

0_0603_5%
PR124
0_0603_5%

PU7B
PU10 RTCVREF
1

PJP8
S-81233SG
1

PR144 PR34 3MM

200_0603_5% 200_0603_5% 1 2 +1.25VS
+1.25VP
CHGRTCP 2 3 1 2 1 2 CHGRTC
IN OUT
4.7U_1206_25V
1

GND
PC129
1U_0805_25V
1

PZD5
1
PC130

RLZ16B
2
2
2

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五, 四月 25, 2003 Sheet 37 of 47
A B C D E
 5 4 3 2 1

D D

PL21
HCB4532K-800T90_9A
1 2 B+

2200P_0603_50V7K

4.7U_1210_25V

4.7U_1210_25V

4.7U_1210_25V

@15U_D_25V
0.1U_0805_25V7K
PR278

PC200

PC229
+ 51_1206_5%

PC196

PC197

PC198

PC199
+5VALWP

2
+2.5V/+1.25V

PR299

PC202
0.1U_0805_25V7K
1
2.2_0603_5%

PC201
2.2U_0805_10V
+2.5V Ipeak =8.49A ~ 14.78A

PD34
PR31

8
7
6
5

DAP202U
SUSP# <16,27,30,33> +2.5VP
PQ79 @1K_0402_5%

2
SI4800DY_SO-8
4

14

28
DDR Termination Voltage

10U_1206_6.3V7K
PC203 PC204

PC205
12 17

VIN

VCC
SOFT1 SOFT2 PC224

1
2
3
PL22 PC206 0.01U_0603_50V7K 0.01U_0805_50V7KPC207 0.1U_0603_16V

2
C +2.5VP 4.7U_SPC-1205P-4R7A 0_0603_5% 0.1U_0805_25V7K C
6 23
8 BOOT1 BOOT2
7
6
5
PR279 0_0603_5% PR280 PQ81
0.1U_0805_25V7K FDS6984S
1

1
220U_D_4V_FP

PR281 5 24 0_0603_5% 4 5
UGATE1 UGATE2
1

PC208

+ @100_0603_5% PU20 +1.25VP

@EC31QS04
220U_D_4V_FP

+ PQ80 0_0603_5% PR282 4 25 PR283 3 6 PL23

PHASE1 PHASE2
PC209

4 1.5U_TPR6D38-1R5M
2

@1000P_0603_50V8J

PD35

2 7 1 2
ISL6225
2

PR284 PR285
PC210

SI4810DY_SO-8 7 22 1 8
1K_0603_5% ISEN1 ISEN2 PR286
1
2
3

2
PC211

220U_D_2V
PC213 2 27 2K_0603_5% @100_0603_5%
LGATE1 LGATE2 +
0.01U_0603_50V7K

PR287

1
PR288 PC214
18.2K_0603_1% @0_0603_5% 3 26 @1000P_0603_50V8J
PGND1 PGND2

9 20
VOUT1 VOUT2
10 19
VSEN1 VSEN2 PC212
8 21
EN1 EN2 SDREF 4.7U_0805_10V4Z
15 16
PG1 PG2/REF

GND

DDR

2
11 18 PC215
PR289 OCSET1 OCSET2 PC216
PR290 IS6225 4.7U_0805_6.3V6K @1000P_0603_50V8J

13

1
10K_0603_1% 0_0603_5%
PC217 PR291
@1000P_0603_50V8J 51K_0603_1%
B +5VALWP B

+2.5VP

PR30
PR292 2 1 SUSP# <16,27,30,33>
<30,33> SYSON 2 1
PR293
10K_0603_0.1% 0_0402_5%
0_0603_5%
PR294
2 1 SYSON <30,33>

470P_0603_50V7K
+3VALWP

1
PC218
PR295 @0_0402_5%
10K_0603_0.1%
1

2
PR296
10K_0603_5%
2

+2.5VPGD

A A

Dell-Compal Confidential
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS B 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401230
Date: 星期五 , 四月 25, 2003 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

AC Adapter Detector

D D

AC Adapter LOW_PWR AC_LOW_PRES# AC_LOW_PRES2# IREF2

90W 0V 0 0 2.96V
VIN

70W Float 0 1 2.31V

VIN

1
PR170 AIRLINE 20V 1 1 1.62V
10K_0603_5% +5VALWP

0.01U_0603_50V7K
2

PC155

1
PR168

2
VIN 10K_0603_5%

2
C C
PU14A

8
LM393A

1
PC156 3 +
1
@1000P_0603_50V8J
2 2 - AC_LOW_PRES# <30>

4
+5VALWP
1

PR173
10K_0603_5% PR171

1
10K_0603_5%
PR169
2

VIN 10K_0603_5%
2

PR302
1 2

2
<34> LOW_PWR PU14B
8

10K_0603_5%
LM393A
1

PC157 5 +
1

7
PR174 @1000P_0603_50V8J AC_LOW_PRES2# <31>
6 -
2

10K_0603_5%
4
2

B B
1

PR172
10K_0603_5%
2

A A

Dell-Compal Confidential
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 39 of 47
5 4 3 2 1
 A B C D E F G H

Different Pin Definition for ISL6215 in PU16 CPU_B+ PL17 B+

FBM-L18-453215-900-LMA 90T_1812
CPU_B+
+5VS
#6 RAMPS #12 ALTV #17 NODV

1
2200P_0603_50V7K
@10U_1210_25V

@10U_1210_25V
+5VS

10U_1210_25V

10U_1210_25V
PC159
@15U_D_25V

@15U_D_25V

47U_EC_25V
0.1U_0805_25V7K
PC230

PC231

PC160

PC161

PC162

PC163

PC164

PC165
+ + +
#8 VMON #13 OFFSET #24 EN

2
5
6
7
8

5
6
7
8
PR300
#11 OCSET #15 VRTN #27 ALTEN PQ65
2.2_0603_5% IR7811A

2
4 4

0.1U_0805_25V7K
#26 SOFT PR232 PR233
10K_0603_5% 1 2
1 PQ66 1

2
PU15

@0_0603_5%
PC166
4.7U_1206_25V
0_0603_5% IR7811A

1
2

PR236

PC167
6 2
VCC BOOT

3
2
1

3
2
1
0_0603_5% PU16 PL18
3 1 1 2
PR238 PWM UGTE 0.6U_HK-AE26A0R6
2 1 1
VID0 VCC
28 +CPU_CORE
<6,8> CPU_VID0 ISL6207_EN 7 8 PR237 +CPU_CORE

1
PR239 EN PHSE
<6,8> CPU_VID1 20_0603_5%1 2 22 0_0603_5%
VID1 PWM1

1
4 5
GND LGTE

1
1PR244
PR240 2 0_0603_5%
1 3 23 PD28 PR241
<6,8> CPU_VID2 VID2 ISEN1

0.01U_0603_50V7K
@5.1_0805_5% PD29

5
6
7
8

2
1U_0805_25V
PR242 2 0_0603_5%
1 4 18 ISL6207 @EC31QS04
<6,8> CPU_VID3 VID3 PWM3

5
6
7
8
PC168
PH6 EC31QS04

2
2

1
PR243 2 0_0603_5%
1 5 19 0_0603_5%

499K_0603_1%

2
<6,8> CPU_VID4 VID4 ISEN3

PC169
4

2
<19,30> VGATE 25 21 4 PC170

2
PR246 0_0603_5% PGOOD PWM2 @1000P_0603_50V8J
24 20 PQ67 PQ68
NC ISEN2 SI4362DY_SO-8 SI4362DY_SO-8
<19> PM_DPRSLPVR 27 10
NC COMP

2
15N_0603_50V7K

3
2
1
PC171

150P_0603_50V8J PC172
17 9 PR245

3
2
1
NC FB

1
<15,19> PM_STPCPU# 6 ISL6219 8
1.96K_0603_1%
NC NC

1
2

1
PR247
11
NC VSEN
16 DE-POP all items in dash- area if
2

1 PR249 2
ISL6215is used for mobile CPU

10K_0603_1%
@10K_0603_5% 12 15

2
PR248 NC NC
13 26 +5VS
1

@3.09K_0603_1% NC NC CPU_B+

2200P_0603_50V7K
0.1U_0805_25V7K
7 14 PQ69
1

FSET/EN GND

5
6
7
8

5
6
7
8

1
1 PC179

@15U_D_25V

@15U_D_25V

10U_1210_25V

10U_1210_25V

10U_1210_25V

10U_1210_25V
2 @0.1U_0603_16V 2
2

PC232

PC233

PC173

PC174

PC175

PC176

PC220

PC221
@5.6N_0603_50V7K
IR7811A + +
2

2
4.7K_0603_3% 681_0603_1%
PC178

2
1 PR298 2
CPU_B+ PR250 PR251 4 4
1
2

2
PR253

0.1U_0805_25V7K
PR254
@10.2K_0603_1% @5.1_0603_5%
1 2

PR297
PQ70
1

1 PR257 2 2

1
2

2
PU17
90.9K_0603_1%

PR255 0_0603_5% IR7811A

0_0603_1%
PR252

PC180
6 2
1

1
2

@80.6K_0603_1% VCC BOOT

3
2
1

3
2
1
1

2
1.15K_0603_1%
PR258 3 1 1 2 PL19
PWM UGTE 0.6U_HK-AE26A0R6 +CPU_CORE
1

+CPU_CORE

@909_0603_1%
@3.24K_0603_1% 1 PH5 ISL6207_EN 7
EN PHSE
8 PR259
PQ71 0_0603_5% PQ72 PQ73
1

100K
2

5
6
7
8

5
6
7
8
499K_0603_1% PR262
2 DTC115EUA 4 5 SI4362DY_SO-8 SI4362DY_SO-8
PR260 GND LGTE

2
1U_0805_25V

1U_0805_25V

@0.01U_0603_50V7K
PR261
2

1
1.74K_0603_1%

@10K_0603_1% 100K ISL6207 4 4 PH7 @5.1_0805_5%

2

1
+5VALWP

PC183
PD31
1

PC181

PR256

PC182
0_0603_5%

1
@EC31QS04
1

1
1

2
2

PC184

2
PR265 PR266 @1000P_0603_50V8J

3
2
1

3
2
1

2
100K_0603_5%
10K_0603_5% PR263
1

1 1

1.43K_0603_1%
ISL6207_EN

1
+3VALWP PR269
1

100K_0603_5% 2
3 PQ74 3
1

2N7002 CPU_B+
3

+5VS

10U_1210_25V

2200P_0603_50V7K
0.1U_0805_25V7K
PC185 2 PQ75

5
6
7
8

5
6
7
8

1
PQ82

PC186

PC187

PC188

PC189
@15U_D_25V

@15U_D_25V

10U_1210_25V

10U_1210_25V

10U_1210_25V
2

PC234

PC235

PC222

PC223
0.1U_0603_16V 2N7002 + +
3

IR7811A

2
2
@280K_0603_1%
PR267

4 4
@300K_0603_5%
PR268

0.1U_0805_25V7K
PR272 PU18 +1.2VP PR270 PR271
1 2 PQ76
0_0603_5% 1.2VDD @5.1_0603_5% IR7811A
1 5
1

VIN VOUT
1

2
PU19 0_0603_5%
1

PC191
PC190 4 6 2
4.7U_1206_16V PG VCC BOOT PL20
2

3
2
1

3
2
1
1

4.7U_1206_16V
PC192

3 2 3 1 1 2
EN GND PWM UGTE 0.6U_HK-AE26A0R6 +CPU_CORE
ISL6207_EN 7 8 PR273 +CPU_CORE
2

PR274 CM2843 EN PHSE 0_0603_5%

1
PR277

0_0603_5% 4 5
GND LGTE

5
6
7
8

5
6
7
8

2
+5VALWP PD32 PR275
2

PH8 @5.1_0805_5%
<30,33> VR_ON
499K_0603_1%
1U_0805_25V

@0.01U_0603_50V7K

PR301 ISL6207 @EC31QS04

2

100K_0603_5% 4 4 0_0603_5%

2
2

1
PC194

1
PC193

PQ77 PQ78
1

SI4362DY_SO-8 SI4362DY_SO-8 PC195

1

2
@1000P_0603_50V8J
1

2
PR276

3
2
1

3
2
1
1.5K_0603_1%
DE-POP PR249 PR256 PR268 P C171

1
4 4

ISL6219 PR247, PR255, PR260

1.PH6,PH7,PH8 pop thermal resistor
for desk-top PR248, PR250,PR258, 7.5K 1.74K unpop 5.6nF 2. Non-pop PR298 and PH5
PC178,PC172,PR236 PTC solution 3.PR297 0 ohm Dell-Compal Confidential
Compal Electronics, Inc.
1.PH6,PH7,PH8 pop 0 ohm resistor Title
ISL6215 PR266, PQ74, PQ71 NTC solution 2. Pop PR298 681_0603_1%,PR297 1.15K_0603_1%
6.04K 1.5K 130K 4.7nF 3. Pop PH5 4.7K thermal resistor THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1452
for mobile PR253, PC179, PR257 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230 1B
Date: 星期五 , 四月 25, 2003 Sheet 40 of 47
A B C D E F G H
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

1 Fireware issue The ICH4 GNTA# strap pull up for EC BIOS 0.1A 18 Depop R153, GNTA# have internal pull up 0.1 SST

D 2 Leakage current issue Reduce Broadcom 4401L leakage current 0.1A 22 Depop L39 and pop L7, conncetor power source from +3VALW 0.1 SST D
to +3V, R31, R32, R33 pull up to +3VAUXLAN, Q3,Q4,Q5 pin3
connect to +3VAUXLAN
3 Fix schematics part value L21, L22, L23, L26 part value different with BOM 0.1B 15 Change L21, L22, L23, L26 part value from CHB2012U121 to 0.1 SST
BLM21A601SPT on schematics
4 BOM issue R445 include wrong part number 0.1B 33 Change R445 part number from SD028470200 to SD028680200. 0.1 SST
PN indicate value from 47K_0402_5% to 68K_0402_5%
5 HDD leakage current issue When AC in +5VSHDD will go up to 5V 0.1C 21 Q6 change to SI2302DS as schematics, SIDEPWR active low 0.1 SST
when HDD power on
6 Capture library package issue 2N7002 Drain is pin1, Source is pin3 0.1C 28 Fixed Q30, Q31, Q32 Capture libaray , pin1 fixed to pin3, 0.1 SST
pin3 fixed to pin1
7 BOM issue Fixed R196~R199 from 56.2K ohm to 56.2 ohm 0.1C 23 Change R196~R199 PN from SD014562207 to SD014562A00 on 0.1 SST
schematics
8 Fix LOM EEPROM issue U8 (AT93C46) is used X16 organization 0.1C 22 NC or pop R452 to pull up U8 pin6 for X16 organization 0.1 SST
select
9 Fix CLKRUN# leakage issue ICH4 not implement CLKRUN#, GPIO24 is resume power well. 0.1D 19 Add a diode D46 to isolate GPIO24 from ICH4 to PCI devices, 0.2 PT
and depop D46.
10 LOM EEPROM issue U8 (AT93C46) is used X16 organization. U8 pin6 pull up or 0.1D 22 U8 pin6 pull up +3VAUXLAN via R452 , and depop R452. 0.2 PT
NC for X16 organization select, pull down for X8
organization selcet.
C 11 SW BD LED keep turn on SW BD LED control transistor Emitter conncet to +5VALW be 0.1D 32 Change JP5 pin9 from +5VS to +3VS 0.2 PT C
keep LED always turn on
12 Fix VCCA_SM voltage drop issue Add current rating for VCCA_SM, VCCA_DPLL, VCCA_FSB 0.1E 10 Change L3, L4, L27, L28 from MLF2012DR68XT to FBM-L11-201209- 0.2 PT
(1.5VS) 121LMA05
13 Change address and control signals Change ddr address and control signal layout 0.1E 12,13 DDR address and control signals layout topology same the 0.2 PT
layout topology topology ddr data layout topology
14 Fix EE issue item 89 Signal COMP/B and Y/G connect error 0.1E 17 Swap COMP/B and Y/G to correct connection 0.2 PT

15 Fix EE issue item 91 BEEP# from EC should be high active 0.1E 28 Change net name BEEP# to BEEP 0.2 PT

16 Fix EE issue item 92 Fix FSB 400MHz when 845GL pop 0.1E 15 Add R455 (8.2K_5%) pull down for H_BSEL0 0.2 PT

17 Fix EE issue item 95 When AC insertion SUSP# may be floating before the KBC 0.1E 33 Add R456 (100K_5%) pull down SUSP# 0.2 PT
can programit.
18 Fix EE issue item 47 Provide enough current rating 0.1F 15 L22 and L26 change frome BLM21A601SPT (300mA) to 0.2 PT
FBM-L11-201209-121LMA05 (500mA) and depop L22
19 Card Bus power bead current rating not Provide enough current rating 0.1F 24 L5 and L6 change frome FBM-11-160808-800LMT_0603 (300mA) 0.2 PT
enough to FBM-L11-201209-121LMA05 (500mA)
20 Fix EE issue item 102 Fix Intel CPU FSB frequency issue 0.1F 10,15 H_SEL0 connect to R270 pin1 from CLK generator, HBSEL0 0.2 PT
B
connector to R270 pin2 from CPU. Depop R270 on GL board. B
21 Battery charge issue ACIN pull up +3VALW can't change power supplier to battery 0.1F 18 Depop R161 0.2 PT
when AC exit
22 NO Change PCMCIA connector 0.1F 24 Change PCMCIA conncetor from AMP_0-1376275-1 to 0.2 PT
JAE_JC21-BRB
23 Fix INTRUDER issue ESD protect for Q22 0.1F 32 Add C638, C639 for Q22 protection 0.2 PT

24 Remove PS2 connector No necessary 0.1G 29 Remove RP7, JP26 0.2 PT

25 Add debug port GL board have not pop minipci connector, we need a port 80 0.1G 33 Add R458, C637 and JP27 0.2 PT
debug tool
27 For cost save For cost save 0.1G 32 Depop C10, C229 (150U Poly Cap), add C641, C642 (100U 0.2 PT
Petit Cap)
28 It no need Use R19 pop and depop to control H_SEL0 high or low 0.1G 15 Remove R455 0.2 PT

29 Fix EE issue item 134 Change ddr address and control signal layout 0.1H 12,13 Change DDR address and control signal to go back SST 0.2 PT
topology topology
30 Fix EE issue item 149 Pop Petit Cap after EA test 0.1H 32 Depop C641, C642 and pop C10, C229 0.2 PT

A
31 Fix EMI issue EMI team's recommendation 0.1I 10 Pop R52, C79 for CLK_CLK_PCI_LAN; R428, C614 for 0.2 PT A
CLK_PCI_MINI; R406, C597 for CLK_PCI_LPC; R321, C395 for
CLK_ICH_66M

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 41 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

32 No Connect MiniPci conncetor metal door to short to GND 0.1I 26 Add JP24 pin 127, 128 on schematics short to GND, JP24
footprint pin 127, 128 (metal lock door) be short to GND 0.2 PT
D 33 No Some text mode use wire, change to line 0.1I 10,30,40 Some text mode use wire, change to line D
0.2 PT
34 Fix power on issue Use PCIRST# to set the SHDN_1632# work after PCIRST# high 0.1I 6 Add Q62 gate connect to PCIRST#, source connect to
when power on SHDN_1632# 0.2 PT
35 No Change to use approve part 0.1I 31 RP118 (8.2K +-5% 4P2R) change to R453, R454 (8.2K_0402_5%)
0.2 PT
36 No Hard Disk source power change to +5VS 0.1I 21 Q6 change back to SI2301DS (PMOS) pin3 connect to +5VS
0.2 PT
37 Fix EE issue item 134 Change DDR address and control signal topology back to 0.1I 12,13 Change DDR address and control signal topology back to
REV0.1 REV0.1 0.2 PT
38 Fix EE issue item 171 For CRT Hsync and Vsync to allow tuning 0.1I 17 Add series resistors R459, R460 for Hsync and Vsync
0.2 PT
39 No Schematic version change for PT build 0.2 ALL Change revision from 0.1I to 0.2
0.2 PT
40 Fix issue item 20 Slow rising and falling time 0.2A 10 Pop R234, C249 for CLK_MCH_DISPLAY; R286, C333 for
CLK_MCH_66M 0.2 PT
41 Fix CRT rising and falling time issue 0.2A Pop L1, L2, L15 Change form FCM-2012C-800 to
Fast rising and falling time 17 FBM-10-201209-260T for PE board 0.2 PT
42 No 0.2A Pop R393 100K_0603_1% for Board ID
Change Board ID output level 30 0.2 PT
C C
43 No 0.2A Add off-page on pg24 PCMCIA connector
Add off-page reference 24 0.2 PT
44 No 0.2B ALL Modify Text
Net in for Rev 0.2A Gerber 0.2A PT-2
45 Fix DFX issue 0.2C 21 Add C643 22U_1206 replace C387's layout location and C387
C387 effect DIMM door lock leave DIMM area. 0.2A PT-2
46 No 0.2C 24
Add JP18 PCMCIA connector GND pads JP18 pin75,76,77,78,79,80,81,82 connect to GND 0.2A PT-2
47 No PM_GMUXSEL for mobil platform to support SpeedStep, 0.2C 19
desktop platform just GPIO fuction Remove PM_GMUXSEL signal net 0.2A PT-2
48 Fix PIR2 issue PIR not match schemaitcs 0.2F 22 Pop L39 and depop L7
0.2A PT-2
49 Fix PIR19 issue PIR not match schemaitcs 0.2F 24 L5, L6 change to FBM-L11-201209-221LMAT (3A). And Depop L5
0.2A PT-2
50 Fix PIR23 issue PIR not match schemaitcs 0.2F 32 Depop C638
0.2A PT-2
51 Fix PIR24 issue PIR not match schemaitcs 0.2F 30 RP7 pop for pull up PS2 signal
0.2A PT-2
52 Fix PIR25 issue PIR not match schemaitcs 0.2F 33 JP27 pop on GL board for debug and depop on PE board
B 0.2A PT-2 B

53 Fix EE issue item 62 Schematics component's PN not match BOM 0.2G 29 JP13 (TP CONN) PN change to "SP020010910" in schematics to 0.2A PT-2
match BOM
54 Fix EE issue item 63 Schematics component's PN not match BOM 0.2G 29 JP25 (MDC CONN) PN change to "SP02F00410L" in schematics 0.2A PT-2
to match BOM
55 Fix EE issue item 64 Schematics component's PN not match BOM 0.2G 32 JP4 (USB CONN) PN change to "DC23310241L" in schematics 0.2A PT-2
to match BOM
56 3VDDCDA, 3VDDCCK rising time issue 3VDDCDA, 3VDDCCK rising slow on SMBus EA measurement 0.2G 17 R5, R201 change from 10K_0402_5% to 2K_0402_5% 0.3 ST

57 EE issue list item 91 CLK_PCI_ICH timing out of spec 0.2H 18 Pop R349 (22_0402_5%), C480 (10P_0402_50V8K) for 0.3 ST
CLK_PCI_ICH AC termination
58 EE issue list item 103 Depop sub thermal sensors for cost save 0.2H 8 Depop U25, U23, C394, C482, R308, R351 and R306 0.3 ST

59 Fix Boardcom 4401L wake up from S3 Fix Boardcom 4401L wake up from S3 issue 0.2H 22 Add R461, R462 and depop R462. Option VESD and VDDBUS 0.3 ST
issue power source from +3VS to +3VAUXLAN. C97, C96, C77, C74,
C88, C87, C80 bypass +3VWOL

60 EE issue list item 103 H_BSEL0 of 845PE should get 1.5V at input and CLK chip 0.2H 15 Add R463 (0_0402_5%) Pop on PE board. R19 move to CPU 0.3 ST
should be seeing 3.3V with 533MHz CPU side and power source +3VS.

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 42 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

61 ESD protection on 2nd FAN ESD protection on 2nd FAN 0.2I 7 Reserve Q63 (SM05) for 2nd FAN ESD protection 0.3 ST
D D
62 Fix EE issue item 105 H_BSEL0 circuit not correct 0.2I 10, 15 Serie resistor R270 for CPU and MCH 0.3 ST

63 No Change Board ID for ST build 0.2I 30 R394 change from 10K_0603_1% to 24.9K_0603_1% 0.3 ST

64 No Change for ITP test on PCBA 0.2I 6, 8 Depop R313, R305 and pop R310, R372, R183, R184, R304 0.3 ST

65 Fix EE issue item 126 Using larger cap for high-pot margin 0.2J 22 C211, C212 change package from 1206 size to 1808. 0.3 ST

66 RJ11 ISN failed EMI team recommend to resolve RJ11 ISN test failed 0.2J 29 Cut a seperated GND for MDC and connect to system GND via 0.3 ST
a schottky diode. Reserve a jump for connect system and
MDC GND.

67 Fix EE issue item 140 Connect 9C/12C#/8C# to EC GPIO for future 9Cell support if 0.2K 31, 34 Connect 9C/12C#/8C# from PR162 to U30 pin17 and remove 0.3 ST
required R388

68 TI TPS793475DBVR damage issue When power on, there are 1.5A sink current when 0.2K 29 For power solution, C558 change package size from 0402 to 0.3 ST
TPS793475DBVR started 0603 for value tolerance
Add hardware circuit to sense Adapter current and
69 Fix EE issue item 136 automatically generate PROCHOT to the CPU to generate 0.2K 6 R311 change to 4.7K_0402_5%, H_PROCHOT# connect to PD36 0.3 ST
C
automatic throttling C

70 Fix ThermTrip function When thermal protective resistor PH1 work, SHDN_1632# 0.2K 6 R320 connect to Q59 base, R316 connect to Q59 collector
can't tie to low and VL power source. Add Q64 between Q59 and Q62. Q62 0.3 ST
change pin1 Drain to connect SHDN_1632#

71 RJ11 ISN failed Change solution for ISN failed 0.3 29 Remove PJP9-13 and D47 0.3 ST

72 Fix EE issue item 136 Follow Intel desing guide recommend pull up resistor value 0.3 6 R311 change back to 62_0402_5% 0.3 ST

73 Fix EE issue item 141 Prevent noise issue 0.3 28 Depop R328 for noise prevention 0.3 ST

74 No For cost save 0.3 7 Depop C148, C150 (470U_D4_2.5VM) and C152 (330U_D2E_2.5VM) 0.3 ST

75 Fix PROTO3 EE issue item 44 Minipci connector pop for PE board only 0.3B 26 Add 2@ symbol for JP24 for PE board pop only 0.3 ST

76 No Vendor schematics review recommendation 0.3B 22 R35 change from 10K_0402_5% to 1K_0402_5% 0.3 ST

Remove R405, R399, C600, C596, C613, C612, C599, C598, 0.3 ST
77 Fix PROTO3 EE issue item 45 Remove minipci suport component for GL board cost save 0.3B 26 C609, L35, C616, C610, L36, R401, R403 on GL board
B B

78 No Modify material value 0.3C 23,26, Change value L11,L30,L31,L35,L36 from BDM21A05 _0805 0.3 ST
27,28 to BLM21A05 _0805

79 No Modify material part number 0.3C 27 U24 STAC9750 change from (SA097500000) to 0.3 ST
(SA097500010) for both BOM

80 No 0.3C 7 Delete R11,D11,D20,U1,R10,R6,Q1,C234,Q8,JP19 0.3 ST

Depop Fan2 Control circuit

79 No EMI require 1.0 17 Pop D1, D3, D18 for EMI requirement 1.0 QT

80 No Modify Fiduial Mark & Screw Hole value for non pop 1.0 29 Fiduial Mark & Screw Hole value add @ symbol 1.0 QT

81 No BD_ID change for QT build 1A 30 R394 change from 24.9K_0603_1% to 43K_0603_1% 1.0 QT

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

82 INTRUDER# issue Sometimes when normal shutdown, INTRUDER# record a event 1A 32 Q22 change from 2N7002 to BJT DTC115EKA 1.0 QT
D D
83 No Because Q22 change to DTC115EKA, C639 is no necessory 1B 32 Depop C639 (1000P_0402_50V7K) 1.0 QT
The serie resistor R441 change from 22_0402_5% to
84 Fix Qual issue item 35 Improve IAC_SDATA_IN1 singnal quaility 1B 29 10_0402_5% 1.0 Pilot

85 Fix audio not switching to headphones or For audio switching to headphones or ext 1C 28 Depop C580 and change C588 from 4.7uf to 0.47uf 1.0 RTS
ext speakers immediately speakers immediately

C C

B B

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
D ate: ¬P 期五, 四月 25, 2003 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 3

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

D 1 CPU_CORE can't power up Pin7 of PU16 can't be used as on/off control pin 0.1B 40 1. Change VCC power source of PU16 from +5VALWP to +5VS 0.1 SST D

Current limtited is about 37A while PH6,PH7,PH8 is 1.5K

2 current limited is not up to 60A that is not enough for design target.Because we don't use 0.1B 40 1. Change PH6,PH7,PH8 from 1.5K_0603_5% to 3K_0603_1% 0.1 SST
PTC resistor on PCB now, the value must be tuned later.

3 Turn on voltage of PQ19 is not eonugh Vgs of PQ19 is 2V while PR72 is 47K. That is not enough. 1. Change PR72 from 47K_0402_5% to 22K_0402_5% 0.1 SST
While PR72 is 22K, the Vgs can be improved to 2.5V. 0.1B 35

4 current rating is not enough. FBM-L11-322513-151LMAT is 5A that is not enough.So FBM 1. Change PL8 from FBM-L11-322513-151LMAT to 0.2 PT
-L18-453215-900LMA90T1812 is 9A that is better. 0.1B 35 FBM -L18-453215-900LMA90T1812.

5 Fix noise issue On SST PCB, we can sound some noise due to PC77, the
cernamic capacitor has sounded noise with thinner type. 0.1C 36 1. Change PC77 from 2.2U_1206_25V to 4.7U_1210_25V 0.2 PT

6 The transient response is too slow. We must to 1. Change PR249 from 3.48K_0603_1% to 5.76K_0603_1%.
Fix CPU_CORE Transient Response fail tune feedback resistor and capacitor to fix it. 0.1E 40 2. Change PR257 from 49.9_0603_1% to 1.1K_0603_1% 0.2 PT
3. Populate PC172 68PF_0603_50V.

C C
7 SDREF output voltage is over spec. Add bypass capacitor pallel pin18 of ISL6225 0.1E 38 Populate PC218 470P_0603_50V7K 0.2 PT

8 PG of CM28423 has a glitch

while VCC is ready and VR_ON is float Add pulldown resistor tie to GND while 0.2 PT
VR_ON is float that can be made sure the logic is low. 0.1E 40 Add PR301 100K_0603_1%

Change VCC power source of PU15, Negative voltage was observed on +5VALWP
9 PU17, PU19 from +5VALWP to +5VS when system powered off 0.1E 40 1. Change VCC power source of PU15, PU17, PU19 0.2 PT
from +5VALWP to +5VS
Prevent abnoral function OVP 1. Add PQ82 2N7002
10 caused by ISL6219 while system ISL6219 caused OVP when on/off pin 0.1E 40 2. Change PR232 from 5.1_0603_5% to 10K_0603_5%
powerwd off ; bouble pulses was observed changed from high to low level 3. Change PC168 from 1U_0805_25V to 0.01U_0603_50V. 0.2 PT
at output PW1, PW2, PWM3 of ISL6219 4. Depop PR251, PR270, PC183, PC194
5. Tie the EN pin of PU15, PU17, PU19 to Pin1 of PQ82

11
Fine-tune current sharing uneven current sharing found 0.1E 40 1. Change PH6, PH7, PH8 form 3K_0603_1% to 0_0603_5%
of CPU VR phase1,2,3 to have 2. Change PR245 from 0_0603_5% to 1.96K_0603_1% 0.2 PT
thermal balance 3. Change PR263 from 0_0603_5% to 1.43K_0603_1%.
4. Change PR276 from 0_0603_5% to 1.5K_0603_1%

B 12 Fine-tune CPU load-line with NTC Fine-tune CPU load-line with NTC 0.1E 40 1. Keep PR268 nonpop B
2. Change PR256 from 2K_0603_1% to 1.74K_0603_1%
3. Change PR297 from 0_0603_5% to 1.15K_0603_1%.
4. Change PH5from depop to 4.7K_0603_1%
5. Change PR298 from depop to 681_0603_1%
6. Change PR257 from 49.9_0603_1% to 909_0603_1% 0.2 PT
7. Change PC179 from 3900P_0603_50V to 5.6N_0603_50V
8. Change PR249 from 3.48K_0603_5% to 7.5K_0603_1%
7. Change PC171 from 6800P_0603_50V to 5.6N_0603_50V
8. Change PC172 from depop to 47P_0603_50V

13 Audio noise found 35, 36,

Still find root cause 0.1E 38, 40 1. reserve 15U_D_25V capacitors on PC226-PC235, 0.2 PT

1. change the size of PC212 from D size to 0805 and

14 PC212 location space change requested by ME to put a connector around 0.1E 38 pop 4.7U_0805_10V 0.2 PT

1.delete PD5 from schematics

15 Remove PD5 no possibilty to have a reverse voltage at Vin 0.2C 34 0.2A PT-2
when adapter plug-in
because of the DC-jack orientation structure
A A

16 Prevent PU14 from burn out When pin1 (GND pin) of DC-jack PCN1 disconnected 0.2A PT-2
from B/M (damaged by force from outside), 0.2C 39 Add PR302 10K_0603_5%
there is a large current going through PU14
resulted in PU14 damaged Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number Rev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 45 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 3

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

D 17 100MHz EMI broad-band over spec. Improve 100MHz EMI broad-band 0.2E 34 Add a FBM-L18-453215-900-LMA90T_1812 bead on PL7 0.2A PT-2 D

1. Change PL6,PL7 from FBM-L18-453215-900-LMA90T_1812 to

MCK4532800YAT_1812
18 100MHz EMI broad-band over spec. Improve 100MHz EMI broad-band 0.2H 34 2. Add PL4 MBH2012102YZT_0805 0.3 ST
3. Change PC45 from 100P to 560P, PC46 from 1000P to
12P,PC47 from 100P to 12P and PC48 from 1000P to 560P

1. Change PR51 from 1M to 2.2M,PR55 from 215K to 191K.

Precharge function has some bug,
19 while AC Adapter plug in firt time
Precharge can reduce surge current from AC
adapter,while Adapter plugged in
2. Change PR54 from 10K to 34K,add PR32 66.5K.
3. Change PC51 from 0.1U_16V to 1000P_50V.
0.2H 34
4. Change PC50 from 1000P_50V to 0.1U_16V.
5. Change net +5VP and RTCVREF to VL. 0.3 ST
6. Change PR113 from 47K_0402_5% to 0_0402_5%.
7. De-pop PC111 and change PC158 from 0.1U_16V to
0.47U_16V.

Power rating of 0.02_2010 is not rating power of 0.02_2010 is 0.5W that is very poor
20 enough. for 90W adpater 0.2H 35 1. Change PR65 from 0.02_2010_1% to 0.02_2512_1%. 0.3 ST
C C

Change size of thermal resistor and cost down

21 Power open issue 0.2H 36 Change PH1 from 10K_0805_1% to 10K_0603_1%. 0.3 ST

The giltch occurs while secondary PWM is enabled 1. Add PR31 1K_0402_5%..
22 Power good giltch issue in ISL6225 that effects system boots up 0.2H 38 2. De-pop PR294 0.3 ST

DELL don't aprove item22 solution, prefer using 1. De-pop PR31 1K_0402_5%.
23 Fix open issue #137 new version ISL6225 0.2J 38 2. De-pop PR294 0_0402_5%. 0.3 ST
3. Add PR30 0_0402_5%.

1. Change PR232 from 10K_0603_5% to 5.1_0603_5%.

24 Fix open issue #124 Fix open issue #124 and using ISL6219A 0.2J 40 2. Populate PR251 and PR270 5.1_0603_5% 0.3 ST
3. Populate PC183 and PC194 0.01U_0603_50V.
4. De-pop PQ82,PD31,PD,32

1. Change PR81 from 66.5K_0603_1% to 47K_0603_1%

25 Fix ISN fail issue Fix ISN fail with 200KHz 0.2J 35 2. Change PC55 and PC56 from 4.7U_1210_25V to 10U_1210_25V 0.3 ST
B B
3. Change PL9 from 15UH to 22UH

Rds(on) of SI4835DY is too high,change

26 Fix open issue #123 PQ14,15,16 to SI4825DY for power stress 0.2J 35 Change PQ14,PQ15,and PQ16 from SI4835DY to SI4825DY 0.3 ST

1. add PR303, PR306 47K_0402_1%.

27 Adapter shut down Adapter current over 5.5A 4 sec 0.3 37 2. add PR304 1M_0402_1%.
while running P4MaxPower 100% while running P4MaxPower 100% 3. add PR305 226K_0402_1%
4. add PR307 147K_0402_1% 0.3 ST
5. add PR308 100K_0402_1%
6. add PC236 0.01U_0603_50V
7. add PC239 0.1U_0603_16V
8. add PC238 1000P_0402_50V
9. add PQ83, PQ84 2N7002
10. add PU21 LM393A

Modify thermal protect temp. from Based on thermal team requirement 0.3A 36 1. ChangePR119 from 21K_0603_1% to 17.8K_0603_1% 0.3 ST
28 95C to 87C 2. Change PR117 from 1.74K_0603_1% to 2.05K_0603_1%
A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number Rev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 46 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 3

Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

D 1. De-pop PR257 and PC179. D

2. Change PC171 from 5.6N_0603_50V to 15N_0603_50V
modify compension for reduce output 3. Change PC172 form 47P_0603_50V to 150P_0603_50V 0.3 ST
29 capacitor modify compension for reduce output capacitor 0.3A 40
4. Change PR249 from 7.5K_0603_1% to 10K_0603_1%

Fix item25 about ISN test without

30 changing inductor Fix item25 about ISN test without 0.3A 35 1. Change PL9 from 22UH_SPC-1205P-220A to 0.3 ST
changing inductor 15UH_SPC-1204P-150

31 Capacitor DFX issues Component layout pad overlap (reservated for noise issue) 35 36 remove PC226, PC227, PC228, PC229, PC230, PC231, 1.0 QT
causes some components shifting when pass the re-flow 0.3D PC232, PC233, PC234, PC235
38 40

32 Noise issue in B+ power Add reservated caps. back for noise issue 0.3E 35 36 reserve PC226, PC227, PC228, PC229, PC230, PC231,
PC232, PC233, PC234, PC235 1.0 QT
38 40

C C
1. Change PR117 from 2.05K_0603_1% to 1.96K_0603_1% 1.0 QT
33 Change OTP from 87C to 90C Change OTP from 87C to 90C 1.0B 36 2. Change PR119 from 17.8K_0603_1% to 19.1K_0603_1%

1. Change PC238 from 1000P_0603_50V% to 0.022U_0402_16V

34 Fine tune adaptor detector Fine tune adaptor detector 1.0B 37 2. Change PC239 from 0.1U_0603_16V to 0.01U_0603_50V 1.0 QT
3. Change PR304 from 1M_0402_1% to 2M_0402_5%
4. Change PR307 from 147K_0402_1% to 137K_0402_1%

35 Use new version ISL6225 Use new version ISL6225 1.0B 38 1. Change PU20 from ISL6225CA to ISL6225BCA 1.0 QT

1. Add PR244,PR262,PR277 499K_0603_1%

2. No populate PR251,PR270,PC183 and PC194.
36 Fix surge voltage in +CPU_CORE while Fix surge voltage in +CPU_CORE while 1.0B 40 3. Change PR232 from 5.1_0603_5% to 10K_0603_5%. 1.0 QT
power up power up 4. Add PQ82 2N7002
B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1452
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number Rev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 1B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401230
Date: 星期五, 四月 25, 2003 Sheet 47 of 47
5 4 3 2 1