Fabrication of IC 7

Nano III
Micro- and nano-fabrication
Michel Calame
Dpt. of Physics, Klingelbergstrasse 82, 4056 Basel
room: 1.20, 1st floor
email: michel.calame@unibas.ch
web: http://calame.unibas.ch/
Outline
• Introduction:
overview, state of the art
semiconductor physics basics (Ö CMOS)
• Fabrication basics
– IC fabrication overview
– clean-rooms
– Silicon: from sand to wafer
– material deposition techniques
– etching
– lithography
– examples of devices: MEMS, NEMS
• Outlook: new and future techniques
Nanofabrication, Nano III / mc / 2

References
• overview books
1. Fundamentals of Microfabrication: The Science of Miniaturization

M. Madou, 2nd ed., CRC Press, 2002
2. Nanoelectronics and Information Technology R. Waser ed., Wiley-
VCH, 2003 (newer edition…)
3. VLSI Technology (more physical) SM. Sze, 2nd ed., McGraw-Hill, 1988
4. Introduction to Semiconductor Manufacturing Technology
H. Xiao, Prentice-Hall, 2001.
Introduction
1947, 24th December ATT Bell Labs

John Bardeen
Walter Brattain
William Schockley
first point contact transfer resistor
Bell labs Bell labs nobel.se

Introduction
1958
Jack Kilby, Texas Instruments
first IC (Integrated Circuit)
Nanofabrication, Nano III / mc / 5 C. Esser, Infineon
Introduction
1961, Robert Noyce,

Fairchild Camera
first integrated circuit

available as a
monolithic chip
Planar technology
(Si substrate and Al
lines)
Nanofabrication, Nano III / mc / 6 C. Esser, Infineon

Introduction
1971 Intel anounces the i4004 microprocessor

"a new era of integrated electronics"
2250 transistors, 10μm technology, 108kHz
Nanofabrication, Nano III / mc / 7 http://www.intel.com
Introduction
1981
Intel i8088
29000 transistors, 3μm
technology, 8MHz
invention of the PC
(personal computer)
IBM, A.Child, B.Gates
Nanofabrication, Nano III / mc / 8 http://www.intel.com

Introduction
1965, Gordon E. Moore

(co-founder Intel Corporation)
Electronics, Vol. 38(8), 1965

“The complexity for minimum component costs has increased at a rate of
roughly a factor of two per year. Certainly over the short this rate can be
expected to continue, if not increase. Over the longer term, the rate of
increase is a bit more uncertain, although there is no reason to believe it
will not remain nearly constant for at least 10 years.”
Nanofabrication, Nano III / mc / 9 http://www.pbs.org/transistor/
Introduction
Scaling trends
Nanofabrication, Nano III / mc / 10 M. Bohr, Intel

Introduction
Scaling trends
performance , power , cost
Nanofabrication, Nano III / mc / 11 M. Bohr, Intel
Introduction
state of the art today 45nm

(near) future: 32nm, …
Nanofabrication, Nano III / mc / 12 www.intel.com/technology/

Introduction
“I think there is a world market for

maybe five computers.”
Thomas Watson,
Chairman of IBM, 1943
“There is no reason for any
individual to have a computer in
their home.”
Ken Olson,
President, Chairman and Founder
of Digital Equipment Corp., 1977
“640K ought to be enough for
anybody.”
Bill Gates, Microsoft founder, 1981
(though today he denies he said it)
Introduction
1958 1 transistor = 10 US$;

first integrated circuit with 4 transistors: 150 US$
market 218·106 US$
2000 for 10 US$, you receive 50·106 transistors (with passive

components, interconnects, ...)
market 200-300·109 US$
unprecedented in industry's history

Introduction
Nanofabrication, Nano III / mc / 15 J. Gobrecht, PSI
Introduction
top-down approach:
extend current techniques to smaller sizes
(EUV-L, x-ray lithography., nano-imprint, flip-
up principle, i.e.: horizontal/vertical exchange,
etc…)
problem: precision, costs
bottom-up approach:
start from individual atoms/molecules
use principles of self-organization (self-
assembly; inspiration from biology,
biochemistry, chemistry)
problem: long-range order difficult to achieve

Introduction
top-down approach:
extend current techniques to smaller sizes 10μm
micro-fabrication
(EUV-L, x-ray lithography., nano-imprint, flip-
up principle, i.e.: horizontal/vertical exchange, UV lithography,
micro-CP
etc…) 1μm
problem: precision, costs

sub-micrometer
100nm fabrication
EBL, FIB
bottom-up approach:
start from individual atoms/molecules 10nm
use principles of self-organization (self-
chemical
assembly; inspiration from biology, synthesis
biochemistry, chemistry) 1nm -SH
problem: long-range order difficult to achieve
nanofabrication (<100nm) Ù combination of both routes
Outline
• Introduction:
overview, state of the art,
semiconductor physics reminder
(Ù condensed matter course)
– clean-rooms
– etching
– lithography

Semiconductors physics reminder
Energy gaps
Si ~ 1.12 eV
Ge ~ 0.66 eV
GaAs ~ 1.43 eV
NB: kT (RT) ~25meV
Si atoms, intrinsic
As doped Si Ga doped Si
n-type p-type
other donors: other acceptors:
P, Sb B, Al
Î e.g.: resistivity changes by > 6 orders of mag.

with a 1ppm B doping

Basic (active) element of IC’s: transistor
• bipolar transistor
current driven, based on pn junction
npn or pnp
• FET (field-effect transistor)

voltage applied to capacitively coupled electrode (gate) creates an
electric field altering the nb of charge carriers in a semiconductor,
thus modulating its conductivity (transfer resistor)
technologies for gate electrode

• pn-junction (junction FET or J-FET)
• Schottky barrier (metal-silicon FET or MESFET)
• insulated gate FET, like metal-oxide-semiconductor MOSFET
pn-junction Current vs voltage: diode behavior

depletion region shrinks
Reverse biased
applied voltage
enhances the
internal potential
difference
Forward biased
applied voltage opposed to
internal potential difference
breakdown
Nanofabrication, Nano III / mc / 22 Ref. 3

npn-transistor
2 diodes back-to-back
n-type
p-type
n-type
MESFET technology
Structure and sign

convention of a metal-
semiconductor junction
metal-semiconductor junction: (Schottky) barrier for electrons and holes
if the Fermi energy of the metal is somewhere between the conduction and
valence band edge
Nanofabrication, Nano III / mc / 24 Course Van Zeghbroeck

Energy band diagram of the metal and the semiconductor
animation
before contact after contact
thermal equilibrium
(Fermi levels adjusted)
Nanofabrication, Nano III / mc / 25 Course Van Zeghbroeck
Workfunction of selected metals and their measured barrier height

(eV) on germanium, silicon and gallium arsenide.
Nanofabrication, Nano III / mc / 26 Course B. Van Zeghbroeck

MOSFET technology: MOS capacitor energy band diagram

Al/SiO2/p-Si
Metal (gate) : Al (Mo, W, Cu), Poly-Si

Oxide : SiO2, d ≈ 1.7-10 nm
Semiconductor : p- or n-type silicon
doping 1013 - 1018 cm-3
orientation typ. <100>
MOS capacitor: ideal case
Assumptions for the ideal MOS structure:

1. No workfunction difference between metal and
semiconductor (aligned vacuum and Fermi niveaus)
2. charges at any bias exist only in the
semiconductor and at the metal surface
3. no carrier transport through the oxide under dc-
biasing conditions
i.e. Flat band condition at V=0

(potential V between gate and back contact)
Nanofabrication, Nano III / mc / 28 B. Föste, Infineon

MOS capacitor: real case
Real MOS structure:
flatband voltage <> 0

VFB=φMS
MOS capacitor
p-type semiconductor

MOS capacitor
MOS capacitor

MOS capacitor
MOS capacitor

MOS capacitor
gate voltage
Ù
control knob for charge
carrier nature
(electron/hole) and
density at
oxide/semiconductor
interface
MOSFET

two different types of

MOSFETs
(n-channel)
• depletion type
(on by default)
Vg=0 Vg<>0
• enhancement type
(off by default)

n- or p-channel
n-channel (NMOS)
(charge carriers:
electrons)
p-channel (PMOS)
(charge carriers:
holes)
for an enhancement-type MOSFET:
Nanofabrication, Nano III / mc / 40 Refs. 1 & 3

CMOS: complementary MOS, today’s most common technology
• n-channel MOS device in series with p-channel MOS device

(when NMOS on, PMOS off and vice-versa, hence "complementary")
• simple design
• draws very little current (except when switched on)
• low-power technology
basic logic gate: inverter

• Vin high (1): NMOS on, PMOS off,
Vout=Vss (low, 0)
• Vin low (0): NMOS off, PMOS on,
Vout=Vdd (high, 1)
CMOS: state-of-the-art
SOI substrate, Cu/low-k interconnection,

5 metal layers, features <0.13mm, 300mm wafers (12 ")
Nanofabrication, Nano III / mc / 42 Refs 1 & 3 M. Bohr, Intel

CMOS: state-of-the-art
SOI substrate, Cu/low-k interconnection, gate structure

5 metal layers, features <0.13mm, 300mm wafers (12 ") very thin oxide layers
Nanofabrication, Nano III / mc / 43 Refs 1 & 3
TEM cross-sections (Chau et al., Intel)
state-of-the-art transistors: sub-50nm technology
gate
dielectric
Nanofabrication, Nano III / mc / 44 http://www.intel.com/technology/silicon/index.htm

CMOS fabrication steps
example of (simple…?!) CMOS process sequence
Nanofabrication, Nano III / mc / 45 H. Xiao, Ref.1
…and then contacting.: wire bonding, packaging
S. Oberholzer
D. Keller

yet…
«The simplest cell (…) is more complex than any machine built
by people so far.»
(Maddox, 1998)
scaling down systems is not only about downsizing,

it's also about the choice of materials,
the interfaces between materials ("contacts")
the geometry / design / architecture of the system
Nanofabrication, Nano III / mc / 47 Refs 2
Outline
• Introduction:
– clean-rooms
– etching
– lithography

IC fabrication
clean room
Silicon
IC fabrication

Outline
• Introduction:
– clean-rooms
– lithography
– etching
Clean room
grain of salt on a
piece of a microprocessor
importance of yield in industrial processes

Î clean rooms
CMI, EPFL
• limit contaminants
(air, people, facility, equipment, gas, chemicals,
static charges, ….)
• special furniture and tools (paper, pens, ...)

Clean room
clean room classes
class 1
less than 1 particle of
diameter larger than
0.5μm in a cubic foot
"normally clean" appartment:

typ. > 500’000 particles
per cubic foot..!
(Federal Standard 209E)
Clean room
maximum particles/ft³
ISO
Class
equivalent
≥0.1 µm ≥0.2 µm ≥0.3 µm ≥0.5 µm ≥5 µm
1 35 7 3 1 ISO 3
10 350 75 30 10 ISO 4
100 750 300 100 ISO 5
1,000 1,000 7 ISO 6
10,000 10,000 70 ISO 7
100,000 100,000 700 ISO 8
clean room standard (ISO 14644-1)
Cn = 10N (0.1 / D)2.08 Cn maximum permitted number of particles per m3

≥ specified particle size (rounded)
N ISO class number ( multiple of 0.1 and ≤ 9)
D particle size (micrometers)

Clean room Particle
Particle Size
(microns)
Beach Sand 100 - 10000
Pollens 10 - 1000
Textile Fibers 10 - 1000
Human Hair 40 - 300
Saw Dust 30 - 600
Tea Dust 8 - 300
Red Blood Cells 5 - 10
Spores 3 - 40
Coal Dust 1 - 100
Smoke from Synthetic Materials 1 - 50
Auto and Car Emission 1 - 150
Metallurgical Dust 0.1 - 1000
Humidifier 0.9 - 3
Copier Toner 0.5 - 15
Bacteria 0.3 - 60
Burning Wood 0.2 - 3
Tobacco Smoke 0.01 - 4
Viruses 0.005 - 0.3
Typical Atmospheric Dust 0.001 to 30
Clean room
simple clean room design

Clean room
more advanced clean room design
Clean room
11. Sit on "dirty" side of bench.

12. Put on one bootie (over plastic shoe cover).
13. Swing bootied foot to "clean" side of bench.
14. Put on other bootie on "dirty" side.
15. Swing bootied foot to "clean" side.
16. Enter main gowning room.
17. Set aside badge, pager, and any other items to be taken inside.
18. Put on nylon gowning gloves.
19. Obtain bunny suit and belt from hanger.
21. If you've never done it before, putting on a bunny suit can take 30 to 40
minutes. The Intel pros can do it in five.
22. Put on bunny suit without letting it touch the floor.
23. Put on belt.
24. Tuck bunny suit pant legs into booties.
25. Fasten snaps at top of booties.
26. Attach filter unit to belt.
27. Attach battery pack to belt.
28. Plug filter unit into battery pack.
29. Obtain helmet, safety glasses, and ID badge from rack.
30. Put on helmet.
31. Tuck helmet skirt into bunny suit.
Steps to enter a cleanroom (Intel) 32. Zip up bunny suit at shoulders.
33. Attach helmet hose to filter unit.
1. Store personal items. 34. Tighten knob at back of helmet.
2. Discard any gum, candy, etc. 35. Put on ID badge.
3. Remove any makeup with cleanroom soap and water. 36. Put on pager.
4. Take a drink of water to wash away throat particles. 37. Put on safety glasses.
5. Cover any facial hair with a surgical mask or beard/mustache lint-free 38. Obtain disposable scope shield.
cover. 39. Remove protective covering from both sides of scope shield.
6. Put on a lint-free head cover. 40. Undo front helmet snaps.
7. Clean shoes with shoe cleaners. 41. Attach face shield to helmet.
8. Put shoe cover on over shoes. 42. Re-snap front helmet snaps.
9. Clean any small, pre-approved items to be taken inside. 43. Examine attire in mirror.
10. Pick up booties. 44. Put on latex gloves.
45. Enter the cleanroom.
Nanofabrication, Nano III / mc / 58 http://www.intel.com/

Outline
• Introduction:
– clean-rooms
– etching
– lithography
Silicon: from sand to wafer
14 +IV
(+II)
Si
Silicon
[Ne]3s23p2
28.085g/mol
1410°C 2.33kg/m3
2nd (after oxygen) most abundant in earth’s crusts: 26%

7th most abundant element in universe

structure: cfc (diamond-like)

Si: nonmetallic element, indirect
semiconductor
SiO2 glass (amorphous),
quartz (cristalline)
SiC very hard (polishing)
Si crystalline (semiconductor
industry)
typical resistivity: 100 mΩ cm
Nanofabrication, Nano III / mc / 61 C. Heedt, Wacker Siltronic
advantadges of Si over other

semiconductors (Ge)
• cheap, abundant
• oxide (SiO2) strong and stable
dielectric (Ö MOS technology);
grown easily by thermal oxidation
• larger band gap (1.1 eV): higher
operation T
• larger breakdown voltage
Doping elements
• n-type: P (phophorus), As
(arsenic), Sb (antimony)
• p-type: B (boron)

Si purification: natural Si oxide Î MGS Î EGS

metallurgical electronic grade
Si purification: MGS Î EGS

EGS Î single cristal ingot: CZ growth (Czochralski method)
Si ingot
up to 300mm diameter (FZ or floating zone purer butlimited to 200mm)

Surface grinding
mark crist. orient.
flat: up to 150mm
notch: > 200mm
wafer sawing
edge rounding

wafer finishing surface roughness after the various treatment
• lapping
(global planarization, double-
sided)
• wet etching , isotropic

(4:1:3 mixture of HNO3, HF
and CH3COOH)
• CMP (chemical mechanical

polishing)
• wet cleaning (RCA1, RCA2)
wafer flats
• Orientation for automatic equipment

• Indicate type and orientation of crystal.
Primary flat – The flat of longest length flat at 180 deg for n-type and 90 deg for p-type
located in the circumference of the
wafer. The primary flat has a specific
crystal orientation relative to the wafer
surface.
Secondary flat – Indicates the crystal

orientation and doping of the wafer.
The location of this flat varies.
flat at 45 deg for n-type, no secondary for p-type
Nanofabrication, Nano III / mc / 70 Ref. 1 www.ee.byu.edu/cleanroom

Miller indices description of lattice planes and lattice directions in crystal
example cubic lattice system

the direction [hkl] defines a vector direction normal to surface of a
particular plane or facet.
type: <110> type: <111>

type: <100>
Equivalent directions: Equivalent directions:
Equivalent directions:
[110], [011], [101], [111], [-111], [1-11], [11-1]
[100],[010],[001]
[-1-10], [0-1-1], [-10-1],
[-110], [0-11], [-101],
[1-10], [01-1], [10-1]
Nanofabrication, Nano III / mc / 71 Ref. 1 www.ee.byu.edu/cleanroom
Outline
• Introduction:
– clean-rooms
additive – material deposition techniques
substractive – etching
– lithography

Fabrication: material deposition techniques
Physical processes
• Physical Vapor Deposition (PVD):
basics of film deposition
thermal evaporation
molecular beam epitaxy (MBE)
pulsed laser deposition (PLD)
sputtering
• Casting
Chemical processes
• Chemical Vapor Deposition (CVD)
• Atomic Layer Deposition (ALD)
• Electrodeposition
• Langmuir-Blodgett films (LB)
Fabrication: physical deposition techniques
fundamentals of film deposition
• gas kinetics
(mean free path: small holes filling, residual gas atoms: purity)
• UHV (p<10-9 mbar) necessary depending on final purity needed
• phase diagrams of materials to deposit (pressure, temperature)
• control type of growth: homoepitaxy; heteroepitaxy; growth of

polycristalline or amorphous layers;
importance of strain Î misfit dislocations
substrate temperature

• gas kinetics
(mean free path: small holes filling, residual gas atoms: purity)
table for residual air at 25°C
• UHV (p<10-9 mbar) necessary depending on final purity needed
Rough Vacuum High Vacuum Ultra-High Vacuum

760 to 10-3 torr 10-3 to 10-8 torr 10-8 to 10-12 torr
load locks evaporation surface analysis
sputtering ion implantation molecular beam

epitaxy (MBE)
reactive ion etching
(RIE)
low pressure chemical

vapor deposition (LPCVD)
NB: 1 torr = 1.33 mbar = 1mm Hg

• phase diagrams of materials to deposit (pressure, temperature)

e.g.: YBa2Cu3Ox
c 500 250
400 200
CuO2 plane b
Tc [K]
a
300 Tetragonal Orthorhombic 150
TN [K]
Insulating Metallic
O(2)
yttrium
200 100
Cu(2)
O(3) baryum
Antiferro-
100 50
O(4) oxygen magnetic Superconducting
(apical)
copper
6.0 6.2 6.4 6.6 6.8 7.0
Cu(1)
O(1)
Oxygen content: x
• type of growth: homoepitaxy
IBM Almaden
STM image, 28nm by 28nm
area of the terraced copper
and copper nitride surface
with Manganese humps (1-
10 atoms long).

• heteroepitaxy
small mismatch large mismatch
Frank-Van der Merwe Volmer-Weber Stranski-Krastanov

(layer growth; ideal) (island growth) (layers then islands due
to strain build up)
• importance of strain Î misfit dislocations: T
strained layer
substrate

Fabrication: thermal evaporation
thermal evaporation: free, isotropic (Langmuir)
resistance heated
evaporation sources:
wires, boats
• Simple, robust, widespread

• T ~ 1800°C
• Use W, Ta, or Mo filaments to heat evaporation
source.
• Typical filament currents are 200-300 Amperes.
• Exposes substrates to visible and IR radiation.
• Typical deposition rates are 1-20 Å/s.
• Common evaporant materials:
– Au, Ag, Al, Sn, Cr, Sb, Ge, In, Mg, Ga
– CdS, PbS, CdSe, NaCl, KCl, AgCl, MgF2, CaF2,
PbCl2
thermal evaporation: free, isotropic (Langmuir)

e-beam evaporation
• More complex, but extremely versatile.

• T > ~ 3000°C
• Use evaporation cones or crucibles (e.g.
graphite) in a copper hearth.
• Typical emission voltage is 8-10 kV.
• Exposes substrates to secondary electron
radiation.
– X-rays can also be generated by high
voltage electron beam.
• Typical deposition rates are 1-100 Å/s
• Common evaporant materials:
– Everything a resistance heated
evaporator will accommodate, plus:
– Ni, Pt, Ir, Rh, Ti, V, Zr, W, Ta, Mo
– Al2O3, SiO, SiO2, SnO2, TiO2, ZrO2

thermal evaporation: ~ directional
effusion (Knudsen) cell

evaporation rate ~ controlled by temperature only
(play with equilibrium vapor pressure and aperture
size)
NB: distribution of vapor beam intensity; depends

on ratio L/d (filling level of cell !)
Biasiol and Sorbia, 2001
NB: shadow effects / step coverage
Ö directionality and adhesion effects

Fabrication: Molecular Beam Epitaxy (MBE)
- source: effusion cells

- multiple cells/shutters
- UHV (Ö in-situ surface
characterisation techniques
possible)
- epitaxy (heated substrate)
excellent control on layer compostion
Nanofabrication, Nano III / mc / 85 Ref. 3 & J.Faist
Fabrication: Molecular Beam Epitaxy (MBE)
Molecular Beam Epitaxy (MBE)
TEM pictures of a QCL

GaAs/AlGaAs structure
(J. Faist, ETHZ)
Nanofabrication, Nano III / mc / 86 J.Faist, ETHZ

Fabrication: Pulsed Laser Deposition (PLD), laser ablation
- source: target, thermal energy (laser pulse ~

few J/cm2)
- multiple target possible (YBCO/PBCO)
- typ. oxide films
- epitaxy (heated substrate)
- off-axis geometry (rotating substrate)
Fabrication: Sputtering
DC sputtering
• few 100V Î plasma (p~10-1 - 10-3mbar)

• sputtering of target by ions, typ. Ar+
(binding energy of target atoms: 4-8eV; min
energy of Ar+ ions: 20-50eV; multiple
collisions necessary)
• stoichiometry of target (~) preserved
• increase ionization rate of plasma with B-field

(magnetron sputtering)
• insulating targets: RF-sputtering (~13MHz)
(erosion)

Fabrication: Casting
Casting (spinning)
(typ. polymers, e.g. photoresists, polyimide)
Fabrication: material deposition techniques
Physical processes
• Physical Vapor Deposition (PVD):
thermal evaporation
molecular beam epitaxy (MBE)
pulsed laser deposition (PLD)
sputtering
• Casting
Chemical processes
• Chemical Vapor Deposition (CVD)
• Atomic Layer Deposition (ALD)
• Electrodeposition
• Langmuir-Blodgett films (LB)

Fabrication: Chemical Vapor Deposition
Chemical Vapor Deposition (CVD)
def: reaction of chemicals (precursors, gas phase) at high T

to form the deposited thin film CMI, EPFL
SiO2 3 SiH4 + O2 Ö SiO2 + 2 H2 450°C
SiO2 SiCl2H2 + 2N2O Ö SiO2 + 2 N2 + 2HCl 900°C

Si3N4 3 SiH4 + 4NH3 Ö Si3N4 + 12 H2 700°C-900°C
poly Si SiH4 Ö Si + 2 H2 580-650°C, 1mbar
note: stress can be critical

(nitride layers)
LPCVD: low-pressure CVD; requires

higher temperatures
PECVD: plasma enhanced CVD,
allows temperature reduction
MOCVD: metal-organic CVD, use
organometallic precursors
Fabrication: chemical deposition techniques
note: thermal oxidation

(note really a deposition process, Si consumed during process)
Ö better oxide quality, very low density of defects, homogeneous
thickness (gate – insulating - material)
dry Si (solid) + O2 (gas) Ö SiO2 (solid)

wet Si (solid) + H2O (steam) Ö SiO2 (solid) + 2H2 (gas)
final thickness: few x 10Å to 2μm (NB: native oxide layer: ~ 2nm)
T ~ 900°C – 1200°C
limited to
materials
able to form
oxides

thermal oxidation
xox(t) ∝ [1+c(t+τ)]1/2
(Deal-Grove)
note: in similar ovens: doping

(diffusion process)
T ~ 800°C

Fabrication: Atomic Layer Deposition (ALD)
Ö self-limiting growth
Nanofabrication, Nano III / mc / 95 Beneq
A: Hydroxylated surface
B: Trimethylaluminium (TMA)
reacts with OH
C: TMA does not react

with itself (passivation)
D: Purge reactor
Nanofabrication, Nano III / mc / 96 Cambridge Nanotech

E: H2O removes CH3

and passivates
F: Purge reactor
G: Ready for new cycle
Repeat A-G for controlled

monolayer deposition
Nanofabrication, Nano III / mc / 97 Cambridge Nanotech
typical conditions Coating uniformity

• Pressure 0.1-5 mbar
• Temperature 60-500ºC
• Gas flow 0.3-1.0 SLM
(std liter / min.)
variety of materials
• Oxides (e.g. Al2O3, HfO2, TiO2, ZrO2 ,
Y2O3)
• Nitrides (e.g. AlN, TiN, WxN)
• Sulfides (e.g. ZnS, CaS)
• Fluorides (e.g. ZnF2, SrF2)
• Metals (e.g. Pt, Ir, Pd)
• Doped materials (e.g. ZnS:Mn, ZnO:Al)
• Polymers (polyimides)
• Biocompatible thin films (hydroxyapatite)
Nanofabrication, Nano III / mc / 98 Beneq

CVD example: carbon nanotubes growth
(CH4, C2H4, C2H2...)
CVD example: CNTs
hydrcarbon gases: C2H2 (acetylene), C2H4 (ethylene), CH4

(methane) (+ …)
carrier gases: H2, Ar
temperature: 600-1000C
catalyst: Fe (Ni, Co)

SWNTs
Fe, ethylene, 900C-1000C
1μm see e.g.: Dai et al. and Hafner et al.
~2nm
lithographically patterned Fe film, acetylene, 600C-700C

120
100
Length (µm)
80
• length of tubes vs time, flow and 60
thickness 40
20
0
• SEM image perp. to SiO2/Si 0 5
Growth Time [min]
10 15
surface
120
Length (µm)
100
80
60
0 5 10 15 20
C2H2 Flow [sccm]
120
Length (µm)
100
80
60
40
20
0 5 10 15 20
Z. Liu et al., 2002 Fe thickness [nm]
M. Perrin et al.,

M. Perrin et al.,
applications: - composite materials

- carbon-based super-capacitors
(large surface to volume ratio)
-…
Fabrication: Electrodeposition (electroplating)
note:
- typ. for thick (>μm) metallic layers - substrate is conducting
- solution with reducible form of metal (electrolyte) - deposition of same material as
- sample at cathode (neg. potential) substrate (seed layer)
e.g. Cu2+ + 2e- Ö Cu (solid)
incorporation of the reduced metal in the substrate
- NB: in pores Ödeposition of wires

Electrodeposition of metallic nanowires
Nanofabrication, Nano III / mc / 107 L. Grüter et al., (PhD thesis, 2005)
SEM picture of Au wires on a Si substrate Au wires after etching off the Ni.
(electrochemical template synthesis) NB: deposition time for Ni: 33 s at V= -0.9 V in both cases.
Gaps: (a) 25 nm and in (b) 60 nm
Nanofabrication, Nano III / mc / 108 L. Grüter et al., (PhD thesis, 2005)

Fabrication: Langmuir-Blodgett (LB) technique
additive techniques: short summary
PVD: physical vapor deposition
film growth mass transport from source to substrate; epitaxial growth possible
(temperature, phase diagrams, vacuum)
source - thermal evaporation (boat, e-beam, effusion cell, laser pulse)

- sputtering
CVD: chemical vapor deposition
film growth deposition of material in gas phase after a

temperature controlled chemical reaction of the
component chemicals
source precursor gases

Outline
• Introduction:
– clean-rooms
additive – material deposition techniques
subtractive – etching
– lithography
Fabrication: etching
Chemical:
• wet etching (can be anisotropic due to crystal-face selectivity)
• fast, up to 10μm/min or more
Physical etching (sputtering)

• ion milling, FIB (focused ion beam)
• dry etching (plasma assisted techniques, pressures up to 10mbar)
(more a combination of physical and chemical material removal)
• slower, typ. 100Å -1000Å/min
key points:
selectivity (etch rates ratio of masking layer and layer to etch)
directionality (defines etch profile)
note:
CMP, chemical mechanical polishing to achieve global planarization
combine mechanical abrasion with chemical etching; key parameters: force, slurry type, pad
velocity

Fabrication: wet etching
• use chemical solutions to dissolve isotropic, typ. 10μm/min

material
• chemical species react with surface

Ö etch products Ö rinse, dry
anisotropic, typ. 1μm/min
Nanofabrication, Nano III / mc / 113 http://www.memsguide.com
SiO2 6:1, buffered in NH4F (BHF) or 10:1 to 100:1 (by vol.) HF in H2O
(NB: 1:1 HF (49% HF in H2O) too fast)
SiO2 + 6 HF → H2SiF6 + 2 H2O (H2SiF6 soluble in H2O)
BHF etch rate: 1000Å/min (room temperature)

masks: photoresist, silicon nitride
Si polycrystalline or single-crystal
isotropic: mix of HNO3 and HF

(cyclic process: HNO3 oxidizes Si, HF removes oxide)
Si + HNO3 + 6 HF → H2SiF6 + HNO2 + H2O + H2

Si anisotropic (cystalline Si): (100) rate / (111) rate ~ 100 at 80°C
e.g.: KOH
23.4% wt, C3H8O 13.3% wt (isopropyl alcohol), H2O 63.3% wt
Si + 4 OH- → Si(OH)4 + 4 e-
exposes slow planes (111)

(~not attacked by etchant)
(110)
ÖV-shaped (or trapezoidal)
groove for (100) wafers
Ö vertical trench for

(110) wafers
Nanofabrication, Nano III / mc / 116 MicroChemicals

Si3N4 H3PO4 91.5% concentration at 180°C (etch rate ~ 100Å/min)
Si3N4 + 4 H3PO4 → Si3(PO4)4 + 4 NH3
silicon phosphate (Si3(PO4)4) and amonia (NH3) are water soluble
selectivity to
thermally grown SiO2 > 10:1
Si > 33:1
metals Al mix of acids (phosphoric, acetic, nitric) and water

Ti mix of sulfuric acid and hydrogen peroxide
NB: selectivity Ö multilayers including stop layer for etching: well-defined wells
Fabrication: dry etching
dry etching: usually plasma based
as compared to wet etch:

- smaller undercut (patterning of smaller lines)
- higher anisotropicity (high aspect-ratio structures possible)
- less selective
- mask etching not negligible
ion milling
purely physical
sputering by accelerated Ar+ ions
p ~ 10-4 – 10-3 torr;
etch rate: few nm/min
note: no selectivity

Si etch with SF6

RIE: reactive ion etching
physical and chemical
SF5+
- accelerated ions (e.g.: Ar+,
directional)
either modify surface state (e.g.: bond
breaking, makes surface more reactive) F-
or help etch products to desorb
- reactive species (e.g. plasma generated from
from SF6) diffuse to substrate surface and
react, forming SiF4 (volatile)
recipes, cf:
T. J. Cotler, M. E. Elta: Plasma-
etch technology, IEEE Circuits &
Devices Mag. 6 (1990) 38–43

DRIE (key process for MEMS)

deep reactive ion etching
Î ICP RIE
SF6 alternated with C4F8 (to

passivate walls), Bosch process
selectivity
Si:SiO2, 150:1
profile angle +/- 1°

SEM/FIB (FEI Nova 600 nanoLab)
Focused Ion Beam (FIB)
• controlled, directed heavy ion

beam (typ. Ga)
• local ion milling (sputtering)
• fine structures, nm range
Electrons
• are very small, inner shell reactions
• High penetration depth
• Low mass -> higher speed for given energy
• Electrons are negative
• Magnetic lens (Lorentz force)
Ions
• Big -> outer shell reactions (no x-rays)
• High interaction probability, less penetration depth
• Ions can remain trapped -> doping
• High mass -> slow speed but high momentum milling !!!
• Ions are positive
• Electrostatic lenses
IBM

FIB operating modes
Pavius et al., CMI EPFL
milling
Pavius et al., CMI EPFL
local cross-sectioning of IC's (Uni Erlangen)

Fabrication: etching, short summary
Chemical:
• wet etching (can be anisotropic due to crystal-face selectivity)
Physical etching (sputtering)

• ion milling, FIB (focused ion beam)
• dry etching (plasma assisted techniques, pressures up to 10mbar)
(more a combination of physical and chemical material removal)
key points:
selectivity (etch rates ratio of masking layer and layer to etch)
directionality (defines etch profile)
Outline
• Introduction:
– clean-rooms
– Silicon: from powder to wafer
– etching
– lithography

lithography: Greek lithos "stone" + graphein "write."
definition: method to define a pattern on

a substrate
typ.: pattern engraving on print block,

inking and transfer to paper
(1st process, Senefelder, 1798)
• first synthetic photo-polymer: 1935,

Eastman Kodak
lithography
overview of lithography process
• Surface Preparation
• Coating (Spin Casting)
• Pre-Bake (Soft Bake)
• Alignment
• Exposure
• Development
• Post-Bake (Hard Bake)
• Processing Using the Photoresist as a Masking Film
• Stripping
• Post Processing Cleaning (Ashing)

lithography
Wafer cleaning
Typical contaminants that must be removed prior to photoresist coating:
• dust from scribing or cleaving (minimized by laser scribing)

• atmospheric dust (minimized by good clean room practice)
• abrasive particles (from lapping or CMP)
• lint from wipers (minimized by using lint-free wipers)
• photoresist residue from previous photolithography (minimized by
performing oxygen plasma ashing)
• bacteria (minimized by good DI water system)
• films from other sources:

– solvent residue
– H2O residue
– photoresist or developer residue
– oil
– silicone
Nanofabrication, Nano III / mc / 129 R.B. Darling
lithography
Wafer cleaning
• Standard degrease:
– 2-5 min. soak in acetone with ultrasonic agitation
– 2-5 min. soak in isopropanol with ultrasonic agitation
– 2-5 min. soak in DI H2O with ultrasonic agitation
– 30 sec. rinse under free flowing DI H2O
– spin rinse dry for wafers; N2 blow off dry for tools and chucks
• For particularly troublesome grease, oil, or wax stains:

– Start with 2-5 min. soak in 1,1,1-trichloroethane (TCA) or
trichloroethylene (TCE) with ultrasonic agitation prior to acetone
• Hazards:
– TCE is carcinogenic; 1,1,1-TCA is less so
– acetone is flammable
– methanol is toxic by skin adsorption

lithography
Wafer priming
• Adhesion promoters are used to assist resist coating.
adhesion factors:
• moisture content on surface
• wetting characteristics of resist
• type of primer
• delay in exposure and prebake
• resist chemistry
• surface smoothness
• stress from coating process
• surface contamination
• for silicon:
– primers form bonds with surface and produce a polar (electrostatic) surface
– most are based upon siloxane linkages (Si-O-Si)
1,1,1,3,3,3-hexamethyldisilazane (HMDS), (CH3)3SiNHSi(CH3)3
lithography
Spin coating of photoresist

lithography
Prebake (soft-bake)
Used to evaporate the coating solvent and to densify the resist after spin
coating.
• Typical thermal cycles:

– 90-100°C for 20 sec. in a convection oven
– 75-85°C for 45 sec. on a hot plate
• Commercially, microwave heating or IR lamps are also used in production
lines.
• Hot plating the resist is usually faster, more controllable, and does not
trap solvent like convection oven baking.
lithography

Different types of lithography
radiation source
DLW
illumination control system
resist coated sample
Optical lithography
source wavelengths: DUV: 157nm-250nm

optical: > 450nm EUV: 11nm-14nm
UV: 365nm-435nm x-ray: < 10nm

Optical lithography
masking methods
contact proximity projection
mask deteriorates poorer resolution better resolution
(diffrac. limited)
Minimum Feature Size
MFS ~ (dλ)1/2 MFS ~ [(d+g)λ]1/2 MFS ~ 0.61 λ/NA
mask deteriorates reduction possible (decreases errors),
stepper (multiple exp.)
Optical lithography
phase-shifting technique
destructive interference

Optical lithography
photoresists
positive: develops at exposed areas

made soluble upon exposure
(chain scission)
e.g. PMMA (DUV, e-beam), DQN
negative: stays at exposed areas

initiates cross-linking of side chains
or polymerization of mono-/oligomeric
species
e.g. maN400
Optical lithography

Optical lithography
Optical lithography

Optical lithography
Optical lithography
Postbake (Hard Bake)

Used to stabilize and harden the developed photoresist prior to processing
steps that the resist will mask.
• Main parameter is the plastic flow or glass transition temperature.

• Postbake removes any remaining traces of the coating solvent or developer
(eliminates the solvent burst effects in vacuum processing).
• Postbake introduces some stress into the photoresist; some shrinkage of the
photoresist may occur.
• Longer or hotter postbake makes resist removal much more difficult.
NB: Postbake is not needed for processes in which a soft resist is desired, e.g.
metal liftoff patterning.

Optical lithography
photoresists profiles
(after development)
R: developing rate of
exposed region
R0: developing rate of

unexposed region
R/R0 > 10: fast developper
γ: resist contrast
(linked to exposure dose, cf Madou)
Optical lithography
Example: lift-off process, undercut control Effect of exposure time

ma-N 400 negative resist (micro resist
technology), 2 µm thickness
tE 90 s,
0 µm undercut
tE 100 s,
0,5 µm undercut
tE 140 s,
1,5 µm undercut
Nanofabrication, Nano III / mc / 146 micro resist technology

EUV lithography (R&D)
reflection optics
(for λ=10-15nm: no transparent enough materials for lenses)
x-ray lithography (R&D)
X-ray Interference Lithography (XIL)

NB: same problem as EUV, no lenses
Nanofabrication, Nano III / mc / 148 J. Gobrecht, H. Solak et al.

X-ray Interference Lithography (XIL)

NB: same problem as EUV, no lenses
• frequency multiplication: factor

depending on the diffraction orders
chosen (2x for 1st order).
• fransmission grating patterned
with e-beam
• coherent beam
EUV: λ=13.5 nm
Ö feature size: 3.5 nm
Nanofabrication, Nano III / mc / 149 J. Gobrecht, H. Solak et al.
Nanofabrication, Nano III / mc / 150 J. Gobrecht et al.

positive tone negative tone
“world record “
for photon-based
lithography
typ. exposure param. for PMMA

field up to 3mm wide (coherence limited)
10 sec exposure, λ=13.4nm
Nanofabrication, Nano III / mc / 151 H. Solak et al.
multiple beam interference
Nanofabrication, Nano III / mc / 152 H. Solak et al.

electron beam lithography (EBL)
precise (energy, dose)

relatively slow
(industrial application: parallel beams)
resolution limit ~ 10nm (50nm)
no mask
large DOF
large scattering of electrons
Nanofabrication, Nano III / mc / 153 Refs. 1 & 3
proximity effects
Nanofabrication, Nano III / mc / 154 J. Gobrecht, PSI

dose test on PMMA: overcut to undercut (A. Kleine) note: undercut

critical for lift-off
EBL compared to optical/UV lithography
+ precise control of dose delivery

+ fast beam deflection and modulation
+ smaller spot on resist (<10nm) as compared to light (500nm), increased resolution
+ no mask needed (direct writing, "software" mask)
+ large depth of focus
- strong electron scattering in solids (practical resolution > 10nm)

- operation in vacuum (electron beam)
- slow exposure speed (scanning)
- high cost

lithography: short summary
• optical (mask contact or projection)
• electron beam (direct writing)
soft lithography and more "exotic" techniques
microcontact printing (MCP)
polydimethylsiloxane (PDMS)
(e.g Sylgard 184, DOW Corning)
B. Michel et al., Advanced Semiconductor Lithography, 2001

microcontact printing (MCP)

microcontact printing (MCP) master
• first used to print alkanethiols on

gold surfaces
stamp
• quick and cheap method to perform
simple assays (e.g.: immunoassay:
crossed stamped lines)
printed and etched pattern

Scanning Probe Microscope - based lithography
First SPM lithography
J. Gobrecht and J. Pethica
1986
AFM Lithography
Th. Jung, H. Hug et al. 1989
Nanofabrication, Nano III / mc / 161 source: J. Gobrecht
STM lithography
Th. Jung et al.

Hot embossing: the principle
Nanofabrication, Nano III / mc / 163 J. Gobrecht
Hot embossing: nanoreplication in polymers
(NB: plasma etch

before eavporation)
S. Chou, 1998
Nanofabrication, Nano III / mc / 164 J. Gobrecht

Multiphoton polymerization
Fig. 1 Fluorescence in a rhodamine B solution excited by single-photon excitation from a

UV lamp (left) and by TPA of a mode-locked Ti:sapphire laser tuned to 800 nm (right).
In the former case, the integrated intensity is equal in all transverse planes, while in the
latter case the integrated intensity squared is peaked in the focal region. (Reprinted with
permission from3. © 2007 Wiley-VCH.)
Nanofabrication, Nano III / mc / 165 Materials Today, June 2007
Multiphoton polymerization
Nanofabrication, Nano III / mc / 166 Materials Today, June 2007

Outline
• Introduction:
– clean-rooms
– Silicon: from powder to wafer
– etching
– lithography
– examples of devices
Si nanowires: SOI wafers
• Silicon on Insulator, thermal oxidation • Si etched: TMAH
80 nm
60 nm
SiO2 150 nm
Si 500 μm
• Contacts etched: HF
• Cr mask ~100 n
1 - 10 m
μm
• Al contacts:
• Plasma etch: CHF3, deposit & anneal
• Cr removed: KMnO4, NaOH

Si nanowires: SOI wafers
Nanofabrication, Nano III / mc / 169 D. Keller, O. Knopfmacher
Si nanowires
• processes: thermal oxidation, spinning (resist), lithography

(optical + e-beam), metallization (Cr mask, with e-beam), dry
etching (RIE SiO2 with CHF3), Cr mask stripping (in solution)
and wet etching of Si (NB: 1st wet etch of SiO2 surface oxide
and then Si), annealing (contact improvement).
Nanofabrication, Nano III / mc / 170 D. Keller, O. Knopfmacher

Si nanowires
G (S)
0.8 5.000E-7 0.8
0.6 0.6
1.581E-7
0.4 pH 4 0.4 pH 7
5.000E-8
0.2 0.2
Vpt (V)
Vpt (V)
0.0 1.581E-8 0.0

-0.2 -0.2
5.000E-9
-0.4 -0.4
-0.6 1.581E-9 -0.6
-0.8 5.000E-10 -0.8
-10 -8 -6 -4 -2 0 -10 -8 -6 -4 -2 0
Vg (V) Vg (V)
molecular electronics: contacting molecules
A V
~ 2 nm
?
mc, J. Seminario
„direct“ nanogaps
Nanogaps fabrication
• UV + e-beam lithography
• angle evaporation
0° a
1mm
PMMA
is
PMMA-MA e ax
wir
SiO2
10 – 20 nm gaps
gold 15/50 nm thick 200nm
Nanofabrication, Nano III / mc / 173 L. Bernard et al.
trapping: dielectrophoresis
AC field : 1Mhz, 106-107 V/m positive dielectrophoresis

(particles with higher permittivity than
dielectrophoresis medium: force towards the highest
interaction “induced dipole moment intensity of the field)
/ applied electric field”
r α% r r 2
FDEP = V ∇ E
2
3ε m (ε p − ε m ) σ
α% = ε%i = ε 0ε i − j
ε p + 2ε m ω
4
V = π d3
3
Nanofabrication, Nano III / mc / 174 L. Bernard et al.

structure for DNA manipulation
Ti/Au electrodes
SiN
SiO
F. Dewarrat et al., Single Molecules, 2002
break junctions
mechanically controllable
break junction
suspended
metallic bridge
24mm
• microfabricated junctions: e-beam
lithography
phosphor bronze / polyimide / Au oxygen
plasma underetched
• elongation: e= 6thz/L2
reduction factor: r=e/z ≈ 1/100'000
Nanofabrication, Nano III / mc / 176 T. Gonzalez et al.

example: colloids arrays for molecular electronics
PDMS
A. master PDMS
fabrication
PDMS PDMS PDMS
B. stamping
transfer of the film stamping on solid substrate:

to a PDMS stamp patterned array
example: colloids arrays for molecular electronics
Nanofabrication, Nano III / mc / 178 "stamper": Jon Agustsson

patterned colloids arrays
Patterned nanoparticle array

b
SiO2/Si
c d
60°
Nanofabrication, Nano III / mc / 179 J. Liao et al.
arrays structure
C8 C12 C16
C8 C12 C16
dC8 = 2.4 ± 0.1nm dC12 = 3.1 ± 0.1nm dC16 = 3.3 ± 0.1nm

lC8 ~ 1.3nm lC12 ~1.8nm lC16 ~2.3nm
(overlap ~ 2Å) (overlap ~ 5Å) (overlap ~ 13Å)

contacting
• TEM grid as shadow mask
a l
w
20μm 20μm
• e-beam metal deposition evaporated contacts
(5nm Ti / 40-60nm Au)

patterned
arrays
SiO2
Si
molecular exchange
stable array (no aggregation) Ar formation of an inter-linked

network of particles by
~ "breadboard"
incorporation of the thiolated
OPE
1mM OPE
in THF, 24h
OPE: A. Pfalz, Basel

a “switch” molecule: light
"ON"
λ1 > 420 nm λ2 = 313 nm

(vis) (UV)
"OFF"
Nanofabrication, Nano III / mc / 183 reversible switching on Au surface: Katsonis et al., Adv. Mat., 2006
a “switch” molecule: light

UV
UV
UV
UV
UV
vis vis vis vis vis vis

switch 3.2
is on "ON"
3.0 (closed)
2.8
G (nS)
2.6
2.4
"OFF"
2.2 (open)
2.0
0 100 200 300 400 500
meas. cycle # (1cycle = 30s)
Nanofabrication, Nano III / mc / 184 S. vd Molen, J. Liao et al.,

a “switch” molecule: redox
oxidation: FeCl3 (iron chloride)

reduction: Fe(C2H5)2 (ferrocene)
S. Decurtins et al.
a “switch” molecule: redox
preliminary results
experiment: exchange Æ oxidation Æ reduction C8 Æ TTF (0)
Æ TTF ox (2+)
Æ TTF red (0)
Nanofabrication, Nano III / mc / 186 J. Liao, J. Agustsson, S. Wu et al.,

colloid arrays: platform for molecular electronics
m mm μm nm
MEMS/NEMS and devices
from MEMS (micro-electromechanical systems) …
e.g. Si gears for watch industry: lower friction and inertia
Nanofabrication, Nano III / mc / 188 CSEM & Ulysse-Nardin

• electrostatic micromotor • individual mechanical

fabricated from silicon micromirrors part of a Texas
Instruments Digital Light
Processor (MOEMS)
Nanofabrication, Nano III / mc / 189 Physics World, Feb. 2001
fabrication process for such structures
structural layer sacrificial layer substrate

… down to NEMS
• masses in 10-15g to 10-18 g range (∝ L3)

• resonators above 10GHz (∝ 1/L)
(f ~ (spring cst/eff. mass)1/2, spring constant ∝ L)
• very low power: 10-18W threshold (thermal fluc. at 300K)
• low dissipation, high Q factor: sensitive to damping Î sensors
(sensitivity potentially reaching quantum limit)
• NB: 10x10x100 nm Si beam contains ~ 5 x 105 atoms,

among which ~3 x 104 reside at the surface
(i.e.: > 10% of the constituents are surface or near-surface atoms)

nano-tweezers:
electrostatic actuation
actuation amplitude
down to 6 pm (rms)/ sqrt(Hz)
Ch. Meyer, H. Lorenz, and K. Karrai, "Optical detection of quasi-static actuation of

nanoelectromechanical systems" Appl. Phys. Lett. 83, 2420 (2003).

axis
(CNT) rotor (metal)
an
ch
o r
300 nm
stator (control electrodes)
Nanofabrication, Nano III / mc / 194 Fuhrer, Zettl et al., Nature 2004

Nanomechanical Electron Transport: videos

quantum-bell: max current at fdrive~ resonance freq.
avg nb of e- shuttled per cycle
A Erbe, Ch Weiss, W Zwerger, and R H Blick, Phys. Rev. Lett. 87, 096106 (2001)
M Jonson and R Shekhter, Phys. World 16, 21 (2003).
Integration: hybrid devices
Nanofabrication, Nano III / mc / 196 Tech. Roadmap for Nanoelectronics, IST program, European Commission

Fabrication of IC 7

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Nano III

Micro- and nano-fabrication

• Outlook: new and future techniques

Nanofabrication, Nano III / mc / 2

1. Fundamentals of Microfabrication: The Science of Miniaturization

Nanofabrication, Nano III / mc / 3

1947, 24th December ATT Bell Labs

first point contact transfer resistor

Bell labs Bell labs nobel.se

Nanofabrication, Nano III / mc / 4

Nanofabrication, Nano III / mc / 5 C. Esser, Infineon

1961, Robert Noyce,

first integrated circuit

Nanofabrication, Nano III / mc / 6 C. Esser, Infineon

1971 Intel anounces the i4004 microprocessor

Nanofabrication, Nano III / mc / 7 http://www.intel.com

Nanofabrication, Nano III / mc / 8 http://www.intel.com

1965, Gordon E. Moore

Electronics, Vol. 38(8), 1965

Nanofabrication, Nano III / mc / 9 http://www.pbs.org/transistor/

Nanofabrication, Nano III / mc / 10 M. Bohr, Intel

performance , power , cost

Nanofabrication, Nano III / mc / 11 M. Bohr, Intel

state of the art today 45nm

Nanofabrication, Nano III / mc / 12 www.intel.com/technology/

“I think there is a world market for

Nanofabrication, Nano III / mc / 13

1958 1 transistor = 10 US$;

2000 for 10 US$, you receive 50·106 transistors (with passive

market 200-300·109 US$

unprecedented in industry's history

Nanofabrication, Nano III / mc / 14

Nanofabrication, Nano III / mc / 15 J. Gobrecht, PSI

Nanofabrication, Nano III / mc / 16

problem: precision, costs

nanofabrication (<100nm) Ù combination of both routes

Nanofabrication, Nano III / mc / 17

• Outlook: new and future techniques

Nanofabrication, Nano III / mc / 18

NB: kT (RT) ~25meV

Nanofabrication, Nano III / mc / 19

Semiconductors physics reminder

Î e.g.: resistivity changes by > 6 orders of mag.

Nanofabrication, Nano III / mc / 20

Basic (active) element of IC’s: transistor

• FET (field-effect transistor)

technologies for gate electrode

Nanofabrication, Nano III / mc / 21

Semiconductors physics reminder

pn-junction Current vs voltage: diode behavior

Nanofabrication, Nano III / mc / 22 Ref. 3

Nanofabrication, Nano III / mc / 23 Ref. 3

Semiconductors physics reminder

Structure and sign

metal-semiconductor junction: (Schottky) barrier for electrons and holes

Nanofabrication, Nano III / mc / 24 Course Van Zeghbroeck

Energy band diagram of the metal and the semiconductor

before contact after contact

Nanofabrication, Nano III / mc / 25 Course Van Zeghbroeck

Semiconductors physics reminder

Workfunction of selected metals and their measured barrier height

Nanofabrication, Nano III / mc / 26 Course B. Van Zeghbroeck

MOSFET technology: MOS capacitor energy band diagram