Beginner help with VHDL, Xilinx 9536XL, and ISE7.

Beginner help with VHDL, Xilinx 9536XL, and

ISE7.1

Source: http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2006−01/msg00260.html

• From: cdsmith69@xxxxxxxxx
• Date: 5 Jan 2006 11:53:33 −0800

So I need some help getting started with programmable logic and VHDL.

In the past all I have done in the programmable logic area are 16V8 and
22V10 PALs.

I actually feel kind of stupid about the simple questions I am about to

ask, since it isn't like I don't know a lot about electonics. I have a
BSEE and in the past I've designed DSP boards and motor controllers
that control hundreds of amps and make electric forklifts able to lift
thousands of pounds. Pretty fun stuff actually.

But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and
the Xilinx XC9536XL experimenter board I am using.

I've gone through ALDEC's Evita VHDL tutoral end to end and I think
I've learned the basics of the language.

So my project was to write a program to take a step and direction input

and output the proper sequences to control a stepper motor. But the
logic output sequences I got didn't make sense, so I decided to walk
before I run and just programmed up a couple very simple programs.
More on that later.

So what I've got is an XC9536XL board I bought on eBay. I connected a

4 position dip switch with 4 pull up resistors connected so that when
you turn on a switch the input is grounded and read as a zero. Turn
off the switch and the pullup pulls high and it's read as a one. I
know this works because I can measure the correct logic signal right at
the CPLD.

I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through
a current limiting resistor. The other end of each LED is connected to
an output of the CPLD. So sending a logic zero to the output should
sink current and turn on the LED. The LEDs work because I can unplug
them from the socket header and connect each to ground and the LED
lights as expected.

The first "simple" program I wrote was to read the switch inputs and

Beginner help with VHDL, Xilinx 9536XL, and ISE7.1 1

 Beginner help with VHDL, Xilinx 9536XL, and ISE7.1

output them to the LEDs, using the following VHDL code in Xilinx ISE
7.1:

−−−−−−−−−−−−−−−−−−−−−−
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Test1 is
Port (SWITCH_IN : in std_logic_vector(3 downto 0);
LEDS_OUT : out std_logic_vector(3 downto 0));
end Test1;

architecture Behavioral of Test1 is

begin
LEDS_OUT <= SWITCH_IN;
end Behavioral;
−−−−−−−−−−−−−−−−−−−−−−

This code shows that the LEDs and switches work. I can flip the
switches and the LEDs change state. But here is the first problem.
The LEDs light opposite what I expect. The LEDs light when the
corresponding switch is set to input a high into the CPLD. It's like
either the inputs or outputs are being inverted inside the CPLD.

So I thought I'd try something simpler −− to turn on all the LEDs by

outputting "0000" to the four pins the LEDs are connected to. I
changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the
LEDs to turn on. They didn't. So I figured maybe the outputs are
what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking
that this way, inverted or not, two LEDs would light and two wouldn't.
The problem is none of the LEDs light. Remember that I showed that
both the switches and LEDs can change state with LEDS_OUT <=
SWITCH_IN;, just backwards from what I expected.

So I remembered from the tutorial that lots of code in VHDL is

triggered by changes in inputs, so I changed the LEDS_OUT assignment to
the following:

LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1)

and SWITCH_IN(0));

This should kill two birds with one stone. It will show me if I can
assign pins directly to values when it is part of an equation that
includes inputs that can change state. I thought mabye my previous
attempts didn't work since there was nothing to "trigger" the equation.

Also, with ANDing the switches and outputting that to one LED, I can
tell if it is the inputs or the outputs that are being inverted inside
the CPLD. If it is the inputs, I would have to set the switches to all

Beginner help with VHDL, Xilinx 9536XL, and ISE7.1 2

 Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
input a zero before the AND will be active and change the state of the
LED. "0000" will be the input that causes a different output then the
other 15 combinations, insted of "1111." If it is the output being
inverted, I'd have to set the inputs all to one, but the LED will light
opposite of what I expect, turning on with the inputs all set to one
(remember the output sinks current from the LED and therefore the LED
lights when a zero is output).

The result is that the upper 3 LEDs still all remain off, despite
directly setting two outputs to a one and one output to a zero. My
logic probe shows a high on those three CPLD pins. Apparently I can't
directly set a pin even when it is part of an equation.

The last LED lights when all four switch inputs are set to input a
high. This indicates that the inputs are not being inverted in the
CPLD. But the LED lights when the switches are all set high and I can
measure a logic low, 0V, on that LED's pin. This would indicate that
the outputs are being inverted from the way the assignment equation
would indicate.

My next experiment was to do something simple − a 4 bit counter right

from the Xilinx language templates. I ended up with the following VHDL
code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter1 is
Port ( CLK_IN : std_logic;
SWITCH_IN : in std_logic_vector(3 downto 0);
LEDS_OUT : out std_logic_vector(3 downto 0));
end Counter1;

architecture Behavioral of Counter1 is

signal count : std_logic_vector(3 downto 0) := "0000";
begin
process (CLK_IN)
begin
if CLK_IN = '1' and CLK_IN'event then
if SWITCH_IN(0)='1' then
count <= count + 1;
else
count <= count − 1;
end if;
end if;
end process;
LEDS_OUT <= count;
end Behavioral;

Beginner help with VHDL, Xilinx 9536XL, and ISE7.1 3

 Beginner help with VHDL, Xilinx 9536XL, and ISE7.1

In the simulator this counter works fine, but when I run this code the
output sequence I get is not a straight count from 0 to 15. I get the
sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly
repeatable, and the sequence reverses when I flip SWITCH_IN(0). After
some looking at the binary for that count sequence, I noticed that
every second number is the inverse of the previous, instead of the
expected number (14 is 1110, inverse of 0001 that preceeded it, not
0010 as expected next). I don't get it.

So my questions are:
1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an
inversion happening somewhere inside the CPLD, apparently at the
outputs?
2. Why can't I just set outputs to a zero and have a LED light? Any
pin I directly assign to a value stays high.
3. Why doesn't my counter count?

It shouldn't be this difficult...

This ended up a lot longer than I expected, so if you made it this far,
thanks for reading it, and thanks for any help you can provide...

cdsmith

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