JOURNAL OF APPLIED PHYSICS VOLUME 88, NUMBER 11 1 DECEMBER 2000

Modeling of organic thin film transistors of different designs

P. V. Necliudova) and M. S. Shur
Rensselaer Polytechnic Institute, Department of Electrical, Computer and System Engineering,
Troy, New York
D. J. Gundlach and T. N. Jackson
Department of Electrical Engineering, Pennsylvania State University, University Park, Pennsylvania
共Received 14 July 2000; accepted for publication 15 September 2000兲
We report on modeling of direct current 共DC兲 characteristics of organic pentacene thin film
transistors of different designs. Our model incorporates a gate-voltage dependent mobility and
highly nonlinear drain and source contact series resistances. The contact nonlinearities are especially
pronounced in bottom source and drain contact thin film transistors. The model successfully
reproduced both below- and above-threshold characteristics of top source and drain contact and
bottom source and drain contact organic pentacene thin film transistors. © 2000 American Institute
of Physics. 关S0021-8979共00兲03524-6兴

I. INTRODUCTION II. DETAILS OF EXPERIMENT

Recently, Gundlach et al. reported a mobility of 2.1
cm /V-s for organic pentacene thin film transistors 共TFTs兲
2 Figs. 1共a兲 and 1共b兲, respectively. The TFT fabrication started
with the on/off ratio as high as 108 . 1 These numbers compare
very favorably with mainstream ␣-Si:H TFT technology.
Simple pentacene-based circuits such as five-stage ring os-
cillators with propagation delay of 73 ␮sec have been
demonstrated.2 A relatively simple technology with low gate
dielectric and active layers deposition temperatures3 allows
fabricating organic TFTs on virtually any substrate including
flexible ones, and therefore makes organic TFTs attractive
for low-end circuits and large-area applications. Moreover,
organic TFTs are natural candidates to the drivers of organic
light emitting diodes 共OLEDs兲, which have already been
used in high-resolution active matrix displays.4
Contemporary pentacene organic TFTs have different
designs. One of them is the so-called top source and drain
contact 共TC兲 TFT design, where both source and drain con-
tact pads are deposited on top of an active layer through a
shadow mask. The TC TFTs are the easiest to fabricate and
they showed superior characteristics over TFTs of other
designs.1 However, there is no suitable procedure to pattern
the TC TFT active layer to isolate the devices from each
other. TFTs of another design, where drain and source con-
tact metal is deposited on the gate dielectric and patterned
prior to the active layer deposition, are referred to as bottom
source and drain contact 共BC兲 TFTs. A special procedure has
been developed to pattern nonchemically the TFT active
layer between individual TFTs on a substrate.5
In this article we present a model simulating DC charac-
teristics of both TC and BC TFTs. We also present an
equivalent circuit allowing us to simulate a highly nonlinear
source and drain series resistance for the BC TFTs. Prelimi-
nary results for the TC TFT modeling were reported at
ISDRS-99.6
a兲
Electronic mail: neclip@rpi.edu
The layouts of the BC and TC TFTs are presented in
from thermal growth of SiO2 gate dielectric of thickness t ox
⫽290 nm and t ox⫽250 nm for BC for TC TFTs, respec-
tively, on a highly doped Si substrate, which served as a
common gate electrode. The gate dielectric surface was
ozone cleaned and treated by a self-assembled octadecyltri-
chlorosilane 共OTS兲 agent prior to the pentacene active region
deposition. Such a treatment considerably improves penta-
cene TFT performance.7 For the BC TFTs, gold was depos-
ited on the gate dielectric and source and drain contact pads
were patterned prior to the pentacene active layer deposition
from a commercially available pre-purified powder. In case
of the TC TFTs, the source and drain contact pads were
formed by gold deposition on top of the pentacene active
layer through a shadow mask. More details on the TFT fab-
rication process can be found elsewhere.8 The gate length L,
defined by the source-drain pads spacing, was 30 ␮m for the
TC TFTs and 20 ␮m for the BC TFTs. The gate width W
共contact pads width兲 was 220 ␮m and the pentacene active
layer thickness was 50 nm for both types of TFTs.
We used an HP 4156B Precision Semiconductor Param-
eter Analyzer to measure the DC electrical characteristics of
the TFTs. In order to minimize effects of environment on the
TFT characteristics,9 we placed our probe-station in a light
isolated dry-nitrogen ambient. The pentacene active layer
was mechanically removed around the measured TFTs in
order to minimize the drain current leakage.
III. MEASURED DC CHARACTERISTICS
Figures 2共a兲 and 2共b兲 show the measured TC TFT output
and transfer characteristics, respectively. The BC TFT
current-voltage characteristics resemble those for the TC
TFTs. However, the BC TFTs have a highly nonlinear region
in the output drain current I D –drain-source voltage V DS
characteristic at low V DS , as shown in Fig. 3. The TC TFT

0021-8979/2000/88(11)/6594/4/$17.00 6594 © 2000 American Institute of Physics

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 J. Appl. Phys., Vol. 88, No. 11, 1 December 2000
FIG. 1. 共a兲 Bottom source and drain and 共b兲 top source and drain pentacene
TFT layouts.
output characteristic is free from this feature, see Fig. 3. A
similar nonlinear I D ⫺V DS behavior was also observed for
␣-hexathienylene TFTs10 and in SiC MOSFETs.11 In the
case of SiC MOSFETs, this nonlinearity was observed only
for the p-channel samples with a nonideal contact fabrication
FIG. 2. Measured TC pentacene TFT 共a兲 output and 共b兲 transfer character-
istics. Gate length L⫽30 ␮ m, gate width W⫽220 ␮ m.
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Necliudov et al. 6595
FIG. 3. Measured output TC 共circles兲 and BC 共squares兲 TFTs characteris-
tics. The drain current is normalized to allow comparison of both TFT
characteristics. Drain-gate voltage V GS ⫽⫺60 V for both TFTs.
process, and therefore was attributed to the presence of para-
sitic Schottky diodes in series with the source and drain con-
tacts. The results of our 1/f noise studies for the BC penta-
cene TFTs suggested that drain and source series resistances
were, in fact, nonlinear12 and depended on the drain current
value. Below, we present an equivalent circuit simulating the
nonlinear BC TFT series resistance.
IV. DC MODEL AND SIMULATION RESULTS
According to the conventional crystalline semiconductor
MOSFET theory, the MOSFET drain current in saturation is
proportional to the square of the effective gate-source volt-
age swing V GT ⫽V GS ⫺V T , 13
W␮ci 2
I d ⫽I sat⫽ V GT , 共1兲
2L
where c i is the gate dielectric capacitance per unit area, ␮ is
the mobility 共hole or electron兲, W and L are the gate width
and length, respectively.
Our previous studies showed that a model based on the
Si MOSFET Unified Charge Control Model13 adequately de-
scribed saturation current in the above-threshold region of
the TC TFT operation, while it considerably deviated in both
linear and below-threshold regions.6 In order to obtain a bet-
ter fit of the measured data, we developed a model incorpo-
rating a gate voltage dependent mobility.6 According to the
model, in pentacene organic TFTs operating above threshold,
most of the charge induced by the gate-source voltage is
trapped in the numerous traps and only a fraction of the
carriers participates in the current conduction. The effect of
the charge trapping is accounted for by the empirical gate-
voltage dependent field-effect mobility,
␮ FET⫽ ␮ 0 冉 V GS ⫺V T
V AA 冊 ␥
, 共2兲
where ␥ and V AA are empirical parameters that can be ex-
tracted from the I DS (V GS ) characteristics and ␮ 0 is a con-
stant. This approach is similar to that used for amorphous Si
 6596 J. Appl. Phys., Vol. 88, No. 11, 1 December 2000 Necliudov et al.

FIG. 5. Proposed equivalent circuit of the BC TFT including nonlinear

source and drain contact resistances. V DD is the extrinsic drain voltage, R S
and R D are the source and drain constant parasitic resistances, respectively.
The diode ideality factors ␩ are fitting parameters.

⫽0.65 eV in our simulations. Comparisons of the circuit

simulation results with the experiment showed that the pair
of diodes connected to the drain terminal was enough to
simulate the measured nonlinearity. Figure 6 shows the
simulation results of the BC TFT output characteristics.
Please note that we were able to obtain a good fit of both
nonlinear region ( 兩 V DS 兩 ⬍5V) and linear as well as satura-
tion region (5V⬍ 兩 V DS 兩 ⬍60V). The model parameters are
presented in Table I. As in the TC TFT case, the extracted

FIG. 4. Modeling of TC pentacene TFT 共a兲 output and 共b兲 transfer charac-
teristics. Modeling parameters are listed in Table I.

TFTs modeling.14 The model includes the parasitic series

drain and source resistances. The full set of equations de-
scribing the above- and below-threshold regimes of the TFTs
operation can be found elsewhere.15 Figure 4 presents the
results of the TC TFTs simulations. We were able to obtain a
satisfactory fit of both the above- and below-threshold re-
gions of the TC TFT operation by the developed model. The
extracted gate-voltage dependent mobility tends to reach the
mobility value ␮ ⫽0.17 cm2 /V-s extracted from the 冑 I D,sat
⫺V GS characteristic. Therefore, the model resembles the
MOSFET Unified Charge Control Model at high gate-source
voltages, at which most of the traps are filled and a larger
fraction of the gate-voltage induced carriers participate in the
drain current conduction.
In order to simulate the nonlinear I D ⫺V DS output char-
acteristics for BC TFTs, we proposed an equivalent BC TFT
circuit that consists of the TFT with linear source and drain
access resistances R D and R S , respectively, and a pair of
antiparallel leaky Schottky diodes connected to each access
resistor in series, see Fig. 5. Two diodes in parallel are
needed to obtain a symmetric current-voltage characteristic.
FIG. 6. Modeling of the BC TFT 共a兲 output and 共b兲 transfer characteristics.
The diode ideality factors ␩, which are responsible for the
The BC TFT equivalent circuit includes diodes in series with the drain and
steepness of the current-voltage characteristic, are the fitting source terminals to simulate the nonlinear source and drain contact
parameters. We used the Schottky barrier height E B resistances.

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 J. Appl. Phys., Vol. 88, No. 11, 1 December 2000 Necliudov et al. 6597

TABLE I. TC and BC TFT parameters used in the DC characteristics modeling.

Mobility,
Gate length L, R S ,R D , cm2/V-s at ␮0 , Diode
TFT width W, ␮m Ohm V T ,V V GS ⫽⫺60 V cm2/V-s ␥ V AA ,V ␩
TC L⫽30 1⫻10 5
⫹5 ␮ ⫽0.22 10 0.45 3⫻10 5
¯
W⫽220
BC L⫽20 5⫻104 ⫹13 ␮ ⫽1.2 10 0.38 1.9⫻104 10
W⫽220

gate-voltage dependent mobility at high V GS reaches the mo-
bility value ␮ ⫽1.1 cm2 /V-s extracted from the 冑 I d,sat⫺V GS
characteristic at high V GS .
V. CONCLUSION
We presented the results of the TC and BC TFT DC
characteristic simulations by a gate-voltage dependent mo-
bility model. The model simulates both above- and below-
threshold regimes of the TC and BC TFTs operation. Unlike
TC TFTs, the BC TFTs exhibit nonlinearities in the output
characteristics at low V DS . We attributed those features to
the effect of nonlinear series resistances. We proposed an
equivalent circuit incorporating a pair of diodes in series
with the source and drain parasitic resistances to model the
measured BC TFT output characteristics. The diode ideality
factors were the fitting parameters. The proposed model al-
lowed us to obtain a good fit of the BC TFT output charac-
teristic in the 0⬍ 兩 V DS 兩 ⬍60 V range.
ACKNOWLEDGMENTS
DARPA 共Program Monitor Dr. G. Henderson兲 has sup-
ported this research under Contract No. N61331-98-C-0021
via subcontract from Sarnoff Corporation.
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