Low Voltage LC –Ladder Gm-C Low-Pass Filters with 42-215 MHz
Tunable Range
Aránzazu Otin∗ Concepción Aldea* Santiago Celma*
Abstract − In this paper we report 3rd-order Gm-C filters based
on fully-balanced pseudo-differential continuous-time
transconductors for applications in low-voltage systems over
VHF range. By using a 0.35 μm standard CMOS process, two
low-pass filter approximations (Butterworth and Elliptic) have
been implemented with a cut-off frequency programmability
from 42 to 215 MHz, which confirm the feasibility of the
proposed strategy in applications such as data storage systems
and IF strips. The filters consume less than 3.8 mW from a 2 V
supply The measured dynamic range was 53 dB at THD of
1%. The estimated active area of the filter is 0.074 mm2.
1 INTRODUCTION
The hard disk drive (HDD) has become in an
important and extremely useful element in every
information processing system. The trends in HDDs
involve high user densities and data rates supported
by current storage systems [1]. This demands
complex read channel ICs, in particular, continuous-
time filters with variable bandwidths, over a wide
range (typically 1:5), to accommodate the different
data rates required by constant density recording and
servo processing [2]. Among the different
continuous-time integrated filter strategies is the Gm-
C approach [3-4] the preferred option, thanks to its
acceptable performance over the VHF/UHF range.
To achieve a digitally programmable CT filter,
compatible with the latest low-cost digital CMOS
processes [5] and suitable with high frequency
requirements, specific design techniques of building
block based filters must be explored.
There are different ways to implement a
transconductor in CMOS technology. Current-mode
pseudo-differential transconductors exhibit low-
voltage, moderated linearity and very high frequency
operation capability with high power efficiency [6,
7]. This approach has been adopted in a new design
of transconductor cell with digital programmability
[8, 9], showing a good choice to implement high
frequency filters which achieve a good trade-off
between dynamic range and tuning capability.
In this paper, two different programmable/tunable
0.35µm CMOS technology filters with a 2 V power
supply are proposed: a 3rd-order Butterworth low-
pass and a 3rd-order elliptic low-pass LC ladder
filters.
The programmability exhibited by the filters is
achieved owing to the design of a generic
∗
Group of Electronic Design. Department of Electronic and Communications Engineering, Zaragoza University, Spain.
E-mail: [aranotin, caldea, scelma]@unizar.es, tel.: +34 976 761 240, fax: +34 976 762 143.
programmable transconductor, which could be used
in other higher order filter topologies.
The proposed filters are made up of parallel
connection of unit folded-cascode cells specifically
designed for wide programmability range. The
tunability range exhibited by the filters covers from
42 MHz to 215 MHz with a total harmonic distortion
(THD) of less than 1% (-40 dB) for 120μA
differential signal (60% Ibias) throughout the whole
operating frequency range in both structures.
2 FILTER DESIGN
2.1 Programmable Fully-balanced Pseudo-
Differential Transconductor
An optimal solution for digitally programmable
analog filters in VHF/UHF range is to take
advantage of current-mode pseudo-differential
topologies and to provide it with digital
programmability.
The folded cascode circuit exhibits a substantial
improvement in biasing flexibility, because of the
increased drain-voltage of the transistors, at the cost
of additional current sources and bias voltages.
Another important benefit by using these stages is
that by avoiding the biasing constrains associated to
the high-swing cascode, i.e., the gate-source voltages
need not be kept small, results in smaller and simpler
devices for a given bias current level, and larger
unity-gain frequencies. This is the option we are
going to use in this work and the fully-balanced
pseudo-differential current-mode transconductance
cell implemented by using the folded stage is shown
in Fig. 1.
In this approach, the use of a cascode output is not
necessary because the DC gain is increased by
providing positive feedback compensation for the
signal current flowing into M3,6 and boosting the
input resistance of the integrator. Theoretically,
adjusting the equivalent negative resistance formed
by transistors M2,5, the DC gain could be infinity but
in practice, mismatching limits the dc gain.
The use of pseudo-differential topologies requires a
careful and efficient control over the common-mode
behaviour of the circuit. It is worth noting that this
structure not only stabilises the common-mode
voltage, but also rejects the input common-mode In consequence, we can conclude that by varying
signals by means of partial positive feedback [6-9]. the digital word from 1 to 5, the expected linear
I-O
dependence of the unity-gain frequency is obtained
I+i and the phase error is effectively reduced over all the
gm gm gm programming range (phase error less than 3º).
R
IBIAS
Driving the gates of MPi with modulated digital
CI
MPi
voltages, we can obtain the desired transconductance
VB with no switches in the signal path and power
Vin
CI VOUT consumption proportional to the total
R
Mi
transconductance. On the other hand, a fine tuning of
VFN
gm gm MNi
the proposed structure can be achieved as the
gm
transconductance value can be controlled by varying
I-
i
I+O the bias current source for a fixed digital word.
Hence, discrete steps are swept maintaining the same
Figure 1: Fully balanced pseudo-differential current- dynamic range by varying the bias current, and a
mode transconductance cell. control over the DC-gain can be achieved by
modifying the ratio between the bias currents of
In order to reach the maximum frequency of M1/M2 and M4/M5.
operation with moderated power consumption, we
use as the integration capacitance CI the parasitic 2.2 Filter Topology
capacitors and an additional one implemented by For demonstrating the performance of the proposed
using a double-poly capacitor. Nevertheless, MOS-C transconductor, two different fully-balanced pseudo-
or metal-metal capacitors could be used depending differential low-pass 3rd-order filters, with
on the CMOS process. Butterworth and elliptic approximations, were
In this way, to control the operation frequency and chosen to be the tested. Both filters are derived from
to reduce the phase error, a shunt connection is made their doubly terminated LC ladder prototype in the
at the input between a resistance (implemented with current mode. The Gm-C implementation can be
a transistor working in the linear region) and the accomplished by substituting the terminating
integration capacitance CI. Then, we obtain a resistors in the prototype by diode-connected
compensation scheme for the transconductor based transconductors and the inductor by a gyrator.
on a RC circuit at the input. According to this idea, Fig. 3 shows the block
By means of a parallel connection of equal diagram of the elliptic filter with resistive
transconductors switched by a digital word we termination using a gyrator-capacitor combination.
guarantee that the dynamic range for each gm value The Butterworth filter is described with the same
and the total external node capacitances will be kept block diagram except for the floating capacitor
almost constant. Fig. 2 shows the conceptual scheme which does not appear. The LC filter shows an
of a 3-bit programmable cell where the feasibility of inherent 6 dB loss and it has been compensated by
the programmable array of transconductors has been using a 2gm-stage in both filters.
proven obtaining frequency scaling as expected According to the nominal transconductance
[8,9]. obtained with the proposed programmable cell, the
filter capacitances were selected in order to obtain a
In gmi Out nominal cut-off frequency of 42 MHz. To achieve a
high cut-off frequency, the filter operates also on
Cpin Cpout parasitic capacitances. This is possible since the
b0 parasitic capacitances are all at nodes where a
capacitance is desired in the filter. The need of a
2gmi
high impedance node obtained with the folded-
cascode transconductor disappears depending on the
way of connecting the cell to the rest of the circuit.
b1
In this way, we can simplify the structure of the
4gmi programmable transconductor and using a simpler
folded stage, i.e., without the four-cascode stage
positive feedback shown in Fig.1. Then, the only
b2 complete programmable transconductor cell is used
to implement the gyrator. The others are
Figure 2: 3-bit programmable transconductor. implemented by using the simpler one.
 C2 R

R R
_ _ _ R _ _ _ _
+ + + + +
2C1 2C3
gm gm gm gm gm gm 2xgm
Iin IOut
_ 2C1 _ _ _ _ 2C3 _ _
+ + + + +
2CL
R R

C2 R

Figure 3: Filter active implementation: Butterworth (C2=0) and Elliptic (C2≠0).

The illustrated cut-off frequencies are tuned from

3 RESULTS
Two different Gm-C low-pass filters have been
designed in a pure digital 0.35 μm double-well
CMOS technology with a 2 V power supply. The
estimated active area of the filter is 0.074 mm2 in
both structures. The filter frequency response
obtained by the post-layout simulations for both
prototypes is reported in Fig. 4.
42 MHz to 215 MHz corresponding to the variation
of the transconductance from 1gm to 5gm. In
accordance, the power consumption is comprised
between 3.7 mW and 18.6 mW. Total harmonic
distortion (THD) of the filters was measured with 1
MHz input signal and 42 MHz cut-off frequency. In
this situation, a THD of less than 1% (-40 dB) is
obtained for 120 μA differential signal (60% Ibias)
throughout the whole operating frequency range in
both structures.
Table 1 summarizes the most important post-layout
simulation results for the elliptic and Butterworth
filters referred to 42 MHz cut-off frequency.

Elliptic Butterworth

Power supply voltage 2 Volts

Frequency range (-3dB) 42-215 MHz 41-217 MHz

Power dissipation/pole 3.7–18.6mW

Total rms input-referred 196.42 nArms 182.53 nArms

noise
Maximum input signal 120 μA
current at 1% THD
(a) Dynamic range 53 dB
(1% THD)

Table 1: Simulations Results for the Filters.

3.1 Comparative Analysis

(b)
Figure 4: Cut-off frequency for several digital words:
(a) Butterworth filter, (b) Elliptic filter.
In this section we present a comparative between
several programmable filters implemented with
similar technologies. In this way, certain conclusions
can be drawn about the proposed design and the
benefits of this technique. The most relevant
characteristics of the compared programmable filters
are summarized in Table 2.
The main striking quality to point out is that the
use of the proposed strategy leads to substantially
lower chip area (0.025 mm2/pole) and power
consumption (3.7 mW/pole) with dynamic ranges of
53 dB. The results obtained with this technique are
extremely encouraging. Although it is only the
qualifying round, post-layout simulation results have
been presented and important benefits of the
proposed technique are clearly identified, specially
the use of a small active area. Nevertheless, to obtain
further details about the specifications of the
compared filters and a more detailed explanation of
the background of these systems, the reader is
referred to the original works [10-12] to draw
additional conclusions.
4 CONCLUSIONS
This paper describes an approach for realizing
digitally programmable CT filters compatible with
the latest low-cost digital CMOS processes over the
VHF/UHF range. The followed strategy is based on a
fully-balanced pseudo-differential current-mode
transconductor with discrete tunability. The apparent
complexity inherent to discrete tuning is overcome
taking into account that in modern communication
systems, the digital circuit controls the filter
bandwidth. Obviously, frequency span and
resolution are in function of the transconductance
ratio and the digital word length.
Acknowledgments
This work has been partially supported by CICYT
(TIC02-00636).
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This work PAVAN [10] GOPIN. [11] BOLL. [12]

3rdorder filter 4th order filter 7th order filter 8th order filter
Technology 0.35 μm n-well 0.25 μm n-well 0.25 μm n-well 0.25 μm n-well
CMOS CMOS CMOS CMOS
Power supply 2 Volts 3.3 Volts 2.5 Volts 2.5 Volts
voltage: VCC
Frequency range 42 – 215 MHz 60 - 350 MHz 30 - 100 MHz 30 - 120 MHz
2 2
Area/pole 0.025 mm 2
0.15 mm 0.43 mm 0.23 mm2
(double-poly) (MOS-C) (metal-metal C) (MOS-C)
Power /pole at the 3.73 mW 17.5 mW 30 mW 15 mW
lowest frequency
Maximum input 120 μA 380 mVpp 455 mVpp 200 mVpp
signal at 1% THD
Dynamic range 53 dB 54 dB -------- 45 dB

Table 2: Comparative Analysis of Several Programmable Structures.