ATIF KHAN

ak552ff0@westpost.net 710 W 27th Stree

t, Los Angeles, CA 90007 (323)
440-6719
Objective: To get a full-time position in VLSI Industry where I can use my analy
tical and technical skills for the growth and
Development of organization
EDUCATION
MASTER OF SCIENCE, ELECTRICAL ENGINEERING
Aug 20
08- May 2010
UNIVERSITY OF SOUTHERN CALIFORNIA [GPA: 3.5]
Coursework: Diagnosis and Design of Reliable Digital Computers, VLSI SYSTEM DES
IGN A/B, Digital System Design Tool and Techniques, Computer System Architecture
, CMOS VLSI DESIGN, Computer System Organization, Real Time Computer System
BACHELOR OF SCIENCE, ELECTRONICS AND COMMUNICATION ENGINEERING
Aug 2004-May 2008
RTMNU (Nagpur, India)
Coursework: Digital Signal Processing, Microprocessor (8085,8086), Linear Elect
ronic Circuits, Electronic System Design, Digital Communication, Mobile Communic
ation, UHF & Microwave, Computer Communication and network, Electronics Devices
and circuits, Electromagnetic Field, C and Data Structure
WORK EXPERIENCE
Directed Research (USC)
Jan 2010 -Present
Worked on the enhancement of Tomasulo processor by adding Free Register List, C
opy Free Check pointing, Return Address Stack.
Walking backward and forward in case of mis-prediction was also carried out. Th
e improved processer will be used as a Course Project in Digital System Design C
ourse
Electrical Engineering Intern (ITag)
Jan 2010 - Present
Research and Development of Phone Tracing Device using GPS Technology
Summer Intern (CDAC Indian government R&D Institute)
May 2008-Ju
ly 2008
Worked on design of Ethernet 802.3 MAC Transmitter
TECHNICAL SKILLS
Languages: Verilog, VHDL, System C, C, C++, TCL Script, UCF, MATLAB, Assembly L
anguage (8085/8086)
Design Tools: Cadence Virtuoso, Xilinx ISE Web pack, ModelSim , Altera Quartus
2, ePD, HSPICE, Nanosim, Simple-Scalar, Real Estimator, Cacti, OrCAD, MultiSim,
SPEC Benchmark , NCSim , Digilent Adept , Cosmoscope, DFT, Synopsys Design Compi
ler
Operating System: Win7/Vista/XP, UNIX
PROJECTS:
DDR2 SDRAM Memory Controller Design (Verilog): Controller to carry out Scalar, A
tomic and Block Read/Write with Denali DDR2 Model using NC-Verilog. The controll
er has a simple FIFO based front end Architecture. The code was synthesized usin
g Synopsis
Design Compiler with the help of TCL script.
Test Generation for an FPGA Chip (C): Led a team of 5 to develop a test generati
on system consisting of Preprocessor, an ATPG and a Fault Simulator. Designed a
preprocessor whose task was creating a reduced fault list Using Fault Equivalenc
e and Dominance and design of Good Circuit Simulator with Inertial, Rise and Fal
l Delay
Out of Order Processor using Tomasulo Algorithm (VHDL): Out of Order processor w
hich used Register renaming to remove Date Hazards. Designed various units like
Instruction Fetch Unit, Dispatch Unit, Issue Unit, Reorder Buffer, Branch Predic
tion Buffer. Synthesis was done using Xillinx ISE. The code was tested on Sparta
n-3E FPGA
16 bit Motion Estimator for DSP (Cadence Virtuoso): ME kernel was designed whic
h contained two 2.048 kb SRAM, 24 bit Ladner Fischer Adder and an accumulator. D
RC and LVS was carried out on the layout. Stimulus file was written and result w
as verified on Nanosim. Logical Efforts were used to reduce the delay in circuit
.
Neural Network chip Design (Cadence Virtuoso): Designed a neuron that emulated a
football Quarterback. Efforts were made to reduce Area-Delay Product
Performance Boosting of CPU (Simple Scalar, Real Estimator, Cacti): Reconfigured
parameter of baseline processor to get higher MIPS rating
Single Cycle, Multi Cycle, Pipelined CPU(ePD): Schematic level design was implem
ented.
Other HDL projects: Lux Meter, I2C, Keyboard Controller with Debounce, Pipelined
CPU
Extracurricular Activities/Achievements
* Graded as superior student in Computer System Organization and Digital System
Design Course
* Won 2nd prize in VHDL coding completion in Kriti'08 at Raisoni College of Engi
neering, Nagpur India.
* Executive member of Communique a student's body during 3rd year of College