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ARM’s Perspective
Emre Ozer
ARM R&D, Cambridge
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ARM
IP Company
Processor IP
Physical IP
Fabric and Peripheral IP look at the power characteristics
Processor Family
M-Class (Ultra-low power and very low-power)
Microcontrollers
R-Class (Real-time and embedded processors)
Automotive, control, critical-safety, military and space
A-Class (Application processors)
Mobile, Smartphone, Consumer Electronics, Netbooks and
Servers
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Current R&D Activities
Process, Voltage and Temperature Variations
Project: Razor- Energy-efficient adaptive processor aiming at
Technology and Environment variations and fault tolerance
Custom Processors
Project: Reconfigurable Array and Fabric – Tool design for
application-specific custom processor
System-level Performance and Power Modelling
Project: Accurate Modelling of SoC – Detailed models of memory
controllers and system power
Memory Bandwidth
Project: EuroCloud - 3D DRAM on Logic
Cloud Computing and low-power Servers
Project: EuroCloud – Low-power server using multi-core Cortex A9
for Mobile Cloud apps
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Challenges
1.P
rocess Variations, Reliability and
Fault Tolerance
2.P
ower – Dark Silicon Problem
3.M emory Wall
4.S calability
5.C loud Computing
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Challenge 1: Variations, Reliability and Fault Tolerance
Variations
Process, voltage, temperature and dynamic
From die to die, wafer to wafer
Yield is a concern
Soft errors
Single-event transients, Single event upsets, Single-event latchups
and etc.
Hard errors
Aging, wear-out, NBTI and etc.
Reliable Execution
Hardware and software solutions required
Fault tolerance techniques
Beyond 22nm, operating requirements for safety-critical and space
applications may also be true for general-purpose apps
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Challenge 2: Power – Dark Silicon Problem
Node 45nm 22nm 11nm
Power
@ 45nm freq 1 0.6 0.3
@ peak freq 1 1 0.6
Exploitable Si
(equivalent Power)
24% 10%
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Challenge 2: Power – Dark Silicon Problem
How to fill the Dark Silicon
On-chip memory (cache, DRAM or other)
Turn off when not used
Hardware accelerators (Video, audio,
encryption and etc)
Only activate the required accelerators
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Challenge 3: Memory Wall
DRAM Bandwidth & Latency cannot keep up with the
computational demands
Get worse with increasing number of many cores
Solution to Bandwidth
3D DRAM Integration
3D Integration
Solution to Latency
Alternative Memory technologies
Phase-change RAM, MRAM and etc
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Challenge 4: Scalability
Future is homogeneous many cores. Good! but
Performance Scalability
Programming and Tools
Interconnection network
Power Scalability
May not power all the cores at the same time!
Heterogeneous many cores or many accelerators could be
more power-scalable option in the future – Corollary to the
Dark Silicon Problem
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Challenge 5: Cloud Computing
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EuroCloud Roadmap = Deliverable
= Vision
ARM Non-coherent
server-on-chip
Comparison
of standard
3D DRAM
controller
Off-chip
NIC
Server PM
design +
Standard
vs. EuroCloud
arch report vs. EuroCloud Heterogeneous server
design design
servers report node arch report demonstration
NOKIA Ovi server Ovi server load 1st Cloud app Cloud app Cloud app Green Nokia
instrumentation analysis report demo ready ready for trial report data center
setup public trials goes online ?
EuroCloud
Server apps
and x86 server server boards EuroCloud
comparison
report
ready Commercial
EuroCloud
Commercial servers in
outsourced EuroCloud volume
Cloud arch and Server HW design start ? server production ?
runtime proto acceleration
prototypes ?
created report
EPFL Multi-Linux
non-coherent
Scalable
caches and
interconnects
Race-free/lock-free
memory ordering
server system report
report report
UCY Faults/errors
Reliability of
cores/clusters
Reliability of
caches/DRAM
Reliability of
3D interconnect
analysis report report report report
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Main Topics EC could focus on
Dark silicon problem
On-chip memory, HW accelerators, perhaps new battery technologies
Custom accelerators
Tools and novel HW structures (e.g. reconfigurable fabric and arrays)
Reliability and Fault tolerance
Beyond 22nm
Memory Technologies
3D integration, novel memory elements and etc.
Cloud computing – HW and SW
Low-power servers in the Data Centres
Mobile devices are also Cloud servers
Cloud Standardization
Virtualization
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EC could encourage
Physical prototype development rather than virtual prototypes:
FPGAs and even ASICs
To understand the variation effects beyond 22nm
Unfortunately, not having a “Euro foundry” is a concern for both researchers and
industry
There is ST, NXP and Infineon but …
GlobalFoundries could be alternative Euro fab (e.g. Dresden fab)
Addressing the Dark silicon problem
Heterogeneity, custom accelerators, on-chip memory and etc.
Memory Technologies
Almost no European memory vendor
In the short term, the focus should be on 3D DRAM Integration
Cloud Computing converges with Embedded Computing
Embedded systems will become future “Cloud client” and “Cloud server”
SW, Virtualization, Infrastructure Standardization
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Industry’s View on EC Projects
In the industry, the general view on EC projects is that they
are not very successful.
Underlying reasons:
Too many partners in the consortia
In ARM, we believe that STREP like (3-to-5 partner) projects are
more agile and successful than the IP projects
Due to previous experiences, ARM avoids participating IP-type
projects
Most of the projects led by the academia with academic agenda
pushes away the industrial participation
No real product comes after the project ends
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What could the EC do better?
EC could encourage the industry-led proposals
e.g. a separate scheme like STREP but the leadership must be from
the industry
With a separate budget of “real prototypes” (e.g. testchips, test
boards, evaluation boards and etc)
In general, the “real prototype” budget could be from 100KEuros to
a couple of MEuros depending on the prototype with 100% EC
contribution
Total project budget 4-6M Euro (EC contribution) for 2 or 3 years
looks reasonable
EC could also encourage small-partner projects without
restrictions:
e.g. no “minimum 3 partners from 3 different countries” condition
Do we have statistics on the success rate of 18-20 partner IP
projects?
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THE END
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