IRFP450

Data Sheet January 2002

14A, 500V, 0.400 Ohm, N-Channel Features

Power MOSFET • 14A, 500V
This N-Channel enhancement mode silicon gate power field
• rDS(ON) = 0.400Ω
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of • Single Pulse Avalanche Energy Rated
energy in the breakdown avalanche mode of operation. All of • SOA is Power Dissipation Limited
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers, • Nanosecond Switching Speeds
relay drivers, and drivers for high power bipolar switching • Linear Transfer Characteristics
transistors requiring high speed and low gate drive power.
• High Input Impedance
These types can be operated directly from integrated
circuits. • Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Formerly developmental type TA17435.
Components to PC Boards”

Ordering Information Symbol

PART NUMBER PACKAGE BRAND D

IRFP450 TO-247 IRFP450

NOTE: When ordering, use the entire part number.

G

Packaging
JEDEC STYLE TO-247

SOURCE
DRAIN
GATE

DRAIN
(TAB)

©2002 Fairchild Semiconductor Corporation IRFP450 Rev. B

 IRFP450

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

IRFP450 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 500 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 500 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 14 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 8.8 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 56 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 180 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 860 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 125oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 500 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 14 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
On Resistance (Note 2) rDS(ON) ID = 7.9A, VGS = 10V (Figures 8, 9) - 0.3 0.4 Ω
Forward Transconductance (Note 2) gfs VDS ≥ 50V, ID = 7.9A (Figure 12) 9.3 13.8 - S
Turn-On Delay Time td(ON) VDD = 250V, ID ≈ 14A, VGS = 10V, RGS = 6.1Ω , - 16 27 ns
Rise Time tr RL = 17.4Ω MOSFET Switching Times are - 45 66 ns
Essentially Independent of Operating Temperature
Turn-Off Delay Time td(OFF) - 68 100 ns
Fall Time tf - 41 60 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID ≈ 14A, VDS = 0.8 x Rated BVDSS - 82 130 nC
(Gate to Source + Gate to Drain) IG(REF) = 1.5mA (Figure 14) Gate Charge is
Essentially Independent of OperatingTemperature
Gate to Source Charge Qgs - 12 - nC
Gate to Drain “Miller” Charge Qgd - 42 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 2000 - pF
Output Capacitance COSS - 400 - pF
Reverse Transfer Capacitance CRSS - 100 - pF
Internal Drain Inductance LD Measured from the Contact Modified MOSFET - 5.0 - nH
Screw on Header Closer to Symbol Showing the
Source and Gate Pins to Internal Device
Center of Die Inductances
D
Internal Source Inductance LS Measured from the Source - 12.5 - nH
Lead, 6.0mm (0.25in) from LD
Header to Source Bonding
Pad
G
LS

S
Thermal Resistance, Junction to Case RθJC - - 0.70 oC/W

Thermal Resistance, Junction to Ambient RθJA Free Air Operation - - 30 oC/W

©2002 Fairchild Semiconductor Corporation IRFP450 Rev. B

 IRFP450

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Symbol - - 14 A
Showing the Integral D
Pulse Source to Drain Current (Note 3) ISDM - - 56 A
Reverse P-N Junction
Rectifier

S
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 14A, VGS = 0V (Figure 13) - - 1.4 V
Reverse Recovery Time trr TJ = 150oC, ISD = 13A, dISD/dt = 100A/µs - 1300 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = 13A, dISD/dt = 100A/µs - 7.4 - µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 7.9mH, RG = 25Ω, peak IAS = 14A.

Typical Performance Curves Unless Otherwise Specified

1.2 15
POWER DISSIPATION MULTIPLIER

1.0
12
ID , DRAIN CURRENT (A)

0.8
9

0.6
6
0.4

3
0.2

0 0
0 50 100 150 25 50 75 100 125 150
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

0.5
ZθJC, THERMAL IMPEDANCE

0.2
0.1
0.1
0.05
0.02 PDM
0.01
10-2
t1
SINGLE PULSE t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

©2002 Fairchild Semiconductor Corporation IRFP450 Rev. B

 IRFP450

Typical Performance Curves Unless Otherwise Specified (Continued)

103 20
OPERATION IN THIS VGS = 10V PULSE DURATION = 80µs
AREA IS LIMITED VGS = 6.0V DUTY CYCLE = 0.5% MAX
BY rDS(ON)
16
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

102 VGS = 5.5V

10µs
12

10 100µs

1ms 8
VGS = 5.0V

1 10ms
4
VGS = 4.5V
DC
TJ = MAX RATED
SINGLE PULSE VGS = 4.0V
0.1 0
1 10 102 103 0 50 100 150 200 250
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

20 102
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VGS = 6.0V VDS ≥ 50V
16
ID, DRAIN CURRENT (A)

VGS = 10V
ID, DRAIN CURRENT(A)
VGS = 5.5V 10

12

1
8
VGS = 5.0V TJ = 150oC TJ = 25oC

4 0.1
VGS = 4.0V VGS = 4.5V

0 10-2
0 3 6 9 12 15 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

10
PULSE DURATION = 2µs 3.0
rDS(ON), NORMALIZED DRAIN TO SOURCE

VGS = 10V VGS = 20V PULSE DURATION = 80µs

rDS(ON), ON-STATE RESISTANCE (S)

DUTY CYCLE = 0.5% MAX

0.9 DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 7.9A
2.4
0.8
ON RESISTANCE

0.7 1.8

0.6
1.2
0.5

0.4 0.6

0.3
0 10 20 30 40 50 60 70 0
-40 0 40 80 120 160
ID , DRAIN CURRENT (A)
TJ , JUNCTION TEMPERATURE (oC)
NOTE: Heating effect of 2µs is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

©2002 Fairchild Semiconductor Corporation IRFP450 Rev. B

 IRFP450

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 10000
rDS(ON), NORMALIZED DRAIN TO SOURCE

ID = 250µA VGS = 0V, f = 1MHz

CISS = CGS + CGD
1.15 8000 CRSS = CGD
COSS ≈ CDS + CGD
BREAKDOWN VOLTAGE

C, CAPACITANCE (pF)
1.05 6000

CISS
0.95 4000
COSS
0.85
2000
CRSS

0.75
-40 0 40 80 120 160 0
1 2 5 10 2 5 102
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

20 102
PULSE DURATION = 80µs
PULSE DURATION = 80µs
ISD, SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX 5 DUTY CYCLE = 0.5% MAX
gfs, TRANSCONDUCTANCE (S)

VDS ≥ 50V
16 TJ = 25oC
2
10
12
TJ = 150oC 5

2
8 TJ = 150oC TJ = 25oC
1
5
4
2

0 0.1
0 4 8 12 16 20 0 0.5 1.0 1.5 2.0 2.5
ID , DRAIN CURRENT (A) VSD , SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 14A

VDS = 400V
16
VGS, GATE TO SOURCE (V)

VDS = 250V
VDS = 100V
12

0
0 25 50 75 100 125
Qg, GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

©2002 Fairchild Semiconductor Corporation IRFP450 Rev. B

 IRFP450

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
RL VDS
90% 90%

+
VDD 10% 10%
RG
- 0

DUT 90%

VGS 50% 50%

PULSE WIDTH
VGS 10%
0

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD

SAME TYPE Qg(TOT)

AS DUT VGS
12V
0.2µF 50kΩ Qgd
BATTERY
0.3µF
Qgs

D
VDS

G DUT
0

IG(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

©2002 Fairchild Semiconductor Corporation IRFP450 Rev. B

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Definition of Terms

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Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

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Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4
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