Joji Joseph

24 Summerfield Drive, Holtsville, NY 11742

631-848-8985 / jjba48a4@westpost.net

POSITION Hardware Design Engineer

EDUCATION Master of Science in Electrical and Computer Engineering
New York Institute of Technology, Old Westbury, NY GPA: 3.75 (08/07)
Master's Thesis: Designed and fully implemented an autonomous robotic system em
ploying multiple robots for assisting the disabled and elderly in various capaci
ties using COTS technology.
Bachelor of Engineering in Computer Engineering
SUNY at Stony Brook, Stony Brook, NY GPA: 3.60 (05/03)

Technical Skills:
* Languages: VHDL, Verilog.
* Operating System: UNIX, Windows, DOS.
* Design: Circuit and Board level - Analog and Digital.
* Sound knowledge in Altera FPGAs and CPLDs.
* Experience in working with Motorola Freescale, Applied Micro and Microchip mic
roprocessors as well as flash, SRAM, DDR and DDR2 SDRAM memory.
* Great engineering knowledge of op-amps, comparators and digital logic.
Strengths:
* Good analytical skill and ability to solve problems efficiently
* Excellent interaction skills to work among project team members
* Determining the most efficient methods for acquiring the correct results
* Good communication skills for presenting items clearly
SOFTWARE OrCAD 9.2 Schematic Capture, PADS Layout 2005, Altera Quartus II Progr
ammer and Timing tools, Altera MAX+PLUSII, ModelSim, Linear Technology LTSpice
- Circuit Simulation Tool, PSPICE, MATLAB, Microsoft Office (Word, Excel, Power
Point, Access, Outlook)

WORK EXPERIENCE
03/06 - 08/10 AFCO Systems Development
Hardware Design Engineer, Melville, NY
* Assisted in research and design as well as simulation and debugging of PCB usi
ng Homeplug technology.
* Familiar with designing motherboards with multiple interfaces: PCI, PCIE, USB,
SPI, JTAG, RS232, Ethernet and I2C in conjunction with Motorola Freescale and A
pplied Micro microprocessors using OrCAD 9.2 Schematic Capture.
* Designed high-speed boards with FPGAs using VHDL for microprocessor to memory
(Flash, DDR and DDR2 SDRAM) interfaces.
* Designed system outline including complete drawings, schematics and layout for
optimal signal integrity along with assisting in EMI testing of various boards.
* Managed project expenditures within boundaries of financial plan.
* Modeled and analyzed high speed digital/analog circuitry for SNR and power est
imation/sequencing using LTSPICE.
05/03 - 03/06 Fonar Corporation
Hardware Design Engineer, Melville, NY
* Designed, modeled, debugged and managed the production of MRI field mapping PC
B using VHDL in the Altera FPGA.
* Developed multiple data transfer boards with various interfaces: USB, RS-485 a
nd RS-232.
* Coded, simulated and analyzed multiple SDRAM controller modules in FPGAs using
 VHDL.
* Developed several alternate component placements and testing procedures for ex
isting designs.
* Performed on-site testing and debugging of legacy controller boards.
HONORS New York Institute of Technology: Graduated Suma Cum Laude (08/07)
SUNY at Stony Brook: Tau Beta Pi, Eta Kappa Nu - Engineering Honor Societies,
National Honor Society
REFERENCES Available upon request