the thetmal and electrical system, the bias heating can bc repli-
2000
cated on a capacitor in thc electric circuit. In Fig. 1, the voltage
across the capacitor COcan be written as
where
Thus, if
a replica of bias heating can be generated on capacitor CO,which
can be used to cancel the bias-heating effect. Thus, Io and C,
should be chosen such that eqn. 6 is satisfied. The ratio of the
current and the capacitance, lo/Co,can be determined from the
given parameters of the microbolometer.
$1 $2
period
CI.
period
time, ps
Fig. 3 SPICE simulirtinn resu1f.s nf bius-lieatbig caricrll~itioncircuit
0 no bias heating cancellation, IR input = 120nW
A no bias healing cancellation, 1R input = 0
V with bias heating cancellation, IR input = 120nW
0 with bias healing cancellation, IR input = 0
Simulation results: The bias-heating cancellation circuit is simu-
bated and verified in SPICE. R,/ is replaced with a microbolometer
model similar to the one in 141. Switches SWO to 5 are imple-
mented using MOS transistors, and the preamplifier using a volt-
age control voltage source (VCVS) with a gain of 20. The aspect
ratios of the switches are optimised so that the effects of the ON
resistance and the charge injection will be as low as possible. In
the simulation, the IR incident power per pixel was set cither to
zero or 120nW. The microbolometer-related parameters used in
simulation arc set as follows: R,, = R, = 5kL2, RI = R3 = 500Q
Rsw = 7 0 7 4 a = O.liK, H = 1.7 x IO"'J/K, G (thcrmal conduct-
ance) = 4.76 x lo-' W/K and &/ = 5V. The siinulation results in
Fig. 3 show that the bias heating can be effectively cancellcd. The
capacitor COand the current I , are chosen to be 50pf and 31 nA,
respectively. There is a small discrepancy between the ratio I,,/Co
determined by eqn. 6 and by simulation for thc complete cancella-
tion of the bias heating. This may arise from thc approximation
made in the derivation of eqn. 6. However, the small discrepancy
is not important a s the ratio Io/C, can to luned through Io, to
achieve the complete bias-heating cancellation. The tunable bias-
heating cancellation is an additional advantage of this circuit.
Conclusion: A circuit to cancel bias heating of a microbolometer
has been described. Based on the equivalence between thc thermal
and electrical systems, the proposed circuit utilises a simple cur-
rent source and a capacitor to generate a replica of bias heating
which is subsequently used to cancel bias heating of the microbo-
lometer. The bias-heating cancellation is tunable through the cur-
rent source. Simulation results have shown that, with properly
chosen current and capacitor values, the bias heating can be effec-
tively cancelled. Although the circuit is demonstrated for a single
pixel, it can be easily extended to an IR focal plane array.
1994 ELECTRONICS LETTERS
a IEE 2000 3 Octohei.
Electronics Letters Online Nri: 2000 1414
DOI: / 0 . 1 0 4 ~ / ~ l ~ 2 0 0 0 1 4 / 4
Y.P. Xu and X.B. Qian (Depmtmenf uf Electricul nnd Cowputer
Engineering, Nafionrrl University of Singaporr, Siiigripore I / 7576)
E-mail: clexuyp~iiiis.edu.sg
G. Karunasiri (Departnienf 01 Pl~j~sics,N r i v u / Posfgmduote Scl~ool,
Monterey, CA 93943. USA)
Refcrences
and LIDDIAIID. u.: 'Theoretical analysis of
JANSSON, r,, R I N G I I , U,,
pulse bias heating or resistance bolometer infrared dctectors and
effccliveness of bias coinpensalion', Proc. SPIE, 1997, 2552, pp.
644 652
RAMAKKISIINA, M.V.S., UAKUNASII<I, G., NliULIL. P., SKIDHAK. U,, illld
ZENG, w.J.: 'Highly sensitive inft.arcd teinpcriilirre sensor using self-
heating compensated microbolomcters', S e m Actciafurs, 2000, 79,
pp, 122-121
xu, Y P.: 'Mcthods and circuits for providing bolometer bias-
heating canccllation'. Patent Application No. 2000.03866-1,
Singapore, 11 July 2000
R A V I UIRAN, s., and KAIIUNASIIII,G.: 'Electro-thermal modclling of
infrared microemittcrs using PSPICE', Seiw. Acturrtors A , 1999, 72,
pp. 110-114
Design of 3:l multiplexer standard cell
P. Corsonello, S. Perri and V. K a n t a b u t r a
A new VLSl 3:1 niultiplexer is presented. The proposed circuit is
biiscd on a double controlled tri-slate buffer. A custom cell which
can easily be added lo the AMS 0.6pn CMOS standard cell
library has been developed. The new cell shows a propagation
delay of -7XOps and dissipates 5.2pW/MHz.
Introduction: Today thc standard cell dcsign style is the most I're-
quently used style [l] due to its lower time to markct in coinpari-
son with the full custom design style. Standard ccll libraries
contain several tcns of different logic gates with different fan-in
and fan-out capabilities. As is well known, multiplexing is one of
the most frequently used logic functions in any digital system.
However, the multiplexer cells included in the standard cell librar-
ies developcd by thc foundries usually have 2, 4 or 8 inputs. In
many cases, the designer needs multiplexers with different ran-in,
such as a 3:l multiplexer. Owing to the lack of this logic lunction
in conventional libraries, designers often have lo use the available
4 1 multiplexer cell or use cascaded 2:l multiplexers 121.
In this Letter, the design of a 3.1 multiplexer custom cell is pro-
posed. The new circuit is realised using double control tri-state
bufrers. Its propagation delay is significantly lower than that
which can be achieved using thc two alternative solutions men-
tioned above. The layout of the new multiplexer has bcen realised
taking into account the rules of the Austria Mikro Systenie (AMS)
O.6pnUn, 2-metal CMOS (CUB process) standard cell library 131. We
have tried addiiig the new cell to the library provided by the foun-
dry and havc found that it can be dircctly nscd in automated
place-and-route operations.
S
a b
Fig. 1 Existinfi mu1tipkxrr.s ririnfi tri-sfiite huffer.\
a 2-input
b 4-input
23rd November2000 Vol. 36 No. 24
Circuit itnplenientcition: In gcncral, a multiplexer allows one of N
inputs to be choscn for transmission to the output using M con-
trol bits. Multiplexers are usually realised using typical single coil-
trol tri-state invcrting buffers [4]. Fig. 1 shows schematic diagrams
of tri-slate buffer bascd 2- and 4-input multiplexers and thcir criti-
cal paths. These multiplexers requirc 12 and 28 transistors, respec-
tively. In both cases, the worst propagation delay occurs between
a selection input and an output signal. In particular, for the 4-
input multiplexer the critical path goes through one inverter and
two tri-state buffers, and Tor the 2-input niultiplexer it goes
through two invcrters and one tri-state buffcr. Thus when only 3-
inputs arc needed, using either a 4-input multiplexer or two cas-
caded 2-input multiplexers lcads to poor speed perforniance.
a
Fig. 2 flew circuit,y
rr 3: I multiplexer schemaiic diagram
h Doublc control tri-state buffer
We investigate the possibility of realising a 3 1 multiplexer
slandard cell using tri-state buffers without sigiiificaiitly varying
the critical path with respect to that of a 2-input multiplcxcr. The
new 3-input multiplexer schematic diagram is shown in Fig. 20.
The new innltiplcxer uscs two customdesigned double control tri-
state inverting buffers, illustrated in Fig. 211. Only 22 transistors
are required, thereby reducing thc transistor count by -20% in
comparison with the transistor count of the 4-input multiplexer
from the AMS standard cell library mentioned earlier. The critical
path of the new multiplexer comprises two inverters and onc doa-
ble control tri-state buffcr. Owing to the increased number or
transistors in scries, careful transistor sizing is necessary in order
to minimise the delay of a double control tri-state buffer of this
type.
The operation of the new circuit can bc describcd as follows:
when both select inputs arc forced low, buffer 1 is on, whereas
buffers 2 and 3 are tri-stated, leading to the transfer of input IO to
the output. When SO and S1 are forced low and high, rcspcctively,
burfer 3 transmits I2 to the output. Finally, i T S O is high, the II
input is transfcrrcd to the output independently by the status of
thc S1 control line.
.. . . . ... . , , ... .. . ... . , , ,
Fig. 3 Liiyout o j n e w .?-input ~nultiplesercell
VLSI itnplernentcrtionund r.esu1t.s:The new circuit was set up using
AMS 0 . 6 I-poly
~ 2-metal CMOS process parameters. To add
ELECTRONICS LETTERS 23rd November 2000
the new cell to the library provided by the foundry, AMS standard
cell design rules were taken into account. These rules requirc the
cell to be 38pn high, with 4pm high power rails. Therefore, the
space ;ivailable for the placement of the transistors forming the
circuit is 3Opm high. The layout of the new cell is illustrated in
Fig. 3. As can be easily seen, thc inputioutput ports werc carcfully
placed in the second metal layer. More spccifically we made sure
that each port had its free vertical routing channel in the metal-2
Iaycr so that it could be easily reached during the global routing
process. The cell is - 4 6 ~wide, but can bc further optimised,
thereby reducing the length of the interconnects. Multiple tub-ties
wcre used in order to prevent latch-ups. Post-layout simulations
were performed on thc extracted netlist with parasitics using
HSPICE. The propagation delays for all the possible input transi-
tions werc measured. using a 5V supply voltage, O.lpF load
capacitance and O.lns rise-fall times for the input signals. Our
simulation rcsults, summarised in Table 1, show that thc worst
propagation delay is -780ps, and that thc output signal rise and
fall times are 4KOps and 470ps, respectively. The AMS library's
4 1 multiplexer, under the same operating conditions, has a worst-
case delay of 1 .Om, and its output signal rises and falls in l . l n s
and 740ps, respectively. Cascaded 2 1 multiplexers exhibit almost
the same behaviour when simulated using HSPICE. (These data
agree with those on the AMS datasheet.) An average power dissi-
pation of -5.2pW/MHz was obtained using a test pattcrn covering
all the possible input combinations.
Table 1 Post-layout simulation results
Input transition Delay Input transition Delay
Pb 1,'
IOT-Q? 700 SO?-@ 660
IOL-QJ 1710 ISOJ-Q& 570
I
Conclusions; A new 3-input lnultiplcxer scheme has been pre-
sented. This multiplexcr represents a better solution to using a 4-
input multiplexer with two of the data inputs shorted together and
using two cascaded 2-input tnultiplexers. The method used here
can be generaliscd for use in the design of multiplexers with an
arbitrary number of inputs.
0 IEE 2000 17 Ocfuher 2000
Electronics Lefters Online Nn: 20001426
Dol: IO.1049/e1:200(11426
P. Corsonello (Departnient of Ciimnpter Science, Mntheinntics,
Electronics und Troinsportntioi~,University ojReggio Cnlcrhricr. Loc. Feu
di Vim, 89060 R e ~ g i oCalrrbrio, Itoly)
S . Pcrri (Deportment o f Electroiiic.7, Computer Science and Systems,
Univer.vifj~of Culoibrio, Arcovacata di Renrle, 87036, Renofe (CS), Italy)
V. Kdntabutra (College o j EngineerinR, Idaho State Universify,
Pocafello, lclfilw 83209, USA)
References
1 MORAES, I., TOKRES, I,., ROBERT, M., 2Uld AUVERGNE, D.: 'Estimation
of layout densities for CMOS digital circuits'. Proc. PATMOS '98
Conf., Denmark, Oct. 1998 (Iittp://www.il.dtu.dk/-ja11/pdtmos98/
webproceedings.htm1)
. 2 CORSONELLO. IW~RI. s.,
11.. and COCOKULLO, G.: 'VLSI
1793/31 implementation or a low-powcr high-speed self-timcd adder'. Proc.
IEEE PATMOS '00 Conf., Gcrmany, Sept. 2000, pp. 195-204
3 Austria Mikro Systcmc, Support Information Center, http://
iisic.vcrtical-globaI.cotni
4 UYEMURA, .I.P.: 'CMOS logic circuit dcsign' (Kluwer Academic,
1999)
Vol. 36 No. 24 1995