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INTEL INTERNSHIP PLACEMENT QUESTIONS

Intel came to VIT University on 15-06-2010 for internship recruitment. These are the
questions asked to SRIRAM KARTHIK SARIPELLA of M.Tech VLSI Design.

I tried to reproduce the maximum questions asked. I think these might be helpful
to boost your confidence…

1st Round (Only Technical)

1) Why did you choose VLSI as your specialization after your B.Tech (E.C.E)?

2) What are the subjects you have in your curriculum?

3) How do you decide the clock frequency of the given circuit?

Flipflop followed by combinational logic and again other flipflop in cascade

4) What are the violations you may have in the above circuit?

5) Why are setup and hold violations such important considerations in your
design?

6) What are different power losses that can occur in a CMOS circuit?

7) Which factor effects more in case of dynamic power loss?

8) If given a chance which factor would you like to alter to reduce dynamic
power loss?

9) Using mathematics which factor provides more reduction in power after it is


altered?

10) You said that mathematics is your favorite subject, so tell me what a
random process is and what is a random variable?

11) Give me an example of random process?

12) How does your vt depend on body bias?

13) always @(A)

begin

If (A)

B=C;

end

What logic does the synthesis tool infer?

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INTEL INTERNSHIP PLACEMENT QUESTIONS

14) Interviewer saw the papers of mine which were published and asked
me “What actually does this spurious power reduction technique do?”

15) Design an ex-or gate using mux?

16) What is FIFO?

17) Why is FIFO used?

18) What actually is the main intension behind using the FIFO?

19) How do you calculate depth of FIFO?

20) If there are setup violations in your design what will you do to get rid of
them?

21) If there are hold violations in your design what will you do to get rid of
them?

22) Assume there is a single memory and two processors need to make
use of the same memory, what circuit would you like to place as an interface
between processors and memory?

23) Do you have any questions for me?

24) What is difference between blocking and Non-blocking statement?

25) What are Incentia Time craft and Design craft? Why are these tools
used?

26) Explain the backend flow of an ASIC in detail?

27) What are the different files you need to include along with your verilog
code for obtaining netlist?

28) What does .lib file consist of?

29) What does .lef file consist of?

30) What is .ctsch?

31) What is difference between one-hot and binary encoding styles?

32) Which encoding style is advantageous and why?

33) What are the no. of flipflops required in different encoding styles?

34) What is .vcd file? What does it consist of?

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INTEL INTERNSHIP PLACEMENT QUESTIONS

35) What are the different files attached along with netlist to give to get
the timing analysis done?

36) What does .sdc and .sdf contain?

2nd Round (Technical + HR)

1) You have given a very broad range of areas of interest. If I place you in
testing using FPGA’s, will you work? What experience do you have in using
FPGA?

2) Did you work hands-on with FPGA?

3) Which FPGA kit did you use?

4) Did you do any projects on FPGA?

5) Explain the steps involved in dumping the code into FPGA?

6) Why do we compile a code?

7) What is the architecture of FPGA? What does an FPGA consist of?

8) What are CLB’s? How do they work?

9) What does programming the FPGA do?

10) Do we program the interconnects in FPGA?

11) Can you tell which logic can be used to work as CLB’s?

12) If read frequency of FIFO is 100 KHz and write frequency of FIFO is 10
KHz, what is depth of FIFO?

13) Did you ever come across a situation where in the total burden of work
is being placed on you? How did you manage to get over it?

14) Suppose you planned with your friend to go to a movie tonight and
manager then asked you to complete a given work by today night itself at
any cost, what will you do? Justify your answer?

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INTEL INTERNSHIP PLACEMENT QUESTIONS

15) If a professor gives you an assignment and due to fever you could not
complete the work, then do you think copying from your friend is a good idea,
to escape punishment?

16) If above case happens to your friend then will you allow him to copy
your assignment? (Assume professor is very strict).

17) Are you planning to pursue ph.d?

18) After getting into Intel if a very good college offers you ph.d and your
manager doesn’t allow you to go out of Intel for next 3months what will you
do?

19) You have any questions for me?

Ans: I asked about recent advances in Silicon Photonics (As I prepared a


study paper on it in B.Tech). Then I asked what would be my role as an intern
and what they expect from an intern.

3rd Round (Technical- Design oriented)

As this was my 3rd round HR said that he would be asking questions in depth.

1) Given a flipflop followed by and gate, or gate, ex-or gate and ex-nor gates in
cascade with one more flipflop. Given clock frequency is 250 MHz and the
clock frequency obtained by summing all delays is 350MHz. Now what will
you do to obtain the desired clock frequency?

2) What is slew?

3) Circuit: Flipflop followed by combinational logic and again other flipflop in


cascade

In this circuit if data input has a slew of 100ns instead of expected slew of
20ns, then how does this affect the setup and hold violations?

Explain with timing diagrams?

4) Design a 2:1 Mux using nmos and pmos? ( I first designed using pass
transistors )

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INTEL INTERNSHIP PLACEMENT QUESTIONS

5) Design a 2:1 Mux using static CMOS logic? Give the total transistor count?

6) Design 4:1 Mux using static CMOS logic and give the transistor count?

I answered almost all the questions………..

The results were given at 8:30 pm. Finally I made it…..Now I am going to be

a part of world’s largest semiconductor company ………….. INTEL. Hoping


to meet you there…

ALL THE BEST DUDES……

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