30-Apr-11 Digital to Analog Conversion

DIGITAL TO ANALOG CONVERTERS

In this section, we will discuss a number of methods of realizing DACs. We will study three main classes of DACs: decoder
based DACs, binary weighted DACs, thermometer code DACs.

Decoder based DACs

A typical decoder based DAC consists of a resistor string (acting as a voltage divider) that provides taps for the different
voltage levels for digital to analog data conversion. One of these voltage taps is selected by a decoder network to connect
appropriate voltage tap to the output node. An example of a 3 bit (8 level) DAC is shown in Figure 3.1

Figure 3.1 A 3 bit decoder based DAC using resitor-string and transmission gate decoder.

The decoding network consists of a number of transmission gates that form a switching network. The switching network is
connected in the form of a tree; only one low impedance path connecting one of the resistor string voltage tap point to the
output node exists. The advantage of using a transmission gate network is that the output voltage will operate at close to the
power supply voltage levels.

Instead of transmission gates, we can use a NMOS transistor based decoder; this results in reduced value of voltage swing at
the output node. However the speed of operation may not be severely diminished because of reduced amount of source and
drain capacitance because of the absence of the PMOS transistors. This reduced capacitance can offset for the increased
resistance due to the absence of pMOS transistors of the transmission gates.

The resistor string tap points ensure that monotonicity is maintained in the tapped voltage and therefore for the DAC. The
accuracy of the DAC depends on the matching of these resistors.

The delay through the decoding network determines the data conversion speed of the DAC. Each of the transmission gate
adds to the resistance of the decoding path and any low impedance path will have N transmission gates that are ON. The

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capacitive load consists of at the source and drain capacitances of nearly 3N transistors (2N from the transistors comprising
transmission gates and source/drain capacitance of N non switching transistors of the high impedance paths).

A higher speed implementation of the DAC is shown in Figure 3.2. It consists of an independent decoder that drives one of the
2N transistors that are connected to the resistive string divider. Although resistance of the switching network is reduced in this
approach, the capacitive load is increased because one end of all transmission gates is connected to the output node.

Fig 3.2 A resistor string DAC using a digital decoder network.

Binary weighted DACs

Since binary number system is used to represent the digital words, individual bits have binary weights depending on the
position of the bit within the digital word. If each bit contributes to a current equal to its binary weight, then a simple summing
amplifier can be used to convert a digital word to its analog value. This scheme is used in binary weighted DACs and we will
look into two different implementations. Although, the examples are illustrated using a resistive network, similar configuration
can be built using capacitive networks.

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Binary weighted resistor DAC

Fig 3.3. A binary weighted DAC implementation (4 bit)

A circuit schematic of a binary weighted DAC is given in Figure 3.3. When the value of the digital bits is a '1', the current
through the binary weighted resitance is diverted to flow through the feedback resistor, Rf; otherwise, the current flows directly
to ground.

The current flowing through the resistors in either position of the switch is constant.

I4 = Vref / 2R

I3 = Vref / 4R

I2 = Vref / 8R

I1 = Vref / 16

The output voltage due to the current flow in the feedback resistor is given as

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Setting the feedback resistor value to R, we get the negative value of the converted analog value of the digital input at the output
terminal of the op amp.

For example in the above circuit with Vref = 8 V; and with a digital input of 1001 results in an output voltage of -5 V.

The binary weighted DAC will be as accurate as the matching between different resistors used in the circuit. When the range of
component values of resistors is very large, it is very difficult to obtain good matching of resistors in an integrated circuit
implementations. For example, with a 10 bit binary weighted DAC, the range of values of resistors can vary by 3 orders of
magnitude. Therefore, binary weighted scheme can result in large mismatch errors.

The next implementation uses only two different values of resitors to obtain binary weighted currents.

R-2R Ladder DACs

A R-2R network is given in Figure 3.4. The network consists of resistors with values R and 2R only. Performing simple series
and parallel resistor reductions we can see that

R1 = R2 = R3 = R4 = 2R

R1' = R2' = R3' = R4' = R

Using voltage division principle recursively, we can show that

V4 = Vref: I4 = Vref / 2R

V3 = Vref / 2; I3 = Vref / 4R

V2 = Vref / 4; I2 = Vref / 8R

V1 = Vref / 8; I1 = Vref / 16R

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Therefore, we obtained similar currents flowing in the resistors as in the previous implementation using resitors of values R and
2R. SInce the values differ by a factor of 2, these resistors should match very well in integrated implementations.

Using a R- 2R network along with summing amplifier and CMOS transmission gate switches, it is possible to implement a
binary weighted DAC as given in Figure 3.5. Depending on the bit values of the input digital word, the binary weighted currents
either flow to the feedback resistor or to the ground. The currents flowing through the feedback resistor will contribute towards
the output voltage.

Thermometer code DACs

Glitches are a major limitation in decoder and binary-weighted converters. When the digital input values changes, it is possible
that some of the bit control signals may cause the switch controls to turn ON and/or OFF faster than other bits resulting in
glitches in the analog output signal values. In particular, if the MSB changes its value faster or slower than all other bits, it is
possible to have glitches of almost half of Vref. This problem ican be alleviated by the use of thermometr code type of
representation of the binary numbers. Although this coding scheme can result in potentially more circuit complexity, it has many
advantages such as guaranteed monotonicity, reduced glitching noise, and linearity.

A thermometer code representation is not an optimal implementation of binary values. For example to represent a 3 bit binary
number we require 7 bit of thermometer code values as given in the Table below.

Thermometer Code
Binary
Decimal d7 d6 d5 d4 d3 d2
b3 b2 b1
d1
0 0 0 0 0 0
0 0 0
0 0
1 0 0 1 0 0 0 0 0
0 1
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2 0 1 0 0 0 0 0 0
1 1
3 0 1 1 0 0 0 0 1
1 1
4 1 0 0 0 0 0 1 1
1 1
5 1 0 1 0 0 1 1 1
1 1
6 1 1 0 0 1 1 1 1
1 1
7 1 1 1 1 1 1 1 1
1 1

In a thermometer code, the number of 1s in the converted signal represent the decimal value. In a thermometer code based
DAC, the switching network consists of 2N -1 switches that have equal resistances and carry equal amounts of currents. The
current through these switches is conditionally directed wither into the feedback resistor of an op amp based summing circuit or
directly to the ground. Since the numbers of switches contributing to the current flow in the feedback resistor (1s in the
thermometer code) increase montonically with larger values of digital input, monotonicity is guaranteed. This DAC minimizes
the effects of glitches very much as compared to binary weighted approaches. A 3-bit DAC using thermometer code is given in
Figure 3.6.

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Figure 4.6. A thermometer code based DAC

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