Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-1

LECTURE 310 – OPEN-LOOP COMPARATORS

LECTURE ORGANIZATION
Outline
• Characterization of comparators
• Dominant pole, open-loop comparators
• Two-pole, open-loop comparators
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 439-461

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-2

CHARACTERIZATION OF COMPARATORS
What is a Comparator?
The comparator is a circuit that compares one analog signal with another analog signal
or a reference voltage and outputs a binary signal based on the comparison.
The comparator is basically a 1-bit analog-to-digital converter:

Reference Analog Comparator

1-Bit ADC
Voltage Input 1
1-Bit 1-Bit
Quantizer Encoder
Analog 1-Bit 1-Bit 1-Bit
Analog
Input Quantizer Encoder Digital
Input 2
Output
060808-01

Comparator symbol:
vP +
vO
vN -
Fig. 8.1-1

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-3

Noninverting and Inverting Comparators

The comparator output is binary with the two-level outputs defined as,
V OH = the high output of the comparator
V OL = the low level output of the comparator
Voltage transfer function of a Noninverting and Inverting Comparator:
vo vo
VOH VOH

vP-vN vP-vN

VOL VOL
Noninverting Comparator Inverting Comparator
Fig. 8.1-2A

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-4

Infinite Gain Comparator

Voltage transfer function curve:
vo
VOH

vP-vN

VOL Fig. 8.1-2

Model:
vP
+ +
vP-vN f0(vP-vN) vO
- -
vN
Comparator
VOH for (vP-vN) > 0
f0(vP-vN) =
VOL for (vP-vN) < 0 Fig. 8.1-3

V -V
lim OH OL
Gain = Av =
V where
V is the input voltage change

V  0

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-5

Finite Gain Comparator

Voltage transfer curve:
vo
VOH
VIL
vP-vN
VIH
VOL
Fig. 8.1-4

where for a noninverting comparator,

V IH = smallest input voltage at which the output voltage is VOH
V IL = largest input voltage at which the output voltage is VOL
Model:
vP
+ + V OH


VOL
vP-vN f1(vP-vN) vO The voltage gain is Av = V IH


VIL
- -
vN
Comparator
VOH for (vP-vN) > VIH
f1(vP-vN) = Av(vP-vN) for VIL< (vP-vN)<VIH
VOL for (vP-vN) < VIL Fig. 8.1-5

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-6

Input Offset Voltage of a Comparator

Voltage transfer curve:
vo
VOS VOH
VIL
vP-vN
VIH
VOL Fig. 8.1-6

V OH+VOL
V OS = the input voltage necessary to make the output equal 2 when vP = vN.
Model:
vP
+vP' +
±VOSv '-v ' f1(vP'-vN') vO
P N
-v ' -
vN N
Comparator Fig. 8.1-7
Other aspects of the model:
ICMR = input common mode voltage range (all transistors remain in saturation)
Rin = input differential resistance
Ricm = common mode input resistance
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-7

;;
Comparator Noise
Noise of a comparator is modeled as if the comparator were biased in the transition
region.
vo
VOH
Rms Noise
vP-vN

VOL
Transition Uncertainty Fig. 8.1-8

Noise leads to an uncertainty in the transition region causing jitter or phase noise.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-8

Input Common Mode Range

Because the input is analog and normally differential, the input common mode range of
the comparator is also important.
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary
without influence the differential performance
As we have seen before, the ICMR is defined by the common-mode voltage range over
which all MOSFETs remain in the saturation region.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-9

Propagation Delay Time

Rising propagation delay time:
vo
VOH
V +V
vo = OH OL
2 t
VOL
vi = vP-vN
VIH
V +V
tpr vi = IH IL tpf
2
t
VIL
070509-01

Rising
propagation
delay
time
+
Falling
propagation
delay
time
Propagation delay time = 2
tpr
+
tpf
= 2

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-10

Linear Frequency Response – Dominant Single-Pole

Model:
Av(0) Av(0)
Av(s) = s = s
c+1
c
+
1
where
Av(0) = dc voltage gain of the comparator
1
c =
c = -3dB frequency of the comparator or the magnitude of the pole
Step Response:
vo(t) = Av(0) [1 - e-t/
c]V in
where
V in = the magnitude of the step input.
Maximum slope of the step response:

dvo(t) Av(0)
-t/

dt =
c e cV in
The maximum slope occurs at t = 0 giving,

dvo(t) | Av(0)
dt t=0 =
c Vin
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-11

Propagation Time Delay

The rising propagation time delay for a single-pole comparator is:
V OH-V OL  1 
-t / 
= A (0) [1 - e V OH
-V OL
p c]V
t =  ln
2 v in p c

1
-
2Av(0)Vin 
Define the minimum input voltage to the comparator as,
V OH
-VOL  1 
V in(min) = A (0)
tp = c ln  V (min)
v  in 
1-
2Vin 
Define k as the ratio, Vin, to the minimum input voltage, Vin(min),
V in  2k 
 
k = V in(min)
tp = c ln 2k-1
Thus, if k = 1, tp = 0.693c.
Illustration: vout
Vin > Vin(min)
VOH
Obviously, the more overdrive vout VOH+VOL
applied to the input, the smaller vin +
2
the propagation delay time. - VOL Vin = Vin(min)
0 t t (max) t
0 p p Fig. 8.1-10

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-12

Dynamic Characteristics - Slew Rate of a Comparator

If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by
the slew rate.
Slew rate comes from the relationship,
dv
i = C dt
where i is the current through a capacitor and v is the voltage across it.
If the current becomes limited, then the voltage rate becomes limited.
Therefore for a comparator that is slew rate limited we have,

V V OH-
V OL
tp =
T = SR = 2·SR
where
SR = slew rate of the comparator.
If SR < |maximum slope|, then the comparator is slewing.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-13

Example 310-1 - Propagation Delay Time of a Comparator

Find the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/μs, and a binary output voltage
swing of 1V. Assume the applied input voltage is 10mV.
Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV
input is 100 times larger than vin(min) giving a k of 100. Therefore, we get
1
 2·100 
200
 
tp = 103 ln2·100-1 = 10-3 ln199 = 5.01μs
For slew rate considerations, we get
104
Maximum slope = -3 ·10mV = 105 V/sec. = 0.1V/μs.
10
Therefore, the propagation delay time for this case is limited by the linear response and is
5.01μs.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-14

DOMINANT POLE, OPEN-LOOP COMPARATORS

Dominant Pole Comparators
Any of the self-compensated op amps provide a straight-forward implementation of an
open loop comparator without any modification.
The previous characterization gives the relationships for:
1.) The static characteristics
• Gain
• Input offset
• Noise
2.) The dynamic characteristics
• Linear frequency response
• Slew rate response

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-15

Single-Stage Dominant Pole Comparator

VDD
M3 M4

VPBias2
MC3 MC4 vo

CL
MC1 MC2
vp M1 M2 v
VBias n

-
+ M5
VNBias1
-
060808-02

• Gain  gm2rds2
• Slew rate = I5/CL
• Dominant pole = -1/(RoutCL) = -1/(gmrds2CL)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-16

Folded-Cascode Comparator
VDD
VPB1

M4 M5

VPB2

M6 vOUT
vP M7
M1 M2 VNB2
M8 M9 CL
vN
M3
VNB1 I3 M11
M10

060808-03

• Gain  gm2rds2
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL)  -1/(gmrds2CL)
• Slightly improved ICMR

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-17

Enhanced-Gain, Folded-Cascode Comparator

VDD

M10 M11
VPB1 M3
vP -A

M8 M9
vOUT
vN M1 M2
M6 M7 CL
-A -A

VNB1 M4
M5

060808-04

• Gain  gm1Rout
• Rout  [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11)
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-18

TWO-POLE, OPEN-LOOP COMPARATORS

Two-Stage Comparator
The two-stage op amp without compensation is an excellent implementation of a
high-gain, open-loop comparator.
VDD

M3 M4
M6
vn vout
M1 M2
vp CL
+ M7
VNB1 M5
-
060808-05

• Much faster linear response – the two poles of the comparator are typically much larger
than the dominant pole of the self-compensated type of comparator.
• Be careful not to close the loop because the amplifier is uncompensated.
I7 I6-I7
• Slew rate: SR- = CII and SR+ = CII

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-19

Performance of the Two-Stage, Open-Loop Comparator

We know the performance should be similar to the uncompensated two-stage op amp.
Emphasis on comparator performance:
• Maximum output voltage
 8I7 

V OH = VDD - (VDD-V G6(min)-|VTP|)1
-
1
-

(V -V (min)-|V |)2

6 DD G6 TP
• Minimum output voltage
V OL = VSS
• Small-signal voltage gain


gm1 
gm6 
Av(0) =
g +g 
g +g 
ds2 ds4 ds6 ds7
• Poles
Input: Output:
-(gds2+gds4) -(gds6+gds7)
p1 = CI p2 = CII
• Frequency response
Av(0)
Av(s) = 
s  

s 

 p1

-
1 p2
-
1


CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-20

Example 310-1 - Performance of a Two-Stage Comparator

Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, VDD = 2.5V
for the two-stage comparator shown. The 15µm
M3 M4
15µm
M6
94µm
large signal model parameters are KN’ = 1µm 1µm 1µm
2 2
110μA/V , KP’ = 50μA/V , VTN = |VTP| = 30µA vout
M1 M2 CI = 0.2pF
3µm 3µm CII = 5p
0.7V,
N = 0.04V-1 and
P = 0.05V-1. -
vin
1µm 1µm
95µA
Assume that the minimum value of VG6 = +
30µA
0V and that CI = 0.2pF and CII = 5pF. 4.5µm 14µm
1µm 4.5µm 1µm
M5
Solution M8 1µm M7
VSS = -2.5V 070509-02

Using the above relations, we find that

 8·234x10-6 

V OH = 2.5 - (2.5-0-0.7) 1
-
1
-
50x10-6·38(2.5-0-0.7)2
 = 2.2V
V OL is -2.5V. The gain can be found as Av (0) = 7696. Therefore, the input resolution is
V in(min) = (VOH-V OL/Av (0) = 4.7V/7,696 = 0.611mV
Next, we find the poles of the comparator, p1 and p2.
p1 = -(gds2 + gds4)/CI = 15x10-6(0.04+0.05)/0.2x10-12 = -6.75x106 (1.074MHz)
and
p2 = -(gds6 + gds7)/CII) =(95x10-6)(0.04+0.05)/5x10-12 = -1.71x106 (0.272MHz)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-21

Linear Step Response of the Two-Stage Comparator

The step response of a circuit with two real poles (p1
p2) is,

p2etp1 p1etp2 
vout(t) = Av(0)V 1
+
p -p
-
p -p  
in
1 2 1 2
Normalizing gives,
vout(t) m 1 p2
vout’(tn ) = Av(0)Vin = 1 - m-1e-tn + m-1e-mtn where m = p1
1 and tn = -tp1
If p1 = p2 (m =1), then vout’(tn) = 1 - etp1 + tp1etp1 = 1 - e-tn - tne-tn
1
m=4
Normalized Output Voltage

0.8
m=2 m = 1 m = 0.5
m = 0.25
0.6

0.4
p2
m= p
1
0.2

0
0 2 4 6 8 10
Normalized Time (tn = -tp1 ) Fig. 8.2-2

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-22

Linear Step Response of the Two-Stage Comparator - Continued

The above results are valid as long as the slope of the linear response does not exceed the
slew rate.
• Slope at t = 0 is zero
• Maximum slope occurs at (m
1)
ln(m)
tn(max) = m-1
and is
dvout’(tn(max)) m  -ln(m) 
 ln(m) 
dtn =  exp
m-1  m-1

-
exp -m
 m-1

• For the two-stage comparator using NMOS input transistors, the slew rate is
I7
SR- = CII

I6-I7 0.56(VDD-V G6(min)-|VTP|)2
-
I7

+
SR = CII = CII

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-23

Example 310-2 - Step Response of Ex. 310-1

Find the maximum slope of Ex. 310-1 and the time it occurs if the magnitude of the
input step is v in(min). If the dc bias current in M7 is 100μA, at what value of load
capacitance, CL would the transient response become slew limited? If the magnitude of
the input step is 100vin(min), what is the new value of CL at which slewing would occur?
Solution
The poles of the comparator were given in Ex. 310-1 as p1 = -6.75x106 rads/sec. and
p2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous expressions,
the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p 1| gives t(max) =
0.272μs. The slope of the transient response at this time is found as
dvout’(tn(max))
dtn = -0.338[exp(-1.84) - exp(-0.253·1.84)] = 0.159 V/sec
Multiplying the above by |p1| gives dvout’(t(max))/dt = 1.072V/μs. If the slew rate is less
than 1.072V/μs, the transient response will experience slewing. Therefore, if CL

100μA/1.072V/μs or 93.3pF, the comparator will slew.
If the input is 100vin(min), then we must unnormalize the output slope as follows.
dvout’(t(max)) vin dvout’(t(max))
dt = vin(min) dt = 100·1.072V/μs = 107.2V/μs
Therefore, the comparator will slew with a load capacitance greater than 0.933pF.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-24

Propagation Delay Time (Non-Slew)

To find tp, we want to set 0.5(VOH-V OL) equal to vout(tn). However, vout(tn) given as

 m 1 

vout(tn) = Av(0)Vin 1
-
m-1e n
+
m-1e n 
 -t -mt

can’t be easily solved so approximate the step response as a power series to get
   
 m
tn2  1
m2tn2  mtn2Av(0)Vin
vout(tn)
Av(0)Vin1
-
m-1
1-tn+
2
+
···
+
m-1
1-mtn+
2
+··· 
2
Therefore, set vout(tn) = 0.5(VOH-V OL)
V OH-V OL mtpn2Av(0)Vin
2
2
or
V OH-V OLV in(min) 1
tpn
mAv(0)Vin =mVin =
mk
This approximation is particularly good for large values of k.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-25

Example 310-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)

Find the propagation time delay of Ex. 310-1 if Vin = 10mV, 100mV and 1V.
Solution
From Ex. 310-1 we know
that Vin(min) = 0.611mV and m 1
= 0.253. For Vin = 10mV, k = m=4
16.366 which gives tpn
0.491.

Normalized Output Voltage

0.8
m=2 m = 1 m = 0.5
The propagation time delay is m = 0.25
equal to 0.491/6.75x106 or 0.6
72.9nS. This corresponds well
with the figure shown where 0.4
the normalized propagation p2
time delay is the time at which m= p
1
the amplitude is 1/2k or 0.031 0.2
which corresponds to tpn of 1
approximately 0.5. Similarly, 2k = 0.0310
for Vin = 100mV and 1V we get 0 2 4 6 8 10
0.52 Normalized Time (tn = tp1 = t/τ1)
a propagation time delay of tp = 0.52 = 77ns
6.75x106 Fig. 8.2-2A
23ns and 7.3ns, respectively.

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-26

Initial Operating States for the Two-Stage, Open-Loop Comparator

What are the initial operating states for the two-stage, open-loop comparator? The
following table summarizes the results for the two-stage, open-loop comparator shown.
Conditions Initial State of vo1 Initial State of vout
vG1>VG2, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS
vG1>>VG2, i1=ISS and i2=0 VDD VSS
vG1<VG2, i1>0 and i2<ISS vo1=VG2-VGS2,act(ISS/2),
VSS if M5 act. VOH see equation below tabl
vG1<<VG2, i1>0 and i2<ISS VSS VOH see equation below tabl
vG2>VG1, i1>0 and i2<ISS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) VOH see equation below tabl
vG2>>VG1, i1>0 and i2<ISS VG1-VGS1(ISS/2) ,
VSS if M5 active VOH see equation below tabl
vG2<VG1, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS
vG2<<VG1, i1=ISS and i2=0 VDD VSS

VDD
VOH = VDD – (VDD-VG6(min)-|VTP|)
i3 i4
 8I7  M3 M4 vo1
x1
-
1
-


CI
M6
 6(VDD-VG6(min)-|VTP|)2  i1 i2
vout
vG1 M1 M2 vG2
CII
ISS
+ M7
VBias M5
-
VSS Fig. 8.2-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-27

Trip Point of an Inverter

VDD
In order to determine the propagation delay time, it is
necessary to know when the second stage of the two-stage M6
+
comparator begins to “turn on”. vin i6
- vout
Second stage:
i7
M7
Trip point: VBias
Assume that M6 and M7 are saturated. (We know that the
VSS Fig. 8.2-4
steepest slope occurs for this condition.)
Equate i6 to i7 and solve for vin which becomes the trip point.
KN(W 7/L7)

vin = VTRP = VDD - |VTP| - KP(W 6/L6) (VBias- VSS -VTN)
Example:
If W7/L7 = W 6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the
circuit above is
V TRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-28

Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator

Previously we calculated the propagation delay time for a nonslewing comparator.
If the comparator slews, then the propagation delay time is found from
dvi
vi
ii = Ci dti = Ci
ti
where
Ci is the capacitance to ground at the output of the i-th stage
The propagation delay time of the i-th stage is,

Vi
ti =
ti = Ci Ii
The propagation delay time is found by summing the delays of each stage.
tp = t1 + t2 + t3 + ···

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-29

Example 310-4 - Propagation Time Delay of a Two-Stage, Open-Loop Comparator

For the two-stage comparator shown VDD = 2.5V
assume that C I = 0.2pF and C II = 5pF. 4.5μm
M3 M4
4.5μm
M6
38μm
Also, assume that vG1 = 0V and that vG2 1μm 1μm 1μm
vo1
has the waveform shown. If the input vout
voltage is large enough to cause slew to 30μA vG1 M1 3μm M2 CI =
dominate, find the propagation time delay 3μm 0.2pF CII =
1μm 1μm 5pF
of the rising and falling output of the vG2
comparator and give the propagation time 234μA
delay of the comparator. 4.5μm
30μA
35μm
vG2 1μm 4.5μm 1μm
M8 M5 1μm M7
2.5V
VSS = -2.5V Fig. 8.2-5A
0V 0.2 0.4 t(μs)
0 0.6
-2.5V Fig. 8.2-5

Solution
1.) Total delay = sum of the first and second stage delays, t1 and t2
2.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2μs.
The last row of table on Slide 310-28 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI,
Vo1, and I5. CI = 0.2pF, I5 = 30μA and
V1 can be calculated by
finding the trip point of the output stage.
CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-30

Example 310-4 - Continued

4.) The trip point of the output stage by setting the current of M6 when saturated equal
to 234μA.
6 234·2
2 (VSG6-|VTP|)2 = 234μA  VSG6 = 0.7 + 50·38 = 1.196V
Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V
Therefore, V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation time
delay of the first stage is
 1.196V

tfo1 = 0.2pF  30μA

 = 8 ns
5.) The rising propagation time delay of the second stage requires CII, Vout, and I6. CII
is given as 5pF,  V out = 2.5V (assuming the trip point of the circuit connected to the
output of the comparator is 0V), and I6 can be found as follows:
V G6(guess)
0.5[VG6(I6=234μA) + VG6(min)]
2·15
V G6(min) = VG1 - VGS1(ISS/2) + VDS2
-VGS1(ISS/2) = -0.7 - 110·3 = -1.00V
V G6(guess)
0.5(1.304V-1.00V) = 0.152V
6 38·50
Therefore VSG6 = 2.348V and I6 = 2 (VSG6-|VTP|)2 = 2 (2.348 - 0.7)2 = 2,580μA
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-31

Example 310-4 - Continued

6.) The rising propagation time delay for the output can expressed as

 2.5V 

trout = 5pF 2580μA-234μA = 5.3 ns
Thus the total propagation time delay of the rising output of the comparator is
approximately 13.3 ns and most of this delay is attributable to the first stage.
7.) Next consider the change of vG2 from 2.5V to -2.5V at 0.4μs. We shall assume that
vG2 has been at 2.5V long enough for the conditions of the table on Slide 310-28 to be
valid. Therefore, vo1
V SS = -2.5V and vout
V DD. The propagation time delays for the
first and second stages are calculated as
 1.304V-(-1.00V) 3V
  vout
tro1 = 0.2pF 
30μA  = 15.4 ns

2V
VTRP6 = 1.304V
2.5V 


tfout = 5pF 234μA = 53.42ns

 1V

8.) The total propagation time delay of the 0V

falling output is 68.82 ns. Taking the vo1
average of the rising and falling propagation -1V
time delays gives a propagation time delay Falling prop.
-2V
for this two-stage, open-loop comparator of Rising prop. delay time
about 41.06ns. -3V
delay time
200ns 300ns 400ns 500ns 600ns
Time Fig. 8.2-6
CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-32

SUMMARY
• The two-stage, open-loop comparator has two poles which should as large as possible
• The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate
• It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time
• If the comparator is gainbandwidth limited then the poles should be as large as possible
for minimum propagation delay time
• If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible

CMOS Analog Circuit Design © P.E. Allen - 2010