5/13/09

All Levels of Review

1. Part and Rev numbers must be accurate

Schematic Review
1. What can go wrong?
2. No floating nets, All nets must be connected
3. No DRC Errors
4. Appropriate labels/comments
a. Accuracy
5. μP, μC or FPGA can be programmed?
6. Pinout correct for new parts
7. Decoupling cap & recommendations
8. Program pins correct
9. Sufficient Current ratings for power components

Layout
1. New/Modified Footprint accuracy
2. Follow ALL layout notes from schematics (green text)
3. Check for recommend layout notes from manuf. for all actives
4. Optimize layout to reduce manufacturing costs
5. Sensitive traces are isolated (Clocks, Analog, Etc…)
a. Optimal Copen placement for reference clocks
6. Power & Ground
a. Connect all ground traces to a solid plane
b. Sufficient Cu for major power traces, especially long traces
c. All supply/GND pins should have their own via, space permitting
7. GND Island connection: 0Ω resistors
a. Place Vias near both sides of 0Ω
b. Optimal placement: under components
c. Comprehensive placement across entire GND border
8. Impedance
a. Verify all Z matched Cu dimensions match document
b. Aim for 1 or 2Ω less for single ended and differential traces respectively
c. Make all Z match traces as wide as possible while maintaining a sym stackup
d. Z Diff traces, always use 5mil separation
e. Generate up to date Z calculations document with Z screenshots and stackup
9. Minimize total DRC errors
a. No different net DRCs
b. Same net DRCs only if necessary
c. Component Overlap not caught by DRC (place space error)
d. Check for shorts between copper pours
10. Drill symbols
a. Consolidate similar drill hole sizes, verify compatibility
b. Each hole/slot has a unique symbol
c. Each hole/slot is represented in drill legend
11. At least two Cu connections for each thermal relief
12. Labeling and Silk Screen
a. MSS logo & Part # in Bottom Cu (preferred) or SSB
b. Reference Designator
i. Accurate Placement: adjacent to part
ii. No obstructions (i.e. over hole, solder mask or under part, etc.)
c. ComBlock.com
d. Label corner pins A1, B1, etc on all 40/12 pin connectors
i. Add “B10” pin label on 40 pin connectors if room
e. COM-XXXX model # (when applicable)
f. Label other connectors (when applicable)
g. Label corner pin number of large non-BGA ICs
h. Label max dBm value of analog inputs (when applicable)
i. For Revision 0 only: renumber, back-annotate and recheck SS
13. BGA Vias must be centered between balls
14. Mounting / Non Plated Thru Holes: define SM for drill hole region (no additional clearance required)
Layout Dimensions
1. Pad / Etch clearance to edge ≥ 1 mm/40mils, 50mil+ preferred
a. Exception: 12 pin edge connector
b. Ceramic Caps and ICs indirectly: ≥ 200 mils when possible (see AVX app note)
2. FP Clearances
a. PBT oversize = 1 mm total, 0.5 mm each side
b. PBT oversize for connectors = 2 mm total, 1 mm each side
c. Via void oversize inside Ex. Pad = 5 mil over via drill size
d. SMT to SMT and SPT to SPT clearance ≥ 0.15mm/6mil
3. SS Label Text Sizes, in mils
a. Absolute minimum: 30x20
b. Non-Passive Ref Des, Pin numbers: ≥40x25
c. Terminal Block Voltages, COM-# and CB.com: ≥80x50
d. Test Pts. and all other text: ≥50x30
4. Via dimensions, Pad x Drill hole size (mils)
a. Absolute minimum: 20x10 / Standard: 24x12 / Power: ≥ 24 drill
b. Pad oversize for all plated holes: ≥15 mil (10 minimum) annular ring

Readme
1. Correct Hole #
a. Circular
b. Slots
2. Pre-preg thickness has top to bottom symmetry
3. Stack up thickness adds up to desired board thickness, typically 62 mils
4. Accurate width and spacing specified
5. File listing accuracy
6. Board dimensions
7. Correct layer listing
8. Layer numbering

BOM
1. No Duplicate parts
2. Parts that can be consolidated same/close value but different line
3. All Pb-Free?
4. Do Not Populate, DNP section
5. Part Properties are accurate & complete
a. Value: complete orderable part number
b. Spec: list all PCRs and mark preferred p/n