A Novel Leakage Power Reduction Technique for CMOS Circuit Design

Jae Woong Chun and C. Y. Roger Chen

Department of Electrical Engineering and Computer Science Syracuse University Syracuse, NY 13244, USA jchun02@syr.edu, crchen@syr.edu

Abstract Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground. We investigate the characteristics of proposed gate types in terms of ability to reduce power consumption and their associated delay overhead. In addition, several variations of drain gating are discussed. In the end, an overall procedure for low-power circuit design is proposed by intelligently mixing various proposed circuit types for gates in the circuits based upon gate criticality analysis. Extensive SPICE simulation results were reported using 45nm, 32nm and 22nm process technologies. Significant power reduction is achieved with zero or little increase in the critical path delay of the overall circuits. Keywords- leakage power consumption, sleep transistors, transistor stacking, low-power design

the next decade [1]. In this paper, we will first conduct experimental investigations on previously proposed techniques for reducing leakage power consumption using 45nm, 32nm and 22nm process technologies and point out the potential problems with them. Next, we propose a family of low-power circuits and conduct experimental investigations on the property of propagation delay and power consumption for each member in the proposed circuit family. Finally, a design procedure is proposed by mixing the various circuit types in the proposed circuit family in a single circuit design. The rest of paper is organized as follows. In Section II previous work regarding existing leakage power reduction techniques is discussed. In Section III the drain gating technique and its variations are described. In Section IV, experimental results of the drain gating technique and its various are presented, followed by a description of the proposed overall low-power circuit design procedure utilizing the proposed family of circuit types for reducing leakage power consumption. Finally, Section V concludes the paper. II. RELATED WORK

I.

INTRODUCTION

As technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry. Energy per operation continues to improve with process and supply voltage scaling because dynamic power is approximately proportional to the square of supply voltage as well as proportional to capacitances of device. Despite the use of a lower supply voltage, total power consumption is increasing in every technology generation because dynamic power consumption increases due to higher operating frequencies and higher transistor density while leakage power consumption increases exponentially due to reduced gate length, oxide thickness and threshold voltage, and higher transistor density. Therefore, the percentage of power consumption due to leakage current continues to grow; leakage power consumption will eventually overwhelm the dynamic power consumption within a few generations. The international technology roadmap for semiconductors (ITRS) identified leakage power consumption as a clear long-term threat to design technology in

In this section, we briefly review existing leakage power reduction techniques. Power gating [3][8] technique uses additional transistors, called sleep transistors, which are inserted in series between the power supply and pull-up (PMOS) network and/or between pull-down (NMOS) network and ground to reduce the standby leakage currents. The sleep transistors are turned on when circuits are in active mode and turned off when circuits are in standby mode. By disconnecting the logic networks from the power supply and/or ground using sleep transistors, this technique reduces the leakage power in standby mode. Power gating technique can also involve multithreshold-voltage CMOS (MTCMOS) [9], which uses high-threshold devices as sleep transistors while low-threshold devices are used to implement the logic. Dual threshold voltage CMOS technique [7] assigned different threshold voltages depending on whether a gate is on critical or non-critical path. Low threshold voltage on the critical path is used to maintain the performance, while high threshold voltage assigned along non-critical path reduces the leakage current. Stacking of series-connected transistors reduces the subthreshold leakage currents when more than one transistor in the stack is turned off. This effect is known as stacking effect [10].

978-1-4244-8631-1/10/$26.00 2010 IEEE

- 119 -

ISOCC 2010

Figure 1. (a) Original Two-input NAND Gate. (b) LECTOR NAND Gate. (c) GALEOR NAND Gate. (d) Drain Gating NAND Gate.

Forced stacking [5] yields the stacking effect by inserting extra transistor for every input of the gate in both NMOS and PMOS networks. Hence, forced stacking guarantees two offtransistors for every OFF-input of the gate, which reduces leakage currents. This technique, however, reduces the drive current significantly, thereby greatly increasing the delay, since number of transistors is doubled compared to the original one. Sleepy stack technique [4] is an upgrade version of the forced stack, using additional sleep transistor inserted parallel to one of the transistors in each set of two stacked transistors (forced stack). The sleep transistors of the sleepy stack operate in a way similar to the sleep transistors used in the sleep transistor technique where sleep transistors are turned on during active mode and turned off during sleep mode. As compared to the forced stack technique, parallel connected sleep transistors cause the decrease in resistance of the path, thereby decreasing the propagation delay during active mode while stacked transistors suppress leakage current during standby mode. Sleepy stack technique, however, comes with some delay and significant area overheads since every transistor is replaced by three transistors. Another technique to reduce leakage power is LECTOR [2], which uses two extra transistors called leakage control transistors (LCTs ) inserted in series between pull-up network and pull- down network in each CMOS gate as shown in Fig. 1(b). Leakage control transistors cause increase in resistance of the path from Vdd to ground since one of the LCTs is always near its cutoff region, thereby decreasing leakage current. GALEOR technique [11] has the same structure as LECTOR except that the locations of extra transistors (referred to as Gated Leakage Transistors (GLTs) ) are switched as shown in Fig. 1(c). PMOS GLT is located between pull-down network and output and NMOS GLT is located between pull-up network and output. However, when applied to sub-45nm process technologies (such as Predictive Technology Model (PTM) [6]), both LECTOR and GALEOR suffer a significant problem, that is, the low signal is very much higher than 0 volt. In addition, GALEOR causes high signal much lower than the Vdd. Such phenomena can make the use of both techniques unfeasible. A typical case for a 2-input NAND gate using 45nm technology is shown in Fig. 2, where the low signal is 0.2V for both LECTOR and GALEOR, and the high signal for GALEOR is 0.8V, rather than 0V and 1V, respectively.

Figure 2. Transient characteristics of two-input LECTOR, GALEOR and Drain Gating simulated by HSPICE.

Similar troubling behaviors are consistently observed for all other gate types such as NOR, OR, AND, XOR. To make things worse, the problems become even more severe as process technology scales down such as in 32nm and 22nm process technologies. The proposed circuit family, which will be described in the next section, is capable of maintain the original signal quality and avoiding the problem. For example, we have included one of them (i.e., drain gating) in Fig. 2. III. DRAIN GATING TECHNIQUE AND ITS VARIATIONS

In this section, we introduce a new family of leakage power reduction technique for CMOS circuit design; none of them suffers the signal quality problems associated with LECTOR and GALEOR as reported in Section II. For explanation purpose, we describe one circuit type in the proposed family called drain gating here. It reduces the leakage current by inserting extra sleep transistors between pull-up and pull-down networks. As shown in Fig. 1(d), a PMOS sleep transistor (S) is placed between pull-up network and network output and an NMOS sleep transistor(S) is placed between network output and pull-down network. During active mode, both sleep transistors are turned on to reduce the resistance of conducting paths, thereby reducing performance degradation. During standby mode, both sleep transistors are turned off to produce stacking effect which reduces leakage current by increasing resistance of the path from power supply to ground. By applying two turned-on sleep transistors in active mode, drain gating produces exact logic levels due to less resistance of the path from Vdd to ground than LECTOR and GALEOR which always have one turned-on LCT/GLT and the other near cutoff region LCT/GLT, thus preventing exact logic state. Furthermore, the proposed drain gating technique has less leakage current than LECTOR and GALEOR techniques because, in standby mode, two turned-off sleep transistors (drain gating) yield more resistance to the path from Vdd to ground than the combined effect of a near cutoff region LCT/GLT and a turned-on LCT/GLT; this is shown in Table I.

- 120 -

ISOCC 2010

TABLE I.

LEAKAGE POWER OF TWO INPUT NAND GATE

Savings (%)

TABLE II. Technology Process 45nm 32nm 22nm

THRESHOLD VOLTAGE OF PTM MODELS (VDD = 1V) Zero-Bias Threshold (Vth0) NMOS PMOS 0.3423V -0.2312V 0.3558V -0.2412V 0.3692V -0.2540V Threshold (Vth) NMOS PMOS 0.2581V -0.2311V 0.2475V -0.2395V 0.2326V -0.2490V

45nm Process Technology, Supply Voltage = 1V NAND Leakage Power (W) of Input Vector gate type (0,0) (0,1) (1,0) (1,1) 1.79E-07 1.50E-07 1.0E-07 2.51E-07 Original 1.75E-07 1.37E-07 1.02E-07 1.88E-07 Lector 1.76E-07 1.36E-07 1.02E-07 1.56E-07 Galeor 1.66E-07 1.29E-07 9.40E-08 1.11E-07 Drain gating

11.53 16.16 26.54

IV.

Simulations were conducted on various gates and propagation delay, dynamic power and leakage power measured by Synopsys HSPICE simulator. Three different process technologies (45nm, 32nm and 22nm) from latest version (2.0) of PTM [6] were used in HSPICE simulations. The threshold voltages used by the technologies are shown in Table II. 1V supply voltage and single-Vth technology for each technology were used in simulation. Sizes of existing transistors are set to W/L=3, P/N=2 during simulation except sleepy stack which is set to be W/L=1.5 with same P/N=2. In order to make a fair comparison, transistor sizes of extra transistors (LCTs, GLTs and sleep transistors) are set to the same W/L=1, P/N=2 ratio except GALEOR and sleepy stack techniques. GLTs are set to W/L=1, N/P=2 since NMOS-GLT is located in PMOS network and PMOS-GLT is located in NMOS network. Sleep transistors of sleepy stack are set to the same as that of existing transistor W/L=1.5, P/N=2 since each sleep transistor connected parallel to existing one. With technology scaling down, the drain gating creates more power savings (%) in both leakage and dynamic power as shown in Fig. 3 and Fig. 4 respectively. In between power gating and drain gating, there are two mixed techniques power gating on PMOS and drain gating on NMOS, and its the opposite. They are referred to as DFPH and DHPF respectively and will be descried in Section IV.

THE PROPOSED LOWER-POWER DESIGN PROCEDURE AND EXPERIMENTAL RESULTS

The proposed drain gating technique and its variations were tested on various gates and compared to other sleep transistor based approaches, including sleepy stack and power gating as shown in Fig 5(b). The two variations of drain gating are called Drain Header Power Footer (DHPF) gating and Drain Footer Power Header (DFPH) gating as shown in Fig. 5(c) and Fig.5(d) respectively. In addition, single sleep transistor power/drain gating (Drain Header, Drain Footer, Power Header and Power Footer) was also tested; only one sleep transistor applied to existing circuit (either PMOS or NMOS network). Simulation settings are same as described in Section III. Figures 6, 7 and 8 show the experimental results. Analysis of the results shows that drain header gating technique has the least propagation delay, while the power gating has the best savings in leakage power reduction due to the location of sleep transistors which are located outsides the network, thereby creating more stacking effect. For example, for a two-input NAND gate in standby mode, power gating NMOS network is set to (XX)0 while drain gating is set to 0(XX), where (XX) stands for input vectors (00,01,10,11). Comparison between dual gating (power/drain gating) and single gating (footer or header only) technique shows that dual gating technique has better results for leakage reduction while single gating technique has better results for propagation delay; this is shown in Table III. Analysis of location of sleep transistor presents that header gating saves more power (both dynamic and leakage power) than footer gating while footer gating has better results for propagation delay. In summary, drain gating achieves up to 53% power consumption while suffering up to 50% propagation delay. Power gating can reduce up to 83% power consumption, which suffering up to 400% propagation delay. DFPH and DHPF however have a behavior between the aforementioned two.

Figure 3. Leakage Power Savings (%) by using Drain Gating.

Figure 4. Dynamic Power Savings (%) by using Drain Gating.

Figure 5. (a) Drain Gating. (b) Power Gating (c) Drain-Header & PowerFooter Gating (DHPF) (d) Drain-Footer & Power-Header Gating (DFPH).

- 121 -

ISOCC 2010

TABLE III.

EXPERIMENTAL RESULTS OF POWER GATING

22nm Process Technology, Supply Voltage = 1V Gate Average Leakage Average Dynamic Average Delay Power Savings (%) Power Savings (%) Penalty (%) Type 79.39 26.20 339 Power Gating 62.45 22.94 228 Power Header 50.29 8.75 166 Power Footer

be used. Through a number of design iterations, highly optimized circuit type can then be determined for each gate. Experiments have shown that reduced power consumption is achieved with little or no increase in critical path delay for the whole circuit.
Figure 6. Leakage power (W) of PTM 22nm.

V.

CONCLUSION

In this paper, we pointed out problems with previously proposed techniques in reducing leakage power consumption. We then proposed a circuit family for reducing leakage current. Based on the experimental investigation on delay and power consumption of each member of the proposed circuit family, we introduced a new leakage power reduction technique. Experiments using 45nm, 32nm, and 22nm process technologies have shown that the proposed technique is capable of reducing significant leakage power consumption while incurring little or no increase in the critical path delay of circuits. REFERENCES
Figure 7. Propagation delay (S) of PTM 22nm [1] International Technology Roadmap for Semiconductors(ITRS-09). http://www.itrs.net/Links/2009ITRS/Home2009.htm [2] N. Hanchate and N.Ranganathan, LECTOR: A Technique for leakage reduction in CMOS circuits, IEEE Trans. VLSI Systems, vol. 12, pp. 196-205, Feb., 2004. [3] M. D. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, Gated-Vdd: A circuit technique to reduce leakage in deep submicron cache memories, in Proc. IEEE ISLPED, 2000, pp. 9095. [4] J.C. Park and V. J. Mooney III, Sleepy stack leakage reduction, IEEE Trans. VLSI Systems, vol. 14, no. 11, pp. 1250-1263, Nov. 2006. [5] S. Narendra, V. D. S. Borkar, D. Antoniadis, and A. Chandrakasan, Scaling of stack effect and its application for leakage reduction, in Proc. IEEE ISLPED, 2001, pp. 195200, Aug. 2001. [6] Predictive Technology Model (PTM). http://ptm.asu.edu . [7] L.Wei, Z. Chen, M. Johnson, K. Roy, Y. Ye, and V. De, Design and optimization of dual threshold circuits for low voltage low power applications, IEEE Trans. VLSI Systems, pp. 1624, Mar. 1999. [8] Z. Chen, M. Johnson, L. Wei and K. Roy, Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks, in Proc. IEEE ISLPED, pp. 239-244, Aug. 1998. [9] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS, IEEE J. Solid-State Circuits, vol. 30, pp. 847854, Aug. 1995. [10] M. Johnson, D. Somasekhar, L.-Y. Chiou, and K. Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, IEEE Trans. VLSI Systems., vol. 10, no. 1, pp. 15, Feb. 2002. [11] Srikanth Katrue and Dhireesha Kudithipudi, GALEOR: Leakage reduction for CMOS circuits, 15th IEEE International Conference on Electronics, Circuits and Systems, pp. 574-577, Aug. 2008.

Figure 8. Dynamic power (W) of PTM 22nm.

With the understanding of the properties of the proposed circuit family, we propose to design a circuit with a mixture of them. Circuits along critical path will first use only original circuit types. Then gates along critical paths are analyzed to measure their criticality. Gates with low criticality will be considered to be replaced with drain-gating based gates as long as the critical path delays are within acceptable range. Gates not along critical paths are then analyzed and divided into a number of groups (such as slightly non-critical, average non-critical, and absolute non-critical). Gates in the absolute non-critical groups will always use power gating. For the slightly non-critical and average non-critical, a mixture of power gating and others will

- 122 -

ISOCC 2010