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Peripheral Devices Computer device, such as a CD-ROM drive or printer, that is not part of the essential computer, i.e., the memory and microprocessor.
Peripheral devices can be external -- such as a mouse, keyboard, printer, monitor, external Zip drive or scanner -- or internal, such as a CDROM drive, CD-R drive or internal modem.
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I/O organization
Peripheral Devices I/O Interface Asynchronous Data transfer Modes of Transfer Priority Interrupt Direct Memory Access(DMA) Input-Output processor Data communication processor
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I/O organization
Input/Output Interfaces
Provides a method for transferring information between internal storage (Such as memory and CPU registers) and external I/O devices Resolves the differences between the computer and peripheral devices Peripherals-electromechanical devices CPU or Memory electronics device Data transfer rate Peripherals-usually slower CPU or Memory-Usually faster than peripherals , some kinds of synchronization mechanism may be needed
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I/O organization
Input/Output Interfaces
Unit of Information Peripherals-byte CPU or Memory-Word Operating Modes Peripherals-Autonomous, Asynchronous CPU or Memory-synchronous
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Isolated I/O Separate I/O read/write control lines in addition to memory read/write control lines Separate (isolated) memory and I/O address spaces Distinct input and output instructions
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Programmed I/O
CPU has direct control over I/O
Sensing status Read/write commands Transferring data
CPU waits for I/O module to complete operation Wastes CPU time
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I/O Commands
CPU issues address
Identifies module (& device if >1 per module)
Read/Write
Module transfers data via buffer from/to device
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I/O Mapping
Memory mapped I/O
Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O
Large selection of memory access commands available
Isolated I/O
Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set
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CPU Viewpoint
Issue read command Do other work Check for interrupt at end of each instruction cycle If interrupted:Save context (registers) Process interrupt
Fetch data & store
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DMA Controller
The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O device. In additional, it needs an address register, a word count register and a set of address lines. The address register and address lines are used for direct communication with the memory The word count register specifies the number of words that must be transferred.
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DMA Controller
The data transfer may be done directly between the device and memory under control of DMA. The DMA controller has three resisters An address register A word count register A control register
a) b) c)
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DMA Controller
The address register contains an address to specify the desired location in memory. The address bits go through bus buffers into the address bus. The address register is incremented after each word that is transferred to memory. The word count register holds the number of words to be transferred.
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DMA Controller
This register is decremented by one after each word transfer. The control register specifies the mode of transfer. All registers in the DMA appear to the CPU as I/O interface register. Thus the CPU can read from or write into the DMA registers under program control via the data bus.
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DMA Controller
The DMA first initialized by the CPU then after the DMA starts and continues to transfer data between memory and peripheral unit until an entire block is transferred. The initialization process is essentially a program consisting of I/O instructions that include the address for selecting particular DMA registers. The CPU initializes the DMA by sending the following information through the data bus:
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DMA Controller
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The starting address of the memory block where data are available for read) or where data are to be stored (for write) The word count, which is the number of words in the memory block Control to specify the mode of transfer such as read or write A control to start the DMA transfer
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DMA Controller
The starting address is stored in the address register. The word count is stored in the word count register and the control information in the control register. Once the DMA is initialized, the CPU stops communicating with DMA unless it receives an interrupt signal or if it wants to check how many words have been transferred.
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DMA TRANSFER
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DMA Function
Additional Module (hardware) on bus DMA controller takes over from CPU for I/O
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DMA Operation
CPU tells DMA controller:Read/Write Device address Starting address of memory block for data Amount of data to be transferred
CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished
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CPU
DMA Controller
I/O Device
I/O Device
Main Memory
Single Bus, Detached DMA controller Each transfer uses bus twice
I/O to DMA then DMA to memory
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I/O Processors
The DMA controller introduced in the previous lecture can improve system performance by speeding up data transfers between memory and I/O devices. However, multiple transfers require separate DMA transfers, along with the necessary setup for each transfer. In some cases, data must be manipulated once it is read from the I/O device; the DMA controller can only transfer data.
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I/O Processors
Each of these shortcomings is addressed by I/O processors. I/O processors, sometimes called I/O controllers, channel controllers or peripheral processing units (PPUs), perform the functions of DMA controllers and much more. The I/O processor is situated between the I/O devices and the rest of the system, very much like the DMA controller.
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I/O Processors
Unlike the DMA controller however, the I/O processor connects to more than one I/O device. The I/O devices are grouped together on an I/O bus, as opposed to the regular system bus. Thus, one I/O processor can coordinate transfers from several different I/O devices. Generally speaking , I/O processors handle all of the interactions between the I/O devices and the CPU.
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I/O Processors
The CPUs only direct I/O interaction is with the I/O processor itself If the CPU must read in data from an I/O device or initiate a block transfer between an I/O device and memory, the CPU instructs the I/O processor to perform this task. The I/O processor coordinates the actual data transfer. The only exception is that the CPU coordinates the transfer of data between itself and the I/O processor.
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Simplex: 0ne direction only Half-duplex: transmitting in both directions but data can be transmitted in only one direction at a time. Need pair of wires. Full-duplex: transmission can send and receive data in both directions simultaneously
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