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Smaller access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, greater access time
Characteristics
Location Capacity Unit of transfer Access method Performance Physical type Physical characteristics Organisation
Location
CPU Internal (main) External (secondary)
Capacity
Word size
The natural unit of organization
Number of words
or Bytes
Unit of Transfer
Internal
Usually governed by data bus width
External
Usually a block which is much larger than a word
Addressable unit
Smallest location which can be uniquely addressed
Direct
Individual blocks have unique address Access is by jumping to vicinity plus sequential search Access time depends on location and previous location e.g. disk
Associative
Data is located by a comparison with contents of a portion of the store Access time is independent of location or previous access e.g. cache
Performance
Access time
Time between presenting the address and getting the valid data
Transfer Rate
Rate at which data can be moved
Physical Types
Semiconductor
RAM
Magnetic
Disk & Tape
Optical
CD & DVD
Physical Characteristics
Decay Volatility/non-volatile Erasable/nonerasable Power consumption
Organisation
Physical arrangement of bits into words e.g. interleaved
How fast?
Time is money
How expensive?
Memory Hierarchy
Registers
In CPU
External memory
Backing store
Hierarchy List
Registers L1 Cache L2 Cache Main memory Disk cache Disk Optical Tape
Locality of Reference
During the course of the execution of a program, memory references tend to cluster e.g. loops
Cache
Small amount of fast memory Sits between normal main memory and CPU May be located on CPU chip or module
Cache Design
Size Mapping Function Replacement Algorithm Write Policy Block Size Number of Caches
Speed
More cache is faster (up to a point) Checking cache for data takes time
Mapping Function
It is the correspondence between the main memory blocks and those in the cache memory. When the cache is full and the processor references a location not in the cache:
A block from the cache should be removed (or returned to memory)
The cache control hardware uses replacement algorithm to select this block
The required block is transferred from the memory to the cache (in the place of the recently removed block).
Cache Management
To find:
Which blocks in the main memory are currently existing in the cache. The position of the blocks in the cache.
In case of blocks replacement, it is required to select the block (Victim) that will be removed from the cache. Memory Mapping:
Direct Mapping Associative Mapping Set-Associative Mapping
Cache Management
Assume that:
The memory and the cache are divided into blocks. Each block has 16 words. The cache is 2 K Words (2 * 1024 = 2048 Words)
The cache consists of 128 blocks (2048/16)
24 bit address 2 bit word identifier (4 byte block) 22 bit block identifier 8 bit tag (=22-14) 14 bit slot or line No two blocks in the same line have the same Tag field Check contents of cache by finding line and checking Tag
Direct Mapping
Each block of main memory maps to only one cache line
i.e. if a block is in cache, it must be in one specific place
Address is in two parts Least Significant w bits identify unique word Most Significant s bits specify one memory block The MSBs are split into a cache line field r and a tag of s-r (most significant)
Direct Mapping
Direct Mapping
Main memory blocks 0, 128, 256, to block 0 of cache Main memory blocks 1, 129, 257, to block 1 of cache Main memory blocks 2, 130, 258, to block 2 of cache Main memory blocks 127, 255, 383, to block 127 of cache
Direct Mapping
64 K memory Memory has 32 Tags Each Tag has 128 Blocks Each Block has 16 words
Tag = 0
216 Memory Memory has 25 Tags Each Tag has 27 Blocks Each Block has 24 words
Tag 5-bit Block 7-bit word 4-bit
Tag = 1
Tag = 31
22 bit tag stored with each 32 bit block of data Compare tag field with tag entry in cache to check for hit Least significant 2 bits of address identify which 16 bit word is required from 32 bit data block e.g. Address Tag Data Cache line FFFFFC FFFFFC 24682468 3FFF
Associative Mapping
A main memory block can load into any line of cache Memory address is interpreted as tag and word Tag uniquely identifies block of memory Every lines tag is examined for a match Cache searching gets expensive
Associative Mapping
Any block of main memory can be placed in any block position in the cache
tag tag
Main memory
Block 0 Cache Block 0 Block 1 Block i Block 127 Block 1
tag
Block 4095
Associative Mapping
64 K memory Memory has 4096 Tags Each Tag has 1 Blocks Each Block has 16 words
Block 0 Block 1
216 Memory Memory has 212 Tags Each Tag has 20 Blocks Each Block has 24 words
Tag 12-bit word 4-bit Block 4095 Block i
Set-Associative Mapping
Blocks 0 64 128 - 4032 can map into set 0 Blocks 1 65 129 - 4033 can map into set 1 Blocks 63 127 191 - 4095 can map into set 63 Main memory
Block 0 Cache Set 0 Set 1 tag tag tag tag Block 0 Block 1 Block 2 Block 3 Block 1
Block i
Set 50
tag
Set 63
tag
Block 127
Set-Associative Mapping
64 K memory Memory has 64 Tags Each set has 2 Blocks; Cache has 64 Sets Each Block has 16 words 216 Memory Memory has 26 Tags Cache has 26 Sets
Set 50 tag Block 100 Set 0 Set 1 tag tag tag tag Cache Block 0 Block 1 Block 2 Block 3
Set 63
tag
Block 127
Set-Associative Mapping The number of blocks in each set may increase or decrease. If the number of blocks in each set is 4, then the set field is 5-bit (cache is divided into 32 sets), the block field is 7-bit, and the word field is 4-bit. If the number of blocks in each set is 8, then the set field is 4-bit (cache is divided into 16 sets), the block field is 8-bit, and the word field is 4-bit. If the number of blocks in each set is 128, then the set field is 0-bit (cache is one set), the block field is 12-bit, and the word field is 4-bit. [Associative mapping] If the number of blocks in each set is 1, then the set field is 7-bit (cache is divided into 128 sets), the block field is 5-bit, and the word field is 4-bit. [Direct mapping]
Mapping Function
Valid Bit:
When the memory is updated from the Disk through the Direct Memory Access (DMA), the cache memory is bypassed In this case the contents of some blocks in the cache differ from the corresponding blocks in memory. these blocks are marked with 0 value in valid bit.
Mapping Function
Valid Bit:
If a block in the cache and the cache applies the write-back protocol; the block in the cache may differ than its corresponding block in the memory If the memory tries to send this block of data to Disk through DMA The dirty bits in this block is first transferred to the memory to update its content, then the block is send to the Disk.
Random
Write Policy
Must not overwrite a cache block unless main memory is up to date Multiple CPUs may have individual caches I/O may address main memory directly
Write through
All writes go to main memory as well as cache Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date Lots of traffic Slows down writes
Write back
Updates initially made in cache only Update bit for cache slot is set when update occurs If block is to be replaced, write to main memory only if update bit is set I/O must access main memory through cache N.B. 15% of memory references are writes