ESSDERC 2002

Roadmap Differentiation and Emerging Trends in BCD Technology

Claudio Contiero, Antonio Andreini and Paola Galbiati* STMicroelectronics, TPA Groups R&D Department, Cornaredo, *Agrate, Milan, Italy E-mail: claudio.contiero@st.com
In parallel to the race towards the minimum lithography reduction to achieve large complexity, other branches with different requirements have developed. For example in the applications up to 700V the primary efforts have been addressed to make possible a reliable coexistence on the same chip of low voltage control circuits and high voltage DMOS stages. Other fields, mainly automotive, have required dedicated BCD approaches to satisfy the demand to provide robust power elements with simplified control sections to guarantee high quality and reliability in harsh application environment at no cost penalty. Modularity, an aspect present at different levels in all the BCD technologies, will be a feature characterizing more and more the new BCD developments. Exploiting modularity it is possible to generate a large variety of very different ICs, with the best trade-off between functions, performance and cost. A typical example is the IC directly mounted on an ink-jet print head, realized with BCD options simplified to the minimum level necessary to realize the application. SOI approach has been evaluated since many years because of the advantages offered in reducing parasitic effects between integrated functions. Penalized by the extra cost of the starting material, only now it is becoming a mainstream approach for some BCD-like technology producers [1]. Anyway this approach is emerging as a good alternative for very specific applications. Very thick copper interconnects have been introduced in the recent years as an approach to overcome the limitation to the improvement of the power device current/resistance performance obtainable with the scaling down of lithography [2]. In this paper the evolution, trends and issues driven by application requirements and opportunities in the BCD field are presented.

Abstract
This paper reviews the BCD technology roadmap and its evolution towards finer lithography features, wider voltage capability offer and the broadening variety of integrable components. The splitting of the roadmap into three main directions - high-voltage, high-power and high-density and the different evolving criteria are discussed. The trend of more recent BCD versions to converge to technology platforms common to advanced CMOS processes, diversifying or simplifying the technology according to different application needs, the emerging and consolidation of new directions are presented. Examples of possible realizations in different application fields using the more suitable BCD approach are also proposed.

1. Introduction
The name BCD (Bipolar-CMOS-DMOS) has been coined around the mid-eighties to classify the family of silicon processes that allows to mix on the same chip different structures such as Bipolars for precise analog functions, CMOS for digital design and DMOS structures such as power and high voltage elements. Several BCD technologies have been generated and updated to properly address specific application needs. In the field of applications below 50V, the largest one, BCD evolution has been driven by the need to integrate on the same chip more and more complex and diversified functions, to the point that today even Non-Volatile Memories are offered. Besides, the density of integration achieved makes it possible to adopt digital design approaches such as integrating micro-controllers, to realize optimal driving solutions to improve performance. In a time of fast technology advancement this approach represents an answer to ever-increasing market demand for System on Silicon devices where both the signal processing part and power actuator can be combined. This is not only an economical requirement because the integration brings several advantages in terms of reliability improvement, electromagnetic interference (EMI) reduction, and last but not least, space and weight reduction.

2.

BCD Roadmap differentiation

Before the advent of BCD technology, power ICs were realized using pure bipolar technologies (I2L for logic) that obtain very limited benefit in improving power device performance and increasing logic density as the lithography is scaled down.

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The introduction of BCD technology brought a revolutionary change and significant advances in the complexity possible in power ICs yielding a roadmap that has shortened the distance from the Moore Law with the difference that while pure CMOS technology progresses towards finer lithography and higher speed, BCD technology also progresses towards greater flexibility. A roadmap differentiation is the result. Since a few years ago this is happening, with different evolving criteria, in three major technology directions: High-Voltage-BCD, High-Power-BCD, High-DensityBCD. New trends are appearing or consolidating like High-Voltage-CMOS-BCD (HVCMOS-BCD), RadioFrequency-BCD (RF-BCD) and BCD on SOI (SOIBCD).

The BCD-offline evolution, in term of reduction of minimum lithography and increasing of complexity, has been up to now very limited. Both technology and marketing reasons are behind this. Moving from the delicate balance between the ingredients necessary to guarantee stability in the high voltage device performance and those required to achieve large density in the control circuit is not simple because they, like dielectric layer thickness, number of metal interconnects, would follow diverging trends. The trade-off between process cost and application value, being finally the key issue to determine the need to progress towards more advanced solutions, has not required this happen so far.

2.1. High-Voltage-BCD
BCD technologies that allow integrating functions with voltage capability ranging from 100V to 700V are included in the high-voltage category. With the junction-isolation technique, the separation of the silicon islands where the various components are integrated is achieved through reverse-biased junctions obtained by diffusing P regions through the entire depth of the N-type epitaxial layer grown on a P-type substrate. With the up and down isolation approach, adding heavily doped N buried layers and sinker plugs, it is straightforward to realise integrated vertical DMOS devices with real high-side operation capability at voltages as high as about 300V. The higher the voltage capability requested the thicker is the epitaxial layer. As a consequence a lot of space is consumed by the side diffusion of the junction isolation. This penalty automatically limits the request for fine lithography feature. As an example BCD250 was introduced in 1987 [3] at 4m to realize products for video and telecomwire-line application and only shrunk, several years later, to 3.5m. Other BCD examples at 100/120V and 170V have been introduced at 2.5m to allow the high-side capability implementation but a real breakthrough in term of minimum feature size reduction becomes achievable by moving to dielectric isolation obtained by SOI plus trench etch and dielectric refill (see 3.3). The majority of the high voltage applications are in the range 500V-700V. The only realistic way to offer a BCD process that satisfies such a high voltage capability is to exploit the resurf principle applied to the Lateral DMOS [4]. This has been done in the so called BCDoffline, now at 2m, utilized mainly in the field of electronic lamp ballasts and power supplies for industrial applications (fig. 1). In the BCD-offline approach it is only possible to implement low-side LDMOS with a limited source floating capability of a few tens of volts. This limitation can be overcome by adopting an SOI approach.

Figure 1. Chip photograph of a Fully Integrated Power Supply realized in BCD-Offline, integrating a resurf LDMOS (1A, 700V). However demand is now emerging to integrate more complex digital sections to perform a more sophisticated control of the high voltage stages. An evolution towards minimum lithography reduction will therefore happen also in the field of electronic lamp ballast and power supply applications.

2.2. High-Power-BCD
The BCD processes belonging to this category are being pursued for those applications, typically ranging from 40V to 90V, in which high current and only moderate control circuit integration are needed. Besides due to typical applications demand, the reduction of the power device areas is limited by the capability to dissipate power. Therefore the evolving criteria of this BCD process category are addressed not to the exasperated use of technology steps typical of VLSI area but more conveniently to the development of steps and process architecture conceptions that support robust

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power device and low cost control section implementation. A process example belonging to this intermediate BCD roadmap line is the so-called BCD4 at 0.8m. BCD4 architecture follows a typical junction isolation approach with power DMOS, both in Lateral and Vertical fashion, implementing highly doped N buried layers and sinker plugs. The N epitaxial layer, grown on a P type substrate, is designed to support VDMOS devices from 70V up to 90V (fig. 2).

high-power and high-density. The first example of this new category is BCD5 at 0.6m generated before BCD4 just to satisfy new emerging requests from the market to have available on the power chip more intelligence and non-volatile memory capability to realise what have been called Super Smart Power ICs.

Figure 2. BCD4 process cross-section through first metal. BCD4 follows therefore the same scheme of the previous BCD generations reducing micro-lithography but also the number of masks and options because of the goal to optimize it for limited market segments. The majority of applications requiring this approach are coming from the automotive field where typically there is the need for high current capability, moderate voltage, limited control circuits, high robustness and reliability and all at the lowest possible cost. Fig. 3 shows an example of a chip realized in this technology. The IC integrates 18 low-side power DMOS actuators rated at 70V and 80V, plus a limited amount of control circuit.

Figure 3. Chip photograph of a BCD4 IC integrating 18 low-side power VDMOS (70V, 80V) for automotive applications. BCD5 architecture still follows a traditional junction isolation scheme with epitaxial layer growth on P type substrate after N and P buried layers formation. Here the innovative approach has been the method to implement complementary LDMOS devices by large angle tilt P and N body implant without compromising the stringent thermal budget requirements due to the possibility to integrate dense non-volatile memory [5,6]. Thanks to this method and to the typical features of advanced silicon technology, like tungsten polycide gate, multilevel metals with tungsten plugs and vias stacked on contacts, in BCD5 it has been possible to design ICs in which both power functions and logic functions are optimised because they have to play an important role in the applications. Besides relevant EPROM and EEPROM blocks have become available on the same BCD chip. Two ICs are shown in fig. 4 and fig. 5 as an example of opposite exploitation of BCD5. The first one (fig. 4) is the IC photograph of a high efficiency class AB power amplifier for car-radio delivering 4 by 65W to the loads. It consists of four H-bridges with complementary LDMOS plus a limited driving and control section mainly composed by analog blocks. The second one (fig. 5) is a motor control for automotive application, integrating many digital blocks such as a 8-bit microcontroller (ST7) plus 128 K-bit EPROM and 1 K-bit EEPROM, analog functions such as A/D converters, voltage regulators, temperature sensors, 40V N and P power LDMOS connected in H-bridge configuration

2.3. High-Density-BCD
This BCD process category represents the main stream of the BCD evolution because here there is a wide variety of possible applications. The voltage capability requested to power devices typically spans from 5V up to 50V with some requests at 70V mainly for automotive applications. The high-density-BCD roadmap follows with some year delay, the digital CMOS roadmap converging to the same process-technology platforms. The challenging goal is to maximize power device performance maintaining full compatibility with original CMOS and non-volatile memories of the equivalent lithography generation. The origin of this BCD category goes back to around 1995 when the BCD roadmap started to differentiate in

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delivering to the load 5A with 60mOhm. This chip represents an example of a new IC category that has been called Super Smart Power.

voltage and power components have been implemented onto an already existing 0.35m CMOS platform. The CMOS module is built with twin retrograde wells plus high energy implanted triple well on a P-/P+ substrate. The power device module is inserted without adding any specific epitaxial layer growth and junction isolation steps [7]. This approach allows the integration of isolated pockets to realize high voltage functions up to 45/70V (fig.6).

Figure 4. BCD5 Chip photograph of a 4x65W power amplifier for car-radio integrating 4 H-bridges with complementary power DMOS.

Figure 6. BCD6 process cross-section through the fifth metal. Thin gate oxide (7nm) and double flavoured gates are used both for 3.3V CMOS and LDMOS devices. To guarantee full compatibility with the 0.35m CMOS process platform, complementary LDMOS body regions are realized by means of a large angle tilt implant self aligned to the gat. To sustain high voltage with very thin gate oxide all the LDMOS require a field-plated configuration to limit high electric field at the drain side poly edge. Two, three or four thin Al/Cu metal layers for high density interconnections plus an extra thick power metal for high current low resistivity capability are used together with Salicide, Ti/TiN barrier layer, W plugs and planarized interlayer dielectrics by Chemical Mechanical Polishing (CMP) technique. The use of Salicide technique in Power LDMOS realization improves device performance both in term of robustness and operating speed. Thanks to the very low sheet resistance a more uniform potential distribution is achieved along the source finger. Robustness against inhomogeneous parasitic NPN turn on during high current operation at high Vds is then increased. To satisfy the need of Super Smart Power integration, BCD6 offers different families of NVM, from OTP for trimming purpose to dense Flash for storing software and data. A typical field of application of BCD has always been the power combo motor drives for hard disk. The trend to reduce disk diameters without penalising memory capacity, the improvements in motor performance,

Figure 5. BCD5 Chip photograph of a complex motor driver for automotive integrating a 5A, 40V Hbridge, an 8 bit micro-controller, 128 Kb EPROM, 1 Kb EEPROM. BCD5 represents a breakthrough step in the BCD roadmap also for its versatility. The process architecture is in fact very modular. Optional components can be added or taken away increasing or decreasing complexity. That allows the more convenient cost vs. performance choice to afford the application. Only Lateral DMOS are offered because at the BCD5 level of lithography and technology features the power device performance obtainable is superior at least up to 70V. A further step versus the complete compatibility with the CMOS technology is achieved in BCD6 where high

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especially in hard disk drives for mobile PCs, induces a decrease in the power requested by spindle and voicecoil motors. The need to implement the head parking function after a power down utilizing the energy generated by the spindle motor used like a generator makes mandatory to guarantee high performance of power stages at low supply voltage. In fact the mechanical energy to move the head to a safety zone is very low and the back electromagnetic force is less than 3V. BCD6 fits well these new requirements because of the high performance achievable at 3.3V both for CMOS and power stages In fig. 7 the chip photograph of a power combo realized in BCD6 for data storage application is showed.

Table 1. Main technology features of more recent BCD processes.

SOIBCD Litho (m) Dual Gate Oxide CMOS Lg (m) CMOS (V) DMOS (Lat./Vert.) Power N&PLDMOS DMOS (V) NVM Metal Levels (last thick) 1.0 N 1.0 5 L Y
30/100/200

BCD4 0.8 N 0.8 5 L&V N

30/45 70/80/90

BCD5 0.6 Y 0.8 5 L Y

16/20/30/45 70/80

BCD6 0.35 Y 0.35 3.3/5 L Y

5/12/20 45/70

BCD8 0.18 Y 0.18 1.8 3.3or5 L Y

5/12/20 45

1-2

2-3

Y 2-3

Y 3-4-5

Y 4-5-6
2

Table 2. Comparison of Specific RON (mOhm*mm ) vs. Voltage capability of DMOS realized in BCD4, BCD5 and BCD6.
Spec Rated (V) 90 80 70 45 30 20 16 12 5 BCD4
NDMOS @Vgs=5/10V @E=1.8/3.6MV/cm

BCD5
NDMOS PDMOS

BCD6
NDMOS PDMOS

@Vgs=5/10V @E=2.7/3.3MV/cm

@Vgs=3.3V @E=4.7MV/cm

440/420 310/280 210/190 90/70 70/50

180 (*) 210/140 76/n.a. 27/n.a. 15/n.a.

255/230 145/n.a. 118/n.a. 85/n.a. 65/n.a. 135 (#) 72 (#) 21 12 7 38 30 19

Figure 7. Chip photograph of a BCD6 motor driver for data storage application. In Table 1 and Table 2 the main technology and electrical features of the more recent BCD processes, included BCD8 now in development, are summarized. Looking at fig. 8 it is evident how the high-density features of BCD6 offer the greatest impact in die size reduction of a power IC, making it cost effective to adopt a sophisticated digital control that allows better performance with lower power dissipation. Going from BCD5 to BCD6 digital gate density increases a factor 4 to 5 according to the number of metal interconnects adopted. BCD6 has been designed to be highly modular so that mask steps can be added or omitted according to the components required for ICs design. In this way the process can be either simplified or differentiated or specialized according to the application requirements. Following this approach a simplified version of BCD6 with the minimum level of options necessary to the goal has been optimised to address the wide market for energy management chips for cellular phones.

(*) @ grounded source

(#) @ source-low bias configuration

Figure 8. Chip photographs of fully digitally controlled power combos for hard-disk-drive applications realised in BCD5 and BCD6. The next step in the BCD roadmap is BCD8 at 0.18m while the 0.25m technology node is skipped to reduce the delay with respect to the CMOS evolution rate. Like BCD6 this new step adopts dual gate oxide architecture to maintain full compatibility with the logic

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CMOS of equivalent generation and the LDMOS power elements ported from BCD6.

3. Emerging trends
The future of the electronic system market will be dominated by multimedia applications, portability and connectivity in general. These systems consist of more and more complex and faster digital ICs plus dedicated mixed function chips to manage the peripherals like displays, lightings, cameras, audio parts, and RF communications. To realise the latter ones the ability to design for very low power consumption and high efficiency power conversion must be accompanied by the availability of mixed technologies offering high voltage capability, extremely low leakage to guarantee long battery life in stand-by conditions and good performance at low voltage supply (battery), even less than 1V, together with low noise components. The roadmap for mixed signal technology has to be tuned to have the best fit among these application requirements and cost, offering modular, flexible and competitive specific process solutions. Three new streams are emerging. HVCMOS-BCD for colour LCD and OLED driver circuits, RF-BCD to realize RF Power Amplifier out-put stages in cellular phone systems and BCD on SOI utilised in telecom wireline applications for xDSL drivers.

In a 0.35/0.18m technology platform the thinner oxide (3.5/7nm) is used for low voltage (1.8V/3.3V) CMOS logic and analog functions, the thicker one, 40nm or 60nm, is introduced for 20V or 40V high voltage drivers. High voltage drain/source capability is achieved through the thick gate oxide and adopting drift MOS structures when LDMOS are not necessary. Another important feature to be considered is trimming on the module. In fact the LCD driving voltage has to be as accurate as possible in order to keep the contrast uniform from module to module. However even if the LCD driving voltage generated by the IC is very accurate (below 1%) there are other sources of error introduced by the module itself (such as spread of the liquid crystal physical properties, spread of the gap between the glasses etc) that contribute to deteriorate the contrast. Therefore trimming the LCD voltage directly on the module corrects every effect and is highly recommended. To perform this function OTP memories like antifuses represent the ideal solution. It must also be emphasized that for COG (Chip On Glass) applications it is important to minimize as much as possible the external components in order to reduce cost and this implies the integration on the driver of all possible functions.

3.2. RF-BCD for RF Power Amplifier

The rapid development of wireless products has pushed research efforts towards low cost and high performance RF devices. Advanced BCD technologies can be optimised to satisfy modern radio-frequency integrated circuits requirements. In BCD6 technology RF Power Amplifier (PA) for mobile phone have been realized introducing a process differentiation to optimise LDMOS RF performance maintaining compatibility with 3.3V CMOS. To realise RF PA, GaAs is the prevailing technology used so far. The excellent performance of GaAs are paid in term of high cost, intrinsic high off-state current, poor compatibility with functions where analog and digital blocks are required on the same die (reduced integration possibility). For these reasons RF LDMOS devices are becoming competitive alternatives for wireless power amplifiers and recently they have been successfully realized with saturated power added efficiencies of more than 60% [8,9]. On RF-BCD6 excellent saturated and linear efficiencies have been measured on LDMOS power components: 70% at 2GHz and 45% at 38dBc ACPR respectively. The main advantage of Si based PA respect to GaAs PA is the use of one technology to realize the PA circuit with strong matching potential between components. The goal is not to make a GaAs pin to pin replacement but to exploit the flexibility of silicon technology integrating control and power stages in the same chip solving for

3.1. HVCMOS-BCD for Colour Display Drivers

A new important market is going to be the 3G mobile phones. The trend is toward increased battery life and integration of multimedia functions (such as video capability), the latter requiring colour displays of larger size. Increasing battery life means reducing power consumption and therefore working at low voltage. At the same time the driving architecture of a large colour display requires a high driving voltage. It follows that the display driver IC has to be interfaced directly with the base-band logic supply voltage (1.7V and below) but at the same time must withstand the high voltage in order to properly drive the pixels of a large display. 20V are necessary for passive LCD and for OLED (Organic Light Emitting Diode), while 40V are needed for TFT-LCD. Besides large static RAMs are required depending on the display size (number of pixel) multiplied by the number of bits per colour. For example for the visualization of 65.5 K different, about 500Kbit is the needed amount of RAM that becomes cost effective to integrate in a CMOS platform at 0.35m or below. The driving architecture makes mandatory the availability of devices capable of handling high voltage, both gate-source and drain-source, inside a high density CMOS process. A double gate oxide approach is the process solution to fit these application fields.

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example mismatch issues between control circuit and the power function. On the future WCDMA standard, the directions towards a monolithic integration will be even more mandatory because the control function is an absolute necessity. In fig. 9 a WCDMA PA test chip realized in RF-BCD6 technology with power control circuitry embedded is shown.

circuitry resulted to be mandatory to realize the integrated functions [10]. More recently the more compact Silicon On Insulator (SOI) approach, obtainable by various techniques, gave a new push to the DI scheme as a viable solution to satisfy specific requirements in mixed function ICs. The process structure is usually based on a relatively thick active silicon layer, with respect to the SOI integration scheme adopted on high-density CMOS processes. The thickness of this layer can be kept within a few microns exploiting the resurf principle to reach high voltage operation. A very thin SOI mixed process has been also presented for applications up to 600V [11]. The size of the isolating trenches greatly reduces the loss of silicon area dedicated to isolate pockets, with respect to conventional Junction Isolation (JI) approach. In the BCD roadmap a SOI-BCD has been developed at 1m to target applications ranging from 30V, 100V to 200V like telecom wire-line xDSL driver, monitor video amplifiers and plasma display panel drivers. The active silicon is 9m thick on a 2m buried oxide. The lateral isolation is realised by oxide re-filled trenches. Complementary LDMOS are integrated with high flexibility in fixing their breakdown voltage together with standard CMOS (fig. 9).

Figure 9. Chip photograph of a test chip of an integrated RF power amplifier for WCDMA application realised in RF-BCD6. With this approach, the stringent WCDMA requirements in terms of linearity and efficiency can be satisfied, saving at the same time the battery life thanks to the smart action of the integrated control part. An integrated DC/DC converter controls the power level, allowing higher amplifier efficiency and low battery consumption. Even if intrinsically, the GaAs transistor has always a cut-off frequency higher than the LDMOS device, the Silicon power amplifier performance, measured at the output of the PA module, is comparable with those of the GaAs module at saturated output power and much better at low power level. To fully exploit the LDMOS capability in these applications, the integration in the PA module of high efficiency passive components like coils and capacitors is becoming mandatory. These targets have to be addressed working not only on the silicon process, but also improving the assembly technology. Figure 9. SOI-BCD: SEM picture of a 200V LDMOS cross-section through first metal. Fast complementary vertical bipolar transistors are realised with good performance (3GHz, 20V) even leaving constant the mask number. Plasma display panel drivers benefit from the size reduction of the high voltage multiple output stages and benefit from the suppression of bipolar parasitics to contain the power consumption [12-14]. The high cut-off frequency of the high voltage complementary DMOS transistors together with the reduced parasitic substrate capacitances are available features to improve performance of video amplifiers for monitors. The advantage of substrate parasitic capacitance reduction is maximized at low voltage operation. This peculiar feature makes SOI attractive to implement highspeed analog functions for fast wire-line data transmission [15]. SOI-BCD offers the best trade-off between technology features and circuit performance to realize xDSL drivers. In fact this transmission technique, adopting DMT (discrete multi tone) modulation scheme, requires the ability to drive large signals as high as 15V40V peak to peak across the copper line in a broadband

3.3. SOI-BCD
The Dielectric Isolation (DI) approach has been adopted since many years in applications where the electrical decoupling of the substrate from the active

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environment with excellent performance in terms of noise and linearity. DMOS components are superior to bipolar transistors in optimising voltage capability. Bipolar components allow the best design of critical circuit blocks where noise optimisation is needed. The simultaneous availability of fast DMOS and high Ft bipolar devices gives to circuit designers the maximum flexibility to find the best compromise between frequency response and power consumption. In fig. 10 an example of a VDSL driver realised in SOI-BCD is shown.

Figure 10. Chip photograph of a VDSL driver realised in SOI-BCD. The new rapidly growing market of fast wire-line data transmission is now becoming the most promising application for this BCD roadmap trend.

4. Conclusions
In this paper the roadmap of BCD processes, the directions followed to address different market requirements, and the emerging trends have been presented and discussed. Process diversification and, as an alternative, simplification have been, and will be more and more, a common guideline to address new applications at the right cost.

5. References
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[3] C. Contiero, A. Andreini, P. Galbiati, C. Lombardi, Experimental and Numerical Analysis of The High Voltage Structures Implemented in The New Mixed Process Multipower BCD 250V, High Voltage and Smart Power Devices Symposium Proceedings, Philadelphia, PA, USA, May 1987, pp. 31-40. [4] S. Colak, B. Singer, E. Stupp, LDMOS Power Transistor Design, IEEE El. Dev. Letters, 1, 1980, pp. 51-53. [5] C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi, LDMOS Implementation by Large Tilt Implant in 0.6 m BCD5 Process, Flash Memory Compatible, ISPSD96 Proceedings, Maui, Hawaii, USA, 1996, pp. 75-78. [6] C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi, Characteristics and Applications of a 0.6 m BipolarCMOS-DMOS Technology combining VLSI NonVolatile Memories, IEDM96 Proceedings, San Francisco, CA, USA, Dec. 1996, pp. 465-468. [7] A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, C. Contiero, LDMOS Implementation in a 0.35 m BCD Technology (BCD6), ISPSD2000 Proceedings, Toulouse, France, May 2000, pp. 323-326. [8] I. Yoshida, 2-GHz Si Power MOSFET Technology, IEDM97 Proceedings, Washington DC, USA, Dec. 1997 [9] K.E. Ehwald et al., High Performance RF LDMOS Transistor with 5nm Gate Oxide in a 0.25m SiGe:C BiCMOS Technology, IEDM01 Proceedings, Washington DC, USA, Dec. 2001 [10] Y. Sugawara, Smart Power ICs: Technologies and Applications 4, B. Murari et al. edts., SpringerVerlag, Berlin, 1996 [11] T. Letavic, E. Arnold, M. Simpson, R. Aquino, H. Bhimnathwala, R. Egloff, A. Emmerik, S. Wong, S. Mukherjee, High Performance 600V Smart Power Technology Based on Thin Silicon-on-Insulator, ISPSD1997 Proceedings, Weimar, Germany, May 1997, pp. 49-52. [12] K. Kobayashi, H. Yanagigawa, K. Mori, S. Yamanaka, A. Fujiwara, High Voltage SOI CMOS IC Technology for Driving Plasma Display Panels, ISPSD1998 Proceedings, Kyoto, Japan, June 1998, pp. 141-144. [13] H. Sumida, A. Hirabayashi, H. Shimabukuro, Y. Takazawa, Y. Shigeta, A High Performance Plasma Display Panel Driver IC Using SOI, ISPSD1998 Proceedings, Kyoto, Japan, June 1998, pp. 137-140. [14] M.R. Lee, O. Kwon, S.S. Lee, I.H. Lee, I.S. Yang, J.H. Paek, L.Y. Hwang, J.I. Ju, B.H. Lee, C. Lee, SOI High Voltage Integrated Circuit Technology for Plasma Display Panel Drivers, ISPSD1999 Proceedings, Toronto, Canada, May 1999, pp. 285-288. [15] R. Patel, W. Milam, G. Cooley, M. Corsi, J. Erdeljac, L. Hutter, A 30V Complementary Bipolar Technology on SOI for High Speed Precision Analog Circuits, IEEE BCTM, Sept. 1997, pp. 48-50.

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