CMOS TRANSISTOR ELECTRICAL AGEING EXPERIMENTS

BEHAVIORAL MODELS TO B U L D VHDL-AMS

Benoit Mongellaz. Frau+ Marc, Yves Danto Lab0ratoir.z EL,Univmitt Bordeaux 1 351 ,MU? de la LibQstion 33405 Talencc (France) htqkJ/www.ixl.fr; wnail: mongclla@ixl.fr

ABSTRAC?
ease Jtudv of CMOS n i S naDe-ro&&ts an .. . technology ageing. Our approach is based 'on a meIl!odology .that implies experimental tests to evaluate electrical ageing&ecis on UOSFET. The experimental data set is used 'to build a MOSFET device ageing VHDL-,4MS model. Then, this ageing model is usedJo build M OTA ageing VHDL-AMs m d l This two electrical ageing oe. models are respectively used in sirnulati- to evaluate ageing effects on electrical performances:

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electrical paramete-r shifts along stress time. We focuse on standard method proposed by JEDEC [3]. This characterization method leads to the definition of reliability models. We propose in experimental contribution to obtain experimental data s a in order to build an ageing behavioural model of MOSFET. The samples are 0.8pm CMOS technology. The MOSFET transistor has a LDD structure. Experimentalageing focuses on the hot-carrier injection failure mechanisms We analyse the MOSFET electrical characteristics along ageing cycle. MOSFETdecmcal panunelm are exbucied in 01de-rto define its ageing time dependence and to build 'ageing analytical model. We,obsmc that threshold voltage and drain resis@cc ire strongly affected by ageing respectively on figure 1.

I. INTRODUCXI~N
T m IS wnsidcrablc interest within the miconductor industry h
to analys~ long-tcnn wear OUI effects on circuit pdormances. The

conccpt of Design For Reliability (DFR) is a o m challenge [I]. Design For Reliability strategy is b a d on reliability simulation in thc design flow that aims to predict the impact of physical phenomena frum MOSFET to IC e l h i c a l characteristics o v n the operating time 121. Consequently, reliability simulators need to take into account reliability transistor modcls. The sation I1 d a n k a CMOS wear out failure and details caperimat methods. Eapaimcnts m u l l s arc used Io estimate MOSFBTs clatncal paramcler shifting l a d s 10 reliability device models. The section 111 duails VHDL-AM3 reliability modelling and shows applications to reliability simulalion.

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11.

CMOS AGEING EXPERIMENTS

Fig. 1 Stressed NUOS I-V.

The hotsnmer injection m e c h a n i k for a NMOS arc activated by the lateral electric field. It accclerales carriers to sufficiently high

111. VHDL-AMS RELIABILITY MODELS

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Furthermore, the interest is to predict the amount of MOSFET b g e by el,?cirical simulation. The goals are to model the physic of f a j l u e and take into account in reliability simulators. This needs io take into account specific reliability models to estimate MOSFETs and circuits reliability along large stress time superior to one day or one month. The purpose is to M o m such reliability simulation using VHDLAMS device or circuit models [SI. These models take into &count reliability equations directly included in the model whose quantities an directly timt-dependent.

This VHDL-AMS MOSFET model is applied in Operational Transcondulance Amplifier design. T h w it is used to evaluate the operational amplifier transfer curve sensitivity io strssed NMOS9 (fig. 3). This transistor is highlighted as the most sensitive to drain voltage stress. We can see by simulation that the stressed MOSFET can sffcct the OTA performance. The offset current and the output dynamic of the OTA transfer curve are affected by the amount of degradation induced along stress time (fig.4).
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IV. CONCLUSION
we & p s e . a rnet&io~opy in codtext of q u n g simulation'to develop ageing VHDL-AMs behavioral models: :yHDLAMS modelling is of p t intbFt as it +lows equations and reliability equations.in &iki transistoror circuit, Our approach is based on ex&menis in order to .hive a complete' data-base of CMOS ageing due to' hot-earria bjcction. The MOSFET ageing elechjcal characte+stics.hre. extract electrical'paramitei~shifthg order to build .WOS &essed in VHDL-AMs m&els.. m,ese models aiC &en into account to build OTA Siressed model aiid I o estimate by simulation MOSFET ageing .reSUp eff&ts o n PTA elb+ca:,perfo*anm: The . models depend on acCurate reliability mcdels.and:YHDL . quality. m e aecyrscy ,of reliabi1ity:simulation w ~ b improved by e using third generation VIfDL-AMs device model. WO& on VHDI&S ,model.have td be &tinu accu,racyand interpretation o f r e l i ~ i l i t y simulation.

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REFERENCES .

Matthewson., A . , ~ "Modelling m d ~ simulation of-reliability.for Design." in @c+ecfnhicr Reliabiliv, 1999, pp. 95-1 17. [2] B. Mongelliz. F. Ma&, N;~Lewis.Y.-Darit& "Contribution to ageing,simulation.of compl& atia!oguc circuit using .WDLAMs behavioural modelling linguag<" .in MicmelecmnieS' Reliabi/iv,ZM)Z, pp, 1353-1358.. [3] JEDEC smdanj .JESD-28, "A pmceduk for mpun@g'Nchannel MOSFET hot canier induced degradation 8i maximum substrateC h t undR DC,stmss,". j F c 1995. C. Hu. "IC ,Reliability Simulation," 'in. IEEE %' Solid-Stare Cimiq. VOL-27, 3, mm.h 1992. No. [5] A. Vichoui, "Analog.and Mixed:Signal ExGsion io VHDL? in Andog Integmted Circuils and Signal Procem~ng,"l998,-pP:

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